drivers/net/ethernet/mellanox/mlx5/core/en_rx.c

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/prefetch.h>
  34 #include <linux/ip.h>
  35 #include <linux/ipv6.h>
  36 #include <linux/tcp.h>
  37 #include <linux/bpf_trace.h>
  38 #include <net/busy_poll.h>
  39 #include "en.h"
  40 #include "en_tc.h"
  41 #include "eswitch.h"
  42 #include "en_rep.h"
  43 #include "ipoib/ipoib.h"
  44 #include "en_accel/ipsec_rxtx.h"
  45 #include "lib/clock.h"
  46
  47 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config)
  48 {
  49         return config->rx_filter == HWTSTAMP_FILTER_ALL;
  50 }
  51
  52 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc,
  53                                        void *data)
  54 {
  55         u32 ci = cqcc & cq->wq.fbc.sz_m1;
  56
  57         memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64));
  58 }
  59
  60 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
  61                                          struct mlx5e_cq *cq, u32 cqcc)
  62 {
  63         mlx5e_read_cqe_slot(cq, cqcc, &cq->title);
  64         cq->decmprs_left        = be32_to_cpu(cq->title.byte_cnt);
  65         cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter);
  66         rq->stats.cqe_compress_blks++;
  67 }
  68
  69 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc)
  70 {
  71         mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr);
  72         cq->mini_arr_idx = 0;
  73 }
  74
  75 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n)
  76 {
  77         struct mlx5_frag_buf_ctrl *fbc = &cq->wq.fbc;
  78         u8 op_own = (cqcc >> fbc->log_sz) & 1;
  79         u32 wq_sz = 1 << fbc->log_sz;
  80         u32 ci = cqcc & fbc->sz_m1;
  81         u32 ci_top = min_t(u32, wq_sz, ci + n);
  82
  83         for (; ci < ci_top; ci++, n--) {
  84                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
  85
  86                 cqe->op_own = op_own;
  87         }
  88
  89         if (unlikely(ci == wq_sz)) {
  90                 op_own = !op_own;
  91                 for (ci = 0; ci < n; ci++) {
  92                         struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
  93
  94                         cqe->op_own = op_own;
  95                 }
  96         }
  97 }
  98
  99 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
 100                                         struct mlx5e_cq *cq, u32 cqcc)
 101 {
 102         cq->title.byte_cnt     = cq->mini_arr[cq->mini_arr_idx].byte_cnt;
 103         cq->title.check_sum    = cq->mini_arr[cq->mini_arr_idx].checksum;
 104         cq->title.op_own      &= 0xf0;
 105         cq->title.op_own      |= 0x01 & (cqcc >> cq->wq.fbc.log_sz);
 106         cq->title.wqe_counter  = cpu_to_be16(cq->decmprs_wqe_counter);
 107
 108         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 109                 cq->decmprs_wqe_counter +=
 110                         mpwrq_get_cqe_consumed_strides(&cq->title);
 111         else
 112                 cq->decmprs_wqe_counter =
 113                         (cq->decmprs_wqe_counter + 1) & rq->wq.sz_m1;
 114 }
 115
 116 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
 117                                                 struct mlx5e_cq *cq, u32 cqcc)
 118 {
 119         mlx5e_decompress_cqe(rq, cq, cqcc);
 120         cq->title.rss_hash_type   = 0;
 121         cq->title.rss_hash_result = 0;
 122 }
 123
 124 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
 125                                              struct mlx5e_cq *cq,
 126                                              int update_owner_only,
 127                                              int budget_rem)
 128 {
 129         u32 cqcc = cq->wq.cc + update_owner_only;
 130         u32 cqe_count;
 131         u32 i;
 132
 133         cqe_count = min_t(u32, cq->decmprs_left, budget_rem);
 134
 135         for (i = update_owner_only; i < cqe_count;
 136              i++, cq->mini_arr_idx++, cqcc++) {
 137                 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
 138                         mlx5e_read_mini_arr_slot(cq, cqcc);
 139
 140                 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc);
 141                 rq->handle_rx_cqe(rq, &cq->title);
 142         }
 143         mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc);
 144         cq->wq.cc = cqcc;
 145         cq->decmprs_left -= cqe_count;
 146         rq->stats.cqe_compress_pkts += cqe_count;
 147
 148         return cqe_count;
 149 }
 150
 151 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
 152                                               struct mlx5e_cq *cq,
 153                                               int budget_rem)
 154 {
 155         mlx5e_read_title_slot(rq, cq, cq->wq.cc);
 156         mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1);
 157         mlx5e_decompress_cqe(rq, cq, cq->wq.cc);
 158         rq->handle_rx_cqe(rq, &cq->title);
 159         cq->mini_arr_idx++;
 160
 161         return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1;
 162 }
 163
 164 #define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT)
 165
 166 static inline bool mlx5e_page_is_reserved(struct page *page)
 167 {
 168         return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id();
 169 }
 170
 171 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
 172                                       struct mlx5e_dma_info *dma_info)
 173 {
 174         struct mlx5e_page_cache *cache = &rq->page_cache;
 175         u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
 176
 177         if (tail_next == cache->head) {
 178                 rq->stats.cache_full++;
 179                 return false;
 180         }
 181
 182         if (unlikely(mlx5e_page_is_reserved(dma_info->page))) {
 183                 rq->stats.cache_waive++;
 184                 return false;
 185         }
 186
 187         cache->page_cache[cache->tail] = *dma_info;
 188         cache->tail = tail_next;
 189         return true;
 190 }
 191
 192 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
 193                                       struct mlx5e_dma_info *dma_info)
 194 {
 195         struct mlx5e_page_cache *cache = &rq->page_cache;
 196
 197         if (unlikely(cache->head == cache->tail)) {
 198                 rq->stats.cache_empty++;
 199                 return false;
 200         }
 201
 202         if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
 203                 rq->stats.cache_busy++;
 204                 return false;
 205         }
 206
 207         *dma_info = cache->page_cache[cache->head];
 208         cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
 209         rq->stats.cache_reuse++;
 210
 211         dma_sync_single_for_device(rq->pdev, dma_info->addr,
 212                                    RQ_PAGE_SIZE(rq),
 213                                    DMA_FROM_DEVICE);
 214         return true;
 215 }
 216
 217 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq,
 218                                           struct mlx5e_dma_info *dma_info)
 219 {
 220         if (mlx5e_rx_cache_get(rq, dma_info))
 221                 return 0;
 222
 223         dma_info->page = dev_alloc_pages(rq->buff.page_order);
 224         if (unlikely(!dma_info->page))
 225                 return -ENOMEM;
 226
 227         dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0,
 228                                       RQ_PAGE_SIZE(rq), rq->buff.map_dir);
 229         if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
 230                 put_page(dma_info->page);
 231                 dma_info->page = NULL;
 232                 return -ENOMEM;
 233         }
 234
 235         return 0;
 236 }
 237
 238 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
 239                         bool recycle)
 240 {
 241         if (likely(recycle) && mlx5e_rx_cache_put(rq, dma_info))
 242                 return;
 243
 244         dma_unmap_page(rq->pdev, dma_info->addr, RQ_PAGE_SIZE(rq),
 245                        rq->buff.map_dir);
 246         put_page(dma_info->page);
 247 }
 248
 249 static inline bool mlx5e_page_reuse(struct mlx5e_rq *rq,
 250                                     struct mlx5e_wqe_frag_info *wi)
 251 {
 252         return rq->wqe.page_reuse && wi->di.page &&
 253                 (wi->offset + rq->wqe.frag_sz <= RQ_PAGE_SIZE(rq)) &&
 254                 !mlx5e_page_is_reserved(wi->di.page);
 255 }
 256
 257 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
 258 {
 259         struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix];
 260
 261         /* check if page exists, hence can be reused */
 262         if (!wi->di.page) {
 263                 if (unlikely(mlx5e_page_alloc_mapped(rq, &wi->di)))
 264                         return -ENOMEM;
 265                 wi->offset = 0;
 266         }
 267
 268         wqe->data.addr = cpu_to_be64(wi->di.addr + wi->offset + rq->buff.headroom);
 269         return 0;
 270 }
 271
 272 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
 273                                      struct mlx5e_wqe_frag_info *wi)
 274 {
 275         mlx5e_page_release(rq, &wi->di, true);
 276         wi->di.page = NULL;
 277 }
 278
 279 static inline void mlx5e_free_rx_wqe_reuse(struct mlx5e_rq *rq,
 280                                            struct mlx5e_wqe_frag_info *wi)
 281 {
 282         if (mlx5e_page_reuse(rq, wi)) {
 283                 rq->stats.page_reuse++;
 284                 return;
 285         }
 286
 287         mlx5e_free_rx_wqe(rq, wi);
 288 }
 289
 290 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
 291 {
 292         struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix];
 293
 294         if (wi->di.page)
 295                 mlx5e_free_rx_wqe(rq, wi);
 296 }
 297
 298 static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq *rq)
 299 {
 300         return rq->mpwqe.num_strides >> MLX5_MPWRQ_WQE_PAGE_ORDER;
 301 }
 302
 303 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq,
 304                                             struct sk_buff *skb,
 305                                             struct mlx5e_mpw_info *wi,
 306                                             u32 page_idx, u32 frag_offset,
 307                                             u32 len)
 308 {
 309         unsigned int truesize = ALIGN(len, BIT(rq->mpwqe.log_stride_sz));
 310
 311         dma_sync_single_for_cpu(rq->pdev,
 312                                 wi->umr.dma_info[page_idx].addr + frag_offset,
 313                                 len, DMA_FROM_DEVICE);
 314         wi->skbs_frags[page_idx]++;
 315         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
 316                         wi->umr.dma_info[page_idx].page, frag_offset,
 317                         len, truesize);
 318 }
 319
 320 static inline void
 321 mlx5e_copy_skb_header_mpwqe(struct device *pdev,
 322                             struct sk_buff *skb,
 323                             struct mlx5e_mpw_info *wi,
 324                             u32 page_idx, u32 offset,
 325                             u32 headlen)
 326 {
 327         u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
 328         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx];
 329         unsigned int len;
 330
 331          /* Aligning len to sizeof(long) optimizes memcpy performance */
 332         len = ALIGN(headlen_pg, sizeof(long));
 333         dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len,
 334                                 DMA_FROM_DEVICE);
 335         skb_copy_to_linear_data_offset(skb, 0,
 336                                        page_address(dma_info->page) + offset,
 337                                        len);
 338         if (unlikely(offset + headlen > PAGE_SIZE)) {
 339                 dma_info++;
 340                 headlen_pg = len;
 341                 len = ALIGN(headlen - headlen_pg, sizeof(long));
 342                 dma_sync_single_for_cpu(pdev, dma_info->addr, len,
 343                                         DMA_FROM_DEVICE);
 344                 skb_copy_to_linear_data_offset(skb, headlen_pg,
 345                                                page_address(dma_info->page),
 346                                                len);
 347         }
 348 }
 349
 350 static inline void mlx5e_post_umr_wqe(struct mlx5e_rq *rq, u16 ix)
 351 {
 352         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 353         struct mlx5e_icosq *sq = &rq->channel->icosq;
 354         struct mlx5_wq_cyc *wq = &sq->wq;
 355         struct mlx5e_umr_wqe *wqe;
 356         u8 num_wqebbs = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_BB);
 357         u16 pi;
 358
 359         /* fill sq edge with nops to avoid wqe wrap around */
 360         while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) {
 361                 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
 362                 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
 363         }
 364
 365         wqe = mlx5_wq_cyc_get_wqe(wq, pi);
 366         memcpy(wqe, &wi->umr.wqe, sizeof(*wqe));
 367         wqe->ctrl.opmod_idx_opcode =
 368                 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
 369                             MLX5_OPCODE_UMR);
 370
 371         sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
 372         sq->pc += num_wqebbs;
 373         mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &wqe->ctrl);
 374 }
 375
 376 static int mlx5e_alloc_rx_umr_mpwqe(struct mlx5e_rq *rq,
 377                                     u16 ix)
 378 {
 379         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 380         int pg_strides = mlx5e_mpwqe_strides_per_page(rq);
 381         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
 382         int err;
 383         int i;
 384
 385         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
 386                 err = mlx5e_page_alloc_mapped(rq, dma_info);
 387                 if (unlikely(err))
 388                         goto err_unmap;
 389                 wi->umr.mtt[i] = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
 390                 page_ref_add(dma_info->page, pg_strides);
 391         }
 392
 393         memset(wi->skbs_frags, 0, sizeof(*wi->skbs_frags) * MLX5_MPWRQ_PAGES_PER_WQE);
 394         wi->consumed_strides = 0;
 395
 396         return 0;
 397
 398 err_unmap:
 399         while (--i >= 0) {
 400                 dma_info--;
 401                 page_ref_sub(dma_info->page, pg_strides);
 402                 mlx5e_page_release(rq, dma_info, true);
 403         }
 404
 405         return err;
 406 }
 407
 408 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi)
 409 {
 410         int pg_strides = mlx5e_mpwqe_strides_per_page(rq);
 411         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
 412         int i;
 413
 414         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
 415                 page_ref_sub(dma_info->page, pg_strides - wi->skbs_frags[i]);
 416                 mlx5e_page_release(rq, dma_info, true);
 417         }
 418 }
 419
 420 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq)
 421 {
 422         struct mlx5_wq_ll *wq = &rq->wq;
 423         struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
 424
 425         rq->mpwqe.umr_in_progress = false;
 426
 427         mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
 428
 429         /* ensure wqes are visible to device before updating doorbell record */
 430         dma_wmb();
 431
 432         mlx5_wq_ll_update_db_record(wq);
 433 }
 434
 435 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 436 {
 437         int err;
 438
 439         err = mlx5e_alloc_rx_umr_mpwqe(rq, ix);
 440         if (unlikely(err)) {
 441                 rq->stats.buff_alloc_err++;
 442                 return err;
 443         }
 444         rq->mpwqe.umr_in_progress = true;
 445         mlx5e_post_umr_wqe(rq, ix);
 446         return 0;
 447 }
 448
 449 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 450 {
 451         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 452
 453         mlx5e_free_rx_mpwqe(rq, wi);
 454 }
 455
 456 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
 457 {
 458         struct mlx5_wq_ll *wq = &rq->wq;
 459         int err;
 460
 461         if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED)))
 462                 return false;
 463
 464         if (mlx5_wq_ll_is_full(wq))
 465                 return false;
 466
 467         do {
 468                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
 469
 470                 err = mlx5e_alloc_rx_wqe(rq, wqe, wq->head);
 471                 if (unlikely(err)) {
 472                         rq->stats.buff_alloc_err++;
 473                         break;
 474                 }
 475
 476                 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
 477         } while (!mlx5_wq_ll_is_full(wq));
 478
 479         /* ensure wqes are visible to device before updating doorbell record */
 480         dma_wmb();
 481
 482         mlx5_wq_ll_update_db_record(wq);
 483
 484         return !!err;
 485 }
 486
 487 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq,
 488                                              struct mlx5e_icosq *sq,
 489                                              struct mlx5e_rq *rq,
 490                                              struct mlx5_cqe64 *cqe)
 491 {
 492         struct mlx5_wq_cyc *wq = &sq->wq;
 493         u16 ci = be16_to_cpu(cqe->wqe_counter) & wq->sz_m1;
 494         struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci];
 495
 496         mlx5_cqwq_pop(&cq->wq);
 497
 498         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) {
 499                 netdev_WARN_ONCE(cq->channel->netdev,
 500                                  "Bad OP in ICOSQ CQE: 0x%x\n", cqe->op_own);
 501                 return;
 502         }
 503
 504         if (likely(icowi->opcode == MLX5_OPCODE_UMR)) {
 505                 mlx5e_post_rx_mpwqe(rq);
 506                 return;
 507         }
 508
 509         if (unlikely(icowi->opcode != MLX5_OPCODE_NOP))
 510                 netdev_WARN_ONCE(cq->channel->netdev,
 511                                  "Bad OPCODE in ICOSQ WQE info: 0x%x\n", icowi->opcode);
 512 }
 513
 514 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq)
 515 {
 516         struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
 517         struct mlx5_cqe64 *cqe;
 518
 519         if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED)))
 520                 return;
 521
 522         cqe = mlx5_cqwq_get_cqe(&cq->wq);
 523         if (likely(!cqe))
 524                 return;
 525
 526         /* by design, there's only a single cqe */
 527         mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe);
 528
 529         mlx5_cqwq_update_db_record(&cq->wq);
 530 }
 531
 532 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
 533 {
 534         struct mlx5_wq_ll *wq = &rq->wq;
 535
 536         if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED)))
 537                 return false;
 538
 539         mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq);
 540
 541         if (mlx5_wq_ll_is_full(wq))
 542                 return false;
 543
 544         if (!rq->mpwqe.umr_in_progress)
 545                 mlx5e_alloc_rx_mpwqe(rq, wq->head);
 546
 547         return true;
 548 }
 549
 550 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
 551                                  u32 cqe_bcnt)
 552 {
 553         struct ethhdr   *eth = (struct ethhdr *)(skb->data);
 554         struct tcphdr   *tcp;
 555         int network_depth = 0;
 556         __be16 proto;
 557         u16 tot_len;
 558         void *ip_p;
 559
 560         u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
 561         u8 tcp_ack = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
 562                 (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
 563
 564         proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
 565
 566         tot_len = cqe_bcnt - network_depth;
 567         ip_p = skb->data + network_depth;
 568
 569         if (proto == htons(ETH_P_IP)) {
 570                 struct iphdr *ipv4 = ip_p;
 571
 572                 tcp = ip_p + sizeof(struct iphdr);
 573                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
 574
 575                 ipv4->ttl               = cqe->lro_min_ttl;
 576                 ipv4->tot_len           = cpu_to_be16(tot_len);
 577                 ipv4->check             = 0;
 578                 ipv4->check             = ip_fast_csum((unsigned char *)ipv4,
 579                                                        ipv4->ihl);
 580         } else {
 581                 struct ipv6hdr *ipv6 = ip_p;
 582
 583                 tcp = ip_p + sizeof(struct ipv6hdr);
 584                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
 585
 586                 ipv6->hop_limit         = cqe->lro_min_ttl;
 587                 ipv6->payload_len       = cpu_to_be16(tot_len -
 588                                                       sizeof(struct ipv6hdr));
 589         }
 590
 591         tcp->psh = get_cqe_lro_tcppsh(cqe);
 592
 593         if (tcp_ack) {
 594                 tcp->ack                = 1;
 595                 tcp->ack_seq            = cqe->lro_ack_seq_num;
 596                 tcp->window             = cqe->lro_tcp_win;
 597         }
 598 }
 599
 600 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
 601                                       struct sk_buff *skb)
 602 {
 603         u8 cht = cqe->rss_hash_type;
 604         int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
 605                  (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
 606                                             PKT_HASH_TYPE_NONE;
 607         skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
 608 }
 609
 610 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth)
 611 {
 612         __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto;
 613
 614         ethertype = __vlan_get_protocol(skb, ethertype, network_depth);
 615         return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6));
 616 }
 617
 618 static inline void mlx5e_handle_csum(struct net_device *netdev,
 619                                      struct mlx5_cqe64 *cqe,
 620                                      struct mlx5e_rq *rq,
 621                                      struct sk_buff *skb,
 622                                      bool   lro)
 623 {
 624         int network_depth = 0;
 625
 626         if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
 627                 goto csum_none;
 628
 629         if (lro) {
 630                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 631                 rq->stats.csum_unnecessary++;
 632                 return;
 633         }
 634
 635         if (likely(is_last_ethertype_ip(skb, &network_depth))) {
 636                 skb->ip_summed = CHECKSUM_COMPLETE;
 637                 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
 638                 if (network_depth > ETH_HLEN)
 639                         /* CQE csum is calculated from the IP header and does
 640                          * not cover VLAN headers (if present). This will add
 641                          * the checksum manually.
 642                          */
 643                         skb->csum = csum_partial(skb->data + ETH_HLEN,
 644                                                  network_depth - ETH_HLEN,
 645                                                  skb->csum);
 646                 rq->stats.csum_complete++;
 647                 return;
 648         }
 649
 650         if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
 651                    (cqe->hds_ip_ext & CQE_L4_OK))) {
 652                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 653                 if (cqe_is_tunneled(cqe)) {
 654                         skb->csum_level = 1;
 655                         skb->encapsulation = 1;
 656                         rq->stats.csum_unnecessary_inner++;
 657                         return;
 658                 }
 659                 rq->stats.csum_unnecessary++;
 660                 return;
 661         }
 662 csum_none:
 663         skb->ip_summed = CHECKSUM_NONE;
 664         rq->stats.csum_none++;
 665 }
 666
 667 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
 668                                       u32 cqe_bcnt,
 669                                       struct mlx5e_rq *rq,
 670                                       struct sk_buff *skb)
 671 {
 672         struct net_device *netdev = rq->netdev;
 673         int lro_num_seg;
 674
 675         skb->mac_len = ETH_HLEN;
 676         lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
 677         if (lro_num_seg > 1) {
 678                 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
 679                 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
 680                 /* Subtract one since we already counted this as one
 681                  * "regular" packet in mlx5e_complete_rx_cqe()
 682                  */
 683                 rq->stats.packets += lro_num_seg - 1;
 684                 rq->stats.lro_packets++;
 685                 rq->stats.lro_bytes += cqe_bcnt;
 686         }
 687
 688         if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp)))
 689                 skb_hwtstamps(skb)->hwtstamp =
 690                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
 691
 692         skb_record_rx_queue(skb, rq->ix);
 693
 694         if (likely(netdev->features & NETIF_F_RXHASH))
 695                 mlx5e_skb_set_hash(cqe, skb);
 696
 697         if (cqe_has_vlan(cqe)) {
 698                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
 699                                        be16_to_cpu(cqe->vlan_info));
 700                 rq->stats.removed_vlan_packets++;
 701         }
 702
 703         skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
 704
 705         mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
 706         skb->protocol = eth_type_trans(skb, netdev);
 707 }
 708
 709 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
 710                                          struct mlx5_cqe64 *cqe,
 711                                          u32 cqe_bcnt,
 712                                          struct sk_buff *skb)
 713 {
 714         rq->stats.packets++;
 715         rq->stats.bytes += cqe_bcnt;
 716         mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
 717 }
 718
 719 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq *sq)
 720 {
 721         struct mlx5_wq_cyc *wq = &sq->wq;
 722         struct mlx5e_tx_wqe *wqe;
 723         u16 pi = (sq->pc - 1) & wq->sz_m1; /* last pi */
 724
 725         wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
 726
 727         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &wqe->ctrl);
 728 }
 729
 730 static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq,
 731                                         struct mlx5e_dma_info *di,
 732                                         const struct xdp_buff *xdp)
 733 {
 734         struct mlx5e_xdpsq       *sq   = &rq->xdpsq;
 735         struct mlx5_wq_cyc       *wq   = &sq->wq;
 736         u16                       pi   = sq->pc & wq->sz_m1;
 737         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
 738
 739         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
 740         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
 741         struct mlx5_wqe_data_seg *dseg;
 742
 743         ptrdiff_t data_offset = xdp->data - xdp->data_hard_start;
 744         dma_addr_t dma_addr  = di->addr + data_offset;
 745         unsigned int dma_len = xdp->data_end - xdp->data;
 746
 747         prefetchw(wqe);
 748
 749         if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE ||
 750                      MLX5E_SW2HW_MTU(rq->channel->priv, rq->netdev->mtu) < dma_len)) {
 751                 rq->stats.xdp_drop++;
 752                 return false;
 753         }
 754
 755         if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1))) {
 756                 if (sq->db.doorbell) {
 757                         /* SQ is full, ring doorbell */
 758                         mlx5e_xmit_xdp_doorbell(sq);
 759                         sq->db.doorbell = false;
 760                 }
 761                 rq->stats.xdp_tx_full++;
 762                 return false;
 763         }
 764
 765         dma_sync_single_for_device(sq->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
 766
 767         cseg->fm_ce_se = 0;
 768
 769         dseg = (struct mlx5_wqe_data_seg *)eseg + 1;
 770
 771         /* copy the inline part if required */
 772         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
 773                 memcpy(eseg->inline_hdr.start, xdp->data, MLX5E_XDP_MIN_INLINE);
 774                 eseg->inline_hdr.sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE);
 775                 dma_len  -= MLX5E_XDP_MIN_INLINE;
 776                 dma_addr += MLX5E_XDP_MIN_INLINE;
 777                 dseg++;
 778         }
 779
 780         /* write the dma part */
 781         dseg->addr       = cpu_to_be64(dma_addr);
 782         dseg->byte_count = cpu_to_be32(dma_len);
 783
 784         cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND);
 785
 786         /* move page to reference to sq responsibility,
 787          * and mark so it's not put back in page-cache.
 788          */
 789         rq->wqe.xdp_xmit = true;
 790         sq->db.di[pi] = *di;
 791         sq->pc++;
 792
 793         sq->db.doorbell = true;
 794
 795         rq->stats.xdp_tx++;
 796         return true;
 797 }
 798
 799 /* returns true if packet was consumed by xdp */
 800 static inline int mlx5e_xdp_handle(struct mlx5e_rq *rq,
 801                                    struct mlx5e_dma_info *di,
 802                                    void *va, u16 *rx_headroom, u32 *len)
 803 {
 804         const struct bpf_prog *prog = READ_ONCE(rq->xdp_prog);
 805         struct xdp_buff xdp;
 806         u32 act;
 807
 808         if (!prog)
 809                 return false;
 810
 811         xdp.data = va + *rx_headroom;
 812         xdp_set_data_meta_invalid(&xdp);
 813         xdp.data_end = xdp.data + *len;
 814         xdp.data_hard_start = va;
 815         xdp.rxq = &rq->xdp_rxq;
 816
 817         act = bpf_prog_run_xdp(prog, &xdp);
 818         switch (act) {
 819         case XDP_PASS:
 820                 *rx_headroom = xdp.data - xdp.data_hard_start;
 821                 *len = xdp.data_end - xdp.data;
 822                 return false;
 823         case XDP_TX:
 824                 if (unlikely(!mlx5e_xmit_xdp_frame(rq, di, &xdp)))
 825                         trace_xdp_exception(rq->netdev, prog, act);
 826                 return true;
 827         default:
 828                 bpf_warn_invalid_xdp_action(act);
 829         case XDP_ABORTED:
 830                 trace_xdp_exception(rq->netdev, prog, act);
 831         case XDP_DROP:
 832                 rq->stats.xdp_drop++;
 833                 return true;
 834         }
 835 }
 836
 837 static inline
 838 struct sk_buff *skb_from_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
 839                              struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
 840 {
 841         struct mlx5e_dma_info *di = &wi->di;
 842         u16 rx_headroom = rq->buff.headroom;
 843         struct sk_buff *skb;
 844         void *va, *data;
 845         bool consumed;
 846         u32 frag_size;
 847
 848         va             = page_address(di->page) + wi->offset;
 849         data           = va + rx_headroom;
 850         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
 851
 852         dma_sync_single_range_for_cpu(rq->pdev,
 853                                       di->addr + wi->offset,
 854                                       0, frag_size,
 855                                       DMA_FROM_DEVICE);
 856         prefetch(data);
 857         wi->offset += frag_size;
 858
 859         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
 860                 rq->stats.wqe_err++;
 861                 return NULL;
 862         }
 863
 864         rcu_read_lock();
 865         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt);
 866         rcu_read_unlock();
 867         if (consumed)
 868                 return NULL; /* page/packet was consumed by XDP */
 869
 870         skb = build_skb(va, frag_size);
 871         if (unlikely(!skb)) {
 872                 rq->stats.buff_alloc_err++;
 873                 return NULL;
 874         }
 875
 876         /* queue up for recycling/reuse */
 877         page_ref_inc(di->page);
 878
 879         skb_reserve(skb, rx_headroom);
 880         skb_put(skb, cqe_bcnt);
 881
 882         return skb;
 883 }
 884
 885 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
 886 {
 887         struct mlx5e_wqe_frag_info *wi;
 888         struct mlx5e_rx_wqe *wqe;
 889         __be16 wqe_counter_be;
 890         struct sk_buff *skb;
 891         u16 wqe_counter;
 892         u32 cqe_bcnt;
 893
 894         wqe_counter_be = cqe->wqe_counter;
 895         wqe_counter    = be16_to_cpu(wqe_counter_be);
 896         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
 897         wi             = &rq->wqe.frag_info[wqe_counter];
 898         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
 899
 900         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
 901         if (!skb) {
 902                 /* probably for XDP */
 903                 if (rq->wqe.xdp_xmit) {
 904                         wi->di.page = NULL;
 905                         rq->wqe.xdp_xmit = false;
 906                         /* do not return page to cache, it will be returned on XDP_TX completion */
 907                         goto wq_ll_pop;
 908                 }
 909                 /* probably an XDP_DROP, save the page-reuse checks */
 910                 mlx5e_free_rx_wqe(rq, wi);
 911                 goto wq_ll_pop;
 912         }
 913
 914         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
 915         napi_gro_receive(rq->cq.napi, skb);
 916
 917         mlx5e_free_rx_wqe_reuse(rq, wi);
 918 wq_ll_pop:
 919         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
 920                        &wqe->next.next_wqe_index);
 921 }
 922
 923 #ifdef CONFIG_MLX5_ESWITCH
 924 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
 925 {
 926         struct net_device *netdev = rq->netdev;
 927         struct mlx5e_priv *priv = netdev_priv(netdev);
 928         struct mlx5e_rep_priv *rpriv  = priv->ppriv;
 929         struct mlx5_eswitch_rep *rep = rpriv->rep;
 930         struct mlx5e_wqe_frag_info *wi;
 931         struct mlx5e_rx_wqe *wqe;
 932         struct sk_buff *skb;
 933         __be16 wqe_counter_be;
 934         u16 wqe_counter;
 935         u32 cqe_bcnt;
 936
 937         wqe_counter_be = cqe->wqe_counter;
 938         wqe_counter    = be16_to_cpu(wqe_counter_be);
 939         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
 940         wi             = &rq->wqe.frag_info[wqe_counter];
 941         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
 942
 943         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
 944         if (!skb) {
 945                 if (rq->wqe.xdp_xmit) {
 946                         wi->di.page = NULL;
 947                         rq->wqe.xdp_xmit = false;
 948                         /* do not return page to cache, it will be returned on XDP_TX completion */
 949                         goto wq_ll_pop;
 950                 }
 951                 /* probably an XDP_DROP, save the page-reuse checks */
 952                 mlx5e_free_rx_wqe(rq, wi);
 953                 goto wq_ll_pop;
 954         }
 955
 956         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
 957
 958         if (rep->vlan && skb_vlan_tag_present(skb))
 959                 skb_vlan_pop(skb);
 960
 961         napi_gro_receive(rq->cq.napi, skb);
 962
 963         mlx5e_free_rx_wqe_reuse(rq, wi);
 964 wq_ll_pop:
 965         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
 966                        &wqe->next.next_wqe_index);
 967 }
 968 #endif
 969
 970 static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq,
 971                                            struct mlx5_cqe64 *cqe,
 972                                            struct mlx5e_mpw_info *wi,
 973                                            u32 cqe_bcnt,
 974                                            struct sk_buff *skb)
 975 {
 976         u16 stride_ix      = mpwrq_get_cqe_stride_index(cqe);
 977         u32 wqe_offset     = stride_ix << rq->mpwqe.log_stride_sz;
 978         u32 head_offset    = wqe_offset & (PAGE_SIZE - 1);
 979         u32 page_idx       = wqe_offset >> PAGE_SHIFT;
 980         u32 head_page_idx  = page_idx;
 981         u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt);
 982         u32 frag_offset    = head_offset + headlen;
 983         u16 byte_cnt       = cqe_bcnt - headlen;
 984
 985         if (unlikely(frag_offset >= PAGE_SIZE)) {
 986                 page_idx++;
 987                 frag_offset -= PAGE_SIZE;
 988         }
 989
 990         while (byte_cnt) {
 991                 u32 pg_consumed_bytes =
 992                         min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
 993
 994                 mlx5e_add_skb_frag_mpwqe(rq, skb, wi, page_idx, frag_offset,
 995                                          pg_consumed_bytes);
 996                 byte_cnt -= pg_consumed_bytes;
 997                 frag_offset = 0;
 998                 page_idx++;
 999         }
1000         /* copy header */
1001         mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, wi, head_page_idx,
1002                                     head_offset, headlen);
1003         /* skb linear part was allocated with headlen and aligned to long */
1004         skb->tail += headlen;
1005         skb->len  += headlen;
1006 }
1007
1008 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1009 {
1010         u16 cstrides       = mpwrq_get_cqe_consumed_strides(cqe);
1011         u16 wqe_id         = be16_to_cpu(cqe->wqe_id);
1012         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1013         struct mlx5e_rx_wqe  *wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id);
1014         struct sk_buff *skb;
1015         u16 cqe_bcnt;
1016
1017         wi->consumed_strides += cstrides;
1018
1019         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1020                 rq->stats.wqe_err++;
1021                 goto mpwrq_cqe_out;
1022         }
1023
1024         if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1025                 rq->stats.mpwqe_filler++;
1026                 goto mpwrq_cqe_out;
1027         }
1028
1029         skb = napi_alloc_skb(rq->cq.napi,
1030                              ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD,
1031                                    sizeof(long)));
1032         if (unlikely(!skb)) {
1033                 rq->stats.buff_alloc_err++;
1034                 goto mpwrq_cqe_out;
1035         }
1036
1037         prefetchw(skb->data);
1038         cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1039
1040         mlx5e_mpwqe_fill_rx_skb(rq, cqe, wi, cqe_bcnt, skb);
1041         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1042         napi_gro_receive(rq->cq.napi, skb);
1043
1044 mpwrq_cqe_out:
1045         if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1046                 return;
1047
1048         mlx5e_free_rx_mpwqe(rq, wi);
1049         mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1050 }
1051
1052 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1053 {
1054         struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1055         struct mlx5e_xdpsq *xdpsq;
1056         struct mlx5_cqe64 *cqe;
1057         int work_done = 0;
1058
1059         if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED)))
1060                 return 0;
1061
1062         if (cq->decmprs_left)
1063                 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
1064
1065         cqe = mlx5_cqwq_get_cqe(&cq->wq);
1066         if (!cqe)
1067                 return 0;
1068
1069         xdpsq = &rq->xdpsq;
1070
1071         do {
1072                 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1073                         work_done +=
1074                                 mlx5e_decompress_cqes_start(rq, cq,
1075                                                             budget - work_done);
1076                         continue;
1077                 }
1078
1079                 mlx5_cqwq_pop(&cq->wq);
1080
1081                 rq->handle_rx_cqe(rq, cqe);
1082         } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1083
1084         if (xdpsq->db.doorbell) {
1085                 mlx5e_xmit_xdp_doorbell(xdpsq);
1086                 xdpsq->db.doorbell = false;
1087         }
1088
1089         mlx5_cqwq_update_db_record(&cq->wq);
1090
1091         /* ensure cq space is freed before enabling more cqes */
1092         wmb();
1093
1094         return work_done;
1095 }
1096
1097 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq)
1098 {
1099         struct mlx5e_xdpsq *sq;
1100         struct mlx5_cqe64 *cqe;
1101         struct mlx5e_rq *rq;
1102         u16 sqcc;
1103         int i;
1104
1105         sq = container_of(cq, struct mlx5e_xdpsq, cq);
1106
1107         if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED)))
1108                 return false;
1109
1110         cqe = mlx5_cqwq_get_cqe(&cq->wq);
1111         if (!cqe)
1112                 return false;
1113
1114         rq = container_of(sq, struct mlx5e_rq, xdpsq);
1115
1116         /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
1117          * otherwise a cq overrun may occur
1118          */
1119         sqcc = sq->cc;
1120
1121         i = 0;
1122         do {
1123                 u16 wqe_counter;
1124                 bool last_wqe;
1125
1126                 mlx5_cqwq_pop(&cq->wq);
1127
1128                 wqe_counter = be16_to_cpu(cqe->wqe_counter);
1129
1130                 do {
1131                         struct mlx5e_dma_info *di;
1132                         u16 ci;
1133
1134                         last_wqe = (sqcc == wqe_counter);
1135
1136                         ci = sqcc & sq->wq.sz_m1;
1137                         di = &sq->db.di[ci];
1138
1139                         sqcc++;
1140                         /* Recycle RX page */
1141                         mlx5e_page_release(rq, di, true);
1142                 } while (!last_wqe);
1143         } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1144
1145         mlx5_cqwq_update_db_record(&cq->wq);
1146
1147         /* ensure cq space is freed before enabling more cqes */
1148         wmb();
1149
1150         sq->cc = sqcc;
1151         return (i == MLX5E_TX_CQ_POLL_BUDGET);
1152 }
1153
1154 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq)
1155 {
1156         struct mlx5e_rq *rq = container_of(sq, struct mlx5e_rq, xdpsq);
1157         struct mlx5e_dma_info *di;
1158         u16 ci;
1159
1160         while (sq->cc != sq->pc) {
1161                 ci = sq->cc & sq->wq.sz_m1;
1162                 di = &sq->db.di[ci];
1163                 sq->cc++;
1164
1165                 mlx5e_page_release(rq, di, false);
1166         }
1167 }
1168
1169 #ifdef CONFIG_MLX5_CORE_IPOIB
1170
1171 #define MLX5_IB_GRH_DGID_OFFSET 24
1172 #define MLX5_GID_SIZE           16
1173
1174 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1175                                          struct mlx5_cqe64 *cqe,
1176                                          u32 cqe_bcnt,
1177                                          struct sk_buff *skb)
1178 {
1179         struct hwtstamp_config *tstamp;
1180         struct net_device *netdev;
1181         struct mlx5e_priv *priv;
1182         char *pseudo_header;
1183         u32 qpn;
1184         u8 *dgid;
1185         u8 g;
1186
1187         qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff;
1188         netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn);
1189
1190         /* No mapping present, cannot process SKB. This might happen if a child
1191          * interface is going down while having unprocessed CQEs on parent RQ
1192          */
1193         if (unlikely(!netdev)) {
1194                 /* TODO: add drop counters support */
1195                 skb->dev = NULL;
1196                 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn);
1197                 return;
1198         }
1199
1200         priv = mlx5i_epriv(netdev);
1201         tstamp = &priv->tstamp;
1202
1203         g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
1204         dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1205         if ((!g) || dgid[0] != 0xff)
1206                 skb->pkt_type = PACKET_HOST;
1207         else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1208                 skb->pkt_type = PACKET_BROADCAST;
1209         else
1210                 skb->pkt_type = PACKET_MULTICAST;
1211
1212         /* TODO: IB/ipoib: Allow mcast packets from other VFs
1213          * 68996a6e760e5c74654723eeb57bf65628ae87f4
1214          */
1215
1216         skb_pull(skb, MLX5_IB_GRH_BYTES);
1217
1218         skb->protocol = *((__be16 *)(skb->data));
1219
1220         skb->ip_summed = CHECKSUM_COMPLETE;
1221         skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1222
1223         if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1224                 skb_hwtstamps(skb)->hwtstamp =
1225                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1226
1227         skb_record_rx_queue(skb, rq->ix);
1228
1229         if (likely(netdev->features & NETIF_F_RXHASH))
1230                 mlx5e_skb_set_hash(cqe, skb);
1231
1232         /* 20 bytes of ipoib header and 4 for encap existing */
1233         pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1234         memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1235         skb_reset_mac_header(skb);
1236         skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1237
1238         skb->dev = netdev;
1239
1240         rq->stats.csum_complete++;
1241         rq->stats.packets++;
1242         rq->stats.bytes += cqe_bcnt;
1243 }
1244
1245 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1246 {
1247         struct mlx5e_wqe_frag_info *wi;
1248         struct mlx5e_rx_wqe *wqe;
1249         __be16 wqe_counter_be;
1250         struct sk_buff *skb;
1251         u16 wqe_counter;
1252         u32 cqe_bcnt;
1253
1254         wqe_counter_be = cqe->wqe_counter;
1255         wqe_counter    = be16_to_cpu(wqe_counter_be);
1256         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
1257         wi             = &rq->wqe.frag_info[wqe_counter];
1258         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
1259
1260         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1261         if (!skb)
1262                 goto wq_free_wqe;
1263
1264         mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1265         if (unlikely(!skb->dev)) {
1266                 dev_kfree_skb_any(skb);
1267                 goto wq_free_wqe;
1268         }
1269         napi_gro_receive(rq->cq.napi, skb);
1270
1271 wq_free_wqe:
1272         mlx5e_free_rx_wqe_reuse(rq, wi);
1273         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
1274                        &wqe->next.next_wqe_index);
1275 }
1276
1277 #endif /* CONFIG_MLX5_CORE_IPOIB */
1278
1279 #ifdef CONFIG_MLX5_EN_IPSEC
1280
1281 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1282 {
1283         struct mlx5e_wqe_frag_info *wi;
1284         struct mlx5e_rx_wqe *wqe;
1285         __be16 wqe_counter_be;
1286         struct sk_buff *skb;
1287         u16 wqe_counter;
1288         u32 cqe_bcnt;
1289
1290         wqe_counter_be = cqe->wqe_counter;
1291         wqe_counter    = be16_to_cpu(wqe_counter_be);
1292         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
1293         wi             = &rq->wqe.frag_info[wqe_counter];
1294         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
1295
1296         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1297         if (unlikely(!skb)) {
1298                 /* a DROP, save the page-reuse checks */
1299                 mlx5e_free_rx_wqe(rq, wi);
1300                 goto wq_ll_pop;
1301         }
1302         skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb);
1303         if (unlikely(!skb)) {
1304                 mlx5e_free_rx_wqe(rq, wi);
1305                 goto wq_ll_pop;
1306         }
1307
1308         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1309         napi_gro_receive(rq->cq.napi, skb);
1310
1311         mlx5e_free_rx_wqe_reuse(rq, wi);
1312 wq_ll_pop:
1313         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
1314                        &wqe->next.next_wqe_index);
1315 }
1316
1317 #endif /* CONFIG_MLX5_EN_IPSEC */