drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <net/geneve.h>
  38 #include <linux/bpf.h>
  39 #include <linux/if_bridge.h>
  40 #include <net/page_pool.h>
  41 #include "eswitch.h"
  42 #include "en.h"
  43 #include "en_tc.h"
  44 #include "en_rep.h"
  45 #include "en_accel/ipsec.h"
  46 #include "en_accel/ipsec_rxtx.h"
  47 #include "en_accel/en_accel.h"
  48 #include "en_accel/tls.h"
  49 #include "accel/ipsec.h"
  50 #include "accel/tls.h"
  51 #include "lib/vxlan.h"
  52 #include "lib/clock.h"
  53 #include "en/port.h"
  54 #include "en/xdp.h"
  55 #include "lib/eq.h"
  56 #include "en/monitor_stats.h"
  57 #include "en/reporter.h"
  58 #include "en/params.h"
  59
  60 struct mlx5e_rq_param {
  61         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  62         struct mlx5_wq_param    wq;
  63         struct mlx5e_rq_frags_info frags_info;
  64 };
  65
  66 struct mlx5e_sq_param {
  67         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  68         struct mlx5_wq_param       wq;
  69         bool                       is_mpw;
  70 };
  71
  72 struct mlx5e_cq_param {
  73         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  74         struct mlx5_wq_param       wq;
  75         u16                        eq_ix;
  76         u8                         cq_period_mode;
  77 };
  78
  79 struct mlx5e_channel_param {
  80         struct mlx5e_rq_param      rq;
  81         struct mlx5e_sq_param      sq;
  82         struct mlx5e_sq_param      xdp_sq;
  83         struct mlx5e_sq_param      icosq;
  84         struct mlx5e_cq_param      rx_cq;
  85         struct mlx5e_cq_param      tx_cq;
  86         struct mlx5e_cq_param      icosq_cq;
  87 };
  88
  89 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  90 {
  91         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  92                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  93                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  94         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  95         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  96
  97         if (!striding_rq_umr)
  98                 return false;
  99         if (!inline_umr) {
 100                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
 101                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
 102                 return false;
 103         }
 104         return true;
 105 }
 106
 107 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
 108                                struct mlx5e_params *params)
 109 {
 110         params->log_rq_mtu_frames = is_kdump_kernel() ?
 111                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
 112                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
 113
 114         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
 115                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
 116                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
 117                        BIT(mlx5e_mpwqe_get_log_rq_size(params)) :
 118                        BIT(params->log_rq_mtu_frames),
 119                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)),
 120                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 121 }
 122
 123 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
 124                                 struct mlx5e_params *params)
 125 {
 126         return mlx5e_check_fragmented_striding_rq_cap(mdev) &&
 127                 !MLX5_IPSEC_DEV(mdev) &&
 128                 !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params));
 129 }
 130
 131 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
 132 {
 133         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
 134                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
 135                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 136                 MLX5_WQ_TYPE_CYCLIC;
 137 }
 138
 139 void mlx5e_update_carrier(struct mlx5e_priv *priv)
 140 {
 141         struct mlx5_core_dev *mdev = priv->mdev;
 142         u8 port_state;
 143
 144         port_state = mlx5_query_vport_state(mdev,
 145                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
 146                                             0);
 147
 148         if (port_state == VPORT_STATE_UP) {
 149                 netdev_info(priv->netdev, "Link up\n");
 150                 netif_carrier_on(priv->netdev);
 151         } else {
 152                 netdev_info(priv->netdev, "Link down\n");
 153                 netif_carrier_off(priv->netdev);
 154         }
 155 }
 156
 157 static void mlx5e_update_carrier_work(struct work_struct *work)
 158 {
 159         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 160                                                update_carrier_work);
 161
 162         mutex_lock(&priv->state_lock);
 163         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 164                 if (priv->profile->update_carrier)
 165                         priv->profile->update_carrier(priv);
 166         mutex_unlock(&priv->state_lock);
 167 }
 168
 169 void mlx5e_update_stats(struct mlx5e_priv *priv)
 170 {
 171         int i;
 172
 173         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 174                 if (mlx5e_stats_grps[i].update_stats)
 175                         mlx5e_stats_grps[i].update_stats(priv);
 176 }
 177
 178 void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
 179 {
 180         int i;
 181
 182         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 183                 if (mlx5e_stats_grps[i].update_stats_mask &
 184                     MLX5E_NDO_UPDATE_STATS)
 185                         mlx5e_stats_grps[i].update_stats(priv);
 186 }
 187
 188 static void mlx5e_update_stats_work(struct work_struct *work)
 189 {
 190         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 191                                                update_stats_work);
 192
 193         mutex_lock(&priv->state_lock);
 194         priv->profile->update_stats(priv);
 195         mutex_unlock(&priv->state_lock);
 196 }
 197
 198 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
 199 {
 200         if (!priv->profile->update_stats)
 201                 return;
 202
 203         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
 204                 return;
 205
 206         queue_work(priv->wq, &priv->update_stats_work);
 207 }
 208
 209 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
 210 {
 211         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
 212         struct mlx5_eqe   *eqe = data;
 213
 214         if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
 215                 return NOTIFY_DONE;
 216
 217         switch (eqe->sub_type) {
 218         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 219         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 220                 queue_work(priv->wq, &priv->update_carrier_work);
 221                 break;
 222         default:
 223                 return NOTIFY_DONE;
 224         }
 225
 226         return NOTIFY_OK;
 227 }
 228
 229 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 230 {
 231         priv->events_nb.notifier_call = async_event;
 232         mlx5_notifier_register(priv->mdev, &priv->events_nb);
 233 }
 234
 235 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 236 {
 237         mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
 238 }
 239
 240 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 241                                        struct mlx5e_icosq *sq,
 242                                        struct mlx5e_umr_wqe *wqe)
 243 {
 244         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 245         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 246         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 247
 248         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 249                                       ds_cnt);
 250         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 251         cseg->imm       = rq->mkey_be;
 252
 253         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 254         ucseg->xlt_octowords =
 255                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 256         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 257 }
 258
 259 static u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq)
 260 {
 261         switch (rq->wq_type) {
 262         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 263                 return mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 264         default:
 265                 return mlx5_wq_cyc_get_size(&rq->wqe.wq);
 266         }
 267 }
 268
 269 static u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq)
 270 {
 271         switch (rq->wq_type) {
 272         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 273                 return rq->mpwqe.wq.cur_sz;
 274         default:
 275                 return rq->wqe.wq.cur_sz;
 276         }
 277 }
 278
 279 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 280                                      struct mlx5e_channel *c)
 281 {
 282         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 283
 284         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 285                                                   sizeof(*rq->mpwqe.info)),
 286                                        GFP_KERNEL, cpu_to_node(c->cpu));
 287         if (!rq->mpwqe.info)
 288                 return -ENOMEM;
 289
 290         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
 291
 292         return 0;
 293 }
 294
 295 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 296                                  u64 npages, u8 page_shift,
 297                                  struct mlx5_core_mkey *umr_mkey)
 298 {
 299         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 300         void *mkc;
 301         u32 *in;
 302         int err;
 303
 304         in = kvzalloc(inlen, GFP_KERNEL);
 305         if (!in)
 306                 return -ENOMEM;
 307
 308         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 309
 310         MLX5_SET(mkc, mkc, free, 1);
 311         MLX5_SET(mkc, mkc, umr_en, 1);
 312         MLX5_SET(mkc, mkc, lw, 1);
 313         MLX5_SET(mkc, mkc, lr, 1);
 314         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 315
 316         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 317         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 318         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 319         MLX5_SET(mkc, mkc, translations_octword_size,
 320                  MLX5_MTT_OCTW(npages));
 321         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 322
 323         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 324
 325         kvfree(in);
 326         return err;
 327 }
 328
 329 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 330 {
 331         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 332
 333         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 334 }
 335
 336 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 337 {
 338         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
 339 }
 340
 341 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 342 {
 343         struct mlx5e_wqe_frag_info next_frag, *prev;
 344         int i;
 345
 346         next_frag.di = &rq->wqe.di[0];
 347         next_frag.offset = 0;
 348         prev = NULL;
 349
 350         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 351                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 352                 struct mlx5e_wqe_frag_info *frag =
 353                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 354                 int f;
 355
 356                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 357                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 358                                 next_frag.di++;
 359                                 next_frag.offset = 0;
 360                                 if (prev)
 361                                         prev->last_in_page = true;
 362                         }
 363                         *frag = next_frag;
 364
 365                         /* prepare next */
 366                         next_frag.offset += frag_info[f].frag_stride;
 367                         prev = frag;
 368                 }
 369         }
 370
 371         if (prev)
 372                 prev->last_in_page = true;
 373 }
 374
 375 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
 376                               int wq_sz, int cpu)
 377 {
 378         int len = wq_sz << rq->wqe.info.log_num_frags;
 379
 380         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
 381                                    GFP_KERNEL, cpu_to_node(cpu));
 382         if (!rq->wqe.di)
 383                 return -ENOMEM;
 384
 385         mlx5e_init_frags_partition(rq);
 386
 387         return 0;
 388 }
 389
 390 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
 391 {
 392         kvfree(rq->wqe.di);
 393 }
 394
 395 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 396                           struct mlx5e_params *params,
 397                           struct mlx5e_rq_param *rqp,
 398                           struct mlx5e_rq *rq)
 399 {
 400         struct page_pool_params pp_params = { 0 };
 401         struct mlx5_core_dev *mdev = c->mdev;
 402         void *rqc = rqp->rqc;
 403         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 404         u32 pool_size;
 405         int wq_sz;
 406         int err;
 407         int i;
 408
 409         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
 410
 411         rq->wq_type = params->rq_wq_type;
 412         rq->pdev    = c->pdev;
 413         rq->netdev  = c->netdev;
 414         rq->tstamp  = c->tstamp;
 415         rq->clock   = &mdev->clock;
 416         rq->channel = c;
 417         rq->ix      = c->ix;
 418         rq->mdev    = mdev;
 419         rq->hw_mtu  = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 420         rq->stats   = &c->priv->channel_stats[c->ix].rq;
 421
 422         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
 423         if (IS_ERR(rq->xdp_prog)) {
 424                 err = PTR_ERR(rq->xdp_prog);
 425                 rq->xdp_prog = NULL;
 426                 goto err_rq_wq_destroy;
 427         }
 428
 429         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
 430         if (err < 0)
 431                 goto err_rq_wq_destroy;
 432
 433         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 434         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params);
 435         pool_size = 1 << params->log_rq_mtu_frames;
 436
 437         switch (rq->wq_type) {
 438         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 439                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 440                                         &rq->wq_ctrl);
 441                 if (err)
 442                         return err;
 443
 444                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 445
 446                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 447
 448                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE << mlx5e_mpwqe_get_log_rq_size(params);
 449
 450                 rq->post_wqes = mlx5e_post_rx_mpwqes;
 451                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 452
 453                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
 454 #ifdef CONFIG_MLX5_EN_IPSEC
 455                 if (MLX5_IPSEC_DEV(mdev)) {
 456                         err = -EINVAL;
 457                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
 458                         goto err_rq_wq_destroy;
 459                 }
 460 #endif
 461                 if (!rq->handle_rx_cqe) {
 462                         err = -EINVAL;
 463                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
 464                         goto err_rq_wq_destroy;
 465                 }
 466
 467                 rq->mpwqe.skb_from_cqe_mpwrq =
 468                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ?
 469                         mlx5e_skb_from_cqe_mpwrq_linear :
 470                         mlx5e_skb_from_cqe_mpwrq_nonlinear;
 471                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params);
 472                 rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params));
 473
 474                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 475                 if (err)
 476                         goto err_rq_wq_destroy;
 477                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 478
 479                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 480                 if (err)
 481                         goto err_free;
 482                 break;
 483         default: /* MLX5_WQ_TYPE_CYCLIC */
 484                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 485                                          &rq->wq_ctrl);
 486                 if (err)
 487                         return err;
 488
 489                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 490
 491                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 492
 493                 rq->wqe.info = rqp->frags_info;
 494                 rq->wqe.frags =
 495                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 496                                         (wq_sz << rq->wqe.info.log_num_frags)),
 497                                       GFP_KERNEL, cpu_to_node(c->cpu));
 498                 if (!rq->wqe.frags) {
 499                         err = -ENOMEM;
 500                         goto err_free;
 501                 }
 502
 503                 err = mlx5e_init_di_list(rq, wq_sz, c->cpu);
 504                 if (err)
 505                         goto err_free;
 506                 rq->post_wqes = mlx5e_post_rx_wqes;
 507                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 508
 509 #ifdef CONFIG_MLX5_EN_IPSEC
 510                 if (c->priv->ipsec)
 511                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
 512                 else
 513 #endif
 514                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
 515                 if (!rq->handle_rx_cqe) {
 516                         err = -EINVAL;
 517                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
 518                         goto err_free;
 519                 }
 520
 521                 rq->wqe.skb_from_cqe = mlx5e_rx_is_linear_skb(params) ?
 522                         mlx5e_skb_from_cqe_linear :
 523                         mlx5e_skb_from_cqe_nonlinear;
 524                 rq->mkey_be = c->mkey_be;
 525         }
 526
 527         /* Create a page_pool and register it with rxq */
 528         pp_params.order     = 0;
 529         pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 530         pp_params.pool_size = pool_size;
 531         pp_params.nid       = cpu_to_node(c->cpu);
 532         pp_params.dev       = c->pdev;
 533         pp_params.dma_dir   = rq->buff.map_dir;
 534
 535         /* page_pool can be used even when there is no rq->xdp_prog,
 536          * given page_pool does not handle DMA mapping there is no
 537          * required state to clear. And page_pool gracefully handle
 538          * elevated refcnt.
 539          */
 540         rq->page_pool = page_pool_create(&pp_params);
 541         if (IS_ERR(rq->page_pool)) {
 542                 err = PTR_ERR(rq->page_pool);
 543                 rq->page_pool = NULL;
 544                 goto err_free;
 545         }
 546         err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 547                                          MEM_TYPE_PAGE_POOL, rq->page_pool);
 548         if (err) {
 549                 page_pool_free(rq->page_pool);
 550                 goto err_free;
 551         }
 552
 553         for (i = 0; i < wq_sz; i++) {
 554                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 555                         struct mlx5e_rx_wqe_ll *wqe =
 556                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 557                         u32 byte_count =
 558                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 559                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
 560
 561                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 562                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 563                         wqe->data[0].lkey = rq->mkey_be;
 564                 } else {
 565                         struct mlx5e_rx_wqe_cyc *wqe =
 566                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 567                         int f;
 568
 569                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 570                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 571                                         MLX5_HW_START_PADDING;
 572
 573                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 574                                 wqe->data[f].lkey = rq->mkey_be;
 575                         }
 576                         /* check if num_frags is not a pow of two */
 577                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 578                                 wqe->data[f].byte_count = 0;
 579                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 580                                 wqe->data[f].addr = 0;
 581                         }
 582                 }
 583         }
 584
 585         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 586
 587         switch (params->rx_cq_moderation.cq_period_mode) {
 588         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 589                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 590                 break;
 591         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 592         default:
 593                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 594         }
 595
 596         rq->page_cache.head = 0;
 597         rq->page_cache.tail = 0;
 598
 599         return 0;
 600
 601 err_free:
 602         switch (rq->wq_type) {
 603         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 604                 kvfree(rq->mpwqe.info);
 605                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 606                 break;
 607         default: /* MLX5_WQ_TYPE_CYCLIC */
 608                 kvfree(rq->wqe.frags);
 609                 mlx5e_free_di_list(rq);
 610         }
 611
 612 err_rq_wq_destroy:
 613         if (rq->xdp_prog)
 614                 bpf_prog_put(rq->xdp_prog);
 615         xdp_rxq_info_unreg(&rq->xdp_rxq);
 616         mlx5_wq_destroy(&rq->wq_ctrl);
 617
 618         return err;
 619 }
 620
 621 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 622 {
 623         int i;
 624
 625         if (rq->xdp_prog)
 626                 bpf_prog_put(rq->xdp_prog);
 627
 628         switch (rq->wq_type) {
 629         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 630                 kvfree(rq->mpwqe.info);
 631                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 632                 break;
 633         default: /* MLX5_WQ_TYPE_CYCLIC */
 634                 kvfree(rq->wqe.frags);
 635                 mlx5e_free_di_list(rq);
 636         }
 637
 638         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 639              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 640                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 641
 642                 mlx5e_page_release(rq, dma_info, false);
 643         }
 644
 645         xdp_rxq_info_unreg(&rq->xdp_rxq);
 646         mlx5_wq_destroy(&rq->wq_ctrl);
 647 }
 648
 649 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 650                            struct mlx5e_rq_param *param)
 651 {
 652         struct mlx5_core_dev *mdev = rq->mdev;
 653
 654         void *in;
 655         void *rqc;
 656         void *wq;
 657         int inlen;
 658         int err;
 659
 660         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 661                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 662         in = kvzalloc(inlen, GFP_KERNEL);
 663         if (!in)
 664                 return -ENOMEM;
 665
 666         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 667         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 668
 669         memcpy(rqc, param->rqc, sizeof(param->rqc));
 670
 671         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 672         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 673         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 674                                                 MLX5_ADAPTER_PAGE_SHIFT);
 675         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 676
 677         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 678                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 679
 680         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 681
 682         kvfree(in);
 683
 684         return err;
 685 }
 686
 687 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 688                                  int next_state)
 689 {
 690         struct mlx5_core_dev *mdev = rq->mdev;
 691
 692         void *in;
 693         void *rqc;
 694         int inlen;
 695         int err;
 696
 697         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 698         in = kvzalloc(inlen, GFP_KERNEL);
 699         if (!in)
 700                 return -ENOMEM;
 701
 702         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 703
 704         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 705         MLX5_SET(rqc, rqc, state, next_state);
 706
 707         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 708
 709         kvfree(in);
 710
 711         return err;
 712 }
 713
 714 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 715 {
 716         struct mlx5e_channel *c = rq->channel;
 717         struct mlx5e_priv *priv = c->priv;
 718         struct mlx5_core_dev *mdev = priv->mdev;
 719
 720         void *in;
 721         void *rqc;
 722         int inlen;
 723         int err;
 724
 725         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 726         in = kvzalloc(inlen, GFP_KERNEL);
 727         if (!in)
 728                 return -ENOMEM;
 729
 730         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 731
 732         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 733         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 734                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 735         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 736         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 737
 738         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 739
 740         kvfree(in);
 741
 742         return err;
 743 }
 744
 745 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 746 {
 747         struct mlx5e_channel *c = rq->channel;
 748         struct mlx5_core_dev *mdev = c->mdev;
 749         void *in;
 750         void *rqc;
 751         int inlen;
 752         int err;
 753
 754         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 755         in = kvzalloc(inlen, GFP_KERNEL);
 756         if (!in)
 757                 return -ENOMEM;
 758
 759         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 760
 761         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 762         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 763                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 764         MLX5_SET(rqc, rqc, vsd, vsd);
 765         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 766
 767         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 768
 769         kvfree(in);
 770
 771         return err;
 772 }
 773
 774 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 775 {
 776         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 777 }
 778
 779 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 780 {
 781         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 782         struct mlx5e_channel *c = rq->channel;
 783
 784         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 785
 786         do {
 787                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 788                         return 0;
 789
 790                 msleep(20);
 791         } while (time_before(jiffies, exp_time));
 792
 793         netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 794                     c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 795
 796         return -ETIMEDOUT;
 797 }
 798
 799 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 800 {
 801         __be16 wqe_ix_be;
 802         u16 wqe_ix;
 803
 804         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 805                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 806                 u16 head = wq->head;
 807                 int i;
 808
 809                 /* Outstanding UMR WQEs (in progress) start at wq->head */
 810                 for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
 811                         rq->dealloc_wqe(rq, head);
 812                         head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
 813                 }
 814
 815                 while (!mlx5_wq_ll_is_empty(wq)) {
 816                         struct mlx5e_rx_wqe_ll *wqe;
 817
 818                         wqe_ix_be = *wq->tail_next;
 819                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 820                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 821                         rq->dealloc_wqe(rq, wqe_ix);
 822                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 823                                        &wqe->next.next_wqe_index);
 824                 }
 825         } else {
 826                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 827
 828                 while (!mlx5_wq_cyc_is_empty(wq)) {
 829                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
 830                         rq->dealloc_wqe(rq, wqe_ix);
 831                         mlx5_wq_cyc_pop(wq);
 832                 }
 833         }
 834
 835 }
 836
 837 static int mlx5e_open_rq(struct mlx5e_channel *c,
 838                          struct mlx5e_params *params,
 839                          struct mlx5e_rq_param *param,
 840                          struct mlx5e_rq *rq)
 841 {
 842         int err;
 843
 844         err = mlx5e_alloc_rq(c, params, param, rq);
 845         if (err)
 846                 return err;
 847
 848         err = mlx5e_create_rq(rq, param);
 849         if (err)
 850                 goto err_free_rq;
 851
 852         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 853         if (err)
 854                 goto err_destroy_rq;
 855
 856         if (params->rx_dim_enabled)
 857                 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 858
 859         /* We disable csum_complete when XDP is enabled since
 860          * XDP programs might manipulate packets which will render
 861          * skb->checksum incorrect.
 862          */
 863         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || c->xdp)
 864                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
 865
 866         return 0;
 867
 868 err_destroy_rq:
 869         mlx5e_destroy_rq(rq);
 870 err_free_rq:
 871         mlx5e_free_rq(rq);
 872
 873         return err;
 874 }
 875
 876 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
 877 {
 878         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 879         mlx5e_trigger_irq(&rq->channel->icosq);
 880 }
 881
 882 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 883 {
 884         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 885         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 886 }
 887
 888 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 889 {
 890         cancel_work_sync(&rq->dim.work);
 891         mlx5e_destroy_rq(rq);
 892         mlx5e_free_rx_descs(rq);
 893         mlx5e_free_rq(rq);
 894 }
 895
 896 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 897 {
 898         kvfree(sq->db.xdpi_fifo.xi);
 899         kvfree(sq->db.wqe_info);
 900 }
 901
 902 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
 903 {
 904         struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
 905         int wq_sz        = mlx5_wq_cyc_get_size(&sq->wq);
 906         int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 907
 908         xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq,
 909                                       GFP_KERNEL, numa);
 910         if (!xdpi_fifo->xi)
 911                 return -ENOMEM;
 912
 913         xdpi_fifo->pc   = &sq->xdpi_fifo_pc;
 914         xdpi_fifo->cc   = &sq->xdpi_fifo_cc;
 915         xdpi_fifo->mask = dsegs_per_wq - 1;
 916
 917         return 0;
 918 }
 919
 920 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 921 {
 922         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 923         int err;
 924
 925         sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz,
 926                                         GFP_KERNEL, numa);
 927         if (!sq->db.wqe_info)
 928                 return -ENOMEM;
 929
 930         err = mlx5e_alloc_xdpsq_fifo(sq, numa);
 931         if (err) {
 932                 mlx5e_free_xdpsq_db(sq);
 933                 return err;
 934         }
 935
 936         return 0;
 937 }
 938
 939 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 940                              struct mlx5e_params *params,
 941                              struct mlx5e_sq_param *param,
 942                              struct mlx5e_xdpsq *sq,
 943                              bool is_redirect)
 944 {
 945         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 946         struct mlx5_core_dev *mdev = c->mdev;
 947         struct mlx5_wq_cyc *wq = &sq->wq;
 948         int err;
 949
 950         sq->pdev      = c->pdev;
 951         sq->mkey_be   = c->mkey_be;
 952         sq->channel   = c;
 953         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
 954         sq->min_inline_mode = params->tx_min_inline_mode;
 955         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 956         sq->stats     = is_redirect ?
 957                 &c->priv->channel_stats[c->ix].xdpsq :
 958                 &c->priv->channel_stats[c->ix].rq_xdpsq;
 959
 960         param->wq.db_numa_node = cpu_to_node(c->cpu);
 961         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
 962         if (err)
 963                 return err;
 964         wq->db = &wq->db[MLX5_SND_DBR];
 965
 966         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
 967         if (err)
 968                 goto err_sq_wq_destroy;
 969
 970         return 0;
 971
 972 err_sq_wq_destroy:
 973         mlx5_wq_destroy(&sq->wq_ctrl);
 974
 975         return err;
 976 }
 977
 978 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
 979 {
 980         mlx5e_free_xdpsq_db(sq);
 981         mlx5_wq_destroy(&sq->wq_ctrl);
 982 }
 983
 984 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
 985 {
 986         kvfree(sq->db.ico_wqe);
 987 }
 988
 989 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
 990 {
 991         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 992
 993         sq->db.ico_wqe = kvzalloc_node(array_size(wq_sz,
 994                                                   sizeof(*sq->db.ico_wqe)),
 995                                        GFP_KERNEL, numa);
 996         if (!sq->db.ico_wqe)
 997                 return -ENOMEM;
 998
 999         return 0;
1000 }
1001
1002 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1003                              struct mlx5e_sq_param *param,
1004                              struct mlx5e_icosq *sq)
1005 {
1006         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1007         struct mlx5_core_dev *mdev = c->mdev;
1008         struct mlx5_wq_cyc *wq = &sq->wq;
1009         int err;
1010
1011         sq->channel   = c;
1012         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1013
1014         param->wq.db_numa_node = cpu_to_node(c->cpu);
1015         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1016         if (err)
1017                 return err;
1018         wq->db = &wq->db[MLX5_SND_DBR];
1019
1020         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1021         if (err)
1022                 goto err_sq_wq_destroy;
1023
1024         return 0;
1025
1026 err_sq_wq_destroy:
1027         mlx5_wq_destroy(&sq->wq_ctrl);
1028
1029         return err;
1030 }
1031
1032 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1033 {
1034         mlx5e_free_icosq_db(sq);
1035         mlx5_wq_destroy(&sq->wq_ctrl);
1036 }
1037
1038 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1039 {
1040         kvfree(sq->db.wqe_info);
1041         kvfree(sq->db.dma_fifo);
1042 }
1043
1044 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1045 {
1046         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1047         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1048
1049         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1050                                                    sizeof(*sq->db.dma_fifo)),
1051                                         GFP_KERNEL, numa);
1052         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1053                                                    sizeof(*sq->db.wqe_info)),
1054                                         GFP_KERNEL, numa);
1055         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1056                 mlx5e_free_txqsq_db(sq);
1057                 return -ENOMEM;
1058         }
1059
1060         sq->dma_fifo_mask = df_sz - 1;
1061
1062         return 0;
1063 }
1064
1065 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1066 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1067                              int txq_ix,
1068                              struct mlx5e_params *params,
1069                              struct mlx5e_sq_param *param,
1070                              struct mlx5e_txqsq *sq,
1071                              int tc)
1072 {
1073         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1074         struct mlx5_core_dev *mdev = c->mdev;
1075         struct mlx5_wq_cyc *wq = &sq->wq;
1076         int err;
1077
1078         sq->pdev      = c->pdev;
1079         sq->tstamp    = c->tstamp;
1080         sq->clock     = &mdev->clock;
1081         sq->mkey_be   = c->mkey_be;
1082         sq->channel   = c;
1083         sq->ch_ix     = c->ix;
1084         sq->txq_ix    = txq_ix;
1085         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1086         sq->min_inline_mode = params->tx_min_inline_mode;
1087         sq->stats     = &c->priv->channel_stats[c->ix].sq[tc];
1088         INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1089         if (MLX5_IPSEC_DEV(c->priv->mdev))
1090                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1091         if (mlx5_accel_is_tls_device(c->priv->mdev))
1092                 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1093
1094         param->wq.db_numa_node = cpu_to_node(c->cpu);
1095         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1096         if (err)
1097                 return err;
1098         wq->db    = &wq->db[MLX5_SND_DBR];
1099
1100         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1101         if (err)
1102                 goto err_sq_wq_destroy;
1103
1104         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1105         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1106
1107         return 0;
1108
1109 err_sq_wq_destroy:
1110         mlx5_wq_destroy(&sq->wq_ctrl);
1111
1112         return err;
1113 }
1114
1115 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1116 {
1117         mlx5e_free_txqsq_db(sq);
1118         mlx5_wq_destroy(&sq->wq_ctrl);
1119 }
1120
1121 struct mlx5e_create_sq_param {
1122         struct mlx5_wq_ctrl        *wq_ctrl;
1123         u32                         cqn;
1124         u32                         tisn;
1125         u8                          tis_lst_sz;
1126         u8                          min_inline_mode;
1127 };
1128
1129 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1130                            struct mlx5e_sq_param *param,
1131                            struct mlx5e_create_sq_param *csp,
1132                            u32 *sqn)
1133 {
1134         void *in;
1135         void *sqc;
1136         void *wq;
1137         int inlen;
1138         int err;
1139
1140         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1141                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1142         in = kvzalloc(inlen, GFP_KERNEL);
1143         if (!in)
1144                 return -ENOMEM;
1145
1146         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1147         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1148
1149         memcpy(sqc, param->sqc, sizeof(param->sqc));
1150         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1151         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1152         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1153
1154         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1155                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1156
1157         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1158         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1159
1160         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1161         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1162         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1163                                           MLX5_ADAPTER_PAGE_SHIFT);
1164         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1165
1166         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1167                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1168
1169         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1170
1171         kvfree(in);
1172
1173         return err;
1174 }
1175
1176 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1177                     struct mlx5e_modify_sq_param *p)
1178 {
1179         void *in;
1180         void *sqc;
1181         int inlen;
1182         int err;
1183
1184         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1185         in = kvzalloc(inlen, GFP_KERNEL);
1186         if (!in)
1187                 return -ENOMEM;
1188
1189         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1190
1191         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1192         MLX5_SET(sqc, sqc, state, p->next_state);
1193         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1194                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1195                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1196         }
1197
1198         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1199
1200         kvfree(in);
1201
1202         return err;
1203 }
1204
1205 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1206 {
1207         mlx5_core_destroy_sq(mdev, sqn);
1208 }
1209
1210 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1211                                struct mlx5e_sq_param *param,
1212                                struct mlx5e_create_sq_param *csp,
1213                                u32 *sqn)
1214 {
1215         struct mlx5e_modify_sq_param msp = {0};
1216         int err;
1217
1218         err = mlx5e_create_sq(mdev, param, csp, sqn);
1219         if (err)
1220                 return err;
1221
1222         msp.curr_state = MLX5_SQC_STATE_RST;
1223         msp.next_state = MLX5_SQC_STATE_RDY;
1224         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1225         if (err)
1226                 mlx5e_destroy_sq(mdev, *sqn);
1227
1228         return err;
1229 }
1230
1231 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1232                                 struct mlx5e_txqsq *sq, u32 rate);
1233
1234 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1235                             u32 tisn,
1236                             int txq_ix,
1237                             struct mlx5e_params *params,
1238                             struct mlx5e_sq_param *param,
1239                             struct mlx5e_txqsq *sq,
1240                             int tc)
1241 {
1242         struct mlx5e_create_sq_param csp = {};
1243         u32 tx_rate;
1244         int err;
1245
1246         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1247         if (err)
1248                 return err;
1249
1250         csp.tisn            = tisn;
1251         csp.tis_lst_sz      = 1;
1252         csp.cqn             = sq->cq.mcq.cqn;
1253         csp.wq_ctrl         = &sq->wq_ctrl;
1254         csp.min_inline_mode = sq->min_inline_mode;
1255         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1256         if (err)
1257                 goto err_free_txqsq;
1258
1259         tx_rate = c->priv->tx_rates[sq->txq_ix];
1260         if (tx_rate)
1261                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1262
1263         if (params->tx_dim_enabled)
1264                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1265
1266         return 0;
1267
1268 err_free_txqsq:
1269         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1270         mlx5e_free_txqsq(sq);
1271
1272         return err;
1273 }
1274
1275 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1276 {
1277         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1278         clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
1279         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1280         netdev_tx_reset_queue(sq->txq);
1281         netif_tx_start_queue(sq->txq);
1282 }
1283
1284 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1285 {
1286         __netif_tx_lock_bh(txq);
1287         netif_tx_stop_queue(txq);
1288         __netif_tx_unlock_bh(txq);
1289 }
1290
1291 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1292 {
1293         struct mlx5e_channel *c = sq->channel;
1294         struct mlx5_wq_cyc *wq = &sq->wq;
1295
1296         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1297         /* prevent netif_tx_wake_queue */
1298         napi_synchronize(&c->napi);
1299
1300         mlx5e_tx_disable_queue(sq->txq);
1301
1302         /* last doorbell out, godspeed .. */
1303         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1304                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1305                 struct mlx5e_tx_wqe *nop;
1306
1307                 sq->db.wqe_info[pi].skb = NULL;
1308                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1309                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1310         }
1311 }
1312
1313 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1314 {
1315         struct mlx5e_channel *c = sq->channel;
1316         struct mlx5_core_dev *mdev = c->mdev;
1317         struct mlx5_rate_limit rl = {0};
1318
1319         cancel_work_sync(&sq->dim.work);
1320         cancel_work_sync(&sq->recover_work);
1321         mlx5e_destroy_sq(mdev, sq->sqn);
1322         if (sq->rate_limit) {
1323                 rl.rate = sq->rate_limit;
1324                 mlx5_rl_remove_rate(mdev, &rl);
1325         }
1326         mlx5e_free_txqsq_descs(sq);
1327         mlx5e_free_txqsq(sq);
1328 }
1329
1330 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1331 {
1332         struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1333                                               recover_work);
1334
1335         mlx5e_tx_reporter_err_cqe(sq);
1336 }
1337
1338 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1339                             struct mlx5e_params *params,
1340                             struct mlx5e_sq_param *param,
1341                             struct mlx5e_icosq *sq)
1342 {
1343         struct mlx5e_create_sq_param csp = {};
1344         int err;
1345
1346         err = mlx5e_alloc_icosq(c, param, sq);
1347         if (err)
1348                 return err;
1349
1350         csp.cqn             = sq->cq.mcq.cqn;
1351         csp.wq_ctrl         = &sq->wq_ctrl;
1352         csp.min_inline_mode = params->tx_min_inline_mode;
1353         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1354         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1355         if (err)
1356                 goto err_free_icosq;
1357
1358         return 0;
1359
1360 err_free_icosq:
1361         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1362         mlx5e_free_icosq(sq);
1363
1364         return err;
1365 }
1366
1367 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1368 {
1369         struct mlx5e_channel *c = sq->channel;
1370
1371         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1372         napi_synchronize(&c->napi);
1373
1374         mlx5e_destroy_sq(c->mdev, sq->sqn);
1375         mlx5e_free_icosq(sq);
1376 }
1377
1378 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1379                             struct mlx5e_params *params,
1380                             struct mlx5e_sq_param *param,
1381                             struct mlx5e_xdpsq *sq,
1382                             bool is_redirect)
1383 {
1384         struct mlx5e_create_sq_param csp = {};
1385         int err;
1386
1387         err = mlx5e_alloc_xdpsq(c, params, param, sq, is_redirect);
1388         if (err)
1389                 return err;
1390
1391         csp.tis_lst_sz      = 1;
1392         csp.tisn            = c->priv->tisn[0]; /* tc = 0 */
1393         csp.cqn             = sq->cq.mcq.cqn;
1394         csp.wq_ctrl         = &sq->wq_ctrl;
1395         csp.min_inline_mode = sq->min_inline_mode;
1396         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1397         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1398         if (err)
1399                 goto err_free_xdpsq;
1400
1401         mlx5e_set_xmit_fp(sq, param->is_mpw);
1402
1403         if (!param->is_mpw) {
1404                 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1405                 unsigned int inline_hdr_sz = 0;
1406                 int i;
1407
1408                 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1409                         inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1410                         ds_cnt++;
1411                 }
1412
1413                 /* Pre initialize fixed WQE fields */
1414                 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1415                         struct mlx5e_xdp_wqe_info *wi  = &sq->db.wqe_info[i];
1416                         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1417                         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1418                         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1419                         struct mlx5_wqe_data_seg *dseg;
1420
1421                         cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1422                         eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1423
1424                         dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1425                         dseg->lkey = sq->mkey_be;
1426
1427                         wi->num_wqebbs = 1;
1428                         wi->num_pkts   = 1;
1429                 }
1430         }
1431
1432         return 0;
1433
1434 err_free_xdpsq:
1435         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1436         mlx5e_free_xdpsq(sq);
1437
1438         return err;
1439 }
1440
1441 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq, struct mlx5e_rq *rq)
1442 {
1443         struct mlx5e_channel *c = sq->channel;
1444
1445         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1446         napi_synchronize(&c->napi);
1447
1448         mlx5e_destroy_sq(c->mdev, sq->sqn);
1449         mlx5e_free_xdpsq_descs(sq, rq);
1450         mlx5e_free_xdpsq(sq);
1451 }
1452
1453 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1454                                  struct mlx5e_cq_param *param,
1455                                  struct mlx5e_cq *cq)
1456 {
1457         struct mlx5_core_cq *mcq = &cq->mcq;
1458         int eqn_not_used;
1459         unsigned int irqn;
1460         int err;
1461         u32 i;
1462
1463         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1464         if (err)
1465                 return err;
1466
1467         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1468                                &cq->wq_ctrl);
1469         if (err)
1470                 return err;
1471
1472         mcq->cqe_sz     = 64;
1473         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1474         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1475         *mcq->set_ci_db = 0;
1476         *mcq->arm_db    = 0;
1477         mcq->vector     = param->eq_ix;
1478         mcq->comp       = mlx5e_completion_event;
1479         mcq->event      = mlx5e_cq_error_event;
1480         mcq->irqn       = irqn;
1481
1482         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1483                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1484
1485                 cqe->op_own = 0xf1;
1486         }
1487
1488         cq->mdev = mdev;
1489
1490         return 0;
1491 }
1492
1493 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1494                           struct mlx5e_cq_param *param,
1495                           struct mlx5e_cq *cq)
1496 {
1497         struct mlx5_core_dev *mdev = c->priv->mdev;
1498         int err;
1499
1500         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1501         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1502         param->eq_ix   = c->ix;
1503
1504         err = mlx5e_alloc_cq_common(mdev, param, cq);
1505
1506         cq->napi    = &c->napi;
1507         cq->channel = c;
1508
1509         return err;
1510 }
1511
1512 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1513 {
1514         mlx5_wq_destroy(&cq->wq_ctrl);
1515 }
1516
1517 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1518 {
1519         struct mlx5_core_dev *mdev = cq->mdev;
1520         struct mlx5_core_cq *mcq = &cq->mcq;
1521
1522         void *in;
1523         void *cqc;
1524         int inlen;
1525         unsigned int irqn_not_used;
1526         int eqn;
1527         int err;
1528
1529         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1530         if (err)
1531                 return err;
1532
1533         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1534                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1535         in = kvzalloc(inlen, GFP_KERNEL);
1536         if (!in)
1537                 return -ENOMEM;
1538
1539         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1540
1541         memcpy(cqc, param->cqc, sizeof(param->cqc));
1542
1543         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1544                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1545
1546         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1547         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1548         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1549         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1550                                             MLX5_ADAPTER_PAGE_SHIFT);
1551         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1552
1553         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1554
1555         kvfree(in);
1556
1557         if (err)
1558                 return err;
1559
1560         mlx5e_cq_arm(cq);
1561
1562         return 0;
1563 }
1564
1565 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1566 {
1567         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1568 }
1569
1570 static int mlx5e_open_cq(struct mlx5e_channel *c,
1571                          struct net_dim_cq_moder moder,
1572                          struct mlx5e_cq_param *param,
1573                          struct mlx5e_cq *cq)
1574 {
1575         struct mlx5_core_dev *mdev = c->mdev;
1576         int err;
1577
1578         err = mlx5e_alloc_cq(c, param, cq);
1579         if (err)
1580                 return err;
1581
1582         err = mlx5e_create_cq(cq, param);
1583         if (err)
1584                 goto err_free_cq;
1585
1586         if (MLX5_CAP_GEN(mdev, cq_moderation))
1587                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1588         return 0;
1589
1590 err_free_cq:
1591         mlx5e_free_cq(cq);
1592
1593         return err;
1594 }
1595
1596 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1597 {
1598         mlx5e_destroy_cq(cq);
1599         mlx5e_free_cq(cq);
1600 }
1601
1602 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1603                              struct mlx5e_params *params,
1604                              struct mlx5e_channel_param *cparam)
1605 {
1606         int err;
1607         int tc;
1608
1609         for (tc = 0; tc < c->num_tc; tc++) {
1610                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1611                                     &cparam->tx_cq, &c->sq[tc].cq);
1612                 if (err)
1613                         goto err_close_tx_cqs;
1614         }
1615
1616         return 0;
1617
1618 err_close_tx_cqs:
1619         for (tc--; tc >= 0; tc--)
1620                 mlx5e_close_cq(&c->sq[tc].cq);
1621
1622         return err;
1623 }
1624
1625 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1626 {
1627         int tc;
1628
1629         for (tc = 0; tc < c->num_tc; tc++)
1630                 mlx5e_close_cq(&c->sq[tc].cq);
1631 }
1632
1633 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1634                           struct mlx5e_params *params,
1635                           struct mlx5e_channel_param *cparam)
1636 {
1637         struct mlx5e_priv *priv = c->priv;
1638         int err, tc, max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
1639
1640         for (tc = 0; tc < params->num_tc; tc++) {
1641                 int txq_ix = c->ix + tc * max_nch;
1642
1643                 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1644                                        params, &cparam->sq, &c->sq[tc], tc);
1645                 if (err)
1646                         goto err_close_sqs;
1647         }
1648
1649         return 0;
1650
1651 err_close_sqs:
1652         for (tc--; tc >= 0; tc--)
1653                 mlx5e_close_txqsq(&c->sq[tc]);
1654
1655         return err;
1656 }
1657
1658 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1659 {
1660         int tc;
1661
1662         for (tc = 0; tc < c->num_tc; tc++)
1663                 mlx5e_close_txqsq(&c->sq[tc]);
1664 }
1665
1666 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1667                                 struct mlx5e_txqsq *sq, u32 rate)
1668 {
1669         struct mlx5e_priv *priv = netdev_priv(dev);
1670         struct mlx5_core_dev *mdev = priv->mdev;
1671         struct mlx5e_modify_sq_param msp = {0};
1672         struct mlx5_rate_limit rl = {0};
1673         u16 rl_index = 0;
1674         int err;
1675
1676         if (rate == sq->rate_limit)
1677                 /* nothing to do */
1678                 return 0;
1679
1680         if (sq->rate_limit) {
1681                 rl.rate = sq->rate_limit;
1682                 /* remove current rl index to free space to next ones */
1683                 mlx5_rl_remove_rate(mdev, &rl);
1684         }
1685
1686         sq->rate_limit = 0;
1687
1688         if (rate) {
1689                 rl.rate = rate;
1690                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1691                 if (err) {
1692                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1693                                    rate, err);
1694                         return err;
1695                 }
1696         }
1697
1698         msp.curr_state = MLX5_SQC_STATE_RDY;
1699         msp.next_state = MLX5_SQC_STATE_RDY;
1700         msp.rl_index   = rl_index;
1701         msp.rl_update  = true;
1702         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1703         if (err) {
1704                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1705                            rate, err);
1706                 /* remove the rate from the table */
1707                 if (rate)
1708                         mlx5_rl_remove_rate(mdev, &rl);
1709                 return err;
1710         }
1711
1712         sq->rate_limit = rate;
1713         return 0;
1714 }
1715
1716 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1717 {
1718         struct mlx5e_priv *priv = netdev_priv(dev);
1719         struct mlx5_core_dev *mdev = priv->mdev;
1720         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1721         int err = 0;
1722
1723         if (!mlx5_rl_is_supported(mdev)) {
1724                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1725                 return -EINVAL;
1726         }
1727
1728         /* rate is given in Mb/sec, HW config is in Kb/sec */
1729         rate = rate << 10;
1730
1731         /* Check whether rate in valid range, 0 is always valid */
1732         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1733                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1734                 return -ERANGE;
1735         }
1736
1737         mutex_lock(&priv->state_lock);
1738         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1739                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1740         if (!err)
1741                 priv->tx_rates[index] = rate;
1742         mutex_unlock(&priv->state_lock);
1743
1744         return err;
1745 }
1746
1747 static int mlx5e_alloc_xps_cpumask(struct mlx5e_channel *c,
1748                                    struct mlx5e_params *params)
1749 {
1750         int num_comp_vectors = mlx5_comp_vectors_count(c->mdev);
1751         int irq;
1752
1753         if (!zalloc_cpumask_var(&c->xps_cpumask, GFP_KERNEL))
1754                 return -ENOMEM;
1755
1756         for (irq = c->ix; irq < num_comp_vectors; irq += params->num_channels) {
1757                 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(c->mdev, irq));
1758
1759                 cpumask_set_cpu(cpu, c->xps_cpumask);
1760         }
1761
1762         return 0;
1763 }
1764
1765 static void mlx5e_free_xps_cpumask(struct mlx5e_channel *c)
1766 {
1767         free_cpumask_var(c->xps_cpumask);
1768 }
1769
1770 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1771                               struct mlx5e_params *params,
1772                               struct mlx5e_channel_param *cparam,
1773                               struct mlx5e_channel **cp)
1774 {
1775         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1776         struct net_dim_cq_moder icocq_moder = {0, 0};
1777         struct net_device *netdev = priv->netdev;
1778         struct mlx5e_channel *c;
1779         unsigned int irq;
1780         int err;
1781         int eqn;
1782
1783         err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1784         if (err)
1785                 return err;
1786
1787         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1788         if (!c)
1789                 return -ENOMEM;
1790
1791         c->priv     = priv;
1792         c->mdev     = priv->mdev;
1793         c->tstamp   = &priv->tstamp;
1794         c->ix       = ix;
1795         c->cpu      = cpu;
1796         c->pdev     = priv->mdev->device;
1797         c->netdev   = priv->netdev;
1798         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1799         c->num_tc   = params->num_tc;
1800         c->xdp      = !!params->xdp_prog;
1801         c->stats    = &priv->channel_stats[ix].ch;
1802         c->irq_desc = irq_to_desc(irq);
1803
1804         err = mlx5e_alloc_xps_cpumask(c, params);
1805         if (err)
1806                 goto err_free_channel;
1807
1808         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1809
1810         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1811         if (err)
1812                 goto err_napi_del;
1813
1814         err = mlx5e_open_tx_cqs(c, params, cparam);
1815         if (err)
1816                 goto err_close_icosq_cq;
1817
1818         err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->tx_cq, &c->xdpsq.cq);
1819         if (err)
1820                 goto err_close_tx_cqs;
1821
1822         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1823         if (err)
1824                 goto err_close_xdp_tx_cqs;
1825
1826         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1827         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1828                                      &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1829         if (err)
1830                 goto err_close_rx_cq;
1831
1832         napi_enable(&c->napi);
1833
1834         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1835         if (err)
1836                 goto err_disable_napi;
1837
1838         err = mlx5e_open_sqs(c, params, cparam);
1839         if (err)
1840                 goto err_close_icosq;
1841
1842         err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq, false) : 0;
1843         if (err)
1844                 goto err_close_sqs;
1845
1846         err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1847         if (err)
1848                 goto err_close_xdp_sq;
1849
1850         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->xdpsq, true);
1851         if (err)
1852                 goto err_close_rq;
1853
1854         *cp = c;
1855
1856         return 0;
1857
1858 err_close_rq:
1859         mlx5e_close_rq(&c->rq);
1860
1861 err_close_xdp_sq:
1862         if (c->xdp)
1863                 mlx5e_close_xdpsq(&c->rq.xdpsq, &c->rq);
1864
1865 err_close_sqs:
1866         mlx5e_close_sqs(c);
1867
1868 err_close_icosq:
1869         mlx5e_close_icosq(&c->icosq);
1870
1871 err_disable_napi:
1872         napi_disable(&c->napi);
1873         if (c->xdp)
1874                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1875
1876 err_close_rx_cq:
1877         mlx5e_close_cq(&c->rq.cq);
1878
1879 err_close_xdp_tx_cqs:
1880         mlx5e_close_cq(&c->xdpsq.cq);
1881
1882 err_close_tx_cqs:
1883         mlx5e_close_tx_cqs(c);
1884
1885 err_close_icosq_cq:
1886         mlx5e_close_cq(&c->icosq.cq);
1887
1888 err_napi_del:
1889         netif_napi_del(&c->napi);
1890         mlx5e_free_xps_cpumask(c);
1891
1892 err_free_channel:
1893         kvfree(c);
1894
1895         return err;
1896 }
1897
1898 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1899 {
1900         int tc;
1901
1902         for (tc = 0; tc < c->num_tc; tc++)
1903                 mlx5e_activate_txqsq(&c->sq[tc]);
1904         mlx5e_activate_rq(&c->rq);
1905         netif_set_xps_queue(c->netdev, c->xps_cpumask, c->ix);
1906 }
1907
1908 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1909 {
1910         int tc;
1911
1912         mlx5e_deactivate_rq(&c->rq);
1913         for (tc = 0; tc < c->num_tc; tc++)
1914                 mlx5e_deactivate_txqsq(&c->sq[tc]);
1915 }
1916
1917 static void mlx5e_close_channel(struct mlx5e_channel *c)
1918 {
1919         mlx5e_close_xdpsq(&c->xdpsq, NULL);
1920         mlx5e_close_rq(&c->rq);
1921         if (c->xdp)
1922                 mlx5e_close_xdpsq(&c->rq.xdpsq, &c->rq);
1923         mlx5e_close_sqs(c);
1924         mlx5e_close_icosq(&c->icosq);
1925         napi_disable(&c->napi);
1926         if (c->xdp)
1927                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1928         mlx5e_close_cq(&c->rq.cq);
1929         mlx5e_close_cq(&c->xdpsq.cq);
1930         mlx5e_close_tx_cqs(c);
1931         mlx5e_close_cq(&c->icosq.cq);
1932         netif_napi_del(&c->napi);
1933         mlx5e_free_xps_cpumask(c);
1934
1935         kvfree(c);
1936 }
1937
1938 #define DEFAULT_FRAG_SIZE (2048)
1939
1940 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
1941                                       struct mlx5e_params *params,
1942                                       struct mlx5e_rq_frags_info *info)
1943 {
1944         u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1945         int frag_size_max = DEFAULT_FRAG_SIZE;
1946         u32 buf_size = 0;
1947         int i;
1948
1949 #ifdef CONFIG_MLX5_EN_IPSEC
1950         if (MLX5_IPSEC_DEV(mdev))
1951                 byte_count += MLX5E_METADATA_ETHER_LEN;
1952 #endif
1953
1954         if (mlx5e_rx_is_linear_skb(params)) {
1955                 int frag_stride;
1956
1957                 frag_stride = mlx5e_rx_get_linear_frag_sz(params);
1958                 frag_stride = roundup_pow_of_two(frag_stride);
1959
1960                 info->arr[0].frag_size = byte_count;
1961                 info->arr[0].frag_stride = frag_stride;
1962                 info->num_frags = 1;
1963                 info->wqe_bulk = PAGE_SIZE / frag_stride;
1964                 goto out;
1965         }
1966
1967         if (byte_count > PAGE_SIZE +
1968             (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
1969                 frag_size_max = PAGE_SIZE;
1970
1971         i = 0;
1972         while (buf_size < byte_count) {
1973                 int frag_size = byte_count - buf_size;
1974
1975                 if (i < MLX5E_MAX_RX_FRAGS - 1)
1976                         frag_size = min(frag_size, frag_size_max);
1977
1978                 info->arr[i].frag_size = frag_size;
1979                 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
1980
1981                 buf_size += frag_size;
1982                 i++;
1983         }
1984         info->num_frags = i;
1985         /* number of different wqes sharing a page */
1986         info->wqe_bulk = 1 + (info->num_frags % 2);
1987
1988 out:
1989         info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
1990         info->log_num_frags = order_base_2(info->num_frags);
1991 }
1992
1993 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
1994 {
1995         int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
1996
1997         switch (wq_type) {
1998         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1999                 sz += sizeof(struct mlx5e_rx_wqe_ll);
2000                 break;
2001         default: /* MLX5_WQ_TYPE_CYCLIC */
2002                 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2003         }
2004
2005         return order_base_2(sz);
2006 }
2007
2008 static u8 mlx5e_get_rq_log_wq_sz(void *rqc)
2009 {
2010         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2011
2012         return MLX5_GET(wq, wq, log_wq_sz);
2013 }
2014
2015 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2016                                  struct mlx5e_params *params,
2017                                  struct mlx5e_rq_param *param)
2018 {
2019         struct mlx5_core_dev *mdev = priv->mdev;
2020         void *rqc = param->rqc;
2021         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2022         int ndsegs = 1;
2023
2024         switch (params->rq_wq_type) {
2025         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2026                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2027                          mlx5e_mpwqe_get_log_num_strides(mdev, params) -
2028                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2029                 MLX5_SET(wq, wq, log_wqe_stride_size,
2030                          mlx5e_mpwqe_get_log_stride_size(mdev, params) -
2031                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2032                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params));
2033                 break;
2034         default: /* MLX5_WQ_TYPE_CYCLIC */
2035                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2036                 mlx5e_build_rq_frags_info(mdev, params, &param->frags_info);
2037                 ndsegs = param->frags_info.num_frags;
2038         }
2039
2040         MLX5_SET(wq, wq, wq_type,          params->rq_wq_type);
2041         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2042         MLX5_SET(wq, wq, log_wq_stride,
2043                  mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2044         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
2045         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2046         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
2047         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
2048
2049         param->wq.buf_numa_node = dev_to_node(mdev->device);
2050 }
2051
2052 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2053                                       struct mlx5e_rq_param *param)
2054 {
2055         struct mlx5_core_dev *mdev = priv->mdev;
2056         void *rqc = param->rqc;
2057         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2058
2059         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2060         MLX5_SET(wq, wq, log_wq_stride,
2061                  mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2062         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2063
2064         param->wq.buf_numa_node = dev_to_node(mdev->device);
2065 }
2066
2067 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2068                                         struct mlx5e_sq_param *param)
2069 {
2070         void *sqc = param->sqc;
2071         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2072
2073         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2074         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
2075
2076         param->wq.buf_numa_node = dev_to_node(priv->mdev->device);
2077 }
2078
2079 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2080                                  struct mlx5e_params *params,
2081                                  struct mlx5e_sq_param *param)
2082 {
2083         void *sqc = param->sqc;
2084         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2085         bool allow_swp;
2086
2087         allow_swp = mlx5_geneve_tx_allowed(priv->mdev) ||
2088                     !!MLX5_IPSEC_DEV(priv->mdev);
2089         mlx5e_build_sq_param_common(priv, param);
2090         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2091         MLX5_SET(sqc, sqc, allow_swp, allow_swp);
2092 }
2093
2094 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2095                                         struct mlx5e_cq_param *param)
2096 {
2097         void *cqc = param->cqc;
2098
2099         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2100         if (MLX5_CAP_GEN(priv->mdev, cqe_128_always) && cache_line_size() >= 128)
2101                 MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD);
2102 }
2103
2104 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2105                                     struct mlx5e_params *params,
2106                                     struct mlx5e_cq_param *param)
2107 {
2108         struct mlx5_core_dev *mdev = priv->mdev;
2109         void *cqc = param->cqc;
2110         u8 log_cq_size;
2111
2112         switch (params->rq_wq_type) {
2113         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2114                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) +
2115                         mlx5e_mpwqe_get_log_num_strides(mdev, params);
2116                 break;
2117         default: /* MLX5_WQ_TYPE_CYCLIC */
2118                 log_cq_size = params->log_rq_mtu_frames;
2119         }
2120
2121         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2122         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2123                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2124                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2125         }
2126
2127         mlx5e_build_common_cq_param(priv, param);
2128         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2129 }
2130
2131 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2132                                     struct mlx5e_params *params,
2133                                     struct mlx5e_cq_param *param)
2134 {
2135         void *cqc = param->cqc;
2136
2137         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2138
2139         mlx5e_build_common_cq_param(priv, param);
2140         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2141 }
2142
2143 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2144                                      u8 log_wq_size,
2145                                      struct mlx5e_cq_param *param)
2146 {
2147         void *cqc = param->cqc;
2148
2149         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2150
2151         mlx5e_build_common_cq_param(priv, param);
2152
2153         param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2154 }
2155
2156 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2157                                     u8 log_wq_size,
2158                                     struct mlx5e_sq_param *param)
2159 {
2160         void *sqc = param->sqc;
2161         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2162
2163         mlx5e_build_sq_param_common(priv, param);
2164
2165         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2166         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2167 }
2168
2169 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2170                                     struct mlx5e_params *params,
2171                                     struct mlx5e_sq_param *param)
2172 {
2173         void *sqc = param->sqc;
2174         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2175
2176         mlx5e_build_sq_param_common(priv, param);
2177         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2178         param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE);
2179 }
2180
2181 static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5e_params *params,
2182                                       struct mlx5e_rq_param *rqp)
2183 {
2184         switch (params->rq_wq_type) {
2185         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2186                 return order_base_2(MLX5E_UMR_WQEBBS) +
2187                         mlx5e_get_rq_log_wq_sz(rqp->rqc);
2188         default: /* MLX5_WQ_TYPE_CYCLIC */
2189                 return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2190         }
2191 }
2192
2193 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2194                                       struct mlx5e_params *params,
2195                                       struct mlx5e_channel_param *cparam)
2196 {
2197         u8 icosq_log_wq_sz;
2198
2199         mlx5e_build_rq_param(priv, params, &cparam->rq);
2200
2201         icosq_log_wq_sz = mlx5e_build_icosq_log_wq_sz(params, &cparam->rq);
2202
2203         mlx5e_build_sq_param(priv, params, &cparam->sq);
2204         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2205         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2206         mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2207         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2208         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2209 }
2210
2211 int mlx5e_open_channels(struct mlx5e_priv *priv,
2212                         struct mlx5e_channels *chs)
2213 {
2214         struct mlx5e_channel_param *cparam;
2215         int err = -ENOMEM;
2216         int i;
2217
2218         chs->num = chs->params.num_channels;
2219
2220         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2221         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2222         if (!chs->c || !cparam)
2223                 goto err_free;
2224
2225         mlx5e_build_channel_param(priv, &chs->params, cparam);
2226         for (i = 0; i < chs->num; i++) {
2227                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2228                 if (err)
2229                         goto err_close_channels;
2230         }
2231
2232         if (!IS_ERR_OR_NULL(priv->tx_reporter))
2233                 devlink_health_reporter_state_update(priv->tx_reporter,
2234                                                      DEVLINK_HEALTH_REPORTER_STATE_HEALTHY);
2235
2236         kvfree(cparam);
2237         return 0;
2238
2239 err_close_channels:
2240         for (i--; i >= 0; i--)
2241                 mlx5e_close_channel(chs->c[i]);
2242
2243 err_free:
2244         kfree(chs->c);
2245         kvfree(cparam);
2246         chs->num = 0;
2247         return err;
2248 }
2249
2250 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2251 {
2252         int i;
2253
2254         for (i = 0; i < chs->num; i++)
2255                 mlx5e_activate_channel(chs->c[i]);
2256 }
2257
2258 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2259
2260 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2261 {
2262         int err = 0;
2263         int i;
2264
2265         for (i = 0; i < chs->num; i++) {
2266                 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2267
2268                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2269         }
2270
2271         return err ? -ETIMEDOUT : 0;
2272 }
2273
2274 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2275 {
2276         int i;
2277
2278         for (i = 0; i < chs->num; i++)
2279                 mlx5e_deactivate_channel(chs->c[i]);
2280 }
2281
2282 void mlx5e_close_channels(struct mlx5e_channels *chs)
2283 {
2284         int i;
2285
2286         for (i = 0; i < chs->num; i++)
2287                 mlx5e_close_channel(chs->c[i]);
2288
2289         kfree(chs->c);
2290         chs->num = 0;
2291 }
2292
2293 static int
2294 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2295 {
2296         struct mlx5_core_dev *mdev = priv->mdev;
2297         void *rqtc;
2298         int inlen;
2299         int err;
2300         u32 *in;
2301         int i;
2302
2303         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2304         in = kvzalloc(inlen, GFP_KERNEL);
2305         if (!in)
2306                 return -ENOMEM;
2307
2308         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2309
2310         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2311         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2312
2313         for (i = 0; i < sz; i++)
2314                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2315
2316         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2317         if (!err)
2318                 rqt->enabled = true;
2319
2320         kvfree(in);
2321         return err;
2322 }
2323
2324 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2325 {
2326         rqt->enabled = false;
2327         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2328 }
2329
2330 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2331 {
2332         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2333         int err;
2334
2335         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2336         if (err)
2337                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2338         return err;
2339 }
2340
2341 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2342 {
2343         struct mlx5e_rqt *rqt;
2344         int err;
2345         int ix;
2346
2347         for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
2348                 rqt = &priv->direct_tir[ix].rqt;
2349                 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2350                 if (err)
2351                         goto err_destroy_rqts;
2352         }
2353
2354         return 0;
2355
2356 err_destroy_rqts:
2357         mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2358         for (ix--; ix >= 0; ix--)
2359                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2360
2361         return err;
2362 }
2363
2364 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2365 {
2366         int i;
2367
2368         for (i = 0; i < mlx5e_get_netdev_max_channels(priv->netdev); i++)
2369                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2370 }
2371
2372 static int mlx5e_rx_hash_fn(int hfunc)
2373 {
2374         return (hfunc == ETH_RSS_HASH_TOP) ?
2375                MLX5_RX_HASH_FN_TOEPLITZ :
2376                MLX5_RX_HASH_FN_INVERTED_XOR8;
2377 }
2378
2379 int mlx5e_bits_invert(unsigned long a, int size)
2380 {
2381         int inv = 0;
2382         int i;
2383
2384         for (i = 0; i < size; i++)
2385                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2386
2387         return inv;
2388 }
2389
2390 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2391                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2392 {
2393         int i;
2394
2395         for (i = 0; i < sz; i++) {
2396                 u32 rqn;
2397
2398                 if (rrp.is_rss) {
2399                         int ix = i;
2400
2401                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2402                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2403
2404                         ix = priv->rss_params.indirection_rqt[ix];
2405                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2406                 } else {
2407                         rqn = rrp.rqn;
2408                 }
2409                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2410         }
2411 }
2412
2413 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2414                        struct mlx5e_redirect_rqt_param rrp)
2415 {
2416         struct mlx5_core_dev *mdev = priv->mdev;
2417         void *rqtc;
2418         int inlen;
2419         u32 *in;
2420         int err;
2421
2422         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2423         in = kvzalloc(inlen, GFP_KERNEL);
2424         if (!in)
2425                 return -ENOMEM;
2426
2427         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2428
2429         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2430         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2431         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2432         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2433
2434         kvfree(in);
2435         return err;
2436 }
2437
2438 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2439                                 struct mlx5e_redirect_rqt_param rrp)
2440 {
2441         if (!rrp.is_rss)
2442                 return rrp.rqn;
2443
2444         if (ix >= rrp.rss.channels->num)
2445                 return priv->drop_rq.rqn;
2446
2447         return rrp.rss.channels->c[ix]->rq.rqn;
2448 }
2449
2450 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2451                                 struct mlx5e_redirect_rqt_param rrp)
2452 {
2453         u32 rqtn;
2454         int ix;
2455
2456         if (priv->indir_rqt.enabled) {
2457                 /* RSS RQ table */
2458                 rqtn = priv->indir_rqt.rqtn;
2459                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2460         }
2461
2462         for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
2463                 struct mlx5e_redirect_rqt_param direct_rrp = {
2464                         .is_rss = false,
2465                         {
2466                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2467                         },
2468                 };
2469
2470                 /* Direct RQ Tables */
2471                 if (!priv->direct_tir[ix].rqt.enabled)
2472                         continue;
2473
2474                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2475                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2476         }
2477 }
2478
2479 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2480                                             struct mlx5e_channels *chs)
2481 {
2482         struct mlx5e_redirect_rqt_param rrp = {
2483                 .is_rss        = true,
2484                 {
2485                         .rss = {
2486                                 .channels  = chs,
2487                                 .hfunc     = priv->rss_params.hfunc,
2488                         }
2489                 },
2490         };
2491
2492         mlx5e_redirect_rqts(priv, rrp);
2493 }
2494
2495 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2496 {
2497         struct mlx5e_redirect_rqt_param drop_rrp = {
2498                 .is_rss = false,
2499                 {
2500                         .rqn = priv->drop_rq.rqn,
2501                 },
2502         };
2503
2504         mlx5e_redirect_rqts(priv, drop_rrp);
2505 }
2506
2507 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {
2508         [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2509                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2510                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2511         },
2512         [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2513                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2514                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2515         },
2516         [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2517                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2518                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2519         },
2520         [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2521                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2522                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2523         },
2524         [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2525                                      .l4_prot_type = 0,
2526                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2527         },
2528         [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2529                                      .l4_prot_type = 0,
2530                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2531         },
2532         [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2533                                       .l4_prot_type = 0,
2534                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2535         },
2536         [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2537                                       .l4_prot_type = 0,
2538                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2539         },
2540         [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2541                             .l4_prot_type = 0,
2542                             .rx_hash_fields = MLX5_HASH_IP,
2543         },
2544         [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2545                             .l4_prot_type = 0,
2546                             .rx_hash_fields = MLX5_HASH_IP,
2547         },
2548 };
2549
2550 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)
2551 {
2552         return tirc_default_config[tt];
2553 }
2554
2555 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2556 {
2557         if (!params->lro_en)
2558                 return;
2559
2560 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2561
2562         MLX5_SET(tirc, tirc, lro_enable_mask,
2563                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2564                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2565         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2566                  (MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2567         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2568 }
2569
2570 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
2571                                     const struct mlx5e_tirc_config *ttconfig,
2572                                     void *tirc, bool inner)
2573 {
2574         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2575                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2576
2577         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc));
2578         if (rss_params->hfunc == ETH_RSS_HASH_TOP) {
2579                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2580                                              rx_hash_toeplitz_key);
2581                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2582                                                rx_hash_toeplitz_key);
2583
2584                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2585                 memcpy(rss_key, rss_params->toeplitz_hash_key, len);
2586         }
2587         MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2588                  ttconfig->l3_prot_type);
2589         MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2590                  ttconfig->l4_prot_type);
2591         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2592                  ttconfig->rx_hash_fields);
2593 }
2594
2595 static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig,
2596                                         enum mlx5e_traffic_types tt,
2597                                         u32 rx_hash_fields)
2598 {
2599         *ttconfig                = tirc_default_config[tt];
2600         ttconfig->rx_hash_fields = rx_hash_fields;
2601 }
2602
2603 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
2604 {
2605         void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2606         struct mlx5e_rss_params *rss = &priv->rss_params;
2607         struct mlx5_core_dev *mdev = priv->mdev;
2608         int ctxlen = MLX5_ST_SZ_BYTES(tirc);
2609         struct mlx5e_tirc_config ttconfig;
2610         int tt;
2611
2612         MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
2613
2614         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2615                 memset(tirc, 0, ctxlen);
2616                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2617                                             rss->rx_hash_fields[tt]);
2618                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false);
2619                 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);
2620         }
2621
2622         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2623                 return;
2624
2625         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2626                 memset(tirc, 0, ctxlen);
2627                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2628                                             rss->rx_hash_fields[tt]);
2629                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true);
2630                 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in,
2631                                      inlen);
2632         }
2633 }
2634
2635 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2636 {
2637         struct mlx5_core_dev *mdev = priv->mdev;
2638
2639         void *in;
2640         void *tirc;
2641         int inlen;
2642         int err;
2643         int tt;
2644         int ix;
2645
2646         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2647         in = kvzalloc(inlen, GFP_KERNEL);
2648         if (!in)
2649                 return -ENOMEM;
2650
2651         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2652         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2653
2654         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2655
2656         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2657                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2658                                            inlen);
2659                 if (err)
2660                         goto free_in;
2661         }
2662
2663         for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
2664                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2665                                            in, inlen);
2666                 if (err)
2667                         goto free_in;
2668         }
2669
2670 free_in:
2671         kvfree(in);
2672
2673         return err;
2674 }
2675
2676 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2677                          struct mlx5e_params *params, u16 mtu)
2678 {
2679         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2680         int err;
2681
2682         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2683         if (err)
2684                 return err;
2685
2686         /* Update vport context MTU */
2687         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2688         return 0;
2689 }
2690
2691 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2692                             struct mlx5e_params *params, u16 *mtu)
2693 {
2694         u16 hw_mtu = 0;
2695         int err;
2696
2697         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2698         if (err || !hw_mtu) /* fallback to port oper mtu */
2699                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2700
2701         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2702 }
2703
2704 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2705 {
2706         struct mlx5e_params *params = &priv->channels.params;
2707         struct net_device *netdev = priv->netdev;
2708         struct mlx5_core_dev *mdev = priv->mdev;
2709         u16 mtu;
2710         int err;
2711
2712         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2713         if (err)
2714                 return err;
2715
2716         mlx5e_query_mtu(mdev, params, &mtu);
2717         if (mtu != params->sw_mtu)
2718                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2719                             __func__, mtu, params->sw_mtu);
2720
2721         params->sw_mtu = mtu;
2722         return 0;
2723 }
2724
2725 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2726 {
2727         struct mlx5e_params *params = &priv->channels.params;
2728         struct net_device *netdev   = priv->netdev;
2729         struct mlx5_core_dev *mdev  = priv->mdev;
2730         u16 max_mtu;
2731
2732         /* MTU range: 68 - hw-specific max */
2733         netdev->min_mtu = ETH_MIN_MTU;
2734
2735         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2736         netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2737                                 ETH_MAX_MTU);
2738 }
2739
2740 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2741 {
2742         struct mlx5e_priv *priv = netdev_priv(netdev);
2743         int nch = priv->channels.params.num_channels;
2744         int ntc = priv->channels.params.num_tc;
2745         int tc;
2746
2747         netdev_reset_tc(netdev);
2748
2749         if (ntc == 1)
2750                 return;
2751
2752         netdev_set_num_tc(netdev, ntc);
2753
2754         /* Map netdev TCs to offset 0
2755          * We have our own UP to TXQ mapping for QoS
2756          */
2757         for (tc = 0; tc < ntc; tc++)
2758                 netdev_set_tc_queue(netdev, tc, nch, 0);
2759 }
2760
2761 static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv)
2762 {
2763         int max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
2764         int i, tc;
2765
2766         for (i = 0; i < max_nch; i++)
2767                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2768                         priv->channel_tc2txq[i][tc] = i + tc * max_nch;
2769 }
2770
2771 static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv)
2772 {
2773         struct mlx5e_channel *c;
2774         struct mlx5e_txqsq *sq;
2775         int i, tc;
2776
2777         for (i = 0; i < priv->channels.num; i++) {
2778                 c = priv->channels.c[i];
2779                 for (tc = 0; tc < c->num_tc; tc++) {
2780                         sq = &c->sq[tc];
2781                         priv->txq2sq[sq->txq_ix] = sq;
2782                 }
2783         }
2784 }
2785
2786 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2787 {
2788         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2789         struct net_device *netdev = priv->netdev;
2790
2791         mlx5e_netdev_set_tcs(netdev);
2792         netif_set_real_num_tx_queues(netdev, num_txqs);
2793         netif_set_real_num_rx_queues(netdev, priv->channels.num);
2794
2795         mlx5e_build_tx2sq_maps(priv);
2796         mlx5e_activate_channels(&priv->channels);
2797         mlx5e_xdp_tx_enable(priv);
2798         netif_tx_start_all_queues(priv->netdev);
2799
2800         if (mlx5e_is_vport_rep(priv))
2801                 mlx5e_add_sqs_fwd_rules(priv);
2802
2803         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2804         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2805 }
2806
2807 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2808 {
2809         mlx5e_redirect_rqts_to_drop(priv);
2810
2811         if (mlx5e_is_vport_rep(priv))
2812                 mlx5e_remove_sqs_fwd_rules(priv);
2813
2814         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2815          * polling for inactive tx queues.
2816          */
2817         netif_tx_stop_all_queues(priv->netdev);
2818         netif_tx_disable(priv->netdev);
2819         mlx5e_xdp_tx_disable(priv);
2820         mlx5e_deactivate_channels(&priv->channels);
2821 }
2822
2823 static void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2824                                        struct mlx5e_channels *new_chs,
2825                                        mlx5e_fp_hw_modify hw_modify)
2826 {
2827         struct net_device *netdev = priv->netdev;
2828         int new_num_txqs;
2829         int carrier_ok;
2830
2831         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2832
2833         carrier_ok = netif_carrier_ok(netdev);
2834         netif_carrier_off(netdev);
2835
2836         if (new_num_txqs < netdev->real_num_tx_queues)
2837                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2838
2839         mlx5e_deactivate_priv_channels(priv);
2840         mlx5e_close_channels(&priv->channels);
2841
2842         priv->channels = *new_chs;
2843
2844         /* New channels are ready to roll, modify HW settings if needed */
2845         if (hw_modify)
2846                 hw_modify(priv);
2847
2848         mlx5e_refresh_tirs(priv, false);
2849         mlx5e_activate_priv_channels(priv);
2850
2851         /* return carrier back if needed */
2852         if (carrier_ok)
2853                 netif_carrier_on(netdev);
2854 }
2855
2856 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
2857                                struct mlx5e_channels *new_chs,
2858                                mlx5e_fp_hw_modify hw_modify)
2859 {
2860         int err;
2861
2862         err = mlx5e_open_channels(priv, new_chs);
2863         if (err)
2864                 return err;
2865
2866         mlx5e_switch_priv_channels(priv, new_chs, hw_modify);
2867         return 0;
2868 }
2869
2870 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
2871 {
2872         struct mlx5e_channels new_channels = {};
2873
2874         new_channels.params = priv->channels.params;
2875         return mlx5e_safe_switch_channels(priv, &new_channels, NULL);
2876 }
2877
2878 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2879 {
2880         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2881         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2882 }
2883
2884 int mlx5e_open_locked(struct net_device *netdev)
2885 {
2886         struct mlx5e_priv *priv = netdev_priv(netdev);
2887         int err;
2888
2889         set_bit(MLX5E_STATE_OPENED, &priv->state);
2890
2891         err = mlx5e_open_channels(priv, &priv->channels);
2892         if (err)
2893                 goto err_clear_state_opened_flag;
2894
2895         mlx5e_refresh_tirs(priv, false);
2896         mlx5e_activate_priv_channels(priv);
2897         if (priv->profile->update_carrier)
2898                 priv->profile->update_carrier(priv);
2899
2900         mlx5e_queue_update_stats(priv);
2901         return 0;
2902
2903 err_clear_state_opened_flag:
2904         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2905         return err;
2906 }
2907
2908 int mlx5e_open(struct net_device *netdev)
2909 {
2910         struct mlx5e_priv *priv = netdev_priv(netdev);
2911         int err;
2912
2913         mutex_lock(&priv->state_lock);
2914         err = mlx5e_open_locked(netdev);
2915         if (!err)
2916                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2917         mutex_unlock(&priv->state_lock);
2918
2919         if (mlx5_vxlan_allowed(priv->mdev->vxlan))
2920                 udp_tunnel_get_rx_info(netdev);
2921
2922         return err;
2923 }
2924
2925 int mlx5e_close_locked(struct net_device *netdev)
2926 {
2927         struct mlx5e_priv *priv = netdev_priv(netdev);
2928
2929         /* May already be CLOSED in case a previous configuration operation
2930          * (e.g RX/TX queue size change) that involves close&open failed.
2931          */
2932         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2933                 return 0;
2934
2935         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2936
2937         netif_carrier_off(priv->netdev);
2938         mlx5e_deactivate_priv_channels(priv);
2939         mlx5e_close_channels(&priv->channels);
2940
2941         return 0;
2942 }
2943
2944 int mlx5e_close(struct net_device *netdev)
2945 {
2946         struct mlx5e_priv *priv = netdev_priv(netdev);
2947         int err;
2948
2949         if (!netif_device_present(netdev))
2950                 return -ENODEV;
2951
2952         mutex_lock(&priv->state_lock);
2953         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
2954         err = mlx5e_close_locked(netdev);
2955         mutex_unlock(&priv->state_lock);
2956
2957         return err;
2958 }
2959
2960 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2961                                struct mlx5e_rq *rq,
2962                                struct mlx5e_rq_param *param)
2963 {
2964         void *rqc = param->rqc;
2965         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2966         int err;
2967
2968         param->wq.db_numa_node = param->wq.buf_numa_node;
2969
2970         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
2971                                  &rq->wq_ctrl);
2972         if (err)
2973                 return err;
2974
2975         /* Mark as unused given "Drop-RQ" packets never reach XDP */
2976         xdp_rxq_info_unused(&rq->xdp_rxq);
2977
2978         rq->mdev = mdev;
2979
2980         return 0;
2981 }
2982
2983 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
2984                                struct mlx5e_cq *cq,
2985                                struct mlx5e_cq_param *param)
2986 {
2987         param->wq.buf_numa_node = dev_to_node(mdev->device);
2988         param->wq.db_numa_node  = dev_to_node(mdev->device);
2989
2990         return mlx5e_alloc_cq_common(mdev, param, cq);
2991 }
2992
2993 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
2994                        struct mlx5e_rq *drop_rq)
2995 {
2996         struct mlx5_core_dev *mdev = priv->mdev;
2997         struct mlx5e_cq_param cq_param = {};
2998         struct mlx5e_rq_param rq_param = {};
2999         struct mlx5e_cq *cq = &drop_rq->cq;
3000         int err;
3001
3002         mlx5e_build_drop_rq_param(priv, &rq_param);
3003
3004         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3005         if (err)
3006                 return err;
3007
3008         err = mlx5e_create_cq(cq, &cq_param);
3009         if (err)
3010                 goto err_free_cq;
3011
3012         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3013         if (err)
3014                 goto err_destroy_cq;
3015
3016         err = mlx5e_create_rq(drop_rq, &rq_param);
3017         if (err)
3018                 goto err_free_rq;
3019
3020         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3021         if (err)
3022                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3023
3024         return 0;
3025
3026 err_free_rq:
3027         mlx5e_free_rq(drop_rq);
3028
3029 err_destroy_cq:
3030         mlx5e_destroy_cq(cq);
3031
3032 err_free_cq:
3033         mlx5e_free_cq(cq);
3034
3035         return err;
3036 }
3037
3038 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3039 {
3040         mlx5e_destroy_rq(drop_rq);
3041         mlx5e_free_rq(drop_rq);
3042         mlx5e_destroy_cq(&drop_rq->cq);
3043         mlx5e_free_cq(&drop_rq->cq);
3044 }
3045
3046 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
3047                      u32 underlay_qpn, u32 *tisn)
3048 {
3049         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
3050         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3051
3052         MLX5_SET(tisc, tisc, prio, tc << 1);
3053         MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
3054         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3055
3056         if (mlx5_lag_is_lacp_owner(mdev))
3057                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3058
3059         return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
3060 }
3061
3062 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3063 {
3064         mlx5_core_destroy_tis(mdev, tisn);
3065 }
3066
3067 int mlx5e_create_tises(struct mlx5e_priv *priv)
3068 {
3069         int err;
3070         int tc;
3071
3072         for (tc = 0; tc < priv->profile->max_tc; tc++) {
3073                 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
3074                 if (err)
3075                         goto err_close_tises;
3076         }
3077
3078         return 0;
3079
3080 err_close_tises:
3081         for (tc--; tc >= 0; tc--)
3082                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3083
3084         return err;
3085 }
3086
3087 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3088 {
3089         int tc;
3090
3091         mlx5e_tx_reporter_destroy(priv);
3092         for (tc = 0; tc < priv->profile->max_tc; tc++)
3093                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3094 }
3095
3096 static void mlx5e_build_indir_tir_ctx_common(struct mlx5e_priv *priv,
3097                                              u32 rqtn, u32 *tirc)
3098 {
3099         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3100         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3101         MLX5_SET(tirc, tirc, indirect_table, rqtn);
3102         MLX5_SET(tirc, tirc, tunneled_offload_en,
3103                  priv->channels.params.tunneled_offload_en);
3104
3105         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3106 }
3107
3108 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3109                                       enum mlx5e_traffic_types tt,
3110                                       u32 *tirc)
3111 {
3112         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3113         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3114                                        &tirc_default_config[tt], tirc, false);
3115 }
3116
3117 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3118 {
3119         mlx5e_build_indir_tir_ctx_common(priv, rqtn, tirc);
3120         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3121 }
3122
3123 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
3124                                             enum mlx5e_traffic_types tt,
3125                                             u32 *tirc)
3126 {
3127         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3128         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3129                                        &tirc_default_config[tt], tirc, true);
3130 }
3131
3132 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3133 {
3134         struct mlx5e_tir *tir;
3135         void *tirc;
3136         int inlen;
3137         int i = 0;
3138         int err;
3139         u32 *in;
3140         int tt;
3141
3142         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3143         in = kvzalloc(inlen, GFP_KERNEL);
3144         if (!in)
3145                 return -ENOMEM;
3146
3147         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3148                 memset(in, 0, inlen);
3149                 tir = &priv->indir_tir[tt];
3150                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3151                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3152                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3153                 if (err) {
3154                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3155                         goto err_destroy_inner_tirs;
3156                 }
3157         }
3158
3159         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3160                 goto out;
3161
3162         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3163                 memset(in, 0, inlen);
3164                 tir = &priv->inner_indir_tir[i];
3165                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3166                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3167                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3168                 if (err) {
3169                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3170                         goto err_destroy_inner_tirs;
3171                 }
3172         }
3173
3174 out:
3175         kvfree(in);
3176
3177         return 0;
3178
3179 err_destroy_inner_tirs:
3180         for (i--; i >= 0; i--)
3181                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3182
3183         for (tt--; tt >= 0; tt--)
3184                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3185
3186         kvfree(in);
3187
3188         return err;
3189 }
3190
3191 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
3192 {
3193         int nch = mlx5e_get_netdev_max_channels(priv->netdev);
3194         struct mlx5e_tir *tir;
3195         void *tirc;
3196         int inlen;
3197         int err;
3198         u32 *in;
3199         int ix;
3200
3201         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3202         in = kvzalloc(inlen, GFP_KERNEL);
3203         if (!in)
3204                 return -ENOMEM;
3205
3206         for (ix = 0; ix < nch; ix++) {
3207                 memset(in, 0, inlen);
3208                 tir = &priv->direct_tir[ix];
3209                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3210                 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
3211                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3212                 if (err)
3213                         goto err_destroy_ch_tirs;
3214         }
3215
3216         kvfree(in);
3217
3218         return 0;
3219
3220 err_destroy_ch_tirs:
3221         mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
3222         for (ix--; ix >= 0; ix--)
3223                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
3224
3225         kvfree(in);
3226
3227         return err;
3228 }
3229
3230 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3231 {
3232         int i;
3233
3234         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3235                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3236
3237         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3238                 return;
3239
3240         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3241                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3242 }
3243
3244 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3245 {
3246         int nch = mlx5e_get_netdev_max_channels(priv->netdev);
3247         int i;
3248
3249         for (i = 0; i < nch; i++)
3250                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3251 }
3252
3253 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3254 {
3255         int err = 0;
3256         int i;
3257
3258         for (i = 0; i < chs->num; i++) {
3259                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3260                 if (err)
3261                         return err;
3262         }
3263
3264         return 0;
3265 }
3266
3267 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3268 {
3269         int err = 0;
3270         int i;
3271
3272         for (i = 0; i < chs->num; i++) {
3273                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3274                 if (err)
3275                         return err;
3276         }
3277
3278         return 0;
3279 }
3280
3281 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3282                                  struct tc_mqprio_qopt *mqprio)
3283 {
3284         struct mlx5e_priv *priv = netdev_priv(netdev);
3285         struct mlx5e_channels new_channels = {};
3286         u8 tc = mqprio->num_tc;
3287         int err = 0;
3288
3289         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3290
3291         if (tc && tc != MLX5E_MAX_NUM_TC)
3292                 return -EINVAL;
3293
3294         mutex_lock(&priv->state_lock);
3295
3296         new_channels.params = priv->channels.params;
3297         new_channels.params.num_tc = tc ? tc : 1;
3298
3299         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3300                 priv->channels.params = new_channels.params;
3301                 goto out;
3302         }
3303
3304         err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
3305         if (err)
3306                 goto out;
3307
3308         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3309                                     new_channels.params.num_tc);
3310 out:
3311         mutex_unlock(&priv->state_lock);
3312         return err;
3313 }
3314
3315 #ifdef CONFIG_MLX5_ESWITCH
3316 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3317                                      struct tc_cls_flower_offload *cls_flower,
3318                                      int flags)
3319 {
3320         switch (cls_flower->command) {
3321         case TC_CLSFLOWER_REPLACE:
3322                 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
3323                                               flags);
3324         case TC_CLSFLOWER_DESTROY:
3325                 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
3326                                            flags);
3327         case TC_CLSFLOWER_STATS:
3328                 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
3329                                           flags);
3330         default:
3331                 return -EOPNOTSUPP;
3332         }
3333 }
3334
3335 static int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3336                                    void *cb_priv)
3337 {
3338         struct mlx5e_priv *priv = cb_priv;
3339
3340         switch (type) {
3341         case TC_SETUP_CLSFLOWER:
3342                 return mlx5e_setup_tc_cls_flower(priv, type_data, MLX5E_TC_INGRESS |
3343                                                  MLX5E_TC_NIC_OFFLOAD);
3344         default:
3345                 return -EOPNOTSUPP;
3346         }
3347 }
3348
3349 static int mlx5e_setup_tc_block(struct net_device *dev,
3350                                 struct tc_block_offload *f)
3351 {
3352         struct mlx5e_priv *priv = netdev_priv(dev);
3353
3354         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3355                 return -EOPNOTSUPP;
3356
3357         switch (f->command) {
3358         case TC_BLOCK_BIND:
3359                 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
3360                                              priv, priv, f->extack);
3361         case TC_BLOCK_UNBIND:
3362                 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3363                                         priv);
3364                 return 0;
3365         default:
3366                 return -EOPNOTSUPP;
3367         }
3368 }
3369 #endif
3370
3371 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3372                           void *type_data)
3373 {
3374         switch (type) {
3375 #ifdef CONFIG_MLX5_ESWITCH
3376         case TC_SETUP_BLOCK:
3377                 return mlx5e_setup_tc_block(dev, type_data);
3378 #endif
3379         case TC_SETUP_QDISC_MQPRIO:
3380                 return mlx5e_setup_tc_mqprio(dev, type_data);
3381         default:
3382                 return -EOPNOTSUPP;
3383         }
3384 }
3385
3386 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3387 {
3388         int i;
3389
3390         for (i = 0; i < mlx5e_get_netdev_max_channels(priv->netdev); i++) {
3391                 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3392                 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3393                 int j;
3394
3395                 s->rx_packets   += rq_stats->packets;
3396                 s->rx_bytes     += rq_stats->bytes;
3397
3398                 for (j = 0; j < priv->max_opened_tc; j++) {
3399                         struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3400
3401                         s->tx_packets    += sq_stats->packets;
3402                         s->tx_bytes      += sq_stats->bytes;
3403                         s->tx_dropped    += sq_stats->dropped;
3404                 }
3405         }
3406 }
3407
3408 void
3409 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3410 {
3411         struct mlx5e_priv *priv = netdev_priv(dev);
3412         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3413         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3414
3415         if (!mlx5e_monitor_counter_supported(priv)) {
3416                 /* update HW stats in background for next time */
3417                 mlx5e_queue_update_stats(priv);
3418         }
3419
3420         if (mlx5e_is_uplink_rep(priv)) {
3421                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3422                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3423                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3424                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3425         } else {
3426                 mlx5e_fold_sw_stats64(priv, stats);
3427         }
3428
3429         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3430
3431         stats->rx_length_errors =
3432                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3433                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3434                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3435         stats->rx_crc_errors =
3436                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3437         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3438         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3439         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3440                            stats->rx_frame_errors;
3441         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3442
3443         /* vport multicast also counts packets that are dropped due to steering
3444          * or rx out of buffer
3445          */
3446         stats->multicast =
3447                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3448 }
3449
3450 static void mlx5e_set_rx_mode(struct net_device *dev)
3451 {
3452         struct mlx5e_priv *priv = netdev_priv(dev);
3453
3454         queue_work(priv->wq, &priv->set_rx_mode_work);
3455 }
3456
3457 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3458 {
3459         struct mlx5e_priv *priv = netdev_priv(netdev);
3460         struct sockaddr *saddr = addr;
3461
3462         if (!is_valid_ether_addr(saddr->sa_data))
3463                 return -EADDRNOTAVAIL;
3464
3465         netif_addr_lock_bh(netdev);
3466         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3467         netif_addr_unlock_bh(netdev);
3468
3469         queue_work(priv->wq, &priv->set_rx_mode_work);
3470
3471         return 0;
3472 }
3473
3474 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3475         do {                                            \
3476                 if (enable)                             \
3477                         *features |= feature;           \
3478                 else                                    \
3479                         *features &= ~feature;          \
3480         } while (0)
3481
3482 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3483
3484 static int set_feature_lro(struct net_device *netdev, bool enable)
3485 {
3486         struct mlx5e_priv *priv = netdev_priv(netdev);
3487         struct mlx5_core_dev *mdev = priv->mdev;
3488         struct mlx5e_channels new_channels = {};
3489         struct mlx5e_params *old_params;
3490         int err = 0;
3491         bool reset;
3492
3493         mutex_lock(&priv->state_lock);
3494
3495         old_params = &priv->channels.params;
3496         if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3497                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3498                 err = -EINVAL;
3499                 goto out;
3500         }
3501
3502         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3503
3504         new_channels.params = *old_params;
3505         new_channels.params.lro_en = enable;
3506
3507         if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3508                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params) ==
3509                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params))
3510                         reset = false;
3511         }
3512
3513         if (!reset) {
3514                 *old_params = new_channels.params;
3515                 err = mlx5e_modify_tirs_lro(priv);
3516                 goto out;
3517         }
3518
3519         err = mlx5e_safe_switch_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3520 out:
3521         mutex_unlock(&priv->state_lock);
3522         return err;
3523 }
3524
3525 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3526 {
3527         struct mlx5e_priv *priv = netdev_priv(netdev);
3528
3529         if (enable)
3530                 mlx5e_enable_cvlan_filter(priv);
3531         else
3532                 mlx5e_disable_cvlan_filter(priv);
3533
3534         return 0;
3535 }
3536
3537 #ifdef CONFIG_MLX5_ESWITCH
3538 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3539 {
3540         struct mlx5e_priv *priv = netdev_priv(netdev);
3541
3542         if (!enable && mlx5e_tc_num_filters(priv, MLX5E_TC_NIC_OFFLOAD)) {
3543                 netdev_err(netdev,
3544                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3545                 return -EINVAL;
3546         }
3547
3548         return 0;
3549 }
3550 #endif
3551
3552 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3553 {
3554         struct mlx5e_priv *priv = netdev_priv(netdev);
3555         struct mlx5_core_dev *mdev = priv->mdev;
3556
3557         return mlx5_set_port_fcs(mdev, !enable);
3558 }
3559
3560 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3561 {
3562         struct mlx5e_priv *priv = netdev_priv(netdev);
3563         int err;
3564
3565         mutex_lock(&priv->state_lock);
3566
3567         priv->channels.params.scatter_fcs_en = enable;
3568         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3569         if (err)
3570                 priv->channels.params.scatter_fcs_en = !enable;
3571
3572         mutex_unlock(&priv->state_lock);
3573
3574         return err;
3575 }
3576
3577 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3578 {
3579         struct mlx5e_priv *priv = netdev_priv(netdev);
3580         int err = 0;
3581
3582         mutex_lock(&priv->state_lock);
3583
3584         priv->channels.params.vlan_strip_disable = !enable;
3585         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3586                 goto unlock;
3587
3588         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3589         if (err)
3590                 priv->channels.params.vlan_strip_disable = enable;
3591
3592 unlock:
3593         mutex_unlock(&priv->state_lock);
3594
3595         return err;
3596 }
3597
3598 #ifdef CONFIG_MLX5_EN_ARFS
3599 static int set_feature_arfs(struct net_device *netdev, bool enable)
3600 {
3601         struct mlx5e_priv *priv = netdev_priv(netdev);
3602         int err;
3603
3604         if (enable)
3605                 err = mlx5e_arfs_enable(priv);
3606         else
3607                 err = mlx5e_arfs_disable(priv);
3608
3609         return err;
3610 }
3611 #endif
3612
3613 static int mlx5e_handle_feature(struct net_device *netdev,
3614                                 netdev_features_t *features,
3615                                 netdev_features_t wanted_features,
3616                                 netdev_features_t feature,
3617                                 mlx5e_feature_handler feature_handler)
3618 {
3619         netdev_features_t changes = wanted_features ^ netdev->features;
3620         bool enable = !!(wanted_features & feature);
3621         int err;
3622
3623         if (!(changes & feature))
3624                 return 0;
3625
3626         err = feature_handler(netdev, enable);
3627         if (err) {
3628                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3629                            enable ? "Enable" : "Disable", &feature, err);
3630                 return err;
3631         }
3632
3633         MLX5E_SET_FEATURE(features, feature, enable);
3634         return 0;
3635 }
3636
3637 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3638 {
3639         netdev_features_t oper_features = netdev->features;
3640         int err = 0;
3641
3642 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3643         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3644
3645         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3646         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3647                                     set_feature_cvlan_filter);
3648 #ifdef CONFIG_MLX5_ESWITCH
3649         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3650 #endif
3651         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3652         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3653         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3654 #ifdef CONFIG_MLX5_EN_ARFS
3655         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3656 #endif
3657
3658         if (err) {
3659                 netdev->features = oper_features;
3660                 return -EINVAL;
3661         }
3662
3663         return 0;
3664 }
3665
3666 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3667                                             netdev_features_t features)
3668 {
3669         struct mlx5e_priv *priv = netdev_priv(netdev);
3670         struct mlx5e_params *params;
3671
3672         mutex_lock(&priv->state_lock);
3673         params = &priv->channels.params;
3674         if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3675                 /* HW strips the outer C-tag header, this is a problem
3676                  * for S-tag traffic.
3677                  */
3678                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3679                 if (!params->vlan_strip_disable)
3680                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3681         }
3682         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3683                 features &= ~NETIF_F_LRO;
3684                 if (params->lro_en)
3685                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3686         }
3687
3688         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3689                 features &= ~NETIF_F_RXHASH;
3690                 if (netdev->features & NETIF_F_RXHASH)
3691                         netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3692         }
3693
3694         mutex_unlock(&priv->state_lock);
3695
3696         return features;
3697 }
3698
3699 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3700                      change_hw_mtu_cb set_mtu_cb)
3701 {
3702         struct mlx5e_priv *priv = netdev_priv(netdev);
3703         struct mlx5e_channels new_channels = {};
3704         struct mlx5e_params *params;
3705         int err = 0;
3706         bool reset;
3707
3708         mutex_lock(&priv->state_lock);
3709
3710         params = &priv->channels.params;
3711
3712         reset = !params->lro_en;
3713         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3714
3715         new_channels.params = *params;
3716         new_channels.params.sw_mtu = new_mtu;
3717
3718         if (params->xdp_prog &&
3719             !mlx5e_rx_is_linear_skb(&new_channels.params)) {
3720                 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3721                            new_mtu, mlx5e_xdp_max_mtu(params));
3722                 err = -EINVAL;
3723                 goto out;
3724         }
3725
3726         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3727                 bool is_linear = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, &new_channels.params);
3728                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params);
3729                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params);
3730
3731                 reset = reset && (is_linear || (ppw_old != ppw_new));
3732         }
3733
3734         if (!reset) {
3735                 params->sw_mtu = new_mtu;
3736                 if (set_mtu_cb)
3737                         set_mtu_cb(priv);
3738                 netdev->mtu = params->sw_mtu;
3739                 goto out;
3740         }
3741
3742         err = mlx5e_safe_switch_channels(priv, &new_channels, set_mtu_cb);
3743         if (err)
3744                 goto out;
3745
3746         netdev->mtu = new_channels.params.sw_mtu;
3747
3748 out:
3749         mutex_unlock(&priv->state_lock);
3750         return err;
3751 }
3752
3753 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3754 {
3755         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu);
3756 }
3757
3758 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3759 {
3760         struct hwtstamp_config config;
3761         int err;
3762
3763         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
3764             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
3765                 return -EOPNOTSUPP;
3766
3767         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3768                 return -EFAULT;
3769
3770         /* TX HW timestamp */
3771         switch (config.tx_type) {
3772         case HWTSTAMP_TX_OFF:
3773         case HWTSTAMP_TX_ON:
3774                 break;
3775         default:
3776                 return -ERANGE;
3777         }
3778
3779         mutex_lock(&priv->state_lock);
3780         /* RX HW timestamp */
3781         switch (config.rx_filter) {
3782         case HWTSTAMP_FILTER_NONE:
3783                 /* Reset CQE compression to Admin default */
3784                 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3785                 break;
3786         case HWTSTAMP_FILTER_ALL:
3787         case HWTSTAMP_FILTER_SOME:
3788         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3789         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3790         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3791         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3792         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3793         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3794         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3795         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3796         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3797         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3798         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3799         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3800         case HWTSTAMP_FILTER_NTP_ALL:
3801                 /* Disable CQE compression */
3802                 netdev_warn(priv->netdev, "Disabling cqe compression");
3803                 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3804                 if (err) {
3805                         netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3806                         mutex_unlock(&priv->state_lock);
3807                         return err;
3808                 }
3809                 config.rx_filter = HWTSTAMP_FILTER_ALL;
3810                 break;
3811         default:
3812                 mutex_unlock(&priv->state_lock);
3813                 return -ERANGE;
3814         }
3815
3816         memcpy(&priv->tstamp, &config, sizeof(config));
3817         mutex_unlock(&priv->state_lock);
3818
3819         /* might need to fix some features */
3820         netdev_update_features(priv->netdev);
3821
3822         return copy_to_user(ifr->ifr_data, &config,
3823                             sizeof(config)) ? -EFAULT : 0;
3824 }
3825
3826 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3827 {
3828         struct hwtstamp_config *cfg = &priv->tstamp;
3829
3830         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3831                 return -EOPNOTSUPP;
3832
3833         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3834 }
3835
3836 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3837 {
3838         struct mlx5e_priv *priv = netdev_priv(dev);
3839
3840         switch (cmd) {
3841         case SIOCSHWTSTAMP:
3842                 return mlx5e_hwstamp_set(priv, ifr);
3843         case SIOCGHWTSTAMP:
3844                 return mlx5e_hwstamp_get(priv, ifr);
3845         default:
3846                 return -EOPNOTSUPP;
3847         }
3848 }
3849
3850 #ifdef CONFIG_MLX5_ESWITCH
3851 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3852 {
3853         struct mlx5e_priv *priv = netdev_priv(dev);
3854         struct mlx5_core_dev *mdev = priv->mdev;
3855
3856         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3857 }
3858
3859 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3860                              __be16 vlan_proto)
3861 {
3862         struct mlx5e_priv *priv = netdev_priv(dev);
3863         struct mlx5_core_dev *mdev = priv->mdev;
3864
3865         if (vlan_proto != htons(ETH_P_8021Q))
3866                 return -EPROTONOSUPPORT;
3867
3868         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3869                                            vlan, qos);
3870 }
3871
3872 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3873 {
3874         struct mlx5e_priv *priv = netdev_priv(dev);
3875         struct mlx5_core_dev *mdev = priv->mdev;
3876
3877         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3878 }
3879
3880 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3881 {
3882         struct mlx5e_priv *priv = netdev_priv(dev);
3883         struct mlx5_core_dev *mdev = priv->mdev;
3884
3885         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3886 }
3887
3888 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3889                       int max_tx_rate)
3890 {
3891         struct mlx5e_priv *priv = netdev_priv(dev);
3892         struct mlx5_core_dev *mdev = priv->mdev;
3893
3894         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3895                                            max_tx_rate, min_tx_rate);
3896 }
3897
3898 static int mlx5_vport_link2ifla(u8 esw_link)
3899 {
3900         switch (esw_link) {
3901         case MLX5_VPORT_ADMIN_STATE_DOWN:
3902                 return IFLA_VF_LINK_STATE_DISABLE;
3903         case MLX5_VPORT_ADMIN_STATE_UP:
3904                 return IFLA_VF_LINK_STATE_ENABLE;
3905         }
3906         return IFLA_VF_LINK_STATE_AUTO;
3907 }
3908
3909 static int mlx5_ifla_link2vport(u8 ifla_link)
3910 {
3911         switch (ifla_link) {
3912         case IFLA_VF_LINK_STATE_DISABLE:
3913                 return MLX5_VPORT_ADMIN_STATE_DOWN;
3914         case IFLA_VF_LINK_STATE_ENABLE:
3915                 return MLX5_VPORT_ADMIN_STATE_UP;
3916         }
3917         return MLX5_VPORT_ADMIN_STATE_AUTO;
3918 }
3919
3920 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3921                                    int link_state)
3922 {
3923         struct mlx5e_priv *priv = netdev_priv(dev);
3924         struct mlx5_core_dev *mdev = priv->mdev;
3925
3926         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3927                                             mlx5_ifla_link2vport(link_state));
3928 }
3929
3930 int mlx5e_get_vf_config(struct net_device *dev,
3931                         int vf, struct ifla_vf_info *ivi)
3932 {
3933         struct mlx5e_priv *priv = netdev_priv(dev);
3934         struct mlx5_core_dev *mdev = priv->mdev;
3935         int err;
3936
3937         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3938         if (err)
3939                 return err;
3940         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3941         return 0;
3942 }
3943
3944 int mlx5e_get_vf_stats(struct net_device *dev,
3945                        int vf, struct ifla_vf_stats *vf_stats)
3946 {
3947         struct mlx5e_priv *priv = netdev_priv(dev);
3948         struct mlx5_core_dev *mdev = priv->mdev;
3949
3950         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3951                                             vf_stats);
3952 }
3953 #endif
3954
3955 struct mlx5e_vxlan_work {
3956         struct work_struct      work;
3957         struct mlx5e_priv       *priv;
3958         u16                     port;
3959 };
3960
3961 static void mlx5e_vxlan_add_work(struct work_struct *work)
3962 {
3963         struct mlx5e_vxlan_work *vxlan_work =
3964                 container_of(work, struct mlx5e_vxlan_work, work);
3965         struct mlx5e_priv *priv = vxlan_work->priv;
3966         u16 port = vxlan_work->port;
3967
3968         mutex_lock(&priv->state_lock);
3969         mlx5_vxlan_add_port(priv->mdev->vxlan, port);
3970         mutex_unlock(&priv->state_lock);
3971
3972         kfree(vxlan_work);
3973 }
3974
3975 static void mlx5e_vxlan_del_work(struct work_struct *work)
3976 {
3977         struct mlx5e_vxlan_work *vxlan_work =
3978                 container_of(work, struct mlx5e_vxlan_work, work);
3979         struct mlx5e_priv *priv         = vxlan_work->priv;
3980         u16 port = vxlan_work->port;
3981
3982         mutex_lock(&priv->state_lock);
3983         mlx5_vxlan_del_port(priv->mdev->vxlan, port);
3984         mutex_unlock(&priv->state_lock);
3985         kfree(vxlan_work);
3986 }
3987
3988 static void mlx5e_vxlan_queue_work(struct mlx5e_priv *priv, u16 port, int add)
3989 {
3990         struct mlx5e_vxlan_work *vxlan_work;
3991
3992         vxlan_work = kmalloc(sizeof(*vxlan_work), GFP_ATOMIC);
3993         if (!vxlan_work)
3994                 return;
3995
3996         if (add)
3997                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_add_work);
3998         else
3999                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_del_work);
4000
4001         vxlan_work->priv = priv;
4002         vxlan_work->port = port;
4003         queue_work(priv->wq, &vxlan_work->work);
4004 }
4005
4006 void mlx5e_add_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4007 {
4008         struct mlx5e_priv *priv = netdev_priv(netdev);
4009
4010         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4011                 return;
4012
4013         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4014                 return;
4015
4016         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 1);
4017 }
4018
4019 void mlx5e_del_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4020 {
4021         struct mlx5e_priv *priv = netdev_priv(netdev);
4022
4023         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4024                 return;
4025
4026         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4027                 return;
4028
4029         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 0);
4030 }
4031
4032 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4033                                                      struct sk_buff *skb,
4034                                                      netdev_features_t features)
4035 {
4036         unsigned int offset = 0;
4037         struct udphdr *udph;
4038         u8 proto;
4039         u16 port;
4040
4041         switch (vlan_get_protocol(skb)) {
4042         case htons(ETH_P_IP):
4043                 proto = ip_hdr(skb)->protocol;
4044                 break;
4045         case htons(ETH_P_IPV6):
4046                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4047                 break;
4048         default:
4049                 goto out;
4050         }
4051
4052         switch (proto) {
4053         case IPPROTO_GRE:
4054                 return features;
4055         case IPPROTO_UDP:
4056                 udph = udp_hdr(skb);
4057                 port = be16_to_cpu(udph->dest);
4058
4059                 /* Verify if UDP port is being offloaded by HW */
4060                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4061                         return features;
4062
4063 #if IS_ENABLED(CONFIG_GENEVE)
4064                 /* Support Geneve offload for default UDP port */
4065                 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4066                         return features;
4067 #endif
4068         }
4069
4070 out:
4071         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4072         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4073 }
4074
4075 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4076                                        struct net_device *netdev,
4077                                        netdev_features_t features)
4078 {
4079         struct mlx5e_priv *priv = netdev_priv(netdev);
4080
4081         features = vlan_features_check(skb, features);
4082         features = vxlan_features_check(skb, features);
4083
4084 #ifdef CONFIG_MLX5_EN_IPSEC
4085         if (mlx5e_ipsec_feature_check(skb, netdev, features))
4086                 return features;
4087 #endif
4088
4089         /* Validate if the tunneled packet is being offloaded by HW */
4090         if (skb->encapsulation &&
4091             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4092                 return mlx5e_tunnel_features_check(priv, skb, features);
4093
4094         return features;
4095 }
4096
4097 static void mlx5e_tx_timeout_work(struct work_struct *work)
4098 {
4099         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4100                                                tx_timeout_work);
4101         bool report_failed = false;
4102         int err;
4103         int i;
4104
4105         rtnl_lock();
4106         mutex_lock(&priv->state_lock);
4107
4108         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4109                 goto unlock;
4110
4111         for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
4112                 struct netdev_queue *dev_queue =
4113                         netdev_get_tx_queue(priv->netdev, i);
4114                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4115
4116                 if (!netif_xmit_stopped(dev_queue))
4117                         continue;
4118
4119                 if (mlx5e_tx_reporter_timeout(sq))
4120                         report_failed = true;
4121         }
4122
4123         if (!report_failed)
4124                 goto unlock;
4125
4126         err = mlx5e_safe_reopen_channels(priv);
4127         if (err)
4128                 netdev_err(priv->netdev,
4129                            "mlx5e_safe_reopen_channels failed recovering from a tx_timeout, err(%d).\n",
4130                            err);
4131
4132 unlock:
4133         mutex_unlock(&priv->state_lock);
4134         rtnl_unlock();
4135 }
4136
4137 static void mlx5e_tx_timeout(struct net_device *dev)
4138 {
4139         struct mlx5e_priv *priv = netdev_priv(dev);
4140
4141         netdev_err(dev, "TX timeout detected\n");
4142         queue_work(priv->wq, &priv->tx_timeout_work);
4143 }
4144
4145 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4146 {
4147         struct net_device *netdev = priv->netdev;
4148         struct mlx5e_channels new_channels = {};
4149
4150         if (priv->channels.params.lro_en) {
4151                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4152                 return -EINVAL;
4153         }
4154
4155         if (MLX5_IPSEC_DEV(priv->mdev)) {
4156                 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4157                 return -EINVAL;
4158         }
4159
4160         new_channels.params = priv->channels.params;
4161         new_channels.params.xdp_prog = prog;
4162
4163         if (!mlx5e_rx_is_linear_skb(&new_channels.params)) {
4164                 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4165                             new_channels.params.sw_mtu,
4166                             mlx5e_xdp_max_mtu(&new_channels.params));
4167                 return -EINVAL;
4168         }
4169
4170         return 0;
4171 }
4172
4173 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4174 {
4175         struct mlx5e_priv *priv = netdev_priv(netdev);
4176         struct bpf_prog *old_prog;
4177         bool reset, was_opened;
4178         int err = 0;
4179         int i;
4180
4181         mutex_lock(&priv->state_lock);
4182
4183         if (prog) {
4184                 err = mlx5e_xdp_allowed(priv, prog);
4185                 if (err)
4186                         goto unlock;
4187         }
4188
4189         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4190         /* no need for full reset when exchanging programs */
4191         reset = (!priv->channels.params.xdp_prog || !prog);
4192
4193         if (was_opened && reset)
4194                 mlx5e_close_locked(netdev);
4195         if (was_opened && !reset) {
4196                 /* num_channels is invariant here, so we can take the
4197                  * batched reference right upfront.
4198                  */
4199                 prog = bpf_prog_add(prog, priv->channels.num);
4200                 if (IS_ERR(prog)) {
4201                         err = PTR_ERR(prog);
4202                         goto unlock;
4203                 }
4204         }
4205
4206         /* exchange programs, extra prog reference we got from caller
4207          * as long as we don't fail from this point onwards.
4208          */
4209         old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4210         if (old_prog)
4211                 bpf_prog_put(old_prog);
4212
4213         if (reset) /* change RQ type according to priv->xdp_prog */
4214                 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4215
4216         if (was_opened && reset)
4217                 err = mlx5e_open_locked(netdev);
4218
4219         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4220                 goto unlock;
4221
4222         /* exchanging programs w/o reset, we update ref counts on behalf
4223          * of the channels RQs here.
4224          */
4225         for (i = 0; i < priv->channels.num; i++) {
4226                 struct mlx5e_channel *c = priv->channels.c[i];
4227
4228                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4229                 napi_synchronize(&c->napi);
4230                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4231
4232                 old_prog = xchg(&c->rq.xdp_prog, prog);
4233
4234                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4235                 /* napi_schedule in case we have missed anything */
4236                 napi_schedule(&c->napi);
4237
4238                 if (old_prog)
4239                         bpf_prog_put(old_prog);
4240         }
4241
4242 unlock:
4243         mutex_unlock(&priv->state_lock);
4244         return err;
4245 }
4246
4247 static u32 mlx5e_xdp_query(struct net_device *dev)
4248 {
4249         struct mlx5e_priv *priv = netdev_priv(dev);
4250         const struct bpf_prog *xdp_prog;
4251         u32 prog_id = 0;
4252
4253         mutex_lock(&priv->state_lock);
4254         xdp_prog = priv->channels.params.xdp_prog;
4255         if (xdp_prog)
4256                 prog_id = xdp_prog->aux->id;
4257         mutex_unlock(&priv->state_lock);
4258
4259         return prog_id;
4260 }
4261
4262 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4263 {
4264         switch (xdp->command) {
4265         case XDP_SETUP_PROG:
4266                 return mlx5e_xdp_set(dev, xdp->prog);
4267         case XDP_QUERY_PROG:
4268                 xdp->prog_id = mlx5e_xdp_query(dev);
4269                 return 0;
4270         default:
4271                 return -EINVAL;
4272         }
4273 }
4274
4275 #ifdef CONFIG_MLX5_ESWITCH
4276 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4277                                 struct net_device *dev, u32 filter_mask,
4278                                 int nlflags)
4279 {
4280         struct mlx5e_priv *priv = netdev_priv(dev);
4281         struct mlx5_core_dev *mdev = priv->mdev;
4282         u8 mode, setting;
4283         int err;
4284
4285         err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4286         if (err)
4287                 return err;
4288         mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4289         return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4290                                        mode,
4291                                        0, 0, nlflags, filter_mask, NULL);
4292 }
4293
4294 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4295                                 u16 flags, struct netlink_ext_ack *extack)
4296 {
4297         struct mlx5e_priv *priv = netdev_priv(dev);
4298         struct mlx5_core_dev *mdev = priv->mdev;
4299         struct nlattr *attr, *br_spec;
4300         u16 mode = BRIDGE_MODE_UNDEF;
4301         u8 setting;
4302         int rem;
4303
4304         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4305         if (!br_spec)
4306                 return -EINVAL;
4307
4308         nla_for_each_nested(attr, br_spec, rem) {
4309                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4310                         continue;
4311
4312                 if (nla_len(attr) < sizeof(mode))
4313                         return -EINVAL;
4314
4315                 mode = nla_get_u16(attr);
4316                 if (mode > BRIDGE_MODE_VEPA)
4317                         return -EINVAL;
4318
4319                 break;
4320         }
4321
4322         if (mode == BRIDGE_MODE_UNDEF)
4323                 return -EINVAL;
4324
4325         setting = (mode == BRIDGE_MODE_VEPA) ?  1 : 0;
4326         return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4327 }
4328 #endif
4329
4330 const struct net_device_ops mlx5e_netdev_ops = {
4331         .ndo_open                = mlx5e_open,
4332         .ndo_stop                = mlx5e_close,
4333         .ndo_start_xmit          = mlx5e_xmit,
4334         .ndo_setup_tc            = mlx5e_setup_tc,
4335         .ndo_select_queue        = mlx5e_select_queue,
4336         .ndo_get_stats64         = mlx5e_get_stats,
4337         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4338         .ndo_set_mac_address     = mlx5e_set_mac,
4339         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4340         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4341         .ndo_set_features        = mlx5e_set_features,
4342         .ndo_fix_features        = mlx5e_fix_features,
4343         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4344         .ndo_do_ioctl            = mlx5e_ioctl,
4345         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4346         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
4347         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
4348         .ndo_features_check      = mlx5e_features_check,
4349         .ndo_tx_timeout          = mlx5e_tx_timeout,
4350         .ndo_bpf                 = mlx5e_xdp,
4351         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4352 #ifdef CONFIG_MLX5_EN_ARFS
4353         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4354 #endif
4355 #ifdef CONFIG_MLX5_ESWITCH
4356         .ndo_bridge_setlink      = mlx5e_bridge_setlink,
4357         .ndo_bridge_getlink      = mlx5e_bridge_getlink,
4358
4359         /* SRIOV E-Switch NDOs */
4360         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4361         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4362         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4363         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4364         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4365         .ndo_get_vf_config       = mlx5e_get_vf_config,
4366         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4367         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4368 #endif
4369 };
4370
4371 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4372 {
4373         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4374                 return -EOPNOTSUPP;
4375         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4376             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4377             !MLX5_CAP_ETH(mdev, csum_cap) ||
4378             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4379             !MLX5_CAP_ETH(mdev, vlan_cap) ||
4380             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4381             MLX5_CAP_FLOWTABLE(mdev,
4382                                flow_table_properties_nic_receive.max_ft_level)
4383                                < 3) {
4384                 mlx5_core_warn(mdev,
4385                                "Not creating net device, some required device capabilities are missing\n");
4386                 return -EOPNOTSUPP;
4387         }
4388         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4389                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4390         if (!MLX5_CAP_GEN(mdev, cq_moderation))
4391                 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4392
4393         return 0;
4394 }
4395
4396 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4397                                    int num_channels)
4398 {
4399         int i;
4400
4401         for (i = 0; i < len; i++)
4402                 indirection_rqt[i] = i % num_channels;
4403 }
4404
4405 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4406 {
4407         u32 link_speed = 0;
4408         u32 pci_bw = 0;
4409
4410         mlx5e_port_max_linkspeed(mdev, &link_speed);
4411         pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4412         mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4413                            link_speed, pci_bw);
4414
4415 #define MLX5E_SLOW_PCI_RATIO (2)
4416
4417         return link_speed && pci_bw &&
4418                 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4419 }
4420
4421 static struct net_dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4422 {
4423         struct net_dim_cq_moder moder;
4424
4425         moder.cq_period_mode = cq_period_mode;
4426         moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4427         moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4428         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4429                 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4430
4431         return moder;
4432 }
4433
4434 static struct net_dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4435 {
4436         struct net_dim_cq_moder moder;
4437
4438         moder.cq_period_mode = cq_period_mode;
4439         moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4440         moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4441         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4442                 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4443
4444         return moder;
4445 }
4446
4447 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4448 {
4449         return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4450                 NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4451                 NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4452 }
4453
4454 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4455 {
4456         if (params->tx_dim_enabled) {
4457                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4458
4459                 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4460         } else {
4461                 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4462         }
4463
4464         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4465                         params->tx_cq_moderation.cq_period_mode ==
4466                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4467 }
4468
4469 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4470 {
4471         if (params->rx_dim_enabled) {
4472                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4473
4474                 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4475         } else {
4476                 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4477         }
4478
4479         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4480                         params->rx_cq_moderation.cq_period_mode ==
4481                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4482 }
4483
4484 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4485 {
4486         int i;
4487
4488         /* The supported periods are organized in ascending order */
4489         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4490                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4491                         break;
4492
4493         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4494 }
4495
4496 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
4497                            struct mlx5e_params *params)
4498 {
4499         /* Prefer Striding RQ, unless any of the following holds:
4500          * - Striding RQ configuration is not possible/supported.
4501          * - Slow PCI heuristic.
4502          * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4503          */
4504         if (!slow_pci_heuristic(mdev) &&
4505             mlx5e_striding_rq_possible(mdev, params) &&
4506             (mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ||
4507              !mlx5e_rx_is_linear_skb(params)))
4508                 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4509         mlx5e_set_rq_type(mdev, params);
4510         mlx5e_init_rq_type_params(mdev, params);
4511 }
4512
4513 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
4514                             u16 num_channels)
4515 {
4516         enum mlx5e_traffic_types tt;
4517
4518         rss_params->hfunc = ETH_RSS_HASH_TOP;
4519         netdev_rss_key_fill(rss_params->toeplitz_hash_key,
4520                             sizeof(rss_params->toeplitz_hash_key));
4521         mlx5e_build_default_indir_rqt(rss_params->indirection_rqt,
4522                                       MLX5E_INDIR_RQT_SIZE, num_channels);
4523         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
4524                 rss_params->rx_hash_fields[tt] =
4525                         tirc_default_config[tt].rx_hash_fields;
4526 }
4527
4528 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4529                             struct mlx5e_rss_params *rss_params,
4530                             struct mlx5e_params *params,
4531                             u16 max_channels, u16 mtu)
4532 {
4533         u8 rx_cq_period_mode;
4534
4535         params->sw_mtu = mtu;
4536         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4537         params->num_channels = max_channels;
4538         params->num_tc       = 1;
4539
4540         /* SQ */
4541         params->log_sq_size = is_kdump_kernel() ?
4542                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4543                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4544
4545         /* XDP SQ */
4546         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE,
4547                         MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
4548
4549         /* set CQE compression */
4550         params->rx_cqe_compress_def = false;
4551         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4552             MLX5_CAP_GEN(mdev, vport_group_manager))
4553                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4554
4555         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4556         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4557
4558         /* RQ */
4559         mlx5e_build_rq_params(mdev, params);
4560
4561         /* HW LRO */
4562
4563         /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4564         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
4565                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
4566                         params->lro_en = !slow_pci_heuristic(mdev);
4567         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4568
4569         /* CQ moderation params */
4570         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4571                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4572                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4573         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4574         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4575         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4576         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4577
4578         /* TX inline */
4579         params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
4580
4581         /* RSS */
4582         mlx5e_build_rss_params(rss_params, params->num_channels);
4583         params->tunneled_offload_en =
4584                 mlx5e_tunnel_inner_ft_supported(mdev);
4585 }
4586
4587 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4588 {
4589         struct mlx5e_priv *priv = netdev_priv(netdev);
4590
4591         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
4592         if (is_zero_ether_addr(netdev->dev_addr) &&
4593             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4594                 eth_hw_addr_random(netdev);
4595                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4596         }
4597 }
4598
4599 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4600 {
4601         struct mlx5e_priv *priv = netdev_priv(netdev);
4602         struct mlx5_core_dev *mdev = priv->mdev;
4603         bool fcs_supported;
4604         bool fcs_enabled;
4605
4606         SET_NETDEV_DEV(netdev, mdev->device);
4607
4608         netdev->netdev_ops = &mlx5e_netdev_ops;
4609
4610 #ifdef CONFIG_MLX5_CORE_EN_DCB
4611         if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4612                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4613 #endif
4614
4615         netdev->watchdog_timeo    = 15 * HZ;
4616
4617         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4618
4619         netdev->vlan_features    |= NETIF_F_SG;
4620         netdev->vlan_features    |= NETIF_F_IP_CSUM;
4621         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
4622         netdev->vlan_features    |= NETIF_F_GRO;
4623         netdev->vlan_features    |= NETIF_F_TSO;
4624         netdev->vlan_features    |= NETIF_F_TSO6;
4625         netdev->vlan_features    |= NETIF_F_RXCSUM;
4626         netdev->vlan_features    |= NETIF_F_RXHASH;
4627
4628         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4629         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4630
4631         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4632             mlx5e_check_fragmented_striding_rq_cap(mdev))
4633                 netdev->vlan_features    |= NETIF_F_LRO;
4634
4635         netdev->hw_features       = netdev->vlan_features;
4636         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4637         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4638         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4639         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4640
4641         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev) ||
4642             MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4643                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
4644                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
4645                 netdev->hw_enc_features |= NETIF_F_TSO;
4646                 netdev->hw_enc_features |= NETIF_F_TSO6;
4647                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4648         }
4649
4650         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4651                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4652                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4653                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4654                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4655                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4656         }
4657
4658         if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4659                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4660                                            NETIF_F_GSO_GRE_CSUM;
4661                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4662                                            NETIF_F_GSO_GRE_CSUM;
4663                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4664                                                 NETIF_F_GSO_GRE_CSUM;
4665         }
4666
4667         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4668         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4669         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4670         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4671
4672         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4673
4674         if (fcs_supported)
4675                 netdev->hw_features |= NETIF_F_RXALL;
4676
4677         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4678                 netdev->hw_features |= NETIF_F_RXFCS;
4679
4680         netdev->features          = netdev->hw_features;
4681         if (!priv->channels.params.lro_en)
4682                 netdev->features  &= ~NETIF_F_LRO;
4683
4684         if (fcs_enabled)
4685                 netdev->features  &= ~NETIF_F_RXALL;
4686
4687         if (!priv->channels.params.scatter_fcs_en)
4688                 netdev->features  &= ~NETIF_F_RXFCS;
4689
4690         /* prefere CQE compression over rxhash */
4691         if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4692                 netdev->features &= ~NETIF_F_RXHASH;
4693
4694 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4695         if (FT_CAP(flow_modify_en) &&
4696             FT_CAP(modify_root) &&
4697             FT_CAP(identified_miss_table_mode) &&
4698             FT_CAP(flow_table_modify)) {
4699 #ifdef CONFIG_MLX5_ESWITCH
4700                 netdev->hw_features      |= NETIF_F_HW_TC;
4701 #endif
4702 #ifdef CONFIG_MLX5_EN_ARFS
4703                 netdev->hw_features      |= NETIF_F_NTUPLE;
4704 #endif
4705         }
4706
4707         netdev->features         |= NETIF_F_HIGHDMA;
4708         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4709
4710         netdev->priv_flags       |= IFF_UNICAST_FLT;
4711
4712         mlx5e_set_netdev_dev_addr(netdev);
4713         mlx5e_ipsec_build_netdev(priv);
4714         mlx5e_tls_build_netdev(priv);
4715 }
4716
4717 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4718 {
4719         struct mlx5_core_dev *mdev = priv->mdev;
4720         int err;
4721
4722         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4723         if (err) {
4724                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4725                 priv->q_counter = 0;
4726         }
4727
4728         err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4729         if (err) {
4730                 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4731                 priv->drop_rq_q_counter = 0;
4732         }
4733 }
4734
4735 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4736 {
4737         if (priv->q_counter)
4738                 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4739
4740         if (priv->drop_rq_q_counter)
4741                 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
4742 }
4743
4744 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
4745                           struct net_device *netdev,
4746                           const struct mlx5e_profile *profile,
4747                           void *ppriv)
4748 {
4749         struct mlx5e_priv *priv = netdev_priv(netdev);
4750         struct mlx5e_rss_params *rss = &priv->rss_params;
4751         int err;
4752
4753         err = mlx5e_netdev_init(netdev, priv, mdev, profile, ppriv);
4754         if (err)
4755                 return err;
4756
4757         mlx5e_build_nic_params(mdev, rss, &priv->channels.params,
4758                                mlx5e_get_netdev_max_channels(netdev),
4759                                netdev->mtu);
4760
4761         mlx5e_timestamp_init(priv);
4762
4763         err = mlx5e_ipsec_init(priv);
4764         if (err)
4765                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4766         err = mlx5e_tls_init(priv);
4767         if (err)
4768                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4769         mlx5e_build_nic_netdev(netdev);
4770         mlx5e_build_tc2txq_maps(priv);
4771
4772         return 0;
4773 }
4774
4775 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4776 {
4777         mlx5e_tls_cleanup(priv);
4778         mlx5e_ipsec_cleanup(priv);
4779         mlx5e_netdev_cleanup(priv->netdev, priv);
4780 }
4781
4782 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4783 {
4784         struct mlx5_core_dev *mdev = priv->mdev;
4785         int err;
4786
4787         mlx5e_create_q_counters(priv);
4788
4789         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4790         if (err) {
4791                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4792                 goto err_destroy_q_counters;
4793         }
4794
4795         err = mlx5e_create_indirect_rqt(priv);
4796         if (err)
4797                 goto err_close_drop_rq;
4798
4799         err = mlx5e_create_direct_rqts(priv);
4800         if (err)
4801                 goto err_destroy_indirect_rqts;
4802
4803         err = mlx5e_create_indirect_tirs(priv, true);
4804         if (err)
4805                 goto err_destroy_direct_rqts;
4806
4807         err = mlx5e_create_direct_tirs(priv);
4808         if (err)
4809                 goto err_destroy_indirect_tirs;
4810
4811         err = mlx5e_create_flow_steering(priv);
4812         if (err) {
4813                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4814                 goto err_destroy_direct_tirs;
4815         }
4816
4817         err = mlx5e_tc_nic_init(priv);
4818         if (err)
4819                 goto err_destroy_flow_steering;
4820
4821         return 0;
4822
4823 err_destroy_flow_steering:
4824         mlx5e_destroy_flow_steering(priv);
4825 err_destroy_direct_tirs:
4826         mlx5e_destroy_direct_tirs(priv);
4827 err_destroy_indirect_tirs:
4828         mlx5e_destroy_indirect_tirs(priv, true);
4829 err_destroy_direct_rqts:
4830         mlx5e_destroy_direct_rqts(priv);
4831 err_destroy_indirect_rqts:
4832         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4833 err_close_drop_rq:
4834         mlx5e_close_drop_rq(&priv->drop_rq);
4835 err_destroy_q_counters:
4836         mlx5e_destroy_q_counters(priv);
4837         return err;
4838 }
4839
4840 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4841 {
4842         mlx5e_tc_nic_cleanup(priv);
4843         mlx5e_destroy_flow_steering(priv);
4844         mlx5e_destroy_direct_tirs(priv);
4845         mlx5e_destroy_indirect_tirs(priv, true);
4846         mlx5e_destroy_direct_rqts(priv);
4847         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4848         mlx5e_close_drop_rq(&priv->drop_rq);
4849         mlx5e_destroy_q_counters(priv);
4850 }
4851
4852 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4853 {
4854         int err;
4855
4856         err = mlx5e_create_tises(priv);
4857         if (err) {
4858                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4859                 return err;
4860         }
4861
4862 #ifdef CONFIG_MLX5_CORE_EN_DCB
4863         mlx5e_dcbnl_initialize(priv);
4864 #endif
4865         mlx5e_tx_reporter_create(priv);
4866         return 0;
4867 }
4868
4869 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4870 {
4871         struct net_device *netdev = priv->netdev;
4872         struct mlx5_core_dev *mdev = priv->mdev;
4873
4874         mlx5e_init_l2_addr(priv);
4875
4876         /* Marking the link as currently not needed by the Driver */
4877         if (!netif_running(netdev))
4878                 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4879
4880         mlx5e_set_netdev_mtu_boundaries(priv);
4881         mlx5e_set_dev_port_mtu(priv);
4882
4883         mlx5_lag_add(mdev, netdev);
4884
4885         mlx5e_enable_async_events(priv);
4886         if (mlx5e_monitor_counter_supported(priv))
4887                 mlx5e_monitor_counter_init(priv);
4888
4889         if (netdev->reg_state != NETREG_REGISTERED)
4890                 return;
4891 #ifdef CONFIG_MLX5_CORE_EN_DCB
4892         mlx5e_dcbnl_init_app(priv);
4893 #endif
4894
4895         queue_work(priv->wq, &priv->set_rx_mode_work);
4896
4897         rtnl_lock();
4898         if (netif_running(netdev))
4899                 mlx5e_open(netdev);
4900         netif_device_attach(netdev);
4901         rtnl_unlock();
4902 }
4903
4904 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4905 {
4906         struct mlx5_core_dev *mdev = priv->mdev;
4907
4908 #ifdef CONFIG_MLX5_CORE_EN_DCB
4909         if (priv->netdev->reg_state == NETREG_REGISTERED)
4910                 mlx5e_dcbnl_delete_app(priv);
4911 #endif
4912
4913         rtnl_lock();
4914         if (netif_running(priv->netdev))
4915                 mlx5e_close(priv->netdev);
4916         netif_device_detach(priv->netdev);
4917         rtnl_unlock();
4918
4919         queue_work(priv->wq, &priv->set_rx_mode_work);
4920
4921         if (mlx5e_monitor_counter_supported(priv))
4922                 mlx5e_monitor_counter_cleanup(priv);
4923
4924         mlx5e_disable_async_events(priv);
4925         mlx5_lag_remove(mdev);
4926 }
4927
4928 static const struct mlx5e_profile mlx5e_nic_profile = {
4929         .init              = mlx5e_nic_init,
4930         .cleanup           = mlx5e_nic_cleanup,
4931         .init_rx           = mlx5e_init_nic_rx,
4932         .cleanup_rx        = mlx5e_cleanup_nic_rx,
4933         .init_tx           = mlx5e_init_nic_tx,
4934         .cleanup_tx        = mlx5e_cleanup_nic_tx,
4935         .enable            = mlx5e_nic_enable,
4936         .disable           = mlx5e_nic_disable,
4937         .update_stats      = mlx5e_update_ndo_stats,
4938         .update_carrier    = mlx5e_update_carrier,
4939         .rx_handlers.handle_rx_cqe       = mlx5e_handle_rx_cqe,
4940         .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
4941         .max_tc            = MLX5E_MAX_NUM_TC,
4942 };
4943
4944 /* mlx5e generic netdev management API (move to en_common.c) */
4945
4946 /* mlx5e_netdev_init/cleanup must be called from profile->init/cleanup callbacks */
4947 int mlx5e_netdev_init(struct net_device *netdev,
4948                       struct mlx5e_priv *priv,
4949                       struct mlx5_core_dev *mdev,
4950                       const struct mlx5e_profile *profile,
4951                       void *ppriv)
4952 {
4953         /* priv init */
4954         priv->mdev        = mdev;
4955         priv->netdev      = netdev;
4956         priv->profile     = profile;
4957         priv->ppriv       = ppriv;
4958         priv->msglevel    = MLX5E_MSG_LEVEL;
4959         priv->max_opened_tc = 1;
4960
4961         mutex_init(&priv->state_lock);
4962         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4963         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
4964         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
4965         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
4966
4967         priv->wq = create_singlethread_workqueue("mlx5e");
4968         if (!priv->wq)
4969                 return -ENOMEM;
4970
4971         /* netdev init */
4972         netif_carrier_off(netdev);
4973
4974 #ifdef CONFIG_MLX5_EN_ARFS
4975         netdev->rx_cpu_rmap =  mlx5_eq_table_get_rmap(mdev);
4976 #endif
4977
4978         return 0;
4979 }
4980
4981 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv)
4982 {
4983         destroy_workqueue(priv->wq);
4984 }
4985
4986 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4987                                        const struct mlx5e_profile *profile,
4988                                        int nch,
4989                                        void *ppriv)
4990 {
4991         struct net_device *netdev;
4992         int err;
4993
4994         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
4995                                     nch * profile->max_tc,
4996                                     nch);
4997         if (!netdev) {
4998                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4999                 return NULL;
5000         }
5001
5002         err = profile->init(mdev, netdev, profile, ppriv);
5003         if (err) {
5004                 mlx5_core_err(mdev, "failed to init mlx5e profile %d\n", err);
5005                 goto err_free_netdev;
5006         }
5007
5008         return netdev;
5009
5010 err_free_netdev:
5011         free_netdev(netdev);
5012
5013         return NULL;
5014 }
5015
5016 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5017 {
5018         const struct mlx5e_profile *profile;
5019         int max_nch;
5020         int err;
5021
5022         profile = priv->profile;
5023         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5024
5025         /* max number of channels may have changed */
5026         max_nch = mlx5e_get_max_num_channels(priv->mdev);
5027         if (priv->channels.params.num_channels > max_nch) {
5028                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5029                 priv->channels.params.num_channels = max_nch;
5030                 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
5031                                               MLX5E_INDIR_RQT_SIZE, max_nch);
5032         }
5033
5034         err = profile->init_tx(priv);
5035         if (err)
5036                 goto out;
5037
5038         err = profile->init_rx(priv);
5039         if (err)
5040                 goto err_cleanup_tx;
5041
5042         if (profile->enable)
5043                 profile->enable(priv);
5044
5045         return 0;
5046
5047 err_cleanup_tx:
5048         profile->cleanup_tx(priv);
5049
5050 out:
5051         return err;
5052 }
5053
5054 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5055 {
5056         const struct mlx5e_profile *profile = priv->profile;
5057
5058         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5059
5060         if (profile->disable)
5061                 profile->disable(priv);
5062         flush_workqueue(priv->wq);
5063
5064         profile->cleanup_rx(priv);
5065         profile->cleanup_tx(priv);
5066         cancel_work_sync(&priv->update_stats_work);
5067 }
5068
5069 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5070 {
5071         const struct mlx5e_profile *profile = priv->profile;
5072         struct net_device *netdev = priv->netdev;
5073
5074         if (profile->cleanup)
5075                 profile->cleanup(priv);
5076         free_netdev(netdev);
5077 }
5078
5079 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
5080  * hardware contexts and to connect it to the current netdev.
5081  */
5082 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
5083 {
5084         struct mlx5e_priv *priv = vpriv;
5085         struct net_device *netdev = priv->netdev;
5086         int err;
5087
5088         if (netif_device_present(netdev))
5089                 return 0;
5090
5091         err = mlx5e_create_mdev_resources(mdev);
5092         if (err)
5093                 return err;
5094
5095         err = mlx5e_attach_netdev(priv);
5096         if (err) {
5097                 mlx5e_destroy_mdev_resources(mdev);
5098                 return err;
5099         }
5100
5101         return 0;
5102 }
5103
5104 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
5105 {
5106         struct mlx5e_priv *priv = vpriv;
5107         struct net_device *netdev = priv->netdev;
5108
5109 #ifdef CONFIG_MLX5_ESWITCH
5110         if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev)
5111                 return;
5112 #endif
5113
5114         if (!netif_device_present(netdev))
5115                 return;
5116
5117         mlx5e_detach_netdev(priv);
5118         mlx5e_destroy_mdev_resources(mdev);
5119 }
5120
5121 static void *mlx5e_add(struct mlx5_core_dev *mdev)
5122 {
5123         struct net_device *netdev;
5124         void *priv;
5125         int err;
5126         int nch;
5127
5128         err = mlx5e_check_required_hca_cap(mdev);
5129         if (err)
5130                 return NULL;
5131
5132 #ifdef CONFIG_MLX5_ESWITCH
5133         if (MLX5_ESWITCH_MANAGER(mdev) &&
5134             mlx5_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
5135                 mlx5e_rep_register_vport_reps(mdev);
5136                 return mdev;
5137         }
5138 #endif
5139
5140         nch = mlx5e_get_max_num_channels(mdev);
5141         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, nch, NULL);
5142         if (!netdev) {
5143                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5144                 return NULL;
5145         }
5146
5147         priv = netdev_priv(netdev);
5148
5149         err = mlx5e_attach(mdev, priv);
5150         if (err) {
5151                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
5152                 goto err_destroy_netdev;
5153         }
5154
5155         err = register_netdev(netdev);
5156         if (err) {
5157                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5158                 goto err_detach;
5159         }
5160
5161 #ifdef CONFIG_MLX5_CORE_EN_DCB
5162         mlx5e_dcbnl_init_app(priv);
5163 #endif
5164         return priv;
5165
5166 err_detach:
5167         mlx5e_detach(mdev, priv);
5168 err_destroy_netdev:
5169         mlx5e_destroy_netdev(priv);
5170         return NULL;
5171 }
5172
5173 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5174 {
5175         struct mlx5e_priv *priv;
5176
5177 #ifdef CONFIG_MLX5_ESWITCH
5178         if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev) {
5179                 mlx5e_rep_unregister_vport_reps(mdev);
5180                 return;
5181         }
5182 #endif
5183         priv = vpriv;
5184 #ifdef CONFIG_MLX5_CORE_EN_DCB
5185         mlx5e_dcbnl_delete_app(priv);
5186 #endif
5187         unregister_netdev(priv->netdev);
5188         mlx5e_detach(mdev, vpriv);
5189         mlx5e_destroy_netdev(priv);
5190 }
5191
5192 static struct mlx5_interface mlx5e_interface = {
5193         .add       = mlx5e_add,
5194         .remove    = mlx5e_remove,
5195         .attach    = mlx5e_attach,
5196         .detach    = mlx5e_detach,
5197         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
5198 };
5199
5200 void mlx5e_init(void)
5201 {
5202         mlx5e_ipsec_build_inverse_table();
5203         mlx5e_build_ptys2ethtool_map();
5204         mlx5_register_interface(&mlx5e_interface);
5205 }
5206
5207 void mlx5e_cleanup(void)
5208 {
5209         mlx5_unregister_interface(&mlx5e_interface);
5210 }