2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/mlx5/fs.h>
37 struct mlx5e_rq_param {
38 u32 rqc[MLX5_ST_SZ_DW(rqc)];
39 struct mlx5_wq_param wq;
42 struct mlx5e_sq_param {
43 u32 sqc[MLX5_ST_SZ_DW(sqc)];
44 struct mlx5_wq_param wq;
48 struct mlx5e_cq_param {
49 u32 cqc[MLX5_ST_SZ_DW(cqc)];
50 struct mlx5_wq_param wq;
54 struct mlx5e_channel_param {
55 struct mlx5e_rq_param rq;
56 struct mlx5e_sq_param sq;
57 struct mlx5e_cq_param rx_cq;
58 struct mlx5e_cq_param tx_cq;
61 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
63 struct mlx5_core_dev *mdev = priv->mdev;
66 port_state = mlx5_query_vport_state(mdev,
67 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
69 if (port_state == VPORT_STATE_UP)
70 netif_carrier_on(priv->netdev);
72 netif_carrier_off(priv->netdev);
75 static void mlx5e_update_carrier_work(struct work_struct *work)
77 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
80 mutex_lock(&priv->state_lock);
81 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
82 mlx5e_update_carrier(priv);
83 mutex_unlock(&priv->state_lock);
86 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
88 struct mlx5_core_dev *mdev = priv->mdev;
89 struct mlx5e_pport_stats *s = &priv->stats.pport;
92 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
94 in = mlx5_vzalloc(sz);
95 out = mlx5_vzalloc(sz);
99 MLX5_SET(ppcnt_reg, in, local_port, 1);
101 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
102 mlx5_core_access_reg(mdev, in, sz, out,
103 sz, MLX5_REG_PPCNT, 0, 0);
104 memcpy(s->IEEE_802_3_counters,
105 MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
106 sizeof(s->IEEE_802_3_counters));
108 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
109 mlx5_core_access_reg(mdev, in, sz, out,
110 sz, MLX5_REG_PPCNT, 0, 0);
111 memcpy(s->RFC_2863_counters,
112 MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
113 sizeof(s->RFC_2863_counters));
115 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
116 mlx5_core_access_reg(mdev, in, sz, out,
117 sz, MLX5_REG_PPCNT, 0, 0);
118 memcpy(s->RFC_2819_counters,
119 MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
120 sizeof(s->RFC_2819_counters));
127 void mlx5e_update_stats(struct mlx5e_priv *priv)
129 struct mlx5_core_dev *mdev = priv->mdev;
130 struct mlx5e_vport_stats *s = &priv->stats.vport;
131 struct mlx5e_rq_stats *rq_stats;
132 struct mlx5e_sq_stats *sq_stats;
133 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
135 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
139 out = mlx5_vzalloc(outlen);
143 /* Collect firts the SW counters and then HW for consistency */
150 s->tx_queue_stopped = 0;
151 s->tx_queue_wake = 0;
152 s->tx_queue_dropped = 0;
159 for (i = 0; i < priv->params.num_channels; i++) {
160 rq_stats = &priv->channel[i]->rq.stats;
162 s->rx_packets += rq_stats->packets;
163 s->rx_bytes += rq_stats->bytes;
164 s->lro_packets += rq_stats->lro_packets;
165 s->lro_bytes += rq_stats->lro_bytes;
166 s->rx_csum_none += rq_stats->csum_none;
167 s->rx_csum_sw += rq_stats->csum_sw;
168 s->rx_wqe_err += rq_stats->wqe_err;
170 for (j = 0; j < priv->params.num_tc; j++) {
171 sq_stats = &priv->channel[i]->sq[j].stats;
173 s->tx_packets += sq_stats->packets;
174 s->tx_bytes += sq_stats->bytes;
175 s->tso_packets += sq_stats->tso_packets;
176 s->tso_bytes += sq_stats->tso_bytes;
177 s->tx_queue_stopped += sq_stats->stopped;
178 s->tx_queue_wake += sq_stats->wake;
179 s->tx_queue_dropped += sq_stats->dropped;
180 tx_offload_none += sq_stats->csum_offload_none;
185 memset(in, 0, sizeof(in));
187 MLX5_SET(query_vport_counter_in, in, opcode,
188 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
189 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
190 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
192 memset(out, 0, outlen);
194 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
197 #define MLX5_GET_CTR(p, x) \
198 MLX5_GET64(query_vport_counter_out, p, x)
200 s->rx_error_packets =
201 MLX5_GET_CTR(out, received_errors.packets);
203 MLX5_GET_CTR(out, received_errors.octets);
204 s->tx_error_packets =
205 MLX5_GET_CTR(out, transmit_errors.packets);
207 MLX5_GET_CTR(out, transmit_errors.octets);
209 s->rx_unicast_packets =
210 MLX5_GET_CTR(out, received_eth_unicast.packets);
211 s->rx_unicast_bytes =
212 MLX5_GET_CTR(out, received_eth_unicast.octets);
213 s->tx_unicast_packets =
214 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
215 s->tx_unicast_bytes =
216 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
218 s->rx_multicast_packets =
219 MLX5_GET_CTR(out, received_eth_multicast.packets);
220 s->rx_multicast_bytes =
221 MLX5_GET_CTR(out, received_eth_multicast.octets);
222 s->tx_multicast_packets =
223 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
224 s->tx_multicast_bytes =
225 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
227 s->rx_broadcast_packets =
228 MLX5_GET_CTR(out, received_eth_broadcast.packets);
229 s->rx_broadcast_bytes =
230 MLX5_GET_CTR(out, received_eth_broadcast.octets);
231 s->tx_broadcast_packets =
232 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
233 s->tx_broadcast_bytes =
234 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
236 /* Update calculated offload counters */
237 s->tx_csum_offload = s->tx_packets - tx_offload_none;
238 s->rx_csum_good = s->rx_packets - s->rx_csum_none -
241 mlx5e_update_pport_counters(priv);
246 static void mlx5e_update_stats_work(struct work_struct *work)
248 struct delayed_work *dwork = to_delayed_work(work);
249 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
251 mutex_lock(&priv->state_lock);
252 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
253 mlx5e_update_stats(priv);
254 schedule_delayed_work(dwork,
256 MLX5E_UPDATE_STATS_INTERVAL));
258 mutex_unlock(&priv->state_lock);
261 static void __mlx5e_async_event(struct mlx5e_priv *priv,
262 enum mlx5_dev_event event)
265 case MLX5_DEV_EVENT_PORT_UP:
266 case MLX5_DEV_EVENT_PORT_DOWN:
267 schedule_work(&priv->update_carrier_work);
275 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
276 enum mlx5_dev_event event, unsigned long param)
278 struct mlx5e_priv *priv = vpriv;
280 spin_lock(&priv->async_events_spinlock);
281 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
282 __mlx5e_async_event(priv, event);
283 spin_unlock(&priv->async_events_spinlock);
286 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
288 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
291 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
293 spin_lock_irq(&priv->async_events_spinlock);
294 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
295 spin_unlock_irq(&priv->async_events_spinlock);
298 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
299 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
301 static int mlx5e_create_rq(struct mlx5e_channel *c,
302 struct mlx5e_rq_param *param,
305 struct mlx5e_priv *priv = c->priv;
306 struct mlx5_core_dev *mdev = priv->mdev;
307 void *rqc = param->rqc;
308 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
313 param->wq.db_numa_node = cpu_to_node(c->cpu);
315 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
320 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
322 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
323 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
324 cpu_to_node(c->cpu));
327 goto err_rq_wq_destroy;
330 rq->wqe_sz = (priv->params.lro_en) ? priv->params.lro_wqe_sz :
331 MLX5E_SW2HW_MTU(priv->netdev->mtu);
332 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz + MLX5E_NET_IP_ALIGN);
334 for (i = 0; i < wq_sz; i++) {
335 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
336 u32 byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
338 wqe->data.lkey = c->mkey_be;
339 wqe->data.byte_count =
340 cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
344 rq->netdev = c->netdev;
345 rq->tstamp = &priv->tstamp;
353 mlx5_wq_destroy(&rq->wq_ctrl);
358 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
361 mlx5_wq_destroy(&rq->wq_ctrl);
364 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
366 struct mlx5e_priv *priv = rq->priv;
367 struct mlx5_core_dev *mdev = priv->mdev;
375 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
376 sizeof(u64) * rq->wq_ctrl.buf.npages;
377 in = mlx5_vzalloc(inlen);
381 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
382 wq = MLX5_ADDR_OF(rqc, rqc, wq);
384 memcpy(rqc, param->rqc, sizeof(param->rqc));
386 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
387 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
388 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
389 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
390 MLX5_ADAPTER_PAGE_SHIFT);
391 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
393 mlx5_fill_page_array(&rq->wq_ctrl.buf,
394 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
396 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
403 static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
405 struct mlx5e_channel *c = rq->channel;
406 struct mlx5e_priv *priv = c->priv;
407 struct mlx5_core_dev *mdev = priv->mdev;
414 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
415 in = mlx5_vzalloc(inlen);
419 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
421 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
422 MLX5_SET(rqc, rqc, state, next_state);
424 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
431 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
433 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
436 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
438 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
439 struct mlx5e_channel *c = rq->channel;
440 struct mlx5e_priv *priv = c->priv;
441 struct mlx5_wq_ll *wq = &rq->wq;
443 while (time_before(jiffies, exp_time)) {
444 if (wq->cur_sz >= priv->params.min_rx_wqes)
453 static int mlx5e_open_rq(struct mlx5e_channel *c,
454 struct mlx5e_rq_param *param,
459 err = mlx5e_create_rq(c, param, rq);
463 err = mlx5e_enable_rq(rq, param);
467 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
471 set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
472 mlx5e_send_nop(&c->sq[0], true); /* trigger mlx5e_post_rx_wqes() */
477 mlx5e_disable_rq(rq);
479 mlx5e_destroy_rq(rq);
484 static void mlx5e_close_rq(struct mlx5e_rq *rq)
486 clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
487 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
489 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
490 while (!mlx5_wq_ll_is_empty(&rq->wq))
493 /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
494 napi_synchronize(&rq->channel->napi);
496 mlx5e_disable_rq(rq);
497 mlx5e_destroy_rq(rq);
500 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
507 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
509 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
510 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
512 sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
513 sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
515 sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
518 if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
519 mlx5e_free_sq_db(sq);
523 sq->dma_fifo_mask = df_sz - 1;
528 static int mlx5e_create_sq(struct mlx5e_channel *c,
530 struct mlx5e_sq_param *param,
533 struct mlx5e_priv *priv = c->priv;
534 struct mlx5_core_dev *mdev = priv->mdev;
536 void *sqc = param->sqc;
537 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
541 err = mlx5_alloc_map_uar(mdev, &sq->uar);
545 param->wq.db_numa_node = cpu_to_node(c->cpu);
547 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq,
550 goto err_unmap_free_uar;
552 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
553 sq->uar_map = sq->uar.map;
554 sq->uar_bf_map = sq->uar.bf_map;
555 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
556 sq->max_inline = param->max_inline;
558 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
560 goto err_sq_wq_destroy;
562 txq_ix = c->ix + tc * priv->params.num_channels;
563 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
566 sq->tstamp = &priv->tstamp;
567 sq->mkey_be = c->mkey_be;
570 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
571 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
572 priv->txq_to_sq_map[txq_ix] = sq;
577 mlx5_wq_destroy(&sq->wq_ctrl);
580 mlx5_unmap_free_uar(mdev, &sq->uar);
585 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
587 struct mlx5e_channel *c = sq->channel;
588 struct mlx5e_priv *priv = c->priv;
590 mlx5e_free_sq_db(sq);
591 mlx5_wq_destroy(&sq->wq_ctrl);
592 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
595 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
597 struct mlx5e_channel *c = sq->channel;
598 struct mlx5e_priv *priv = c->priv;
599 struct mlx5_core_dev *mdev = priv->mdev;
607 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
608 sizeof(u64) * sq->wq_ctrl.buf.npages;
609 in = mlx5_vzalloc(inlen);
613 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
614 wq = MLX5_ADDR_OF(sqc, sqc, wq);
616 memcpy(sqc, param->sqc, sizeof(param->sqc));
618 MLX5_SET(sqc, sqc, tis_num_0, priv->tisn[sq->tc]);
619 MLX5_SET(sqc, sqc, cqn, c->sq[sq->tc].cq.mcq.cqn);
620 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
621 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
622 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
624 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
625 MLX5_SET(wq, wq, uar_page, sq->uar.index);
626 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
627 MLX5_ADAPTER_PAGE_SHIFT);
628 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
630 mlx5_fill_page_array(&sq->wq_ctrl.buf,
631 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
633 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
640 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
642 struct mlx5e_channel *c = sq->channel;
643 struct mlx5e_priv *priv = c->priv;
644 struct mlx5_core_dev *mdev = priv->mdev;
651 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
652 in = mlx5_vzalloc(inlen);
656 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
658 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
659 MLX5_SET(sqc, sqc, state, next_state);
661 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
668 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
670 struct mlx5e_channel *c = sq->channel;
671 struct mlx5e_priv *priv = c->priv;
672 struct mlx5_core_dev *mdev = priv->mdev;
674 mlx5_core_destroy_sq(mdev, sq->sqn);
677 static int mlx5e_open_sq(struct mlx5e_channel *c,
679 struct mlx5e_sq_param *param,
684 err = mlx5e_create_sq(c, tc, param, sq);
688 err = mlx5e_enable_sq(sq, param);
692 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
696 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
697 netdev_tx_reset_queue(sq->txq);
698 netif_tx_start_queue(sq->txq);
703 mlx5e_disable_sq(sq);
705 mlx5e_destroy_sq(sq);
710 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
712 __netif_tx_lock_bh(txq);
713 netif_tx_stop_queue(txq);
714 __netif_tx_unlock_bh(txq);
717 static void mlx5e_close_sq(struct mlx5e_sq *sq)
719 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
720 napi_synchronize(&sq->channel->napi); /* prevent netif_tx_wake_queue */
721 netif_tx_disable_queue(sq->txq);
723 /* ensure hw is notified of all pending wqes */
724 if (mlx5e_sq_has_room_for(sq, 1))
725 mlx5e_send_nop(sq, true);
727 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
728 while (sq->cc != sq->pc) /* wait till sq is empty */
731 /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
732 napi_synchronize(&sq->channel->napi);
734 mlx5e_disable_sq(sq);
735 mlx5e_destroy_sq(sq);
738 static int mlx5e_create_cq(struct mlx5e_channel *c,
739 struct mlx5e_cq_param *param,
742 struct mlx5e_priv *priv = c->priv;
743 struct mlx5_core_dev *mdev = priv->mdev;
744 struct mlx5_core_cq *mcq = &cq->mcq;
750 param->wq.buf_numa_node = cpu_to_node(c->cpu);
751 param->wq.db_numa_node = cpu_to_node(c->cpu);
752 param->eq_ix = c->ix;
754 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
759 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
764 mcq->set_ci_db = cq->wq_ctrl.db.db;
765 mcq->arm_db = cq->wq_ctrl.db.db + 1;
768 mcq->vector = param->eq_ix;
769 mcq->comp = mlx5e_completion_event;
770 mcq->event = mlx5e_cq_error_event;
772 mcq->uar = &priv->cq_uar;
774 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
775 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
786 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
788 mlx5_wq_destroy(&cq->wq_ctrl);
791 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
793 struct mlx5e_priv *priv = cq->priv;
794 struct mlx5_core_dev *mdev = priv->mdev;
795 struct mlx5_core_cq *mcq = &cq->mcq;
800 unsigned int irqn_not_used;
804 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
805 sizeof(u64) * cq->wq_ctrl.buf.npages;
806 in = mlx5_vzalloc(inlen);
810 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
812 memcpy(cqc, param->cqc, sizeof(param->cqc));
814 mlx5_fill_page_array(&cq->wq_ctrl.buf,
815 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
817 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
819 MLX5_SET(cqc, cqc, c_eqn, eqn);
820 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
821 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
822 MLX5_ADAPTER_PAGE_SHIFT);
823 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
825 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
837 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
839 struct mlx5e_priv *priv = cq->priv;
840 struct mlx5_core_dev *mdev = priv->mdev;
842 mlx5_core_destroy_cq(mdev, &cq->mcq);
845 static int mlx5e_open_cq(struct mlx5e_channel *c,
846 struct mlx5e_cq_param *param,
848 u16 moderation_usecs,
849 u16 moderation_frames)
852 struct mlx5e_priv *priv = c->priv;
853 struct mlx5_core_dev *mdev = priv->mdev;
855 err = mlx5e_create_cq(c, param, cq);
859 err = mlx5e_enable_cq(cq, param);
863 err = mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
872 mlx5e_destroy_cq(cq);
877 static void mlx5e_close_cq(struct mlx5e_cq *cq)
879 mlx5e_disable_cq(cq);
880 mlx5e_destroy_cq(cq);
883 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
885 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
888 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
889 struct mlx5e_channel_param *cparam)
891 struct mlx5e_priv *priv = c->priv;
895 for (tc = 0; tc < c->num_tc; tc++) {
896 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
897 priv->params.tx_cq_moderation_usec,
898 priv->params.tx_cq_moderation_pkts);
900 goto err_close_tx_cqs;
906 for (tc--; tc >= 0; tc--)
907 mlx5e_close_cq(&c->sq[tc].cq);
912 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
916 for (tc = 0; tc < c->num_tc; tc++)
917 mlx5e_close_cq(&c->sq[tc].cq);
920 static int mlx5e_open_sqs(struct mlx5e_channel *c,
921 struct mlx5e_channel_param *cparam)
926 for (tc = 0; tc < c->num_tc; tc++) {
927 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
935 for (tc--; tc >= 0; tc--)
936 mlx5e_close_sq(&c->sq[tc]);
941 static void mlx5e_close_sqs(struct mlx5e_channel *c)
945 for (tc = 0; tc < c->num_tc; tc++)
946 mlx5e_close_sq(&c->sq[tc]);
949 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
953 for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
954 priv->channeltc_to_txq_map[ix][i] =
955 ix + i * priv->params.num_channels;
958 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
959 struct mlx5e_channel_param *cparam,
960 struct mlx5e_channel **cp)
962 struct net_device *netdev = priv->netdev;
963 int cpu = mlx5e_get_cpu(priv, ix);
964 struct mlx5e_channel *c;
967 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
974 c->pdev = &priv->mdev->pdev->dev;
975 c->netdev = priv->netdev;
976 c->mkey_be = cpu_to_be32(priv->mkey.key);
977 c->num_tc = priv->params.num_tc;
979 mlx5e_build_channeltc_to_txq_map(priv, ix);
981 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
983 err = mlx5e_open_tx_cqs(c, cparam);
987 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
988 priv->params.rx_cq_moderation_usec,
989 priv->params.rx_cq_moderation_pkts);
991 goto err_close_tx_cqs;
993 napi_enable(&c->napi);
995 err = mlx5e_open_sqs(c, cparam);
997 goto err_disable_napi;
999 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1003 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1012 napi_disable(&c->napi);
1013 mlx5e_close_cq(&c->rq.cq);
1016 mlx5e_close_tx_cqs(c);
1019 netif_napi_del(&c->napi);
1020 napi_hash_del(&c->napi);
1026 static void mlx5e_close_channel(struct mlx5e_channel *c)
1028 mlx5e_close_rq(&c->rq);
1030 napi_disable(&c->napi);
1031 mlx5e_close_cq(&c->rq.cq);
1032 mlx5e_close_tx_cqs(c);
1033 netif_napi_del(&c->napi);
1035 napi_hash_del(&c->napi);
1041 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1042 struct mlx5e_rq_param *param)
1044 void *rqc = param->rqc;
1045 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1047 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1048 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1049 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1050 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1051 MLX5_SET(wq, wq, pd, priv->pdn);
1053 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1054 param->wq.linear = 1;
1057 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1058 struct mlx5e_sq_param *param)
1060 void *sqc = param->sqc;
1061 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1063 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1064 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1065 MLX5_SET(wq, wq, pd, priv->pdn);
1067 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1068 param->max_inline = priv->params.tx_max_inline;
1071 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1072 struct mlx5e_cq_param *param)
1074 void *cqc = param->cqc;
1076 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1079 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1080 struct mlx5e_cq_param *param)
1082 void *cqc = param->cqc;
1084 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1086 mlx5e_build_common_cq_param(priv, param);
1089 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1090 struct mlx5e_cq_param *param)
1092 void *cqc = param->cqc;
1094 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1096 mlx5e_build_common_cq_param(priv, param);
1099 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1100 struct mlx5e_channel_param *cparam)
1102 memset(cparam, 0, sizeof(*cparam));
1104 mlx5e_build_rq_param(priv, &cparam->rq);
1105 mlx5e_build_sq_param(priv, &cparam->sq);
1106 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1107 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1110 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1112 struct mlx5e_channel_param cparam;
1113 int nch = priv->params.num_channels;
1118 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1121 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1122 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1124 if (!priv->channel || !priv->txq_to_sq_map)
1125 goto err_free_txq_to_sq_map;
1127 mlx5e_build_channel_param(priv, &cparam);
1128 for (i = 0; i < nch; i++) {
1129 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1131 goto err_close_channels;
1134 for (j = 0; j < nch; j++) {
1135 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1137 goto err_close_channels;
1143 for (i--; i >= 0; i--)
1144 mlx5e_close_channel(priv->channel[i]);
1146 err_free_txq_to_sq_map:
1147 kfree(priv->txq_to_sq_map);
1148 kfree(priv->channel);
1153 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1157 for (i = 0; i < priv->params.num_channels; i++)
1158 mlx5e_close_channel(priv->channel[i]);
1160 kfree(priv->txq_to_sq_map);
1161 kfree(priv->channel);
1164 static int mlx5e_rx_hash_fn(int hfunc)
1166 return (hfunc == ETH_RSS_HASH_TOP) ?
1167 MLX5_RX_HASH_FN_TOEPLITZ :
1168 MLX5_RX_HASH_FN_INVERTED_XOR8;
1171 static int mlx5e_bits_invert(unsigned long a, int size)
1176 for (i = 0; i < size; i++)
1177 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1182 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1186 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1189 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1190 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1192 ix = priv->params.indirection_rqt[ix];
1193 MLX5_SET(rqtc, rqtc, rq_num[i],
1194 test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1195 priv->channel[ix]->rq.rqn :
1200 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, void *rqtc,
1201 enum mlx5e_rqt_ix rqt_ix)
1205 case MLX5E_INDIRECTION_RQT:
1206 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1210 default: /* MLX5E_SINGLE_RQ_RQT */
1211 MLX5_SET(rqtc, rqtc, rq_num[0],
1212 test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1213 priv->channel[0]->rq.rqn :
1220 static int mlx5e_create_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1222 struct mlx5_core_dev *mdev = priv->mdev;
1229 sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1231 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1232 in = mlx5_vzalloc(inlen);
1236 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1238 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1239 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1241 mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1243 err = mlx5_core_create_rqt(mdev, in, inlen, &priv->rqtn[rqt_ix]);
1250 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1252 struct mlx5_core_dev *mdev = priv->mdev;
1259 sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1261 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1262 in = mlx5_vzalloc(inlen);
1266 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1268 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1270 mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1272 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1274 err = mlx5_core_modify_rqt(mdev, priv->rqtn[rqt_ix], in, inlen);
1281 static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1283 mlx5_core_destroy_rqt(priv->mdev, priv->rqtn[rqt_ix]);
1286 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1288 mlx5e_redirect_rqt(priv, MLX5E_INDIRECTION_RQT);
1289 mlx5e_redirect_rqt(priv, MLX5E_SINGLE_RQ_RQT);
1292 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1294 if (!priv->params.lro_en)
1297 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1299 MLX5_SET(tirc, tirc, lro_enable_mask,
1300 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1301 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1302 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1303 (priv->params.lro_wqe_sz -
1304 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1305 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1306 MLX5_CAP_ETH(priv->mdev,
1307 lro_timer_supported_periods[2]));
1310 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1312 MLX5_SET(tirc, tirc, rx_hash_fn,
1313 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1314 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1315 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1316 rx_hash_toeplitz_key);
1317 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1318 rx_hash_toeplitz_key);
1320 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1321 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1325 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1327 struct mlx5_core_dev *mdev = priv->mdev;
1335 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1336 in = mlx5_vzalloc(inlen);
1340 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1341 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1343 mlx5e_build_tir_ctx_lro(tirc, priv);
1345 for (tt = 0; tt < MLX5E_NUM_TT; tt++) {
1346 err = mlx5_core_modify_tir(mdev, priv->tirn[tt], in, inlen);
1356 static int mlx5e_refresh_tir_self_loopback_enable(struct mlx5_core_dev *mdev,
1363 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1364 in = mlx5_vzalloc(inlen);
1368 MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1370 err = mlx5_core_modify_tir(mdev, tirn, in, inlen);
1377 static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1382 for (i = 0; i < MLX5E_NUM_TT; i++) {
1383 err = mlx5e_refresh_tir_self_loopback_enable(priv->mdev,
1392 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1394 struct mlx5e_priv *priv = netdev_priv(netdev);
1395 struct mlx5_core_dev *mdev = priv->mdev;
1399 err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1403 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1405 if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1406 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1407 __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1409 netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1413 int mlx5e_open_locked(struct net_device *netdev)
1415 struct mlx5e_priv *priv = netdev_priv(netdev);
1419 set_bit(MLX5E_STATE_OPENED, &priv->state);
1421 num_txqs = priv->params.num_channels * priv->params.num_tc;
1422 netif_set_real_num_tx_queues(netdev, num_txqs);
1423 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1425 err = mlx5e_set_dev_port_mtu(netdev);
1427 goto err_clear_state_opened_flag;
1429 err = mlx5e_open_channels(priv);
1431 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1433 goto err_clear_state_opened_flag;
1436 err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1438 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1440 goto err_close_channels;
1443 mlx5e_update_carrier(priv);
1444 mlx5e_redirect_rqts(priv);
1445 mlx5e_timestamp_init(priv);
1447 schedule_delayed_work(&priv->update_stats_work, 0);
1452 mlx5e_close_channels(priv);
1453 err_clear_state_opened_flag:
1454 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1458 static int mlx5e_open(struct net_device *netdev)
1460 struct mlx5e_priv *priv = netdev_priv(netdev);
1463 mutex_lock(&priv->state_lock);
1464 err = mlx5e_open_locked(netdev);
1465 mutex_unlock(&priv->state_lock);
1470 int mlx5e_close_locked(struct net_device *netdev)
1472 struct mlx5e_priv *priv = netdev_priv(netdev);
1474 /* May already be CLOSED in case a previous configuration operation
1475 * (e.g RX/TX queue size change) that involves close&open failed.
1477 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1480 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1482 mlx5e_timestamp_cleanup(priv);
1483 mlx5e_redirect_rqts(priv);
1484 netif_carrier_off(priv->netdev);
1485 mlx5e_close_channels(priv);
1490 static int mlx5e_close(struct net_device *netdev)
1492 struct mlx5e_priv *priv = netdev_priv(netdev);
1495 mutex_lock(&priv->state_lock);
1496 err = mlx5e_close_locked(netdev);
1497 mutex_unlock(&priv->state_lock);
1502 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1503 struct mlx5e_rq *rq,
1504 struct mlx5e_rq_param *param)
1506 struct mlx5_core_dev *mdev = priv->mdev;
1507 void *rqc = param->rqc;
1508 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1511 param->wq.db_numa_node = param->wq.buf_numa_node;
1513 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
1523 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1524 struct mlx5e_cq *cq,
1525 struct mlx5e_cq_param *param)
1527 struct mlx5_core_dev *mdev = priv->mdev;
1528 struct mlx5_core_cq *mcq = &cq->mcq;
1533 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1538 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1541 mcq->set_ci_db = cq->wq_ctrl.db.db;
1542 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1543 *mcq->set_ci_db = 0;
1545 mcq->vector = param->eq_ix;
1546 mcq->comp = mlx5e_completion_event;
1547 mcq->event = mlx5e_cq_error_event;
1549 mcq->uar = &priv->cq_uar;
1556 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1558 struct mlx5e_cq_param cq_param;
1559 struct mlx5e_rq_param rq_param;
1560 struct mlx5e_rq *rq = &priv->drop_rq;
1561 struct mlx5e_cq *cq = &priv->drop_rq.cq;
1564 memset(&cq_param, 0, sizeof(cq_param));
1565 memset(&rq_param, 0, sizeof(rq_param));
1566 mlx5e_build_rx_cq_param(priv, &cq_param);
1567 mlx5e_build_rq_param(priv, &rq_param);
1569 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1573 err = mlx5e_enable_cq(cq, &cq_param);
1575 goto err_destroy_cq;
1577 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1579 goto err_disable_cq;
1581 err = mlx5e_enable_rq(rq, &rq_param);
1583 goto err_destroy_rq;
1588 mlx5e_destroy_rq(&priv->drop_rq);
1591 mlx5e_disable_cq(&priv->drop_rq.cq);
1594 mlx5e_destroy_cq(&priv->drop_rq.cq);
1599 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1601 mlx5e_disable_rq(&priv->drop_rq);
1602 mlx5e_destroy_rq(&priv->drop_rq);
1603 mlx5e_disable_cq(&priv->drop_rq.cq);
1604 mlx5e_destroy_cq(&priv->drop_rq.cq);
1607 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1609 struct mlx5_core_dev *mdev = priv->mdev;
1610 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1611 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1613 memset(in, 0, sizeof(in));
1615 MLX5_SET(tisc, tisc, prio, tc);
1616 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1618 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1621 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1623 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1626 static int mlx5e_create_tises(struct mlx5e_priv *priv)
1631 for (tc = 0; tc < priv->params.num_tc; tc++) {
1632 err = mlx5e_create_tis(priv, tc);
1634 goto err_close_tises;
1640 for (tc--; tc >= 0; tc--)
1641 mlx5e_destroy_tis(priv, tc);
1646 static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1650 for (tc = 0; tc < priv->params.num_tc; tc++)
1651 mlx5e_destroy_tis(priv, tc);
1654 static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1656 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1658 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1660 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
1661 MLX5_HASH_FIELD_SEL_DST_IP)
1663 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
1664 MLX5_HASH_FIELD_SEL_DST_IP |\
1665 MLX5_HASH_FIELD_SEL_L4_SPORT |\
1666 MLX5_HASH_FIELD_SEL_L4_DPORT)
1668 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
1669 MLX5_HASH_FIELD_SEL_DST_IP |\
1670 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1672 mlx5e_build_tir_ctx_lro(tirc, priv);
1674 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1678 MLX5_SET(tirc, tirc, indirect_table,
1679 priv->rqtn[MLX5E_SINGLE_RQ_RQT]);
1680 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
1683 MLX5_SET(tirc, tirc, indirect_table,
1684 priv->rqtn[MLX5E_INDIRECTION_RQT]);
1685 mlx5e_build_tir_ctx_hash(tirc, priv);
1690 case MLX5E_TT_IPV4_TCP:
1691 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1692 MLX5_L3_PROT_TYPE_IPV4);
1693 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1694 MLX5_L4_PROT_TYPE_TCP);
1695 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1696 MLX5_HASH_IP_L4PORTS);
1699 case MLX5E_TT_IPV6_TCP:
1700 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1701 MLX5_L3_PROT_TYPE_IPV6);
1702 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1703 MLX5_L4_PROT_TYPE_TCP);
1704 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1705 MLX5_HASH_IP_L4PORTS);
1708 case MLX5E_TT_IPV4_UDP:
1709 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1710 MLX5_L3_PROT_TYPE_IPV4);
1711 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1712 MLX5_L4_PROT_TYPE_UDP);
1713 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1714 MLX5_HASH_IP_L4PORTS);
1717 case MLX5E_TT_IPV6_UDP:
1718 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1719 MLX5_L3_PROT_TYPE_IPV6);
1720 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1721 MLX5_L4_PROT_TYPE_UDP);
1722 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1723 MLX5_HASH_IP_L4PORTS);
1726 case MLX5E_TT_IPV4_IPSEC_AH:
1727 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1728 MLX5_L3_PROT_TYPE_IPV4);
1729 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1730 MLX5_HASH_IP_IPSEC_SPI);
1733 case MLX5E_TT_IPV6_IPSEC_AH:
1734 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1735 MLX5_L3_PROT_TYPE_IPV6);
1736 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1737 MLX5_HASH_IP_IPSEC_SPI);
1740 case MLX5E_TT_IPV4_IPSEC_ESP:
1741 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1742 MLX5_L3_PROT_TYPE_IPV4);
1743 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1744 MLX5_HASH_IP_IPSEC_SPI);
1747 case MLX5E_TT_IPV6_IPSEC_ESP:
1748 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1749 MLX5_L3_PROT_TYPE_IPV6);
1750 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1751 MLX5_HASH_IP_IPSEC_SPI);
1755 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1756 MLX5_L3_PROT_TYPE_IPV4);
1757 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1762 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1763 MLX5_L3_PROT_TYPE_IPV6);
1764 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1770 static int mlx5e_create_tir(struct mlx5e_priv *priv, int tt)
1772 struct mlx5_core_dev *mdev = priv->mdev;
1778 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1779 in = mlx5_vzalloc(inlen);
1783 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1785 mlx5e_build_tir_ctx(priv, tirc, tt);
1787 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
1794 static void mlx5e_destroy_tir(struct mlx5e_priv *priv, int tt)
1796 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
1799 static int mlx5e_create_tirs(struct mlx5e_priv *priv)
1804 for (i = 0; i < MLX5E_NUM_TT; i++) {
1805 err = mlx5e_create_tir(priv, i);
1807 goto err_destroy_tirs;
1813 for (i--; i >= 0; i--)
1814 mlx5e_destroy_tir(priv, i);
1819 static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
1823 for (i = 0; i < MLX5E_NUM_TT; i++)
1824 mlx5e_destroy_tir(priv, i);
1827 static struct rtnl_link_stats64 *
1828 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
1830 struct mlx5e_priv *priv = netdev_priv(dev);
1831 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
1833 stats->rx_packets = vstats->rx_packets;
1834 stats->rx_bytes = vstats->rx_bytes;
1835 stats->tx_packets = vstats->tx_packets;
1836 stats->tx_bytes = vstats->tx_bytes;
1837 stats->multicast = vstats->rx_multicast_packets +
1838 vstats->tx_multicast_packets;
1839 stats->tx_errors = vstats->tx_error_packets;
1840 stats->rx_errors = vstats->rx_error_packets;
1841 stats->tx_dropped = vstats->tx_queue_dropped;
1842 stats->rx_crc_errors = 0;
1843 stats->rx_length_errors = 0;
1848 static void mlx5e_set_rx_mode(struct net_device *dev)
1850 struct mlx5e_priv *priv = netdev_priv(dev);
1852 schedule_work(&priv->set_rx_mode_work);
1855 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
1857 struct mlx5e_priv *priv = netdev_priv(netdev);
1858 struct sockaddr *saddr = addr;
1860 if (!is_valid_ether_addr(saddr->sa_data))
1861 return -EADDRNOTAVAIL;
1863 netif_addr_lock_bh(netdev);
1864 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
1865 netif_addr_unlock_bh(netdev);
1867 schedule_work(&priv->set_rx_mode_work);
1872 static int mlx5e_set_features(struct net_device *netdev,
1873 netdev_features_t features)
1875 struct mlx5e_priv *priv = netdev_priv(netdev);
1877 netdev_features_t changes = features ^ netdev->features;
1879 mutex_lock(&priv->state_lock);
1881 if (changes & NETIF_F_LRO) {
1882 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1885 mlx5e_close_locked(priv->netdev);
1887 priv->params.lro_en = !!(features & NETIF_F_LRO);
1888 err = mlx5e_modify_tirs_lro(priv);
1890 mlx5_core_warn(priv->mdev, "lro modify failed, %d\n",
1894 err = mlx5e_open_locked(priv->netdev);
1897 mutex_unlock(&priv->state_lock);
1899 if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) {
1900 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1901 mlx5e_enable_vlan_filter(priv);
1903 mlx5e_disable_vlan_filter(priv);
1909 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
1911 struct mlx5e_priv *priv = netdev_priv(netdev);
1912 struct mlx5_core_dev *mdev = priv->mdev;
1917 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
1919 max_mtu = MLX5E_HW2SW_MTU(max_mtu);
1921 if (new_mtu > max_mtu) {
1923 "%s: Bad MTU (%d) > (%d) Max\n",
1924 __func__, new_mtu, max_mtu);
1928 mutex_lock(&priv->state_lock);
1930 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1932 mlx5e_close_locked(netdev);
1934 netdev->mtu = new_mtu;
1937 err = mlx5e_open_locked(netdev);
1939 mutex_unlock(&priv->state_lock);
1944 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1948 return mlx5e_hwstamp_set(dev, ifr);
1950 return mlx5e_hwstamp_get(dev, ifr);
1956 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
1958 struct mlx5e_priv *priv = netdev_priv(dev);
1959 struct mlx5_core_dev *mdev = priv->mdev;
1961 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
1964 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
1966 struct mlx5e_priv *priv = netdev_priv(dev);
1967 struct mlx5_core_dev *mdev = priv->mdev;
1969 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
1973 static int mlx5_vport_link2ifla(u8 esw_link)
1976 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
1977 return IFLA_VF_LINK_STATE_DISABLE;
1978 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
1979 return IFLA_VF_LINK_STATE_ENABLE;
1981 return IFLA_VF_LINK_STATE_AUTO;
1984 static int mlx5_ifla_link2vport(u8 ifla_link)
1986 switch (ifla_link) {
1987 case IFLA_VF_LINK_STATE_DISABLE:
1988 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
1989 case IFLA_VF_LINK_STATE_ENABLE:
1990 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
1992 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
1995 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
1998 struct mlx5e_priv *priv = netdev_priv(dev);
1999 struct mlx5_core_dev *mdev = priv->mdev;
2001 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2002 mlx5_ifla_link2vport(link_state));
2005 static int mlx5e_get_vf_config(struct net_device *dev,
2006 int vf, struct ifla_vf_info *ivi)
2008 struct mlx5e_priv *priv = netdev_priv(dev);
2009 struct mlx5_core_dev *mdev = priv->mdev;
2012 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2015 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2019 static int mlx5e_get_vf_stats(struct net_device *dev,
2020 int vf, struct ifla_vf_stats *vf_stats)
2022 struct mlx5e_priv *priv = netdev_priv(dev);
2023 struct mlx5_core_dev *mdev = priv->mdev;
2025 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2029 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2030 .ndo_open = mlx5e_open,
2031 .ndo_stop = mlx5e_close,
2032 .ndo_start_xmit = mlx5e_xmit,
2033 .ndo_get_stats64 = mlx5e_get_stats,
2034 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2035 .ndo_set_mac_address = mlx5e_set_mac,
2036 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2037 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2038 .ndo_set_features = mlx5e_set_features,
2039 .ndo_change_mtu = mlx5e_change_mtu,
2040 .ndo_do_ioctl = mlx5e_ioctl,
2043 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2044 .ndo_open = mlx5e_open,
2045 .ndo_stop = mlx5e_close,
2046 .ndo_start_xmit = mlx5e_xmit,
2047 .ndo_get_stats64 = mlx5e_get_stats,
2048 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2049 .ndo_set_mac_address = mlx5e_set_mac,
2050 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2051 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2052 .ndo_set_features = mlx5e_set_features,
2053 .ndo_change_mtu = mlx5e_change_mtu,
2054 .ndo_do_ioctl = mlx5e_ioctl,
2055 .ndo_set_vf_mac = mlx5e_set_vf_mac,
2056 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
2057 .ndo_get_vf_config = mlx5e_get_vf_config,
2058 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
2059 .ndo_get_vf_stats = mlx5e_get_vf_stats,
2062 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2064 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2066 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2067 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2068 !MLX5_CAP_ETH(mdev, csum_cap) ||
2069 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2070 !MLX5_CAP_ETH(mdev, vlan_cap) ||
2071 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2072 MLX5_CAP_FLOWTABLE(mdev,
2073 flow_table_properties_nic_receive.max_ft_level)
2075 mlx5_core_warn(mdev,
2076 "Not creating net device, some required device capabilities are missing\n");
2079 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2080 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2085 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2087 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2089 return bf_buf_size -
2090 sizeof(struct mlx5e_tx_wqe) +
2091 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2094 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
2099 for (i = 0; i < len; i++)
2100 indirection_rqt[i] = i % num_channels;
2103 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2104 struct net_device *netdev,
2107 struct mlx5e_priv *priv = netdev_priv(netdev);
2109 priv->params.log_sq_size =
2110 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2111 priv->params.log_rq_size =
2112 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2113 priv->params.rx_cq_moderation_usec =
2114 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2115 priv->params.rx_cq_moderation_pkts =
2116 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2117 priv->params.tx_cq_moderation_usec =
2118 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2119 priv->params.tx_cq_moderation_pkts =
2120 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2121 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
2122 priv->params.min_rx_wqes =
2123 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
2124 priv->params.num_tc = 1;
2125 priv->params.default_vlan_prio = 0;
2126 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
2128 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2129 sizeof(priv->params.toeplitz_hash_key));
2131 mlx5e_build_default_indir_rqt(priv->params.indirection_rqt,
2132 MLX5E_INDIR_RQT_SIZE, num_channels);
2134 priv->params.lro_wqe_sz =
2135 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2138 priv->netdev = netdev;
2139 priv->params.num_channels = num_channels;
2140 priv->default_vlan_prio = priv->params.default_vlan_prio;
2142 spin_lock_init(&priv->async_events_spinlock);
2143 mutex_init(&priv->state_lock);
2145 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2146 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2147 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2150 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2152 struct mlx5e_priv *priv = netdev_priv(netdev);
2154 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
2155 if (is_zero_ether_addr(netdev->dev_addr) &&
2156 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2157 eth_hw_addr_random(netdev);
2158 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2162 static void mlx5e_build_netdev(struct net_device *netdev)
2164 struct mlx5e_priv *priv = netdev_priv(netdev);
2165 struct mlx5_core_dev *mdev = priv->mdev;
2167 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2169 if (MLX5_CAP_GEN(mdev, vport_group_manager))
2170 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
2172 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
2174 netdev->watchdog_timeo = 15 * HZ;
2176 netdev->ethtool_ops = &mlx5e_ethtool_ops;
2178 netdev->vlan_features |= NETIF_F_SG;
2179 netdev->vlan_features |= NETIF_F_IP_CSUM;
2180 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
2181 netdev->vlan_features |= NETIF_F_GRO;
2182 netdev->vlan_features |= NETIF_F_TSO;
2183 netdev->vlan_features |= NETIF_F_TSO6;
2184 netdev->vlan_features |= NETIF_F_RXCSUM;
2185 netdev->vlan_features |= NETIF_F_RXHASH;
2187 if (!!MLX5_CAP_ETH(mdev, lro_cap))
2188 netdev->vlan_features |= NETIF_F_LRO;
2190 netdev->hw_features = netdev->vlan_features;
2191 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
2192 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
2193 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2195 netdev->features = netdev->hw_features;
2196 if (!priv->params.lro_en)
2197 netdev->features &= ~NETIF_F_LRO;
2199 netdev->features |= NETIF_F_HIGHDMA;
2201 netdev->priv_flags |= IFF_UNICAST_FLT;
2203 mlx5e_set_netdev_dev_addr(netdev);
2206 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2207 struct mlx5_core_mkey *mkey)
2209 struct mlx5_core_dev *mdev = priv->mdev;
2210 struct mlx5_create_mkey_mbox_in *in;
2213 in = mlx5_vzalloc(sizeof(*in));
2217 in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2218 MLX5_PERM_LOCAL_READ |
2219 MLX5_ACCESS_MODE_PA;
2220 in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2221 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2223 err = mlx5_core_create_mkey(mdev, mkey, in, sizeof(*in), NULL, NULL,
2231 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
2233 struct net_device *netdev;
2234 struct mlx5e_priv *priv;
2235 int nch = mlx5e_get_max_num_channels(mdev);
2238 if (mlx5e_check_required_hca_cap(mdev))
2241 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), nch, nch);
2243 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
2247 mlx5e_build_netdev_priv(mdev, netdev, nch);
2248 mlx5e_build_netdev(netdev);
2250 netif_carrier_off(netdev);
2252 priv = netdev_priv(netdev);
2254 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
2256 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
2257 goto err_free_netdev;
2260 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2262 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
2263 goto err_unmap_free_uar;
2266 err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
2268 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
2269 goto err_dealloc_pd;
2272 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mkey);
2274 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
2275 goto err_dealloc_transport_domain;
2278 err = mlx5e_create_tises(priv);
2280 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
2281 goto err_destroy_mkey;
2284 err = mlx5e_open_drop_rq(priv);
2286 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
2287 goto err_destroy_tises;
2290 err = mlx5e_create_rqt(priv, MLX5E_INDIRECTION_RQT);
2292 mlx5_core_warn(mdev, "create rqt(INDIR) failed, %d\n", err);
2293 goto err_close_drop_rq;
2296 err = mlx5e_create_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2298 mlx5_core_warn(mdev, "create rqt(SINGLE) failed, %d\n", err);
2299 goto err_destroy_rqt_indir;
2302 err = mlx5e_create_tirs(priv);
2304 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
2305 goto err_destroy_rqt_single;
2308 err = mlx5e_create_flow_tables(priv);
2310 mlx5_core_warn(mdev, "create flow tables failed, %d\n", err);
2311 goto err_destroy_tirs;
2314 mlx5e_init_eth_addr(priv);
2316 err = register_netdev(netdev);
2318 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
2319 goto err_destroy_flow_tables;
2322 mlx5e_enable_async_events(priv);
2323 schedule_work(&priv->set_rx_mode_work);
2327 err_destroy_flow_tables:
2328 mlx5e_destroy_flow_tables(priv);
2331 mlx5e_destroy_tirs(priv);
2333 err_destroy_rqt_single:
2334 mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2336 err_destroy_rqt_indir:
2337 mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2340 mlx5e_close_drop_rq(priv);
2343 mlx5e_destroy_tises(priv);
2346 mlx5_core_destroy_mkey(mdev, &priv->mkey);
2348 err_dealloc_transport_domain:
2349 mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
2352 mlx5_core_dealloc_pd(mdev, priv->pdn);
2355 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
2358 free_netdev(netdev);
2363 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
2365 struct mlx5e_priv *priv = vpriv;
2366 struct net_device *netdev = priv->netdev;
2368 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
2370 schedule_work(&priv->set_rx_mode_work);
2371 mlx5e_disable_async_events(priv);
2372 flush_scheduled_work();
2373 unregister_netdev(netdev);
2374 mlx5e_destroy_flow_tables(priv);
2375 mlx5e_destroy_tirs(priv);
2376 mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2377 mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2378 mlx5e_close_drop_rq(priv);
2379 mlx5e_destroy_tises(priv);
2380 mlx5_core_destroy_mkey(priv->mdev, &priv->mkey);
2381 mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
2382 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
2383 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
2384 free_netdev(netdev);
2387 static void *mlx5e_get_netdev(void *vpriv)
2389 struct mlx5e_priv *priv = vpriv;
2391 return priv->netdev;
2394 static struct mlx5_interface mlx5e_interface = {
2395 .add = mlx5e_create_netdev,
2396 .remove = mlx5e_destroy_netdev,
2397 .event = mlx5e_async_event,
2398 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
2399 .get_dev = mlx5e_get_netdev,
2402 void mlx5e_init(void)
2404 mlx5_register_interface(&mlx5e_interface);
2407 void mlx5e_cleanup(void)
2409 mlx5_unregister_interface(&mlx5e_interface);