drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <net/geneve.h>
  38 #include <linux/bpf.h>
  39 #include <linux/if_bridge.h>
  40 #include <net/page_pool.h>
  41 #include "eswitch.h"
  42 #include "en.h"
  43 #include "en_tc.h"
  44 #include "en_rep.h"
  45 #include "en_accel/ipsec.h"
  46 #include "en_accel/ipsec_rxtx.h"
  47 #include "en_accel/en_accel.h"
  48 #include "en_accel/tls.h"
  49 #include "accel/ipsec.h"
  50 #include "accel/tls.h"
  51 #include "lib/vxlan.h"
  52 #include "lib/clock.h"
  53 #include "en/port.h"
  54 #include "en/xdp.h"
  55 #include "lib/eq.h"
  56 #include "en/monitor_stats.h"
  57 #include "en/reporter.h"
  58 #include "en/params.h"
  59
  60 struct mlx5e_rq_param {
  61         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  62         struct mlx5_wq_param    wq;
  63         struct mlx5e_rq_frags_info frags_info;
  64 };
  65
  66 struct mlx5e_sq_param {
  67         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  68         struct mlx5_wq_param       wq;
  69         bool                       is_mpw;
  70 };
  71
  72 struct mlx5e_cq_param {
  73         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  74         struct mlx5_wq_param       wq;
  75         u16                        eq_ix;
  76         u8                         cq_period_mode;
  77 };
  78
  79 struct mlx5e_channel_param {
  80         struct mlx5e_rq_param      rq;
  81         struct mlx5e_sq_param      sq;
  82         struct mlx5e_sq_param      xdp_sq;
  83         struct mlx5e_sq_param      icosq;
  84         struct mlx5e_cq_param      rx_cq;
  85         struct mlx5e_cq_param      tx_cq;
  86         struct mlx5e_cq_param      icosq_cq;
  87 };
  88
  89 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  90 {
  91         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  92                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  93                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  94         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  95         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  96
  97         if (!striding_rq_umr)
  98                 return false;
  99         if (!inline_umr) {
 100                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
 101                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
 102                 return false;
 103         }
 104         return true;
 105 }
 106
 107 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
 108                                struct mlx5e_params *params)
 109 {
 110         params->log_rq_mtu_frames = is_kdump_kernel() ?
 111                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
 112                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
 113
 114         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
 115                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
 116                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
 117                        BIT(mlx5e_mpwqe_get_log_rq_size(params)) :
 118                        BIT(params->log_rq_mtu_frames),
 119                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)),
 120                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 121 }
 122
 123 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
 124                                 struct mlx5e_params *params)
 125 {
 126         return mlx5e_check_fragmented_striding_rq_cap(mdev) &&
 127                 !MLX5_IPSEC_DEV(mdev) &&
 128                 !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params));
 129 }
 130
 131 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
 132 {
 133         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
 134                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
 135                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 136                 MLX5_WQ_TYPE_CYCLIC;
 137 }
 138
 139 void mlx5e_update_carrier(struct mlx5e_priv *priv)
 140 {
 141         struct mlx5_core_dev *mdev = priv->mdev;
 142         u8 port_state;
 143
 144         port_state = mlx5_query_vport_state(mdev,
 145                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
 146                                             0);
 147
 148         if (port_state == VPORT_STATE_UP) {
 149                 netdev_info(priv->netdev, "Link up\n");
 150                 netif_carrier_on(priv->netdev);
 151         } else {
 152                 netdev_info(priv->netdev, "Link down\n");
 153                 netif_carrier_off(priv->netdev);
 154         }
 155 }
 156
 157 static void mlx5e_update_carrier_work(struct work_struct *work)
 158 {
 159         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 160                                                update_carrier_work);
 161
 162         mutex_lock(&priv->state_lock);
 163         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 164                 if (priv->profile->update_carrier)
 165                         priv->profile->update_carrier(priv);
 166         mutex_unlock(&priv->state_lock);
 167 }
 168
 169 void mlx5e_update_stats(struct mlx5e_priv *priv)
 170 {
 171         int i;
 172
 173         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 174                 if (mlx5e_stats_grps[i].update_stats)
 175                         mlx5e_stats_grps[i].update_stats(priv);
 176 }
 177
 178 void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
 179 {
 180         int i;
 181
 182         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 183                 if (mlx5e_stats_grps[i].update_stats_mask &
 184                     MLX5E_NDO_UPDATE_STATS)
 185                         mlx5e_stats_grps[i].update_stats(priv);
 186 }
 187
 188 static void mlx5e_update_stats_work(struct work_struct *work)
 189 {
 190         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 191                                                update_stats_work);
 192
 193         mutex_lock(&priv->state_lock);
 194         priv->profile->update_stats(priv);
 195         mutex_unlock(&priv->state_lock);
 196 }
 197
 198 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
 199 {
 200         if (!priv->profile->update_stats)
 201                 return;
 202
 203         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
 204                 return;
 205
 206         queue_work(priv->wq, &priv->update_stats_work);
 207 }
 208
 209 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
 210 {
 211         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
 212         struct mlx5_eqe   *eqe = data;
 213
 214         if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
 215                 return NOTIFY_DONE;
 216
 217         switch (eqe->sub_type) {
 218         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 219         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 220                 queue_work(priv->wq, &priv->update_carrier_work);
 221                 break;
 222         default:
 223                 return NOTIFY_DONE;
 224         }
 225
 226         return NOTIFY_OK;
 227 }
 228
 229 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 230 {
 231         priv->events_nb.notifier_call = async_event;
 232         mlx5_notifier_register(priv->mdev, &priv->events_nb);
 233 }
 234
 235 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 236 {
 237         mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
 238 }
 239
 240 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 241                                        struct mlx5e_icosq *sq,
 242                                        struct mlx5e_umr_wqe *wqe)
 243 {
 244         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 245         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 246         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 247
 248         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 249                                       ds_cnt);
 250         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 251         cseg->imm       = rq->mkey_be;
 252
 253         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 254         ucseg->xlt_octowords =
 255                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 256         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 257 }
 258
 259 static u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq)
 260 {
 261         switch (rq->wq_type) {
 262         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 263                 return mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 264         default:
 265                 return mlx5_wq_cyc_get_size(&rq->wqe.wq);
 266         }
 267 }
 268
 269 static u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq)
 270 {
 271         switch (rq->wq_type) {
 272         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 273                 return rq->mpwqe.wq.cur_sz;
 274         default:
 275                 return rq->wqe.wq.cur_sz;
 276         }
 277 }
 278
 279 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 280                                      struct mlx5e_channel *c)
 281 {
 282         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 283
 284         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 285                                                   sizeof(*rq->mpwqe.info)),
 286                                        GFP_KERNEL, cpu_to_node(c->cpu));
 287         if (!rq->mpwqe.info)
 288                 return -ENOMEM;
 289
 290         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
 291
 292         return 0;
 293 }
 294
 295 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 296                                  u64 npages, u8 page_shift,
 297                                  struct mlx5_core_mkey *umr_mkey)
 298 {
 299         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 300         void *mkc;
 301         u32 *in;
 302         int err;
 303
 304         in = kvzalloc(inlen, GFP_KERNEL);
 305         if (!in)
 306                 return -ENOMEM;
 307
 308         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 309
 310         MLX5_SET(mkc, mkc, free, 1);
 311         MLX5_SET(mkc, mkc, umr_en, 1);
 312         MLX5_SET(mkc, mkc, lw, 1);
 313         MLX5_SET(mkc, mkc, lr, 1);
 314         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 315
 316         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 317         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 318         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 319         MLX5_SET(mkc, mkc, translations_octword_size,
 320                  MLX5_MTT_OCTW(npages));
 321         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 322
 323         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 324
 325         kvfree(in);
 326         return err;
 327 }
 328
 329 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 330 {
 331         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 332
 333         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 334 }
 335
 336 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 337 {
 338         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
 339 }
 340
 341 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 342 {
 343         struct mlx5e_wqe_frag_info next_frag, *prev;
 344         int i;
 345
 346         next_frag.di = &rq->wqe.di[0];
 347         next_frag.offset = 0;
 348         prev = NULL;
 349
 350         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 351                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 352                 struct mlx5e_wqe_frag_info *frag =
 353                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 354                 int f;
 355
 356                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 357                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 358                                 next_frag.di++;
 359                                 next_frag.offset = 0;
 360                                 if (prev)
 361                                         prev->last_in_page = true;
 362                         }
 363                         *frag = next_frag;
 364
 365                         /* prepare next */
 366                         next_frag.offset += frag_info[f].frag_stride;
 367                         prev = frag;
 368                 }
 369         }
 370
 371         if (prev)
 372                 prev->last_in_page = true;
 373 }
 374
 375 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
 376                               int wq_sz, int cpu)
 377 {
 378         int len = wq_sz << rq->wqe.info.log_num_frags;
 379
 380         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
 381                                    GFP_KERNEL, cpu_to_node(cpu));
 382         if (!rq->wqe.di)
 383                 return -ENOMEM;
 384
 385         mlx5e_init_frags_partition(rq);
 386
 387         return 0;
 388 }
 389
 390 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
 391 {
 392         kvfree(rq->wqe.di);
 393 }
 394
 395 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 396                           struct mlx5e_params *params,
 397                           struct mlx5e_rq_param *rqp,
 398                           struct mlx5e_rq *rq)
 399 {
 400         struct page_pool_params pp_params = { 0 };
 401         struct mlx5_core_dev *mdev = c->mdev;
 402         void *rqc = rqp->rqc;
 403         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 404         u32 pool_size;
 405         int wq_sz;
 406         int err;
 407         int i;
 408
 409         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
 410
 411         rq->wq_type = params->rq_wq_type;
 412         rq->pdev    = c->pdev;
 413         rq->netdev  = c->netdev;
 414         rq->tstamp  = c->tstamp;
 415         rq->clock   = &mdev->clock;
 416         rq->channel = c;
 417         rq->ix      = c->ix;
 418         rq->mdev    = mdev;
 419         rq->hw_mtu  = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 420         rq->stats   = &c->priv->channel_stats[c->ix].rq;
 421
 422         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
 423         if (IS_ERR(rq->xdp_prog)) {
 424                 err = PTR_ERR(rq->xdp_prog);
 425                 rq->xdp_prog = NULL;
 426                 goto err_rq_wq_destroy;
 427         }
 428
 429         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
 430         if (err < 0)
 431                 goto err_rq_wq_destroy;
 432
 433         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 434         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params);
 435         pool_size = 1 << params->log_rq_mtu_frames;
 436
 437         switch (rq->wq_type) {
 438         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 439                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 440                                         &rq->wq_ctrl);
 441                 if (err)
 442                         return err;
 443
 444                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 445
 446                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 447
 448                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE << mlx5e_mpwqe_get_log_rq_size(params);
 449
 450                 rq->post_wqes = mlx5e_post_rx_mpwqes;
 451                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 452
 453                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
 454 #ifdef CONFIG_MLX5_EN_IPSEC
 455                 if (MLX5_IPSEC_DEV(mdev)) {
 456                         err = -EINVAL;
 457                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
 458                         goto err_rq_wq_destroy;
 459                 }
 460 #endif
 461                 if (!rq->handle_rx_cqe) {
 462                         err = -EINVAL;
 463                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
 464                         goto err_rq_wq_destroy;
 465                 }
 466
 467                 rq->mpwqe.skb_from_cqe_mpwrq =
 468                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ?
 469                         mlx5e_skb_from_cqe_mpwrq_linear :
 470                         mlx5e_skb_from_cqe_mpwrq_nonlinear;
 471                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params);
 472                 rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params));
 473
 474                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 475                 if (err)
 476                         goto err_rq_wq_destroy;
 477                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 478
 479                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 480                 if (err)
 481                         goto err_free;
 482                 break;
 483         default: /* MLX5_WQ_TYPE_CYCLIC */
 484                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 485                                          &rq->wq_ctrl);
 486                 if (err)
 487                         return err;
 488
 489                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 490
 491                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 492
 493                 rq->wqe.info = rqp->frags_info;
 494                 rq->wqe.frags =
 495                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 496                                         (wq_sz << rq->wqe.info.log_num_frags)),
 497                                       GFP_KERNEL, cpu_to_node(c->cpu));
 498                 if (!rq->wqe.frags) {
 499                         err = -ENOMEM;
 500                         goto err_free;
 501                 }
 502
 503                 err = mlx5e_init_di_list(rq, wq_sz, c->cpu);
 504                 if (err)
 505                         goto err_free;
 506                 rq->post_wqes = mlx5e_post_rx_wqes;
 507                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 508
 509 #ifdef CONFIG_MLX5_EN_IPSEC
 510                 if (c->priv->ipsec)
 511                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
 512                 else
 513 #endif
 514                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
 515                 if (!rq->handle_rx_cqe) {
 516                         err = -EINVAL;
 517                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
 518                         goto err_free;
 519                 }
 520
 521                 rq->wqe.skb_from_cqe = mlx5e_rx_is_linear_skb(params) ?
 522                         mlx5e_skb_from_cqe_linear :
 523                         mlx5e_skb_from_cqe_nonlinear;
 524                 rq->mkey_be = c->mkey_be;
 525         }
 526
 527         /* Create a page_pool and register it with rxq */
 528         pp_params.order     = 0;
 529         pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 530         pp_params.pool_size = pool_size;
 531         pp_params.nid       = cpu_to_node(c->cpu);
 532         pp_params.dev       = c->pdev;
 533         pp_params.dma_dir   = rq->buff.map_dir;
 534
 535         /* page_pool can be used even when there is no rq->xdp_prog,
 536          * given page_pool does not handle DMA mapping there is no
 537          * required state to clear. And page_pool gracefully handle
 538          * elevated refcnt.
 539          */
 540         rq->page_pool = page_pool_create(&pp_params);
 541         if (IS_ERR(rq->page_pool)) {
 542                 err = PTR_ERR(rq->page_pool);
 543                 rq->page_pool = NULL;
 544                 goto err_free;
 545         }
 546         err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 547                                          MEM_TYPE_PAGE_POOL, rq->page_pool);
 548         if (err)
 549                 goto err_free;
 550
 551         for (i = 0; i < wq_sz; i++) {
 552                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 553                         struct mlx5e_rx_wqe_ll *wqe =
 554                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 555                         u32 byte_count =
 556                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 557                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
 558
 559                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 560                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 561                         wqe->data[0].lkey = rq->mkey_be;
 562                 } else {
 563                         struct mlx5e_rx_wqe_cyc *wqe =
 564                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 565                         int f;
 566
 567                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 568                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 569                                         MLX5_HW_START_PADDING;
 570
 571                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 572                                 wqe->data[f].lkey = rq->mkey_be;
 573                         }
 574                         /* check if num_frags is not a pow of two */
 575                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 576                                 wqe->data[f].byte_count = 0;
 577                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 578                                 wqe->data[f].addr = 0;
 579                         }
 580                 }
 581         }
 582
 583         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 584
 585         switch (params->rx_cq_moderation.cq_period_mode) {
 586         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 587                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 588                 break;
 589         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 590         default:
 591                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 592         }
 593
 594         rq->page_cache.head = 0;
 595         rq->page_cache.tail = 0;
 596
 597         return 0;
 598
 599 err_free:
 600         switch (rq->wq_type) {
 601         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 602                 kvfree(rq->mpwqe.info);
 603                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 604                 break;
 605         default: /* MLX5_WQ_TYPE_CYCLIC */
 606                 kvfree(rq->wqe.frags);
 607                 mlx5e_free_di_list(rq);
 608         }
 609
 610 err_rq_wq_destroy:
 611         if (rq->xdp_prog)
 612                 bpf_prog_put(rq->xdp_prog);
 613         xdp_rxq_info_unreg(&rq->xdp_rxq);
 614         if (rq->page_pool)
 615                 page_pool_destroy(rq->page_pool);
 616         mlx5_wq_destroy(&rq->wq_ctrl);
 617
 618         return err;
 619 }
 620
 621 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 622 {
 623         int i;
 624
 625         if (rq->xdp_prog)
 626                 bpf_prog_put(rq->xdp_prog);
 627
 628         xdp_rxq_info_unreg(&rq->xdp_rxq);
 629         if (rq->page_pool)
 630                 page_pool_destroy(rq->page_pool);
 631
 632         switch (rq->wq_type) {
 633         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 634                 kvfree(rq->mpwqe.info);
 635                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 636                 break;
 637         default: /* MLX5_WQ_TYPE_CYCLIC */
 638                 kvfree(rq->wqe.frags);
 639                 mlx5e_free_di_list(rq);
 640         }
 641
 642         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 643              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 644                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 645
 646                 mlx5e_page_release(rq, dma_info, false);
 647         }
 648         mlx5_wq_destroy(&rq->wq_ctrl);
 649 }
 650
 651 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 652                            struct mlx5e_rq_param *param)
 653 {
 654         struct mlx5_core_dev *mdev = rq->mdev;
 655
 656         void *in;
 657         void *rqc;
 658         void *wq;
 659         int inlen;
 660         int err;
 661
 662         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 663                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 664         in = kvzalloc(inlen, GFP_KERNEL);
 665         if (!in)
 666                 return -ENOMEM;
 667
 668         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 669         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 670
 671         memcpy(rqc, param->rqc, sizeof(param->rqc));
 672
 673         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 674         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 675         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 676                                                 MLX5_ADAPTER_PAGE_SHIFT);
 677         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 678
 679         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 680                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 681
 682         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 683
 684         kvfree(in);
 685
 686         return err;
 687 }
 688
 689 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 690                                  int next_state)
 691 {
 692         struct mlx5_core_dev *mdev = rq->mdev;
 693
 694         void *in;
 695         void *rqc;
 696         int inlen;
 697         int err;
 698
 699         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 700         in = kvzalloc(inlen, GFP_KERNEL);
 701         if (!in)
 702                 return -ENOMEM;
 703
 704         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 705
 706         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 707         MLX5_SET(rqc, rqc, state, next_state);
 708
 709         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 710
 711         kvfree(in);
 712
 713         return err;
 714 }
 715
 716 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 717 {
 718         struct mlx5e_channel *c = rq->channel;
 719         struct mlx5e_priv *priv = c->priv;
 720         struct mlx5_core_dev *mdev = priv->mdev;
 721
 722         void *in;
 723         void *rqc;
 724         int inlen;
 725         int err;
 726
 727         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 728         in = kvzalloc(inlen, GFP_KERNEL);
 729         if (!in)
 730                 return -ENOMEM;
 731
 732         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 733
 734         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 735         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 736                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 737         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 738         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 739
 740         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 741
 742         kvfree(in);
 743
 744         return err;
 745 }
 746
 747 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 748 {
 749         struct mlx5e_channel *c = rq->channel;
 750         struct mlx5_core_dev *mdev = c->mdev;
 751         void *in;
 752         void *rqc;
 753         int inlen;
 754         int err;
 755
 756         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 757         in = kvzalloc(inlen, GFP_KERNEL);
 758         if (!in)
 759                 return -ENOMEM;
 760
 761         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 762
 763         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 764         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 765                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 766         MLX5_SET(rqc, rqc, vsd, vsd);
 767         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 768
 769         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 770
 771         kvfree(in);
 772
 773         return err;
 774 }
 775
 776 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 777 {
 778         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 779 }
 780
 781 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 782 {
 783         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 784         struct mlx5e_channel *c = rq->channel;
 785
 786         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 787
 788         do {
 789                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 790                         return 0;
 791
 792                 msleep(20);
 793         } while (time_before(jiffies, exp_time));
 794
 795         netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 796                     c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 797
 798         return -ETIMEDOUT;
 799 }
 800
 801 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 802 {
 803         __be16 wqe_ix_be;
 804         u16 wqe_ix;
 805
 806         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 807                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 808                 u16 head = wq->head;
 809                 int i;
 810
 811                 /* Outstanding UMR WQEs (in progress) start at wq->head */
 812                 for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
 813                         rq->dealloc_wqe(rq, head);
 814                         head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
 815                 }
 816
 817                 while (!mlx5_wq_ll_is_empty(wq)) {
 818                         struct mlx5e_rx_wqe_ll *wqe;
 819
 820                         wqe_ix_be = *wq->tail_next;
 821                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 822                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 823                         rq->dealloc_wqe(rq, wqe_ix);
 824                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 825                                        &wqe->next.next_wqe_index);
 826                 }
 827         } else {
 828                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 829
 830                 while (!mlx5_wq_cyc_is_empty(wq)) {
 831                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
 832                         rq->dealloc_wqe(rq, wqe_ix);
 833                         mlx5_wq_cyc_pop(wq);
 834                 }
 835         }
 836
 837 }
 838
 839 static int mlx5e_open_rq(struct mlx5e_channel *c,
 840                          struct mlx5e_params *params,
 841                          struct mlx5e_rq_param *param,
 842                          struct mlx5e_rq *rq)
 843 {
 844         int err;
 845
 846         err = mlx5e_alloc_rq(c, params, param, rq);
 847         if (err)
 848                 return err;
 849
 850         err = mlx5e_create_rq(rq, param);
 851         if (err)
 852                 goto err_free_rq;
 853
 854         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 855         if (err)
 856                 goto err_destroy_rq;
 857
 858         if (params->rx_dim_enabled)
 859                 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 860
 861         /* We disable csum_complete when XDP is enabled since
 862          * XDP programs might manipulate packets which will render
 863          * skb->checksum incorrect.
 864          */
 865         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || c->xdp)
 866                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
 867
 868         return 0;
 869
 870 err_destroy_rq:
 871         mlx5e_destroy_rq(rq);
 872 err_free_rq:
 873         mlx5e_free_rq(rq);
 874
 875         return err;
 876 }
 877
 878 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
 879 {
 880         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 881         mlx5e_trigger_irq(&rq->channel->icosq);
 882 }
 883
 884 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 885 {
 886         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 887         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 888 }
 889
 890 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 891 {
 892         cancel_work_sync(&rq->dim.work);
 893         mlx5e_destroy_rq(rq);
 894         mlx5e_free_rx_descs(rq);
 895         mlx5e_free_rq(rq);
 896 }
 897
 898 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 899 {
 900         kvfree(sq->db.xdpi_fifo.xi);
 901         kvfree(sq->db.wqe_info);
 902 }
 903
 904 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
 905 {
 906         struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
 907         int wq_sz        = mlx5_wq_cyc_get_size(&sq->wq);
 908         int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 909
 910         xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq,
 911                                       GFP_KERNEL, numa);
 912         if (!xdpi_fifo->xi)
 913                 return -ENOMEM;
 914
 915         xdpi_fifo->pc   = &sq->xdpi_fifo_pc;
 916         xdpi_fifo->cc   = &sq->xdpi_fifo_cc;
 917         xdpi_fifo->mask = dsegs_per_wq - 1;
 918
 919         return 0;
 920 }
 921
 922 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 923 {
 924         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 925         int err;
 926
 927         sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz,
 928                                         GFP_KERNEL, numa);
 929         if (!sq->db.wqe_info)
 930                 return -ENOMEM;
 931
 932         err = mlx5e_alloc_xdpsq_fifo(sq, numa);
 933         if (err) {
 934                 mlx5e_free_xdpsq_db(sq);
 935                 return err;
 936         }
 937
 938         return 0;
 939 }
 940
 941 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 942                              struct mlx5e_params *params,
 943                              struct mlx5e_sq_param *param,
 944                              struct mlx5e_xdpsq *sq,
 945                              bool is_redirect)
 946 {
 947         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 948         struct mlx5_core_dev *mdev = c->mdev;
 949         struct mlx5_wq_cyc *wq = &sq->wq;
 950         int err;
 951
 952         sq->pdev      = c->pdev;
 953         sq->mkey_be   = c->mkey_be;
 954         sq->channel   = c;
 955         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
 956         sq->min_inline_mode = params->tx_min_inline_mode;
 957         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 958         sq->stats     = is_redirect ?
 959                 &c->priv->channel_stats[c->ix].xdpsq :
 960                 &c->priv->channel_stats[c->ix].rq_xdpsq;
 961
 962         param->wq.db_numa_node = cpu_to_node(c->cpu);
 963         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
 964         if (err)
 965                 return err;
 966         wq->db = &wq->db[MLX5_SND_DBR];
 967
 968         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
 969         if (err)
 970                 goto err_sq_wq_destroy;
 971
 972         return 0;
 973
 974 err_sq_wq_destroy:
 975         mlx5_wq_destroy(&sq->wq_ctrl);
 976
 977         return err;
 978 }
 979
 980 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
 981 {
 982         mlx5e_free_xdpsq_db(sq);
 983         mlx5_wq_destroy(&sq->wq_ctrl);
 984 }
 985
 986 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
 987 {
 988         kvfree(sq->db.ico_wqe);
 989 }
 990
 991 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
 992 {
 993         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 994
 995         sq->db.ico_wqe = kvzalloc_node(array_size(wq_sz,
 996                                                   sizeof(*sq->db.ico_wqe)),
 997                                        GFP_KERNEL, numa);
 998         if (!sq->db.ico_wqe)
 999                 return -ENOMEM;
1000
1001         return 0;
1002 }
1003
1004 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1005                              struct mlx5e_sq_param *param,
1006                              struct mlx5e_icosq *sq)
1007 {
1008         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1009         struct mlx5_core_dev *mdev = c->mdev;
1010         struct mlx5_wq_cyc *wq = &sq->wq;
1011         int err;
1012
1013         sq->channel   = c;
1014         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1015
1016         param->wq.db_numa_node = cpu_to_node(c->cpu);
1017         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1018         if (err)
1019                 return err;
1020         wq->db = &wq->db[MLX5_SND_DBR];
1021
1022         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1023         if (err)
1024                 goto err_sq_wq_destroy;
1025
1026         return 0;
1027
1028 err_sq_wq_destroy:
1029         mlx5_wq_destroy(&sq->wq_ctrl);
1030
1031         return err;
1032 }
1033
1034 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1035 {
1036         mlx5e_free_icosq_db(sq);
1037         mlx5_wq_destroy(&sq->wq_ctrl);
1038 }
1039
1040 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1041 {
1042         kvfree(sq->db.wqe_info);
1043         kvfree(sq->db.dma_fifo);
1044 }
1045
1046 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1047 {
1048         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1049         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1050
1051         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1052                                                    sizeof(*sq->db.dma_fifo)),
1053                                         GFP_KERNEL, numa);
1054         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1055                                                    sizeof(*sq->db.wqe_info)),
1056                                         GFP_KERNEL, numa);
1057         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1058                 mlx5e_free_txqsq_db(sq);
1059                 return -ENOMEM;
1060         }
1061
1062         sq->dma_fifo_mask = df_sz - 1;
1063
1064         return 0;
1065 }
1066
1067 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1068 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1069                              int txq_ix,
1070                              struct mlx5e_params *params,
1071                              struct mlx5e_sq_param *param,
1072                              struct mlx5e_txqsq *sq,
1073                              int tc)
1074 {
1075         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1076         struct mlx5_core_dev *mdev = c->mdev;
1077         struct mlx5_wq_cyc *wq = &sq->wq;
1078         int err;
1079
1080         sq->pdev      = c->pdev;
1081         sq->tstamp    = c->tstamp;
1082         sq->clock     = &mdev->clock;
1083         sq->mkey_be   = c->mkey_be;
1084         sq->channel   = c;
1085         sq->txq_ix    = txq_ix;
1086         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1087         sq->min_inline_mode = params->tx_min_inline_mode;
1088         sq->stats     = &c->priv->channel_stats[c->ix].sq[tc];
1089         INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1090         if (MLX5_IPSEC_DEV(c->priv->mdev))
1091                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1092         if (mlx5_accel_is_tls_device(c->priv->mdev))
1093                 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1094
1095         param->wq.db_numa_node = cpu_to_node(c->cpu);
1096         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1097         if (err)
1098                 return err;
1099         wq->db    = &wq->db[MLX5_SND_DBR];
1100
1101         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1102         if (err)
1103                 goto err_sq_wq_destroy;
1104
1105         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1106         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1107
1108         return 0;
1109
1110 err_sq_wq_destroy:
1111         mlx5_wq_destroy(&sq->wq_ctrl);
1112
1113         return err;
1114 }
1115
1116 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1117 {
1118         mlx5e_free_txqsq_db(sq);
1119         mlx5_wq_destroy(&sq->wq_ctrl);
1120 }
1121
1122 struct mlx5e_create_sq_param {
1123         struct mlx5_wq_ctrl        *wq_ctrl;
1124         u32                         cqn;
1125         u32                         tisn;
1126         u8                          tis_lst_sz;
1127         u8                          min_inline_mode;
1128 };
1129
1130 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1131                            struct mlx5e_sq_param *param,
1132                            struct mlx5e_create_sq_param *csp,
1133                            u32 *sqn)
1134 {
1135         void *in;
1136         void *sqc;
1137         void *wq;
1138         int inlen;
1139         int err;
1140
1141         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1142                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1143         in = kvzalloc(inlen, GFP_KERNEL);
1144         if (!in)
1145                 return -ENOMEM;
1146
1147         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1148         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1149
1150         memcpy(sqc, param->sqc, sizeof(param->sqc));
1151         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1152         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1153         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1154
1155         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1156                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1157
1158         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1159         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1160
1161         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1162         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1163         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1164                                           MLX5_ADAPTER_PAGE_SHIFT);
1165         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1166
1167         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1168                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1169
1170         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1171
1172         kvfree(in);
1173
1174         return err;
1175 }
1176
1177 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1178                     struct mlx5e_modify_sq_param *p)
1179 {
1180         void *in;
1181         void *sqc;
1182         int inlen;
1183         int err;
1184
1185         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1186         in = kvzalloc(inlen, GFP_KERNEL);
1187         if (!in)
1188                 return -ENOMEM;
1189
1190         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1191
1192         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1193         MLX5_SET(sqc, sqc, state, p->next_state);
1194         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1195                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1196                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1197         }
1198
1199         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1200
1201         kvfree(in);
1202
1203         return err;
1204 }
1205
1206 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1207 {
1208         mlx5_core_destroy_sq(mdev, sqn);
1209 }
1210
1211 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1212                                struct mlx5e_sq_param *param,
1213                                struct mlx5e_create_sq_param *csp,
1214                                u32 *sqn)
1215 {
1216         struct mlx5e_modify_sq_param msp = {0};
1217         int err;
1218
1219         err = mlx5e_create_sq(mdev, param, csp, sqn);
1220         if (err)
1221                 return err;
1222
1223         msp.curr_state = MLX5_SQC_STATE_RST;
1224         msp.next_state = MLX5_SQC_STATE_RDY;
1225         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1226         if (err)
1227                 mlx5e_destroy_sq(mdev, *sqn);
1228
1229         return err;
1230 }
1231
1232 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1233                                 struct mlx5e_txqsq *sq, u32 rate);
1234
1235 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1236                             u32 tisn,
1237                             int txq_ix,
1238                             struct mlx5e_params *params,
1239                             struct mlx5e_sq_param *param,
1240                             struct mlx5e_txqsq *sq,
1241                             int tc)
1242 {
1243         struct mlx5e_create_sq_param csp = {};
1244         u32 tx_rate;
1245         int err;
1246
1247         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1248         if (err)
1249                 return err;
1250
1251         csp.tisn            = tisn;
1252         csp.tis_lst_sz      = 1;
1253         csp.cqn             = sq->cq.mcq.cqn;
1254         csp.wq_ctrl         = &sq->wq_ctrl;
1255         csp.min_inline_mode = sq->min_inline_mode;
1256         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1257         if (err)
1258                 goto err_free_txqsq;
1259
1260         tx_rate = c->priv->tx_rates[sq->txq_ix];
1261         if (tx_rate)
1262                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1263
1264         if (params->tx_dim_enabled)
1265                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1266
1267         return 0;
1268
1269 err_free_txqsq:
1270         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1271         mlx5e_free_txqsq(sq);
1272
1273         return err;
1274 }
1275
1276 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1277 {
1278         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1279         clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
1280         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1281         netdev_tx_reset_queue(sq->txq);
1282         netif_tx_start_queue(sq->txq);
1283 }
1284
1285 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1286 {
1287         __netif_tx_lock_bh(txq);
1288         netif_tx_stop_queue(txq);
1289         __netif_tx_unlock_bh(txq);
1290 }
1291
1292 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1293 {
1294         struct mlx5e_channel *c = sq->channel;
1295         struct mlx5_wq_cyc *wq = &sq->wq;
1296
1297         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1298         /* prevent netif_tx_wake_queue */
1299         napi_synchronize(&c->napi);
1300
1301         mlx5e_tx_disable_queue(sq->txq);
1302
1303         /* last doorbell out, godspeed .. */
1304         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1305                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1306                 struct mlx5e_tx_wqe *nop;
1307
1308                 sq->db.wqe_info[pi].skb = NULL;
1309                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1310                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1311         }
1312 }
1313
1314 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1315 {
1316         struct mlx5e_channel *c = sq->channel;
1317         struct mlx5_core_dev *mdev = c->mdev;
1318         struct mlx5_rate_limit rl = {0};
1319
1320         cancel_work_sync(&sq->dim.work);
1321         cancel_work_sync(&sq->recover_work);
1322         mlx5e_destroy_sq(mdev, sq->sqn);
1323         if (sq->rate_limit) {
1324                 rl.rate = sq->rate_limit;
1325                 mlx5_rl_remove_rate(mdev, &rl);
1326         }
1327         mlx5e_free_txqsq_descs(sq);
1328         mlx5e_free_txqsq(sq);
1329 }
1330
1331 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1332 {
1333         struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1334                                               recover_work);
1335
1336         mlx5e_tx_reporter_err_cqe(sq);
1337 }
1338
1339 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1340                             struct mlx5e_params *params,
1341                             struct mlx5e_sq_param *param,
1342                             struct mlx5e_icosq *sq)
1343 {
1344         struct mlx5e_create_sq_param csp = {};
1345         int err;
1346
1347         err = mlx5e_alloc_icosq(c, param, sq);
1348         if (err)
1349                 return err;
1350
1351         csp.cqn             = sq->cq.mcq.cqn;
1352         csp.wq_ctrl         = &sq->wq_ctrl;
1353         csp.min_inline_mode = params->tx_min_inline_mode;
1354         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1355         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1356         if (err)
1357                 goto err_free_icosq;
1358
1359         return 0;
1360
1361 err_free_icosq:
1362         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1363         mlx5e_free_icosq(sq);
1364
1365         return err;
1366 }
1367
1368 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1369 {
1370         struct mlx5e_channel *c = sq->channel;
1371
1372         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1373         napi_synchronize(&c->napi);
1374
1375         mlx5e_destroy_sq(c->mdev, sq->sqn);
1376         mlx5e_free_icosq(sq);
1377 }
1378
1379 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1380                             struct mlx5e_params *params,
1381                             struct mlx5e_sq_param *param,
1382                             struct mlx5e_xdpsq *sq,
1383                             bool is_redirect)
1384 {
1385         struct mlx5e_create_sq_param csp = {};
1386         int err;
1387
1388         err = mlx5e_alloc_xdpsq(c, params, param, sq, is_redirect);
1389         if (err)
1390                 return err;
1391
1392         csp.tis_lst_sz      = 1;
1393         csp.tisn            = c->priv->tisn[0]; /* tc = 0 */
1394         csp.cqn             = sq->cq.mcq.cqn;
1395         csp.wq_ctrl         = &sq->wq_ctrl;
1396         csp.min_inline_mode = sq->min_inline_mode;
1397         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1398         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1399         if (err)
1400                 goto err_free_xdpsq;
1401
1402         mlx5e_set_xmit_fp(sq, param->is_mpw);
1403
1404         if (!param->is_mpw) {
1405                 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1406                 unsigned int inline_hdr_sz = 0;
1407                 int i;
1408
1409                 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1410                         inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1411                         ds_cnt++;
1412                 }
1413
1414                 /* Pre initialize fixed WQE fields */
1415                 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1416                         struct mlx5e_xdp_wqe_info *wi  = &sq->db.wqe_info[i];
1417                         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1418                         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1419                         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1420                         struct mlx5_wqe_data_seg *dseg;
1421
1422                         cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1423                         eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1424
1425                         dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1426                         dseg->lkey = sq->mkey_be;
1427
1428                         wi->num_wqebbs = 1;
1429                         wi->num_pkts   = 1;
1430                 }
1431         }
1432
1433         return 0;
1434
1435 err_free_xdpsq:
1436         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1437         mlx5e_free_xdpsq(sq);
1438
1439         return err;
1440 }
1441
1442 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq, struct mlx5e_rq *rq)
1443 {
1444         struct mlx5e_channel *c = sq->channel;
1445
1446         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1447         napi_synchronize(&c->napi);
1448
1449         mlx5e_destroy_sq(c->mdev, sq->sqn);
1450         mlx5e_free_xdpsq_descs(sq, rq);
1451         mlx5e_free_xdpsq(sq);
1452 }
1453
1454 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1455                                  struct mlx5e_cq_param *param,
1456                                  struct mlx5e_cq *cq)
1457 {
1458         struct mlx5_core_cq *mcq = &cq->mcq;
1459         int eqn_not_used;
1460         unsigned int irqn;
1461         int err;
1462         u32 i;
1463
1464         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1465         if (err)
1466                 return err;
1467
1468         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1469                                &cq->wq_ctrl);
1470         if (err)
1471                 return err;
1472
1473         mcq->cqe_sz     = 64;
1474         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1475         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1476         *mcq->set_ci_db = 0;
1477         *mcq->arm_db    = 0;
1478         mcq->vector     = param->eq_ix;
1479         mcq->comp       = mlx5e_completion_event;
1480         mcq->event      = mlx5e_cq_error_event;
1481         mcq->irqn       = irqn;
1482
1483         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1484                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1485
1486                 cqe->op_own = 0xf1;
1487         }
1488
1489         cq->mdev = mdev;
1490
1491         return 0;
1492 }
1493
1494 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1495                           struct mlx5e_cq_param *param,
1496                           struct mlx5e_cq *cq)
1497 {
1498         struct mlx5_core_dev *mdev = c->priv->mdev;
1499         int err;
1500
1501         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1502         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1503         param->eq_ix   = c->ix;
1504
1505         err = mlx5e_alloc_cq_common(mdev, param, cq);
1506
1507         cq->napi    = &c->napi;
1508         cq->channel = c;
1509
1510         return err;
1511 }
1512
1513 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1514 {
1515         mlx5_wq_destroy(&cq->wq_ctrl);
1516 }
1517
1518 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1519 {
1520         struct mlx5_core_dev *mdev = cq->mdev;
1521         struct mlx5_core_cq *mcq = &cq->mcq;
1522
1523         void *in;
1524         void *cqc;
1525         int inlen;
1526         unsigned int irqn_not_used;
1527         int eqn;
1528         int err;
1529
1530         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1531         if (err)
1532                 return err;
1533
1534         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1535                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1536         in = kvzalloc(inlen, GFP_KERNEL);
1537         if (!in)
1538                 return -ENOMEM;
1539
1540         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1541
1542         memcpy(cqc, param->cqc, sizeof(param->cqc));
1543
1544         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1545                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1546
1547         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1548         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1549         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1550         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1551                                             MLX5_ADAPTER_PAGE_SHIFT);
1552         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1553
1554         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1555
1556         kvfree(in);
1557
1558         if (err)
1559                 return err;
1560
1561         mlx5e_cq_arm(cq);
1562
1563         return 0;
1564 }
1565
1566 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1567 {
1568         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1569 }
1570
1571 static int mlx5e_open_cq(struct mlx5e_channel *c,
1572                          struct net_dim_cq_moder moder,
1573                          struct mlx5e_cq_param *param,
1574                          struct mlx5e_cq *cq)
1575 {
1576         struct mlx5_core_dev *mdev = c->mdev;
1577         int err;
1578
1579         err = mlx5e_alloc_cq(c, param, cq);
1580         if (err)
1581                 return err;
1582
1583         err = mlx5e_create_cq(cq, param);
1584         if (err)
1585                 goto err_free_cq;
1586
1587         if (MLX5_CAP_GEN(mdev, cq_moderation))
1588                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1589         return 0;
1590
1591 err_free_cq:
1592         mlx5e_free_cq(cq);
1593
1594         return err;
1595 }
1596
1597 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1598 {
1599         mlx5e_destroy_cq(cq);
1600         mlx5e_free_cq(cq);
1601 }
1602
1603 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1604                              struct mlx5e_params *params,
1605                              struct mlx5e_channel_param *cparam)
1606 {
1607         int err;
1608         int tc;
1609
1610         for (tc = 0; tc < c->num_tc; tc++) {
1611                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1612                                     &cparam->tx_cq, &c->sq[tc].cq);
1613                 if (err)
1614                         goto err_close_tx_cqs;
1615         }
1616
1617         return 0;
1618
1619 err_close_tx_cqs:
1620         for (tc--; tc >= 0; tc--)
1621                 mlx5e_close_cq(&c->sq[tc].cq);
1622
1623         return err;
1624 }
1625
1626 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1627 {
1628         int tc;
1629
1630         for (tc = 0; tc < c->num_tc; tc++)
1631                 mlx5e_close_cq(&c->sq[tc].cq);
1632 }
1633
1634 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1635                           struct mlx5e_params *params,
1636                           struct mlx5e_channel_param *cparam)
1637 {
1638         struct mlx5e_priv *priv = c->priv;
1639         int err, tc, max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
1640
1641         for (tc = 0; tc < params->num_tc; tc++) {
1642                 int txq_ix = c->ix + tc * max_nch;
1643
1644                 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1645                                        params, &cparam->sq, &c->sq[tc], tc);
1646                 if (err)
1647                         goto err_close_sqs;
1648         }
1649
1650         return 0;
1651
1652 err_close_sqs:
1653         for (tc--; tc >= 0; tc--)
1654                 mlx5e_close_txqsq(&c->sq[tc]);
1655
1656         return err;
1657 }
1658
1659 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1660 {
1661         int tc;
1662
1663         for (tc = 0; tc < c->num_tc; tc++)
1664                 mlx5e_close_txqsq(&c->sq[tc]);
1665 }
1666
1667 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1668                                 struct mlx5e_txqsq *sq, u32 rate)
1669 {
1670         struct mlx5e_priv *priv = netdev_priv(dev);
1671         struct mlx5_core_dev *mdev = priv->mdev;
1672         struct mlx5e_modify_sq_param msp = {0};
1673         struct mlx5_rate_limit rl = {0};
1674         u16 rl_index = 0;
1675         int err;
1676
1677         if (rate == sq->rate_limit)
1678                 /* nothing to do */
1679                 return 0;
1680
1681         if (sq->rate_limit) {
1682                 rl.rate = sq->rate_limit;
1683                 /* remove current rl index to free space to next ones */
1684                 mlx5_rl_remove_rate(mdev, &rl);
1685         }
1686
1687         sq->rate_limit = 0;
1688
1689         if (rate) {
1690                 rl.rate = rate;
1691                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1692                 if (err) {
1693                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1694                                    rate, err);
1695                         return err;
1696                 }
1697         }
1698
1699         msp.curr_state = MLX5_SQC_STATE_RDY;
1700         msp.next_state = MLX5_SQC_STATE_RDY;
1701         msp.rl_index   = rl_index;
1702         msp.rl_update  = true;
1703         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1704         if (err) {
1705                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1706                            rate, err);
1707                 /* remove the rate from the table */
1708                 if (rate)
1709                         mlx5_rl_remove_rate(mdev, &rl);
1710                 return err;
1711         }
1712
1713         sq->rate_limit = rate;
1714         return 0;
1715 }
1716
1717 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1718 {
1719         struct mlx5e_priv *priv = netdev_priv(dev);
1720         struct mlx5_core_dev *mdev = priv->mdev;
1721         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1722         int err = 0;
1723
1724         if (!mlx5_rl_is_supported(mdev)) {
1725                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1726                 return -EINVAL;
1727         }
1728
1729         /* rate is given in Mb/sec, HW config is in Kb/sec */
1730         rate = rate << 10;
1731
1732         /* Check whether rate in valid range, 0 is always valid */
1733         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1734                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1735                 return -ERANGE;
1736         }
1737
1738         mutex_lock(&priv->state_lock);
1739         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1740                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1741         if (!err)
1742                 priv->tx_rates[index] = rate;
1743         mutex_unlock(&priv->state_lock);
1744
1745         return err;
1746 }
1747
1748 static int mlx5e_alloc_xps_cpumask(struct mlx5e_channel *c,
1749                                    struct mlx5e_params *params)
1750 {
1751         int num_comp_vectors = mlx5_comp_vectors_count(c->mdev);
1752         int irq;
1753
1754         if (!zalloc_cpumask_var(&c->xps_cpumask, GFP_KERNEL))
1755                 return -ENOMEM;
1756
1757         for (irq = c->ix; irq < num_comp_vectors; irq += params->num_channels) {
1758                 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(c->mdev, irq));
1759
1760                 cpumask_set_cpu(cpu, c->xps_cpumask);
1761         }
1762
1763         return 0;
1764 }
1765
1766 static void mlx5e_free_xps_cpumask(struct mlx5e_channel *c)
1767 {
1768         free_cpumask_var(c->xps_cpumask);
1769 }
1770
1771 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1772                               struct mlx5e_params *params,
1773                               struct mlx5e_channel_param *cparam,
1774                               struct mlx5e_channel **cp)
1775 {
1776         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1777         struct net_dim_cq_moder icocq_moder = {0, 0};
1778         struct net_device *netdev = priv->netdev;
1779         struct mlx5e_channel *c;
1780         unsigned int irq;
1781         int err;
1782         int eqn;
1783
1784         err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1785         if (err)
1786                 return err;
1787
1788         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1789         if (!c)
1790                 return -ENOMEM;
1791
1792         c->priv     = priv;
1793         c->mdev     = priv->mdev;
1794         c->tstamp   = &priv->tstamp;
1795         c->ix       = ix;
1796         c->cpu      = cpu;
1797         c->pdev     = priv->mdev->device;
1798         c->netdev   = priv->netdev;
1799         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1800         c->num_tc   = params->num_tc;
1801         c->xdp      = !!params->xdp_prog;
1802         c->stats    = &priv->channel_stats[ix].ch;
1803         c->irq_desc = irq_to_desc(irq);
1804
1805         err = mlx5e_alloc_xps_cpumask(c, params);
1806         if (err)
1807                 goto err_free_channel;
1808
1809         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1810
1811         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1812         if (err)
1813                 goto err_napi_del;
1814
1815         err = mlx5e_open_tx_cqs(c, params, cparam);
1816         if (err)
1817                 goto err_close_icosq_cq;
1818
1819         err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->tx_cq, &c->xdpsq.cq);
1820         if (err)
1821                 goto err_close_tx_cqs;
1822
1823         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1824         if (err)
1825                 goto err_close_xdp_tx_cqs;
1826
1827         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1828         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1829                                      &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1830         if (err)
1831                 goto err_close_rx_cq;
1832
1833         napi_enable(&c->napi);
1834
1835         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1836         if (err)
1837                 goto err_disable_napi;
1838
1839         err = mlx5e_open_sqs(c, params, cparam);
1840         if (err)
1841                 goto err_close_icosq;
1842
1843         err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq, false) : 0;
1844         if (err)
1845                 goto err_close_sqs;
1846
1847         err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1848         if (err)
1849                 goto err_close_xdp_sq;
1850
1851         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->xdpsq, true);
1852         if (err)
1853                 goto err_close_rq;
1854
1855         *cp = c;
1856
1857         return 0;
1858
1859 err_close_rq:
1860         mlx5e_close_rq(&c->rq);
1861
1862 err_close_xdp_sq:
1863         if (c->xdp)
1864                 mlx5e_close_xdpsq(&c->rq.xdpsq, &c->rq);
1865
1866 err_close_sqs:
1867         mlx5e_close_sqs(c);
1868
1869 err_close_icosq:
1870         mlx5e_close_icosq(&c->icosq);
1871
1872 err_disable_napi:
1873         napi_disable(&c->napi);
1874         if (c->xdp)
1875                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1876
1877 err_close_rx_cq:
1878         mlx5e_close_cq(&c->rq.cq);
1879
1880 err_close_xdp_tx_cqs:
1881         mlx5e_close_cq(&c->xdpsq.cq);
1882
1883 err_close_tx_cqs:
1884         mlx5e_close_tx_cqs(c);
1885
1886 err_close_icosq_cq:
1887         mlx5e_close_cq(&c->icosq.cq);
1888
1889 err_napi_del:
1890         netif_napi_del(&c->napi);
1891         mlx5e_free_xps_cpumask(c);
1892
1893 err_free_channel:
1894         kvfree(c);
1895
1896         return err;
1897 }
1898
1899 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1900 {
1901         int tc;
1902
1903         for (tc = 0; tc < c->num_tc; tc++)
1904                 mlx5e_activate_txqsq(&c->sq[tc]);
1905         mlx5e_activate_rq(&c->rq);
1906         netif_set_xps_queue(c->netdev, c->xps_cpumask, c->ix);
1907 }
1908
1909 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1910 {
1911         int tc;
1912
1913         mlx5e_deactivate_rq(&c->rq);
1914         for (tc = 0; tc < c->num_tc; tc++)
1915                 mlx5e_deactivate_txqsq(&c->sq[tc]);
1916 }
1917
1918 static void mlx5e_close_channel(struct mlx5e_channel *c)
1919 {
1920         mlx5e_close_xdpsq(&c->xdpsq, NULL);
1921         mlx5e_close_rq(&c->rq);
1922         if (c->xdp)
1923                 mlx5e_close_xdpsq(&c->rq.xdpsq, &c->rq);
1924         mlx5e_close_sqs(c);
1925         mlx5e_close_icosq(&c->icosq);
1926         napi_disable(&c->napi);
1927         if (c->xdp)
1928                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1929         mlx5e_close_cq(&c->rq.cq);
1930         mlx5e_close_cq(&c->xdpsq.cq);
1931         mlx5e_close_tx_cqs(c);
1932         mlx5e_close_cq(&c->icosq.cq);
1933         netif_napi_del(&c->napi);
1934         mlx5e_free_xps_cpumask(c);
1935
1936         kvfree(c);
1937 }
1938
1939 #define DEFAULT_FRAG_SIZE (2048)
1940
1941 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
1942                                       struct mlx5e_params *params,
1943                                       struct mlx5e_rq_frags_info *info)
1944 {
1945         u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1946         int frag_size_max = DEFAULT_FRAG_SIZE;
1947         u32 buf_size = 0;
1948         int i;
1949
1950 #ifdef CONFIG_MLX5_EN_IPSEC
1951         if (MLX5_IPSEC_DEV(mdev))
1952                 byte_count += MLX5E_METADATA_ETHER_LEN;
1953 #endif
1954
1955         if (mlx5e_rx_is_linear_skb(params)) {
1956                 int frag_stride;
1957
1958                 frag_stride = mlx5e_rx_get_linear_frag_sz(params);
1959                 frag_stride = roundup_pow_of_two(frag_stride);
1960
1961                 info->arr[0].frag_size = byte_count;
1962                 info->arr[0].frag_stride = frag_stride;
1963                 info->num_frags = 1;
1964                 info->wqe_bulk = PAGE_SIZE / frag_stride;
1965                 goto out;
1966         }
1967
1968         if (byte_count > PAGE_SIZE +
1969             (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
1970                 frag_size_max = PAGE_SIZE;
1971
1972         i = 0;
1973         while (buf_size < byte_count) {
1974                 int frag_size = byte_count - buf_size;
1975
1976                 if (i < MLX5E_MAX_RX_FRAGS - 1)
1977                         frag_size = min(frag_size, frag_size_max);
1978
1979                 info->arr[i].frag_size = frag_size;
1980                 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
1981
1982                 buf_size += frag_size;
1983                 i++;
1984         }
1985         info->num_frags = i;
1986         /* number of different wqes sharing a page */
1987         info->wqe_bulk = 1 + (info->num_frags % 2);
1988
1989 out:
1990         info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
1991         info->log_num_frags = order_base_2(info->num_frags);
1992 }
1993
1994 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
1995 {
1996         int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
1997
1998         switch (wq_type) {
1999         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2000                 sz += sizeof(struct mlx5e_rx_wqe_ll);
2001                 break;
2002         default: /* MLX5_WQ_TYPE_CYCLIC */
2003                 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2004         }
2005
2006         return order_base_2(sz);
2007 }
2008
2009 static u8 mlx5e_get_rq_log_wq_sz(void *rqc)
2010 {
2011         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2012
2013         return MLX5_GET(wq, wq, log_wq_sz);
2014 }
2015
2016 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2017                                  struct mlx5e_params *params,
2018                                  struct mlx5e_rq_param *param)
2019 {
2020         struct mlx5_core_dev *mdev = priv->mdev;
2021         void *rqc = param->rqc;
2022         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2023         int ndsegs = 1;
2024
2025         switch (params->rq_wq_type) {
2026         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2027                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2028                          mlx5e_mpwqe_get_log_num_strides(mdev, params) -
2029                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2030                 MLX5_SET(wq, wq, log_wqe_stride_size,
2031                          mlx5e_mpwqe_get_log_stride_size(mdev, params) -
2032                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2033                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params));
2034                 break;
2035         default: /* MLX5_WQ_TYPE_CYCLIC */
2036                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2037                 mlx5e_build_rq_frags_info(mdev, params, &param->frags_info);
2038                 ndsegs = param->frags_info.num_frags;
2039         }
2040
2041         MLX5_SET(wq, wq, wq_type,          params->rq_wq_type);
2042         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2043         MLX5_SET(wq, wq, log_wq_stride,
2044                  mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2045         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
2046         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2047         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
2048         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
2049
2050         param->wq.buf_numa_node = dev_to_node(mdev->device);
2051 }
2052
2053 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2054                                       struct mlx5e_rq_param *param)
2055 {
2056         struct mlx5_core_dev *mdev = priv->mdev;
2057         void *rqc = param->rqc;
2058         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2059
2060         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2061         MLX5_SET(wq, wq, log_wq_stride,
2062                  mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2063         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2064
2065         param->wq.buf_numa_node = dev_to_node(mdev->device);
2066 }
2067
2068 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2069                                         struct mlx5e_sq_param *param)
2070 {
2071         void *sqc = param->sqc;
2072         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2073
2074         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2075         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
2076
2077         param->wq.buf_numa_node = dev_to_node(priv->mdev->device);
2078 }
2079
2080 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2081                                  struct mlx5e_params *params,
2082                                  struct mlx5e_sq_param *param)
2083 {
2084         void *sqc = param->sqc;
2085         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2086         bool allow_swp;
2087
2088         allow_swp = mlx5_geneve_tx_allowed(priv->mdev) ||
2089                     !!MLX5_IPSEC_DEV(priv->mdev);
2090         mlx5e_build_sq_param_common(priv, param);
2091         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2092         MLX5_SET(sqc, sqc, allow_swp, allow_swp);
2093 }
2094
2095 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2096                                         struct mlx5e_cq_param *param)
2097 {
2098         void *cqc = param->cqc;
2099
2100         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2101         if (MLX5_CAP_GEN(priv->mdev, cqe_128_always) && cache_line_size() >= 128)
2102                 MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD);
2103 }
2104
2105 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2106                                     struct mlx5e_params *params,
2107                                     struct mlx5e_cq_param *param)
2108 {
2109         struct mlx5_core_dev *mdev = priv->mdev;
2110         void *cqc = param->cqc;
2111         u8 log_cq_size;
2112
2113         switch (params->rq_wq_type) {
2114         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2115                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) +
2116                         mlx5e_mpwqe_get_log_num_strides(mdev, params);
2117                 break;
2118         default: /* MLX5_WQ_TYPE_CYCLIC */
2119                 log_cq_size = params->log_rq_mtu_frames;
2120         }
2121
2122         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2123         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2124                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2125                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2126         }
2127
2128         mlx5e_build_common_cq_param(priv, param);
2129         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2130 }
2131
2132 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2133                                     struct mlx5e_params *params,
2134                                     struct mlx5e_cq_param *param)
2135 {
2136         void *cqc = param->cqc;
2137
2138         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2139
2140         mlx5e_build_common_cq_param(priv, param);
2141         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2142 }
2143
2144 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2145                                      u8 log_wq_size,
2146                                      struct mlx5e_cq_param *param)
2147 {
2148         void *cqc = param->cqc;
2149
2150         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2151
2152         mlx5e_build_common_cq_param(priv, param);
2153
2154         param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2155 }
2156
2157 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2158                                     u8 log_wq_size,
2159                                     struct mlx5e_sq_param *param)
2160 {
2161         void *sqc = param->sqc;
2162         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2163
2164         mlx5e_build_sq_param_common(priv, param);
2165
2166         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2167         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2168 }
2169
2170 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2171                                     struct mlx5e_params *params,
2172                                     struct mlx5e_sq_param *param)
2173 {
2174         void *sqc = param->sqc;
2175         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2176
2177         mlx5e_build_sq_param_common(priv, param);
2178         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2179         param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE);
2180 }
2181
2182 static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5e_params *params,
2183                                       struct mlx5e_rq_param *rqp)
2184 {
2185         switch (params->rq_wq_type) {
2186         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2187                 return order_base_2(MLX5E_UMR_WQEBBS) +
2188                         mlx5e_get_rq_log_wq_sz(rqp->rqc);
2189         default: /* MLX5_WQ_TYPE_CYCLIC */
2190                 return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2191         }
2192 }
2193
2194 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2195                                       struct mlx5e_params *params,
2196                                       struct mlx5e_channel_param *cparam)
2197 {
2198         u8 icosq_log_wq_sz;
2199
2200         mlx5e_build_rq_param(priv, params, &cparam->rq);
2201
2202         icosq_log_wq_sz = mlx5e_build_icosq_log_wq_sz(params, &cparam->rq);
2203
2204         mlx5e_build_sq_param(priv, params, &cparam->sq);
2205         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2206         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2207         mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2208         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2209         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2210 }
2211
2212 int mlx5e_open_channels(struct mlx5e_priv *priv,
2213                         struct mlx5e_channels *chs)
2214 {
2215         struct mlx5e_channel_param *cparam;
2216         int err = -ENOMEM;
2217         int i;
2218
2219         chs->num = chs->params.num_channels;
2220
2221         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2222         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2223         if (!chs->c || !cparam)
2224                 goto err_free;
2225
2226         mlx5e_build_channel_param(priv, &chs->params, cparam);
2227         for (i = 0; i < chs->num; i++) {
2228                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2229                 if (err)
2230                         goto err_close_channels;
2231         }
2232
2233         if (!IS_ERR_OR_NULL(priv->tx_reporter))
2234                 devlink_health_reporter_state_update(priv->tx_reporter,
2235                                                      DEVLINK_HEALTH_REPORTER_STATE_HEALTHY);
2236
2237         kvfree(cparam);
2238         return 0;
2239
2240 err_close_channels:
2241         for (i--; i >= 0; i--)
2242                 mlx5e_close_channel(chs->c[i]);
2243
2244 err_free:
2245         kfree(chs->c);
2246         kvfree(cparam);
2247         chs->num = 0;
2248         return err;
2249 }
2250
2251 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2252 {
2253         int i;
2254
2255         for (i = 0; i < chs->num; i++)
2256                 mlx5e_activate_channel(chs->c[i]);
2257 }
2258
2259 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2260
2261 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2262 {
2263         int err = 0;
2264         int i;
2265
2266         for (i = 0; i < chs->num; i++) {
2267                 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2268
2269                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2270         }
2271
2272         return err ? -ETIMEDOUT : 0;
2273 }
2274
2275 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2276 {
2277         int i;
2278
2279         for (i = 0; i < chs->num; i++)
2280                 mlx5e_deactivate_channel(chs->c[i]);
2281 }
2282
2283 void mlx5e_close_channels(struct mlx5e_channels *chs)
2284 {
2285         int i;
2286
2287         for (i = 0; i < chs->num; i++)
2288                 mlx5e_close_channel(chs->c[i]);
2289
2290         kfree(chs->c);
2291         chs->num = 0;
2292 }
2293
2294 static int
2295 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2296 {
2297         struct mlx5_core_dev *mdev = priv->mdev;
2298         void *rqtc;
2299         int inlen;
2300         int err;
2301         u32 *in;
2302         int i;
2303
2304         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2305         in = kvzalloc(inlen, GFP_KERNEL);
2306         if (!in)
2307                 return -ENOMEM;
2308
2309         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2310
2311         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2312         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2313
2314         for (i = 0; i < sz; i++)
2315                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2316
2317         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2318         if (!err)
2319                 rqt->enabled = true;
2320
2321         kvfree(in);
2322         return err;
2323 }
2324
2325 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2326 {
2327         rqt->enabled = false;
2328         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2329 }
2330
2331 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2332 {
2333         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2334         int err;
2335
2336         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2337         if (err)
2338                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2339         return err;
2340 }
2341
2342 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2343 {
2344         struct mlx5e_rqt *rqt;
2345         int err;
2346         int ix;
2347
2348         for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
2349                 rqt = &priv->direct_tir[ix].rqt;
2350                 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2351                 if (err)
2352                         goto err_destroy_rqts;
2353         }
2354
2355         return 0;
2356
2357 err_destroy_rqts:
2358         mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2359         for (ix--; ix >= 0; ix--)
2360                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2361
2362         return err;
2363 }
2364
2365 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2366 {
2367         int i;
2368
2369         for (i = 0; i < mlx5e_get_netdev_max_channels(priv->netdev); i++)
2370                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2371 }
2372
2373 static int mlx5e_rx_hash_fn(int hfunc)
2374 {
2375         return (hfunc == ETH_RSS_HASH_TOP) ?
2376                MLX5_RX_HASH_FN_TOEPLITZ :
2377                MLX5_RX_HASH_FN_INVERTED_XOR8;
2378 }
2379
2380 int mlx5e_bits_invert(unsigned long a, int size)
2381 {
2382         int inv = 0;
2383         int i;
2384
2385         for (i = 0; i < size; i++)
2386                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2387
2388         return inv;
2389 }
2390
2391 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2392                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2393 {
2394         int i;
2395
2396         for (i = 0; i < sz; i++) {
2397                 u32 rqn;
2398
2399                 if (rrp.is_rss) {
2400                         int ix = i;
2401
2402                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2403                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2404
2405                         ix = priv->rss_params.indirection_rqt[ix];
2406                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2407                 } else {
2408                         rqn = rrp.rqn;
2409                 }
2410                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2411         }
2412 }
2413
2414 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2415                        struct mlx5e_redirect_rqt_param rrp)
2416 {
2417         struct mlx5_core_dev *mdev = priv->mdev;
2418         void *rqtc;
2419         int inlen;
2420         u32 *in;
2421         int err;
2422
2423         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2424         in = kvzalloc(inlen, GFP_KERNEL);
2425         if (!in)
2426                 return -ENOMEM;
2427
2428         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2429
2430         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2431         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2432         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2433         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2434
2435         kvfree(in);
2436         return err;
2437 }
2438
2439 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2440                                 struct mlx5e_redirect_rqt_param rrp)
2441 {
2442         if (!rrp.is_rss)
2443                 return rrp.rqn;
2444
2445         if (ix >= rrp.rss.channels->num)
2446                 return priv->drop_rq.rqn;
2447
2448         return rrp.rss.channels->c[ix]->rq.rqn;
2449 }
2450
2451 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2452                                 struct mlx5e_redirect_rqt_param rrp)
2453 {
2454         u32 rqtn;
2455         int ix;
2456
2457         if (priv->indir_rqt.enabled) {
2458                 /* RSS RQ table */
2459                 rqtn = priv->indir_rqt.rqtn;
2460                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2461         }
2462
2463         for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
2464                 struct mlx5e_redirect_rqt_param direct_rrp = {
2465                         .is_rss = false,
2466                         {
2467                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2468                         },
2469                 };
2470
2471                 /* Direct RQ Tables */
2472                 if (!priv->direct_tir[ix].rqt.enabled)
2473                         continue;
2474
2475                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2476                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2477         }
2478 }
2479
2480 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2481                                             struct mlx5e_channels *chs)
2482 {
2483         struct mlx5e_redirect_rqt_param rrp = {
2484                 .is_rss        = true,
2485                 {
2486                         .rss = {
2487                                 .channels  = chs,
2488                                 .hfunc     = priv->rss_params.hfunc,
2489                         }
2490                 },
2491         };
2492
2493         mlx5e_redirect_rqts(priv, rrp);
2494 }
2495
2496 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2497 {
2498         struct mlx5e_redirect_rqt_param drop_rrp = {
2499                 .is_rss = false,
2500                 {
2501                         .rqn = priv->drop_rq.rqn,
2502                 },
2503         };
2504
2505         mlx5e_redirect_rqts(priv, drop_rrp);
2506 }
2507
2508 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {
2509         [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2510                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2511                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2512         },
2513         [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2514                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2515                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2516         },
2517         [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2518                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2519                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2520         },
2521         [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2522                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2523                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2524         },
2525         [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2526                                      .l4_prot_type = 0,
2527                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2528         },
2529         [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2530                                      .l4_prot_type = 0,
2531                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2532         },
2533         [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2534                                       .l4_prot_type = 0,
2535                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2536         },
2537         [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2538                                       .l4_prot_type = 0,
2539                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2540         },
2541         [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2542                             .l4_prot_type = 0,
2543                             .rx_hash_fields = MLX5_HASH_IP,
2544         },
2545         [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2546                             .l4_prot_type = 0,
2547                             .rx_hash_fields = MLX5_HASH_IP,
2548         },
2549 };
2550
2551 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)
2552 {
2553         return tirc_default_config[tt];
2554 }
2555
2556 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2557 {
2558         if (!params->lro_en)
2559                 return;
2560
2561 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2562
2563         MLX5_SET(tirc, tirc, lro_enable_mask,
2564                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2565                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2566         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2567                  (MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2568         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2569 }
2570
2571 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
2572                                     const struct mlx5e_tirc_config *ttconfig,
2573                                     void *tirc, bool inner)
2574 {
2575         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2576                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2577
2578         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc));
2579         if (rss_params->hfunc == ETH_RSS_HASH_TOP) {
2580                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2581                                              rx_hash_toeplitz_key);
2582                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2583                                                rx_hash_toeplitz_key);
2584
2585                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2586                 memcpy(rss_key, rss_params->toeplitz_hash_key, len);
2587         }
2588         MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2589                  ttconfig->l3_prot_type);
2590         MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2591                  ttconfig->l4_prot_type);
2592         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2593                  ttconfig->rx_hash_fields);
2594 }
2595
2596 static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig,
2597                                         enum mlx5e_traffic_types tt,
2598                                         u32 rx_hash_fields)
2599 {
2600         *ttconfig                = tirc_default_config[tt];
2601         ttconfig->rx_hash_fields = rx_hash_fields;
2602 }
2603
2604 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
2605 {
2606         void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2607         struct mlx5e_rss_params *rss = &priv->rss_params;
2608         struct mlx5_core_dev *mdev = priv->mdev;
2609         int ctxlen = MLX5_ST_SZ_BYTES(tirc);
2610         struct mlx5e_tirc_config ttconfig;
2611         int tt;
2612
2613         MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
2614
2615         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2616                 memset(tirc, 0, ctxlen);
2617                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2618                                             rss->rx_hash_fields[tt]);
2619                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false);
2620                 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);
2621         }
2622
2623         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2624                 return;
2625
2626         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2627                 memset(tirc, 0, ctxlen);
2628                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2629                                             rss->rx_hash_fields[tt]);
2630                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true);
2631                 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in,
2632                                      inlen);
2633         }
2634 }
2635
2636 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2637 {
2638         struct mlx5_core_dev *mdev = priv->mdev;
2639
2640         void *in;
2641         void *tirc;
2642         int inlen;
2643         int err;
2644         int tt;
2645         int ix;
2646
2647         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2648         in = kvzalloc(inlen, GFP_KERNEL);
2649         if (!in)
2650                 return -ENOMEM;
2651
2652         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2653         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2654
2655         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2656
2657         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2658                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2659                                            inlen);
2660                 if (err)
2661                         goto free_in;
2662         }
2663
2664         for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
2665                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2666                                            in, inlen);
2667                 if (err)
2668                         goto free_in;
2669         }
2670
2671 free_in:
2672         kvfree(in);
2673
2674         return err;
2675 }
2676
2677 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2678                          struct mlx5e_params *params, u16 mtu)
2679 {
2680         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2681         int err;
2682
2683         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2684         if (err)
2685                 return err;
2686
2687         /* Update vport context MTU */
2688         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2689         return 0;
2690 }
2691
2692 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2693                             struct mlx5e_params *params, u16 *mtu)
2694 {
2695         u16 hw_mtu = 0;
2696         int err;
2697
2698         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2699         if (err || !hw_mtu) /* fallback to port oper mtu */
2700                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2701
2702         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2703 }
2704
2705 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2706 {
2707         struct mlx5e_params *params = &priv->channels.params;
2708         struct net_device *netdev = priv->netdev;
2709         struct mlx5_core_dev *mdev = priv->mdev;
2710         u16 mtu;
2711         int err;
2712
2713         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2714         if (err)
2715                 return err;
2716
2717         mlx5e_query_mtu(mdev, params, &mtu);
2718         if (mtu != params->sw_mtu)
2719                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2720                             __func__, mtu, params->sw_mtu);
2721
2722         params->sw_mtu = mtu;
2723         return 0;
2724 }
2725
2726 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2727 {
2728         struct mlx5e_params *params = &priv->channels.params;
2729         struct net_device *netdev   = priv->netdev;
2730         struct mlx5_core_dev *mdev  = priv->mdev;
2731         u16 max_mtu;
2732
2733         /* MTU range: 68 - hw-specific max */
2734         netdev->min_mtu = ETH_MIN_MTU;
2735
2736         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2737         netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2738                                 ETH_MAX_MTU);
2739 }
2740
2741 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2742 {
2743         struct mlx5e_priv *priv = netdev_priv(netdev);
2744         int nch = priv->channels.params.num_channels;
2745         int ntc = priv->channels.params.num_tc;
2746         int tc;
2747
2748         netdev_reset_tc(netdev);
2749
2750         if (ntc == 1)
2751                 return;
2752
2753         netdev_set_num_tc(netdev, ntc);
2754
2755         /* Map netdev TCs to offset 0
2756          * We have our own UP to TXQ mapping for QoS
2757          */
2758         for (tc = 0; tc < ntc; tc++)
2759                 netdev_set_tc_queue(netdev, tc, nch, 0);
2760 }
2761
2762 static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv)
2763 {
2764         int max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
2765         int i, tc;
2766
2767         for (i = 0; i < max_nch; i++)
2768                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2769                         priv->channel_tc2txq[i][tc] = i + tc * max_nch;
2770 }
2771
2772 static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv)
2773 {
2774         struct mlx5e_channel *c;
2775         struct mlx5e_txqsq *sq;
2776         int i, tc;
2777
2778         for (i = 0; i < priv->channels.num; i++) {
2779                 c = priv->channels.c[i];
2780                 for (tc = 0; tc < c->num_tc; tc++) {
2781                         sq = &c->sq[tc];
2782                         priv->txq2sq[sq->txq_ix] = sq;
2783                 }
2784         }
2785 }
2786
2787 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2788 {
2789         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2790         struct net_device *netdev = priv->netdev;
2791
2792         mlx5e_netdev_set_tcs(netdev);
2793         netif_set_real_num_tx_queues(netdev, num_txqs);
2794         netif_set_real_num_rx_queues(netdev, priv->channels.num);
2795
2796         mlx5e_build_tx2sq_maps(priv);
2797         mlx5e_activate_channels(&priv->channels);
2798         mlx5e_xdp_tx_enable(priv);
2799         netif_tx_start_all_queues(priv->netdev);
2800
2801         if (mlx5e_is_vport_rep(priv))
2802                 mlx5e_add_sqs_fwd_rules(priv);
2803
2804         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2805         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2806 }
2807
2808 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2809 {
2810         mlx5e_redirect_rqts_to_drop(priv);
2811
2812         if (mlx5e_is_vport_rep(priv))
2813                 mlx5e_remove_sqs_fwd_rules(priv);
2814
2815         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2816          * polling for inactive tx queues.
2817          */
2818         netif_tx_stop_all_queues(priv->netdev);
2819         netif_tx_disable(priv->netdev);
2820         mlx5e_xdp_tx_disable(priv);
2821         mlx5e_deactivate_channels(&priv->channels);
2822 }
2823
2824 static void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2825                                        struct mlx5e_channels *new_chs,
2826                                        mlx5e_fp_hw_modify hw_modify)
2827 {
2828         struct net_device *netdev = priv->netdev;
2829         int new_num_txqs;
2830         int carrier_ok;
2831
2832         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2833
2834         carrier_ok = netif_carrier_ok(netdev);
2835         netif_carrier_off(netdev);
2836
2837         if (new_num_txqs < netdev->real_num_tx_queues)
2838                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2839
2840         mlx5e_deactivate_priv_channels(priv);
2841         mlx5e_close_channels(&priv->channels);
2842
2843         priv->channels = *new_chs;
2844
2845         /* New channels are ready to roll, modify HW settings if needed */
2846         if (hw_modify)
2847                 hw_modify(priv);
2848
2849         mlx5e_refresh_tirs(priv, false);
2850         mlx5e_activate_priv_channels(priv);
2851
2852         /* return carrier back if needed */
2853         if (carrier_ok)
2854                 netif_carrier_on(netdev);
2855 }
2856
2857 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
2858                                struct mlx5e_channels *new_chs,
2859                                mlx5e_fp_hw_modify hw_modify)
2860 {
2861         int err;
2862
2863         err = mlx5e_open_channels(priv, new_chs);
2864         if (err)
2865                 return err;
2866
2867         mlx5e_switch_priv_channels(priv, new_chs, hw_modify);
2868         return 0;
2869 }
2870
2871 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
2872 {
2873         struct mlx5e_channels new_channels = {};
2874
2875         new_channels.params = priv->channels.params;
2876         return mlx5e_safe_switch_channels(priv, &new_channels, NULL);
2877 }
2878
2879 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2880 {
2881         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2882         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2883 }
2884
2885 int mlx5e_open_locked(struct net_device *netdev)
2886 {
2887         struct mlx5e_priv *priv = netdev_priv(netdev);
2888         int err;
2889
2890         set_bit(MLX5E_STATE_OPENED, &priv->state);
2891
2892         err = mlx5e_open_channels(priv, &priv->channels);
2893         if (err)
2894                 goto err_clear_state_opened_flag;
2895
2896         mlx5e_refresh_tirs(priv, false);
2897         mlx5e_activate_priv_channels(priv);
2898         if (priv->profile->update_carrier)
2899                 priv->profile->update_carrier(priv);
2900
2901         mlx5e_queue_update_stats(priv);
2902         return 0;
2903
2904 err_clear_state_opened_flag:
2905         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2906         return err;
2907 }
2908
2909 int mlx5e_open(struct net_device *netdev)
2910 {
2911         struct mlx5e_priv *priv = netdev_priv(netdev);
2912         int err;
2913
2914         mutex_lock(&priv->state_lock);
2915         err = mlx5e_open_locked(netdev);
2916         if (!err)
2917                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2918         mutex_unlock(&priv->state_lock);
2919
2920         if (mlx5_vxlan_allowed(priv->mdev->vxlan))
2921                 udp_tunnel_get_rx_info(netdev);
2922
2923         return err;
2924 }
2925
2926 int mlx5e_close_locked(struct net_device *netdev)
2927 {
2928         struct mlx5e_priv *priv = netdev_priv(netdev);
2929
2930         /* May already be CLOSED in case a previous configuration operation
2931          * (e.g RX/TX queue size change) that involves close&open failed.
2932          */
2933         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2934                 return 0;
2935
2936         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2937
2938         netif_carrier_off(priv->netdev);
2939         mlx5e_deactivate_priv_channels(priv);
2940         mlx5e_close_channels(&priv->channels);
2941
2942         return 0;
2943 }
2944
2945 int mlx5e_close(struct net_device *netdev)
2946 {
2947         struct mlx5e_priv *priv = netdev_priv(netdev);
2948         int err;
2949
2950         if (!netif_device_present(netdev))
2951                 return -ENODEV;
2952
2953         mutex_lock(&priv->state_lock);
2954         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
2955         err = mlx5e_close_locked(netdev);
2956         mutex_unlock(&priv->state_lock);
2957
2958         return err;
2959 }
2960
2961 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2962                                struct mlx5e_rq *rq,
2963                                struct mlx5e_rq_param *param)
2964 {
2965         void *rqc = param->rqc;
2966         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2967         int err;
2968
2969         param->wq.db_numa_node = param->wq.buf_numa_node;
2970
2971         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
2972                                  &rq->wq_ctrl);
2973         if (err)
2974                 return err;
2975
2976         /* Mark as unused given "Drop-RQ" packets never reach XDP */
2977         xdp_rxq_info_unused(&rq->xdp_rxq);
2978
2979         rq->mdev = mdev;
2980
2981         return 0;
2982 }
2983
2984 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
2985                                struct mlx5e_cq *cq,
2986                                struct mlx5e_cq_param *param)
2987 {
2988         param->wq.buf_numa_node = dev_to_node(mdev->device);
2989         param->wq.db_numa_node  = dev_to_node(mdev->device);
2990
2991         return mlx5e_alloc_cq_common(mdev, param, cq);
2992 }
2993
2994 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
2995                        struct mlx5e_rq *drop_rq)
2996 {
2997         struct mlx5_core_dev *mdev = priv->mdev;
2998         struct mlx5e_cq_param cq_param = {};
2999         struct mlx5e_rq_param rq_param = {};
3000         struct mlx5e_cq *cq = &drop_rq->cq;
3001         int err;
3002
3003         mlx5e_build_drop_rq_param(priv, &rq_param);
3004
3005         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3006         if (err)
3007                 return err;
3008
3009         err = mlx5e_create_cq(cq, &cq_param);
3010         if (err)
3011                 goto err_free_cq;
3012
3013         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3014         if (err)
3015                 goto err_destroy_cq;
3016
3017         err = mlx5e_create_rq(drop_rq, &rq_param);
3018         if (err)
3019                 goto err_free_rq;
3020
3021         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3022         if (err)
3023                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3024
3025         return 0;
3026
3027 err_free_rq:
3028         mlx5e_free_rq(drop_rq);
3029
3030 err_destroy_cq:
3031         mlx5e_destroy_cq(cq);
3032
3033 err_free_cq:
3034         mlx5e_free_cq(cq);
3035
3036         return err;
3037 }
3038
3039 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3040 {
3041         mlx5e_destroy_rq(drop_rq);
3042         mlx5e_free_rq(drop_rq);
3043         mlx5e_destroy_cq(&drop_rq->cq);
3044         mlx5e_free_cq(&drop_rq->cq);
3045 }
3046
3047 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
3048                      u32 underlay_qpn, u32 *tisn)
3049 {
3050         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
3051         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3052
3053         MLX5_SET(tisc, tisc, prio, tc << 1);
3054         MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
3055         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3056
3057         if (mlx5_lag_is_lacp_owner(mdev))
3058                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3059
3060         return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
3061 }
3062
3063 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3064 {
3065         mlx5_core_destroy_tis(mdev, tisn);
3066 }
3067
3068 int mlx5e_create_tises(struct mlx5e_priv *priv)
3069 {
3070         int err;
3071         int tc;
3072
3073         for (tc = 0; tc < priv->profile->max_tc; tc++) {
3074                 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
3075                 if (err)
3076                         goto err_close_tises;
3077         }
3078
3079         return 0;
3080
3081 err_close_tises:
3082         for (tc--; tc >= 0; tc--)
3083                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3084
3085         return err;
3086 }
3087
3088 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3089 {
3090         int tc;
3091
3092         mlx5e_tx_reporter_destroy(priv);
3093         for (tc = 0; tc < priv->profile->max_tc; tc++)
3094                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3095 }
3096
3097 static void mlx5e_build_indir_tir_ctx_common(struct mlx5e_priv *priv,
3098                                              u32 rqtn, u32 *tirc)
3099 {
3100         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3101         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3102         MLX5_SET(tirc, tirc, indirect_table, rqtn);
3103         MLX5_SET(tirc, tirc, tunneled_offload_en,
3104                  priv->channels.params.tunneled_offload_en);
3105
3106         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3107 }
3108
3109 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3110                                       enum mlx5e_traffic_types tt,
3111                                       u32 *tirc)
3112 {
3113         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3114         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3115                                        &tirc_default_config[tt], tirc, false);
3116 }
3117
3118 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3119 {
3120         mlx5e_build_indir_tir_ctx_common(priv, rqtn, tirc);
3121         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3122 }
3123
3124 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
3125                                             enum mlx5e_traffic_types tt,
3126                                             u32 *tirc)
3127 {
3128         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3129         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3130                                        &tirc_default_config[tt], tirc, true);
3131 }
3132
3133 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3134 {
3135         struct mlx5e_tir *tir;
3136         void *tirc;
3137         int inlen;
3138         int i = 0;
3139         int err;
3140         u32 *in;
3141         int tt;
3142
3143         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3144         in = kvzalloc(inlen, GFP_KERNEL);
3145         if (!in)
3146                 return -ENOMEM;
3147
3148         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3149                 memset(in, 0, inlen);
3150                 tir = &priv->indir_tir[tt];
3151                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3152                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3153                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3154                 if (err) {
3155                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3156                         goto err_destroy_inner_tirs;
3157                 }
3158         }
3159
3160         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3161                 goto out;
3162
3163         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3164                 memset(in, 0, inlen);
3165                 tir = &priv->inner_indir_tir[i];
3166                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3167                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3168                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3169                 if (err) {
3170                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3171                         goto err_destroy_inner_tirs;
3172                 }
3173         }
3174
3175 out:
3176         kvfree(in);
3177
3178         return 0;
3179
3180 err_destroy_inner_tirs:
3181         for (i--; i >= 0; i--)
3182                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3183
3184         for (tt--; tt >= 0; tt--)
3185                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3186
3187         kvfree(in);
3188
3189         return err;
3190 }
3191
3192 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
3193 {
3194         int nch = mlx5e_get_netdev_max_channels(priv->netdev);
3195         struct mlx5e_tir *tir;
3196         void *tirc;
3197         int inlen;
3198         int err;
3199         u32 *in;
3200         int ix;
3201
3202         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3203         in = kvzalloc(inlen, GFP_KERNEL);
3204         if (!in)
3205                 return -ENOMEM;
3206
3207         for (ix = 0; ix < nch; ix++) {
3208                 memset(in, 0, inlen);
3209                 tir = &priv->direct_tir[ix];
3210                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3211                 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
3212                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3213                 if (err)
3214                         goto err_destroy_ch_tirs;
3215         }
3216
3217         kvfree(in);
3218
3219         return 0;
3220
3221 err_destroy_ch_tirs:
3222         mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
3223         for (ix--; ix >= 0; ix--)
3224                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
3225
3226         kvfree(in);
3227
3228         return err;
3229 }
3230
3231 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3232 {
3233         int i;
3234
3235         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3236                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3237
3238         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3239                 return;
3240
3241         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3242                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3243 }
3244
3245 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3246 {
3247         int nch = mlx5e_get_netdev_max_channels(priv->netdev);
3248         int i;
3249
3250         for (i = 0; i < nch; i++)
3251                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3252 }
3253
3254 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3255 {
3256         int err = 0;
3257         int i;
3258
3259         for (i = 0; i < chs->num; i++) {
3260                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3261                 if (err)
3262                         return err;
3263         }
3264
3265         return 0;
3266 }
3267
3268 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3269 {
3270         int err = 0;
3271         int i;
3272
3273         for (i = 0; i < chs->num; i++) {
3274                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3275                 if (err)
3276                         return err;
3277         }
3278
3279         return 0;
3280 }
3281
3282 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3283                                  struct tc_mqprio_qopt *mqprio)
3284 {
3285         struct mlx5e_priv *priv = netdev_priv(netdev);
3286         struct mlx5e_channels new_channels = {};
3287         u8 tc = mqprio->num_tc;
3288         int err = 0;
3289
3290         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3291
3292         if (tc && tc != MLX5E_MAX_NUM_TC)
3293                 return -EINVAL;
3294
3295         mutex_lock(&priv->state_lock);
3296
3297         new_channels.params = priv->channels.params;
3298         new_channels.params.num_tc = tc ? tc : 1;
3299
3300         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3301                 priv->channels.params = new_channels.params;
3302                 goto out;
3303         }
3304
3305         err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
3306         if (err)
3307                 goto out;
3308
3309         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3310                                     new_channels.params.num_tc);
3311 out:
3312         mutex_unlock(&priv->state_lock);
3313         return err;
3314 }
3315
3316 #ifdef CONFIG_MLX5_ESWITCH
3317 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3318                                      struct tc_cls_flower_offload *cls_flower,
3319                                      int flags)
3320 {
3321         switch (cls_flower->command) {
3322         case TC_CLSFLOWER_REPLACE:
3323                 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
3324                                               flags);
3325         case TC_CLSFLOWER_DESTROY:
3326                 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
3327                                            flags);
3328         case TC_CLSFLOWER_STATS:
3329                 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
3330                                           flags);
3331         default:
3332                 return -EOPNOTSUPP;
3333         }
3334 }
3335
3336 static int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3337                                    void *cb_priv)
3338 {
3339         struct mlx5e_priv *priv = cb_priv;
3340
3341         switch (type) {
3342         case TC_SETUP_CLSFLOWER:
3343                 return mlx5e_setup_tc_cls_flower(priv, type_data, MLX5E_TC_INGRESS |
3344                                                  MLX5E_TC_NIC_OFFLOAD);
3345         default:
3346                 return -EOPNOTSUPP;
3347         }
3348 }
3349
3350 static int mlx5e_setup_tc_block(struct net_device *dev,
3351                                 struct tc_block_offload *f)
3352 {
3353         struct mlx5e_priv *priv = netdev_priv(dev);
3354
3355         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3356                 return -EOPNOTSUPP;
3357
3358         switch (f->command) {
3359         case TC_BLOCK_BIND:
3360                 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
3361                                              priv, priv, f->extack);
3362         case TC_BLOCK_UNBIND:
3363                 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3364                                         priv);
3365                 return 0;
3366         default:
3367                 return -EOPNOTSUPP;
3368         }
3369 }
3370 #endif
3371
3372 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3373                           void *type_data)
3374 {
3375         switch (type) {
3376 #ifdef CONFIG_MLX5_ESWITCH
3377         case TC_SETUP_BLOCK:
3378                 return mlx5e_setup_tc_block(dev, type_data);
3379 #endif
3380         case TC_SETUP_QDISC_MQPRIO:
3381                 return mlx5e_setup_tc_mqprio(dev, type_data);
3382         default:
3383                 return -EOPNOTSUPP;
3384         }
3385 }
3386
3387 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3388 {
3389         int i;
3390
3391         for (i = 0; i < mlx5e_get_netdev_max_channels(priv->netdev); i++) {
3392                 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3393                 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3394                 int j;
3395
3396                 s->rx_packets   += rq_stats->packets;
3397                 s->rx_bytes     += rq_stats->bytes;
3398
3399                 for (j = 0; j < priv->max_opened_tc; j++) {
3400                         struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3401
3402                         s->tx_packets    += sq_stats->packets;
3403                         s->tx_bytes      += sq_stats->bytes;
3404                         s->tx_dropped    += sq_stats->dropped;
3405                 }
3406         }
3407 }
3408
3409 void
3410 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3411 {
3412         struct mlx5e_priv *priv = netdev_priv(dev);
3413         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3414         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3415
3416         if (!mlx5e_monitor_counter_supported(priv)) {
3417                 /* update HW stats in background for next time */
3418                 mlx5e_queue_update_stats(priv);
3419         }
3420
3421         if (mlx5e_is_uplink_rep(priv)) {
3422                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3423                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3424                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3425                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3426         } else {
3427                 mlx5e_fold_sw_stats64(priv, stats);
3428         }
3429
3430         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3431
3432         stats->rx_length_errors =
3433                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3434                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3435                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3436         stats->rx_crc_errors =
3437                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3438         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3439         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3440         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3441                            stats->rx_frame_errors;
3442         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3443
3444         /* vport multicast also counts packets that are dropped due to steering
3445          * or rx out of buffer
3446          */
3447         stats->multicast =
3448                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3449 }
3450
3451 static void mlx5e_set_rx_mode(struct net_device *dev)
3452 {
3453         struct mlx5e_priv *priv = netdev_priv(dev);
3454
3455         queue_work(priv->wq, &priv->set_rx_mode_work);
3456 }
3457
3458 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3459 {
3460         struct mlx5e_priv *priv = netdev_priv(netdev);
3461         struct sockaddr *saddr = addr;
3462
3463         if (!is_valid_ether_addr(saddr->sa_data))
3464                 return -EADDRNOTAVAIL;
3465
3466         netif_addr_lock_bh(netdev);
3467         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3468         netif_addr_unlock_bh(netdev);
3469
3470         queue_work(priv->wq, &priv->set_rx_mode_work);
3471
3472         return 0;
3473 }
3474
3475 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3476         do {                                            \
3477                 if (enable)                             \
3478                         *features |= feature;           \
3479                 else                                    \
3480                         *features &= ~feature;          \
3481         } while (0)
3482
3483 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3484
3485 static int set_feature_lro(struct net_device *netdev, bool enable)
3486 {
3487         struct mlx5e_priv *priv = netdev_priv(netdev);
3488         struct mlx5_core_dev *mdev = priv->mdev;
3489         struct mlx5e_channels new_channels = {};
3490         struct mlx5e_params *old_params;
3491         int err = 0;
3492         bool reset;
3493
3494         mutex_lock(&priv->state_lock);
3495
3496         old_params = &priv->channels.params;
3497         if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3498                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3499                 err = -EINVAL;
3500                 goto out;
3501         }
3502
3503         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3504
3505         new_channels.params = *old_params;
3506         new_channels.params.lro_en = enable;
3507
3508         if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3509                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params) ==
3510                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params))
3511                         reset = false;
3512         }
3513
3514         if (!reset) {
3515                 *old_params = new_channels.params;
3516                 err = mlx5e_modify_tirs_lro(priv);
3517                 goto out;
3518         }
3519
3520         err = mlx5e_safe_switch_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3521 out:
3522         mutex_unlock(&priv->state_lock);
3523         return err;
3524 }
3525
3526 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3527 {
3528         struct mlx5e_priv *priv = netdev_priv(netdev);
3529
3530         if (enable)
3531                 mlx5e_enable_cvlan_filter(priv);
3532         else
3533                 mlx5e_disable_cvlan_filter(priv);
3534
3535         return 0;
3536 }
3537
3538 #ifdef CONFIG_MLX5_ESWITCH
3539 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3540 {
3541         struct mlx5e_priv *priv = netdev_priv(netdev);
3542
3543         if (!enable && mlx5e_tc_num_filters(priv, MLX5E_TC_NIC_OFFLOAD)) {
3544                 netdev_err(netdev,
3545                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3546                 return -EINVAL;
3547         }
3548
3549         return 0;
3550 }
3551 #endif
3552
3553 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3554 {
3555         struct mlx5e_priv *priv = netdev_priv(netdev);
3556         struct mlx5_core_dev *mdev = priv->mdev;
3557
3558         return mlx5_set_port_fcs(mdev, !enable);
3559 }
3560
3561 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3562 {
3563         struct mlx5e_priv *priv = netdev_priv(netdev);
3564         int err;
3565
3566         mutex_lock(&priv->state_lock);
3567
3568         priv->channels.params.scatter_fcs_en = enable;
3569         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3570         if (err)
3571                 priv->channels.params.scatter_fcs_en = !enable;
3572
3573         mutex_unlock(&priv->state_lock);
3574
3575         return err;
3576 }
3577
3578 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3579 {
3580         struct mlx5e_priv *priv = netdev_priv(netdev);
3581         int err = 0;
3582
3583         mutex_lock(&priv->state_lock);
3584
3585         priv->channels.params.vlan_strip_disable = !enable;
3586         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3587                 goto unlock;
3588
3589         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3590         if (err)
3591                 priv->channels.params.vlan_strip_disable = enable;
3592
3593 unlock:
3594         mutex_unlock(&priv->state_lock);
3595
3596         return err;
3597 }
3598
3599 #ifdef CONFIG_MLX5_EN_ARFS
3600 static int set_feature_arfs(struct net_device *netdev, bool enable)
3601 {
3602         struct mlx5e_priv *priv = netdev_priv(netdev);
3603         int err;
3604
3605         if (enable)
3606                 err = mlx5e_arfs_enable(priv);
3607         else
3608                 err = mlx5e_arfs_disable(priv);
3609
3610         return err;
3611 }
3612 #endif
3613
3614 static int mlx5e_handle_feature(struct net_device *netdev,
3615                                 netdev_features_t *features,
3616                                 netdev_features_t wanted_features,
3617                                 netdev_features_t feature,
3618                                 mlx5e_feature_handler feature_handler)
3619 {
3620         netdev_features_t changes = wanted_features ^ netdev->features;
3621         bool enable = !!(wanted_features & feature);
3622         int err;
3623
3624         if (!(changes & feature))
3625                 return 0;
3626
3627         err = feature_handler(netdev, enable);
3628         if (err) {
3629                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3630                            enable ? "Enable" : "Disable", &feature, err);
3631                 return err;
3632         }
3633
3634         MLX5E_SET_FEATURE(features, feature, enable);
3635         return 0;
3636 }
3637
3638 static int mlx5e_set_features(struct net_device *netdev,
3639                               netdev_features_t features)
3640 {
3641         netdev_features_t oper_features = netdev->features;
3642         int err = 0;
3643
3644 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3645         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3646
3647         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3648         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3649                                     set_feature_cvlan_filter);
3650 #ifdef CONFIG_MLX5_ESWITCH
3651         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3652 #endif
3653         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3654         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3655         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3656 #ifdef CONFIG_MLX5_EN_ARFS
3657         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3658 #endif
3659
3660         if (err) {
3661                 netdev->features = oper_features;
3662                 return -EINVAL;
3663         }
3664
3665         return 0;
3666 }
3667
3668 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3669                                             netdev_features_t features)
3670 {
3671         struct mlx5e_priv *priv = netdev_priv(netdev);
3672         struct mlx5e_params *params;
3673
3674         mutex_lock(&priv->state_lock);
3675         params = &priv->channels.params;
3676         if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3677                 /* HW strips the outer C-tag header, this is a problem
3678                  * for S-tag traffic.
3679                  */
3680                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3681                 if (!params->vlan_strip_disable)
3682                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3683         }
3684         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3685                 features &= ~NETIF_F_LRO;
3686                 if (params->lro_en)
3687                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3688         }
3689
3690         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3691                 features &= ~NETIF_F_RXHASH;
3692                 if (netdev->features & NETIF_F_RXHASH)
3693                         netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3694         }
3695
3696         mutex_unlock(&priv->state_lock);
3697
3698         return features;
3699 }
3700
3701 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3702                      change_hw_mtu_cb set_mtu_cb)
3703 {
3704         struct mlx5e_priv *priv = netdev_priv(netdev);
3705         struct mlx5e_channels new_channels = {};
3706         struct mlx5e_params *params;
3707         int err = 0;
3708         bool reset;
3709
3710         mutex_lock(&priv->state_lock);
3711
3712         params = &priv->channels.params;
3713
3714         reset = !params->lro_en;
3715         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3716
3717         new_channels.params = *params;
3718         new_channels.params.sw_mtu = new_mtu;
3719
3720         if (params->xdp_prog &&
3721             !mlx5e_rx_is_linear_skb(&new_channels.params)) {
3722                 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3723                            new_mtu, mlx5e_xdp_max_mtu(params));
3724                 err = -EINVAL;
3725                 goto out;
3726         }
3727
3728         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3729                 bool is_linear = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, &new_channels.params);
3730                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params);
3731                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params);
3732
3733                 reset = reset && (is_linear || (ppw_old != ppw_new));
3734         }
3735
3736         if (!reset) {
3737                 params->sw_mtu = new_mtu;
3738                 if (set_mtu_cb)
3739                         set_mtu_cb(priv);
3740                 netdev->mtu = params->sw_mtu;
3741                 goto out;
3742         }
3743
3744         err = mlx5e_safe_switch_channels(priv, &new_channels, set_mtu_cb);
3745         if (err)
3746                 goto out;
3747
3748         netdev->mtu = new_channels.params.sw_mtu;
3749
3750 out:
3751         mutex_unlock(&priv->state_lock);
3752         return err;
3753 }
3754
3755 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3756 {
3757         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu);
3758 }
3759
3760 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3761 {
3762         struct hwtstamp_config config;
3763         int err;
3764
3765         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
3766             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
3767                 return -EOPNOTSUPP;
3768
3769         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3770                 return -EFAULT;
3771
3772         /* TX HW timestamp */
3773         switch (config.tx_type) {
3774         case HWTSTAMP_TX_OFF:
3775         case HWTSTAMP_TX_ON:
3776                 break;
3777         default:
3778                 return -ERANGE;
3779         }
3780
3781         mutex_lock(&priv->state_lock);
3782         /* RX HW timestamp */
3783         switch (config.rx_filter) {
3784         case HWTSTAMP_FILTER_NONE:
3785                 /* Reset CQE compression to Admin default */
3786                 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3787                 break;
3788         case HWTSTAMP_FILTER_ALL:
3789         case HWTSTAMP_FILTER_SOME:
3790         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3791         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3792         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3793         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3794         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3795         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3796         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3797         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3798         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3799         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3800         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3801         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3802         case HWTSTAMP_FILTER_NTP_ALL:
3803                 /* Disable CQE compression */
3804                 netdev_warn(priv->netdev, "Disabling cqe compression");
3805                 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3806                 if (err) {
3807                         netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3808                         mutex_unlock(&priv->state_lock);
3809                         return err;
3810                 }
3811                 config.rx_filter = HWTSTAMP_FILTER_ALL;
3812                 break;
3813         default:
3814                 mutex_unlock(&priv->state_lock);
3815                 return -ERANGE;
3816         }
3817
3818         memcpy(&priv->tstamp, &config, sizeof(config));
3819         mutex_unlock(&priv->state_lock);
3820
3821         /* might need to fix some features */
3822         netdev_update_features(priv->netdev);
3823
3824         return copy_to_user(ifr->ifr_data, &config,
3825                             sizeof(config)) ? -EFAULT : 0;
3826 }
3827
3828 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3829 {
3830         struct hwtstamp_config *cfg = &priv->tstamp;
3831
3832         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3833                 return -EOPNOTSUPP;
3834
3835         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3836 }
3837
3838 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3839 {
3840         struct mlx5e_priv *priv = netdev_priv(dev);
3841
3842         switch (cmd) {
3843         case SIOCSHWTSTAMP:
3844                 return mlx5e_hwstamp_set(priv, ifr);
3845         case SIOCGHWTSTAMP:
3846                 return mlx5e_hwstamp_get(priv, ifr);
3847         default:
3848                 return -EOPNOTSUPP;
3849         }
3850 }
3851
3852 #ifdef CONFIG_MLX5_ESWITCH
3853 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3854 {
3855         struct mlx5e_priv *priv = netdev_priv(dev);
3856         struct mlx5_core_dev *mdev = priv->mdev;
3857
3858         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3859 }
3860
3861 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3862                              __be16 vlan_proto)
3863 {
3864         struct mlx5e_priv *priv = netdev_priv(dev);
3865         struct mlx5_core_dev *mdev = priv->mdev;
3866
3867         if (vlan_proto != htons(ETH_P_8021Q))
3868                 return -EPROTONOSUPPORT;
3869
3870         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3871                                            vlan, qos);
3872 }
3873
3874 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3875 {
3876         struct mlx5e_priv *priv = netdev_priv(dev);
3877         struct mlx5_core_dev *mdev = priv->mdev;
3878
3879         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3880 }
3881
3882 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3883 {
3884         struct mlx5e_priv *priv = netdev_priv(dev);
3885         struct mlx5_core_dev *mdev = priv->mdev;
3886
3887         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3888 }
3889
3890 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3891                       int max_tx_rate)
3892 {
3893         struct mlx5e_priv *priv = netdev_priv(dev);
3894         struct mlx5_core_dev *mdev = priv->mdev;
3895
3896         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3897                                            max_tx_rate, min_tx_rate);
3898 }
3899
3900 static int mlx5_vport_link2ifla(u8 esw_link)
3901 {
3902         switch (esw_link) {
3903         case MLX5_VPORT_ADMIN_STATE_DOWN:
3904                 return IFLA_VF_LINK_STATE_DISABLE;
3905         case MLX5_VPORT_ADMIN_STATE_UP:
3906                 return IFLA_VF_LINK_STATE_ENABLE;
3907         }
3908         return IFLA_VF_LINK_STATE_AUTO;
3909 }
3910
3911 static int mlx5_ifla_link2vport(u8 ifla_link)
3912 {
3913         switch (ifla_link) {
3914         case IFLA_VF_LINK_STATE_DISABLE:
3915                 return MLX5_VPORT_ADMIN_STATE_DOWN;
3916         case IFLA_VF_LINK_STATE_ENABLE:
3917                 return MLX5_VPORT_ADMIN_STATE_UP;
3918         }
3919         return MLX5_VPORT_ADMIN_STATE_AUTO;
3920 }
3921
3922 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3923                                    int link_state)
3924 {
3925         struct mlx5e_priv *priv = netdev_priv(dev);
3926         struct mlx5_core_dev *mdev = priv->mdev;
3927
3928         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3929                                             mlx5_ifla_link2vport(link_state));
3930 }
3931
3932 int mlx5e_get_vf_config(struct net_device *dev,
3933                         int vf, struct ifla_vf_info *ivi)
3934 {
3935         struct mlx5e_priv *priv = netdev_priv(dev);
3936         struct mlx5_core_dev *mdev = priv->mdev;
3937         int err;
3938
3939         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3940         if (err)
3941                 return err;
3942         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3943         return 0;
3944 }
3945
3946 int mlx5e_get_vf_stats(struct net_device *dev,
3947                        int vf, struct ifla_vf_stats *vf_stats)
3948 {
3949         struct mlx5e_priv *priv = netdev_priv(dev);
3950         struct mlx5_core_dev *mdev = priv->mdev;
3951
3952         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3953                                             vf_stats);
3954 }
3955 #endif
3956
3957 struct mlx5e_vxlan_work {
3958         struct work_struct      work;
3959         struct mlx5e_priv       *priv;
3960         u16                     port;
3961 };
3962
3963 static void mlx5e_vxlan_add_work(struct work_struct *work)
3964 {
3965         struct mlx5e_vxlan_work *vxlan_work =
3966                 container_of(work, struct mlx5e_vxlan_work, work);
3967         struct mlx5e_priv *priv = vxlan_work->priv;
3968         u16 port = vxlan_work->port;
3969
3970         mutex_lock(&priv->state_lock);
3971         mlx5_vxlan_add_port(priv->mdev->vxlan, port);
3972         mutex_unlock(&priv->state_lock);
3973
3974         kfree(vxlan_work);
3975 }
3976
3977 static void mlx5e_vxlan_del_work(struct work_struct *work)
3978 {
3979         struct mlx5e_vxlan_work *vxlan_work =
3980                 container_of(work, struct mlx5e_vxlan_work, work);
3981         struct mlx5e_priv *priv         = vxlan_work->priv;
3982         u16 port = vxlan_work->port;
3983
3984         mutex_lock(&priv->state_lock);
3985         mlx5_vxlan_del_port(priv->mdev->vxlan, port);
3986         mutex_unlock(&priv->state_lock);
3987         kfree(vxlan_work);
3988 }
3989
3990 static void mlx5e_vxlan_queue_work(struct mlx5e_priv *priv, u16 port, int add)
3991 {
3992         struct mlx5e_vxlan_work *vxlan_work;
3993
3994         vxlan_work = kmalloc(sizeof(*vxlan_work), GFP_ATOMIC);
3995         if (!vxlan_work)
3996                 return;
3997
3998         if (add)
3999                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_add_work);
4000         else
4001                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_del_work);
4002
4003         vxlan_work->priv = priv;
4004         vxlan_work->port = port;
4005         queue_work(priv->wq, &vxlan_work->work);
4006 }
4007
4008 void mlx5e_add_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4009 {
4010         struct mlx5e_priv *priv = netdev_priv(netdev);
4011
4012         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4013                 return;
4014
4015         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4016                 return;
4017
4018         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 1);
4019 }
4020
4021 void mlx5e_del_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4022 {
4023         struct mlx5e_priv *priv = netdev_priv(netdev);
4024
4025         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4026                 return;
4027
4028         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4029                 return;
4030
4031         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 0);
4032 }
4033
4034 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4035                                                      struct sk_buff *skb,
4036                                                      netdev_features_t features)
4037 {
4038         unsigned int offset = 0;
4039         struct udphdr *udph;
4040         u8 proto;
4041         u16 port;
4042
4043         switch (vlan_get_protocol(skb)) {
4044         case htons(ETH_P_IP):
4045                 proto = ip_hdr(skb)->protocol;
4046                 break;
4047         case htons(ETH_P_IPV6):
4048                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4049                 break;
4050         default:
4051                 goto out;
4052         }
4053
4054         switch (proto) {
4055         case IPPROTO_GRE:
4056                 return features;
4057         case IPPROTO_UDP:
4058                 udph = udp_hdr(skb);
4059                 port = be16_to_cpu(udph->dest);
4060
4061                 /* Verify if UDP port is being offloaded by HW */
4062                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4063                         return features;
4064
4065 #if IS_ENABLED(CONFIG_GENEVE)
4066                 /* Support Geneve offload for default UDP port */
4067                 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4068                         return features;
4069 #endif
4070         }
4071
4072 out:
4073         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4074         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4075 }
4076
4077 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4078                                        struct net_device *netdev,
4079                                        netdev_features_t features)
4080 {
4081         struct mlx5e_priv *priv = netdev_priv(netdev);
4082
4083         features = vlan_features_check(skb, features);
4084         features = vxlan_features_check(skb, features);
4085
4086 #ifdef CONFIG_MLX5_EN_IPSEC
4087         if (mlx5e_ipsec_feature_check(skb, netdev, features))
4088                 return features;
4089 #endif
4090
4091         /* Validate if the tunneled packet is being offloaded by HW */
4092         if (skb->encapsulation &&
4093             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4094                 return mlx5e_tunnel_features_check(priv, skb, features);
4095
4096         return features;
4097 }
4098
4099 static void mlx5e_tx_timeout_work(struct work_struct *work)
4100 {
4101         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4102                                                tx_timeout_work);
4103         bool report_failed = false;
4104         int err;
4105         int i;
4106
4107         rtnl_lock();
4108         mutex_lock(&priv->state_lock);
4109
4110         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4111                 goto unlock;
4112
4113         for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
4114                 struct netdev_queue *dev_queue =
4115                         netdev_get_tx_queue(priv->netdev, i);
4116                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4117
4118                 if (!netif_xmit_stopped(dev_queue))
4119                         continue;
4120
4121                 if (mlx5e_tx_reporter_timeout(sq))
4122                         report_failed = true;
4123         }
4124
4125         if (!report_failed)
4126                 goto unlock;
4127
4128         err = mlx5e_safe_reopen_channels(priv);
4129         if (err)
4130                 netdev_err(priv->netdev,
4131                            "mlx5e_safe_reopen_channels failed recovering from a tx_timeout, err(%d).\n",
4132                            err);
4133
4134 unlock:
4135         mutex_unlock(&priv->state_lock);
4136         rtnl_unlock();
4137 }
4138
4139 static void mlx5e_tx_timeout(struct net_device *dev)
4140 {
4141         struct mlx5e_priv *priv = netdev_priv(dev);
4142
4143         netdev_err(dev, "TX timeout detected\n");
4144         queue_work(priv->wq, &priv->tx_timeout_work);
4145 }
4146
4147 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4148 {
4149         struct net_device *netdev = priv->netdev;
4150         struct mlx5e_channels new_channels = {};
4151
4152         if (priv->channels.params.lro_en) {
4153                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4154                 return -EINVAL;
4155         }
4156
4157         if (MLX5_IPSEC_DEV(priv->mdev)) {
4158                 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4159                 return -EINVAL;
4160         }
4161
4162         new_channels.params = priv->channels.params;
4163         new_channels.params.xdp_prog = prog;
4164
4165         if (!mlx5e_rx_is_linear_skb(&new_channels.params)) {
4166                 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4167                             new_channels.params.sw_mtu,
4168                             mlx5e_xdp_max_mtu(&new_channels.params));
4169                 return -EINVAL;
4170         }
4171
4172         return 0;
4173 }
4174
4175 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4176 {
4177         struct mlx5e_priv *priv = netdev_priv(netdev);
4178         struct bpf_prog *old_prog;
4179         bool reset, was_opened;
4180         int err = 0;
4181         int i;
4182
4183         mutex_lock(&priv->state_lock);
4184
4185         if (prog) {
4186                 err = mlx5e_xdp_allowed(priv, prog);
4187                 if (err)
4188                         goto unlock;
4189         }
4190
4191         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4192         /* no need for full reset when exchanging programs */
4193         reset = (!priv->channels.params.xdp_prog || !prog);
4194
4195         if (was_opened && reset)
4196                 mlx5e_close_locked(netdev);
4197         if (was_opened && !reset) {
4198                 /* num_channels is invariant here, so we can take the
4199                  * batched reference right upfront.
4200                  */
4201                 prog = bpf_prog_add(prog, priv->channels.num);
4202                 if (IS_ERR(prog)) {
4203                         err = PTR_ERR(prog);
4204                         goto unlock;
4205                 }
4206         }
4207
4208         /* exchange programs, extra prog reference we got from caller
4209          * as long as we don't fail from this point onwards.
4210          */
4211         old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4212         if (old_prog)
4213                 bpf_prog_put(old_prog);
4214
4215         if (reset) /* change RQ type according to priv->xdp_prog */
4216                 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4217
4218         if (was_opened && reset)
4219                 err = mlx5e_open_locked(netdev);
4220
4221         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4222                 goto unlock;
4223
4224         /* exchanging programs w/o reset, we update ref counts on behalf
4225          * of the channels RQs here.
4226          */
4227         for (i = 0; i < priv->channels.num; i++) {
4228                 struct mlx5e_channel *c = priv->channels.c[i];
4229
4230                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4231                 napi_synchronize(&c->napi);
4232                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4233
4234                 old_prog = xchg(&c->rq.xdp_prog, prog);
4235
4236                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4237                 /* napi_schedule in case we have missed anything */
4238                 napi_schedule(&c->napi);
4239
4240                 if (old_prog)
4241                         bpf_prog_put(old_prog);
4242         }
4243
4244 unlock:
4245         mutex_unlock(&priv->state_lock);
4246         return err;
4247 }
4248
4249 static u32 mlx5e_xdp_query(struct net_device *dev)
4250 {
4251         struct mlx5e_priv *priv = netdev_priv(dev);
4252         const struct bpf_prog *xdp_prog;
4253         u32 prog_id = 0;
4254
4255         mutex_lock(&priv->state_lock);
4256         xdp_prog = priv->channels.params.xdp_prog;
4257         if (xdp_prog)
4258                 prog_id = xdp_prog->aux->id;
4259         mutex_unlock(&priv->state_lock);
4260
4261         return prog_id;
4262 }
4263
4264 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4265 {
4266         switch (xdp->command) {
4267         case XDP_SETUP_PROG:
4268                 return mlx5e_xdp_set(dev, xdp->prog);
4269         case XDP_QUERY_PROG:
4270                 xdp->prog_id = mlx5e_xdp_query(dev);
4271                 return 0;
4272         default:
4273                 return -EINVAL;
4274         }
4275 }
4276
4277 #ifdef CONFIG_MLX5_ESWITCH
4278 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4279                                 struct net_device *dev, u32 filter_mask,
4280                                 int nlflags)
4281 {
4282         struct mlx5e_priv *priv = netdev_priv(dev);
4283         struct mlx5_core_dev *mdev = priv->mdev;
4284         u8 mode, setting;
4285         int err;
4286
4287         err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4288         if (err)
4289                 return err;
4290         mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4291         return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4292                                        mode,
4293                                        0, 0, nlflags, filter_mask, NULL);
4294 }
4295
4296 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4297                                 u16 flags, struct netlink_ext_ack *extack)
4298 {
4299         struct mlx5e_priv *priv = netdev_priv(dev);
4300         struct mlx5_core_dev *mdev = priv->mdev;
4301         struct nlattr *attr, *br_spec;
4302         u16 mode = BRIDGE_MODE_UNDEF;
4303         u8 setting;
4304         int rem;
4305
4306         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4307         if (!br_spec)
4308                 return -EINVAL;
4309
4310         nla_for_each_nested(attr, br_spec, rem) {
4311                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4312                         continue;
4313
4314                 if (nla_len(attr) < sizeof(mode))
4315                         return -EINVAL;
4316
4317                 mode = nla_get_u16(attr);
4318                 if (mode > BRIDGE_MODE_VEPA)
4319                         return -EINVAL;
4320
4321                 break;
4322         }
4323
4324         if (mode == BRIDGE_MODE_UNDEF)
4325                 return -EINVAL;
4326
4327         setting = (mode == BRIDGE_MODE_VEPA) ?  1 : 0;
4328         return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4329 }
4330 #endif
4331
4332 const struct net_device_ops mlx5e_netdev_ops = {
4333         .ndo_open                = mlx5e_open,
4334         .ndo_stop                = mlx5e_close,
4335         .ndo_start_xmit          = mlx5e_xmit,
4336         .ndo_setup_tc            = mlx5e_setup_tc,
4337         .ndo_select_queue        = mlx5e_select_queue,
4338         .ndo_get_stats64         = mlx5e_get_stats,
4339         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4340         .ndo_set_mac_address     = mlx5e_set_mac,
4341         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4342         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4343         .ndo_set_features        = mlx5e_set_features,
4344         .ndo_fix_features        = mlx5e_fix_features,
4345         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4346         .ndo_do_ioctl            = mlx5e_ioctl,
4347         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4348         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
4349         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
4350         .ndo_features_check      = mlx5e_features_check,
4351         .ndo_tx_timeout          = mlx5e_tx_timeout,
4352         .ndo_bpf                 = mlx5e_xdp,
4353         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4354 #ifdef CONFIG_MLX5_EN_ARFS
4355         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4356 #endif
4357 #ifdef CONFIG_MLX5_ESWITCH
4358         .ndo_bridge_setlink      = mlx5e_bridge_setlink,
4359         .ndo_bridge_getlink      = mlx5e_bridge_getlink,
4360
4361         /* SRIOV E-Switch NDOs */
4362         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4363         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4364         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4365         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4366         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4367         .ndo_get_vf_config       = mlx5e_get_vf_config,
4368         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4369         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4370 #endif
4371 };
4372
4373 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4374 {
4375         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4376                 return -EOPNOTSUPP;
4377         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4378             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4379             !MLX5_CAP_ETH(mdev, csum_cap) ||
4380             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4381             !MLX5_CAP_ETH(mdev, vlan_cap) ||
4382             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4383             MLX5_CAP_FLOWTABLE(mdev,
4384                                flow_table_properties_nic_receive.max_ft_level)
4385                                < 3) {
4386                 mlx5_core_warn(mdev,
4387                                "Not creating net device, some required device capabilities are missing\n");
4388                 return -EOPNOTSUPP;
4389         }
4390         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4391                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4392         if (!MLX5_CAP_GEN(mdev, cq_moderation))
4393                 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4394
4395         return 0;
4396 }
4397
4398 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4399                                    int num_channels)
4400 {
4401         int i;
4402
4403         for (i = 0; i < len; i++)
4404                 indirection_rqt[i] = i % num_channels;
4405 }
4406
4407 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4408 {
4409         u32 link_speed = 0;
4410         u32 pci_bw = 0;
4411
4412         mlx5e_port_max_linkspeed(mdev, &link_speed);
4413         pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4414         mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4415                            link_speed, pci_bw);
4416
4417 #define MLX5E_SLOW_PCI_RATIO (2)
4418
4419         return link_speed && pci_bw &&
4420                 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4421 }
4422
4423 static struct net_dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4424 {
4425         struct net_dim_cq_moder moder;
4426
4427         moder.cq_period_mode = cq_period_mode;
4428         moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4429         moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4430         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4431                 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4432
4433         return moder;
4434 }
4435
4436 static struct net_dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4437 {
4438         struct net_dim_cq_moder moder;
4439
4440         moder.cq_period_mode = cq_period_mode;
4441         moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4442         moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4443         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4444                 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4445
4446         return moder;
4447 }
4448
4449 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4450 {
4451         return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4452                 NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4453                 NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4454 }
4455
4456 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4457 {
4458         if (params->tx_dim_enabled) {
4459                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4460
4461                 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4462         } else {
4463                 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4464         }
4465
4466         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4467                         params->tx_cq_moderation.cq_period_mode ==
4468                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4469 }
4470
4471 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4472 {
4473         if (params->rx_dim_enabled) {
4474                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4475
4476                 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4477         } else {
4478                 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4479         }
4480
4481         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4482                         params->rx_cq_moderation.cq_period_mode ==
4483                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4484 }
4485
4486 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4487 {
4488         int i;
4489
4490         /* The supported periods are organized in ascending order */
4491         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4492                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4493                         break;
4494
4495         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4496 }
4497
4498 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
4499                            struct mlx5e_params *params)
4500 {
4501         /* Prefer Striding RQ, unless any of the following holds:
4502          * - Striding RQ configuration is not possible/supported.
4503          * - Slow PCI heuristic.
4504          * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4505          */
4506         if (!slow_pci_heuristic(mdev) &&
4507             mlx5e_striding_rq_possible(mdev, params) &&
4508             (mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ||
4509              !mlx5e_rx_is_linear_skb(params)))
4510                 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4511         mlx5e_set_rq_type(mdev, params);
4512         mlx5e_init_rq_type_params(mdev, params);
4513 }
4514
4515 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
4516                             u16 num_channels)
4517 {
4518         enum mlx5e_traffic_types tt;
4519
4520         rss_params->hfunc = ETH_RSS_HASH_TOP;
4521         netdev_rss_key_fill(rss_params->toeplitz_hash_key,
4522                             sizeof(rss_params->toeplitz_hash_key));
4523         mlx5e_build_default_indir_rqt(rss_params->indirection_rqt,
4524                                       MLX5E_INDIR_RQT_SIZE, num_channels);
4525         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
4526                 rss_params->rx_hash_fields[tt] =
4527                         tirc_default_config[tt].rx_hash_fields;
4528 }
4529
4530 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4531                             struct mlx5e_rss_params *rss_params,
4532                             struct mlx5e_params *params,
4533                             u16 max_channels, u16 mtu)
4534 {
4535         u8 rx_cq_period_mode;
4536
4537         params->sw_mtu = mtu;
4538         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4539         params->num_channels = max_channels;
4540         params->num_tc       = 1;
4541
4542         /* SQ */
4543         params->log_sq_size = is_kdump_kernel() ?
4544                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4545                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4546
4547         /* XDP SQ */
4548         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE,
4549                         MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
4550
4551         /* set CQE compression */
4552         params->rx_cqe_compress_def = false;
4553         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4554             MLX5_CAP_GEN(mdev, vport_group_manager))
4555                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4556
4557         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4558         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4559
4560         /* RQ */
4561         mlx5e_build_rq_params(mdev, params);
4562
4563         /* HW LRO */
4564
4565         /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4566         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
4567                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
4568                         params->lro_en = !slow_pci_heuristic(mdev);
4569         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4570
4571         /* CQ moderation params */
4572         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4573                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4574                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4575         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4576         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4577         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4578         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4579
4580         /* TX inline */
4581         params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
4582
4583         /* RSS */
4584         mlx5e_build_rss_params(rss_params, params->num_channels);
4585         params->tunneled_offload_en =
4586                 mlx5e_tunnel_inner_ft_supported(mdev);
4587 }
4588
4589 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4590 {
4591         struct mlx5e_priv *priv = netdev_priv(netdev);
4592
4593         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
4594         if (is_zero_ether_addr(netdev->dev_addr) &&
4595             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4596                 eth_hw_addr_random(netdev);
4597                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4598         }
4599 }
4600
4601 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4602 {
4603         struct mlx5e_priv *priv = netdev_priv(netdev);
4604         struct mlx5_core_dev *mdev = priv->mdev;
4605         bool fcs_supported;
4606         bool fcs_enabled;
4607
4608         SET_NETDEV_DEV(netdev, mdev->device);
4609
4610         netdev->netdev_ops = &mlx5e_netdev_ops;
4611
4612 #ifdef CONFIG_MLX5_CORE_EN_DCB
4613         if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4614                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4615 #endif
4616
4617         netdev->watchdog_timeo    = 15 * HZ;
4618
4619         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4620
4621         netdev->vlan_features    |= NETIF_F_SG;
4622         netdev->vlan_features    |= NETIF_F_IP_CSUM;
4623         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
4624         netdev->vlan_features    |= NETIF_F_GRO;
4625         netdev->vlan_features    |= NETIF_F_TSO;
4626         netdev->vlan_features    |= NETIF_F_TSO6;
4627         netdev->vlan_features    |= NETIF_F_RXCSUM;
4628         netdev->vlan_features    |= NETIF_F_RXHASH;
4629
4630         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4631         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4632
4633         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4634             mlx5e_check_fragmented_striding_rq_cap(mdev))
4635                 netdev->vlan_features    |= NETIF_F_LRO;
4636
4637         netdev->hw_features       = netdev->vlan_features;
4638         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4639         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4640         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4641         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4642
4643         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev) ||
4644             MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4645                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
4646                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
4647                 netdev->hw_enc_features |= NETIF_F_TSO;
4648                 netdev->hw_enc_features |= NETIF_F_TSO6;
4649                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4650         }
4651
4652         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4653                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4654                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4655                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4656                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4657                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4658         }
4659
4660         if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4661                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4662                                            NETIF_F_GSO_GRE_CSUM;
4663                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4664                                            NETIF_F_GSO_GRE_CSUM;
4665                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4666                                                 NETIF_F_GSO_GRE_CSUM;
4667         }
4668
4669         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4670         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4671         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4672         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4673
4674         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4675
4676         if (fcs_supported)
4677                 netdev->hw_features |= NETIF_F_RXALL;
4678
4679         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4680                 netdev->hw_features |= NETIF_F_RXFCS;
4681
4682         netdev->features          = netdev->hw_features;
4683         if (!priv->channels.params.lro_en)
4684                 netdev->features  &= ~NETIF_F_LRO;
4685
4686         if (fcs_enabled)
4687                 netdev->features  &= ~NETIF_F_RXALL;
4688
4689         if (!priv->channels.params.scatter_fcs_en)
4690                 netdev->features  &= ~NETIF_F_RXFCS;
4691
4692         /* prefere CQE compression over rxhash */
4693         if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4694                 netdev->features &= ~NETIF_F_RXHASH;
4695
4696 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4697         if (FT_CAP(flow_modify_en) &&
4698             FT_CAP(modify_root) &&
4699             FT_CAP(identified_miss_table_mode) &&
4700             FT_CAP(flow_table_modify)) {
4701 #ifdef CONFIG_MLX5_ESWITCH
4702                 netdev->hw_features      |= NETIF_F_HW_TC;
4703 #endif
4704 #ifdef CONFIG_MLX5_EN_ARFS
4705                 netdev->hw_features      |= NETIF_F_NTUPLE;
4706 #endif
4707         }
4708
4709         netdev->features         |= NETIF_F_HIGHDMA;
4710         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4711
4712         netdev->priv_flags       |= IFF_UNICAST_FLT;
4713
4714         mlx5e_set_netdev_dev_addr(netdev);
4715         mlx5e_ipsec_build_netdev(priv);
4716         mlx5e_tls_build_netdev(priv);
4717 }
4718
4719 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4720 {
4721         struct mlx5_core_dev *mdev = priv->mdev;
4722         int err;
4723
4724         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4725         if (err) {
4726                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4727                 priv->q_counter = 0;
4728         }
4729
4730         err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4731         if (err) {
4732                 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4733                 priv->drop_rq_q_counter = 0;
4734         }
4735 }
4736
4737 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4738 {
4739         if (priv->q_counter)
4740                 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4741
4742         if (priv->drop_rq_q_counter)
4743                 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
4744 }
4745
4746 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
4747                           struct net_device *netdev,
4748                           const struct mlx5e_profile *profile,
4749                           void *ppriv)
4750 {
4751         struct mlx5e_priv *priv = netdev_priv(netdev);
4752         struct mlx5e_rss_params *rss = &priv->rss_params;
4753         int err;
4754
4755         err = mlx5e_netdev_init(netdev, priv, mdev, profile, ppriv);
4756         if (err)
4757                 return err;
4758
4759         mlx5e_build_nic_params(mdev, rss, &priv->channels.params,
4760                                mlx5e_get_netdev_max_channels(netdev),
4761                                netdev->mtu);
4762
4763         mlx5e_timestamp_init(priv);
4764
4765         err = mlx5e_ipsec_init(priv);
4766         if (err)
4767                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4768         err = mlx5e_tls_init(priv);
4769         if (err)
4770                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4771         mlx5e_build_nic_netdev(netdev);
4772         mlx5e_build_tc2txq_maps(priv);
4773
4774         return 0;
4775 }
4776
4777 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4778 {
4779         mlx5e_tls_cleanup(priv);
4780         mlx5e_ipsec_cleanup(priv);
4781         mlx5e_netdev_cleanup(priv->netdev, priv);
4782 }
4783
4784 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4785 {
4786         struct mlx5_core_dev *mdev = priv->mdev;
4787         int err;
4788
4789         mlx5e_create_q_counters(priv);
4790
4791         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4792         if (err) {
4793                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4794                 goto err_destroy_q_counters;
4795         }
4796
4797         err = mlx5e_create_indirect_rqt(priv);
4798         if (err)
4799                 goto err_close_drop_rq;
4800
4801         err = mlx5e_create_direct_rqts(priv);
4802         if (err)
4803                 goto err_destroy_indirect_rqts;
4804
4805         err = mlx5e_create_indirect_tirs(priv, true);
4806         if (err)
4807                 goto err_destroy_direct_rqts;
4808
4809         err = mlx5e_create_direct_tirs(priv);
4810         if (err)
4811                 goto err_destroy_indirect_tirs;
4812
4813         err = mlx5e_create_flow_steering(priv);
4814         if (err) {
4815                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4816                 goto err_destroy_direct_tirs;
4817         }
4818
4819         err = mlx5e_tc_nic_init(priv);
4820         if (err)
4821                 goto err_destroy_flow_steering;
4822
4823         return 0;
4824
4825 err_destroy_flow_steering:
4826         mlx5e_destroy_flow_steering(priv);
4827 err_destroy_direct_tirs:
4828         mlx5e_destroy_direct_tirs(priv);
4829 err_destroy_indirect_tirs:
4830         mlx5e_destroy_indirect_tirs(priv, true);
4831 err_destroy_direct_rqts:
4832         mlx5e_destroy_direct_rqts(priv);
4833 err_destroy_indirect_rqts:
4834         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4835 err_close_drop_rq:
4836         mlx5e_close_drop_rq(&priv->drop_rq);
4837 err_destroy_q_counters:
4838         mlx5e_destroy_q_counters(priv);
4839         return err;
4840 }
4841
4842 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4843 {
4844         mlx5e_tc_nic_cleanup(priv);
4845         mlx5e_destroy_flow_steering(priv);
4846         mlx5e_destroy_direct_tirs(priv);
4847         mlx5e_destroy_indirect_tirs(priv, true);
4848         mlx5e_destroy_direct_rqts(priv);
4849         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4850         mlx5e_close_drop_rq(&priv->drop_rq);
4851         mlx5e_destroy_q_counters(priv);
4852 }
4853
4854 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4855 {
4856         int err;
4857
4858         err = mlx5e_create_tises(priv);
4859         if (err) {
4860                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4861                 return err;
4862         }
4863
4864 #ifdef CONFIG_MLX5_CORE_EN_DCB
4865         mlx5e_dcbnl_initialize(priv);
4866 #endif
4867         mlx5e_tx_reporter_create(priv);
4868         return 0;
4869 }
4870
4871 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4872 {
4873         struct net_device *netdev = priv->netdev;
4874         struct mlx5_core_dev *mdev = priv->mdev;
4875
4876         mlx5e_init_l2_addr(priv);
4877
4878         /* Marking the link as currently not needed by the Driver */
4879         if (!netif_running(netdev))
4880                 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4881
4882         mlx5e_set_netdev_mtu_boundaries(priv);
4883         mlx5e_set_dev_port_mtu(priv);
4884
4885         mlx5_lag_add(mdev, netdev);
4886
4887         mlx5e_enable_async_events(priv);
4888         if (mlx5e_monitor_counter_supported(priv))
4889                 mlx5e_monitor_counter_init(priv);
4890
4891         if (netdev->reg_state != NETREG_REGISTERED)
4892                 return;
4893 #ifdef CONFIG_MLX5_CORE_EN_DCB
4894         mlx5e_dcbnl_init_app(priv);
4895 #endif
4896
4897         queue_work(priv->wq, &priv->set_rx_mode_work);
4898
4899         rtnl_lock();
4900         if (netif_running(netdev))
4901                 mlx5e_open(netdev);
4902         netif_device_attach(netdev);
4903         rtnl_unlock();
4904 }
4905
4906 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4907 {
4908         struct mlx5_core_dev *mdev = priv->mdev;
4909
4910 #ifdef CONFIG_MLX5_CORE_EN_DCB
4911         if (priv->netdev->reg_state == NETREG_REGISTERED)
4912                 mlx5e_dcbnl_delete_app(priv);
4913 #endif
4914
4915         rtnl_lock();
4916         if (netif_running(priv->netdev))
4917                 mlx5e_close(priv->netdev);
4918         netif_device_detach(priv->netdev);
4919         rtnl_unlock();
4920
4921         queue_work(priv->wq, &priv->set_rx_mode_work);
4922
4923         if (mlx5e_monitor_counter_supported(priv))
4924                 mlx5e_monitor_counter_cleanup(priv);
4925
4926         mlx5e_disable_async_events(priv);
4927         mlx5_lag_remove(mdev);
4928 }
4929
4930 static const struct mlx5e_profile mlx5e_nic_profile = {
4931         .init              = mlx5e_nic_init,
4932         .cleanup           = mlx5e_nic_cleanup,
4933         .init_rx           = mlx5e_init_nic_rx,
4934         .cleanup_rx        = mlx5e_cleanup_nic_rx,
4935         .init_tx           = mlx5e_init_nic_tx,
4936         .cleanup_tx        = mlx5e_cleanup_nic_tx,
4937         .enable            = mlx5e_nic_enable,
4938         .disable           = mlx5e_nic_disable,
4939         .update_stats      = mlx5e_update_ndo_stats,
4940         .update_carrier    = mlx5e_update_carrier,
4941         .rx_handlers.handle_rx_cqe       = mlx5e_handle_rx_cqe,
4942         .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
4943         .max_tc            = MLX5E_MAX_NUM_TC,
4944 };
4945
4946 /* mlx5e generic netdev management API (move to en_common.c) */
4947
4948 /* mlx5e_netdev_init/cleanup must be called from profile->init/cleanup callbacks */
4949 int mlx5e_netdev_init(struct net_device *netdev,
4950                       struct mlx5e_priv *priv,
4951                       struct mlx5_core_dev *mdev,
4952                       const struct mlx5e_profile *profile,
4953                       void *ppriv)
4954 {
4955         /* priv init */
4956         priv->mdev        = mdev;
4957         priv->netdev      = netdev;
4958         priv->profile     = profile;
4959         priv->ppriv       = ppriv;
4960         priv->msglevel    = MLX5E_MSG_LEVEL;
4961         priv->max_opened_tc = 1;
4962
4963         mutex_init(&priv->state_lock);
4964         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4965         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
4966         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
4967         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
4968
4969         priv->wq = create_singlethread_workqueue("mlx5e");
4970         if (!priv->wq)
4971                 return -ENOMEM;
4972
4973         /* netdev init */
4974         netif_carrier_off(netdev);
4975
4976 #ifdef CONFIG_MLX5_EN_ARFS
4977         netdev->rx_cpu_rmap =  mlx5_eq_table_get_rmap(mdev);
4978 #endif
4979
4980         return 0;
4981 }
4982
4983 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv)
4984 {
4985         destroy_workqueue(priv->wq);
4986 }
4987
4988 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4989                                        const struct mlx5e_profile *profile,
4990                                        int nch,
4991                                        void *ppriv)
4992 {
4993         struct net_device *netdev;
4994         int err;
4995
4996         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
4997                                     nch * profile->max_tc,
4998                                     nch);
4999         if (!netdev) {
5000                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5001                 return NULL;
5002         }
5003
5004         err = profile->init(mdev, netdev, profile, ppriv);
5005         if (err) {
5006                 mlx5_core_err(mdev, "failed to init mlx5e profile %d\n", err);
5007                 goto err_free_netdev;
5008         }
5009
5010         return netdev;
5011
5012 err_free_netdev:
5013         free_netdev(netdev);
5014
5015         return NULL;
5016 }
5017
5018 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5019 {
5020         const struct mlx5e_profile *profile;
5021         int max_nch;
5022         int err;
5023
5024         profile = priv->profile;
5025         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5026
5027         /* max number of channels may have changed */
5028         max_nch = mlx5e_get_max_num_channels(priv->mdev);
5029         if (priv->channels.params.num_channels > max_nch) {
5030                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5031                 priv->channels.params.num_channels = max_nch;
5032                 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
5033                                               MLX5E_INDIR_RQT_SIZE, max_nch);
5034         }
5035
5036         err = profile->init_tx(priv);
5037         if (err)
5038                 goto out;
5039
5040         err = profile->init_rx(priv);
5041         if (err)
5042                 goto err_cleanup_tx;
5043
5044         if (profile->enable)
5045                 profile->enable(priv);
5046
5047         return 0;
5048
5049 err_cleanup_tx:
5050         profile->cleanup_tx(priv);
5051
5052 out:
5053         return err;
5054 }
5055
5056 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5057 {
5058         const struct mlx5e_profile *profile = priv->profile;
5059
5060         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5061
5062         if (profile->disable)
5063                 profile->disable(priv);
5064         flush_workqueue(priv->wq);
5065
5066         profile->cleanup_rx(priv);
5067         profile->cleanup_tx(priv);
5068         cancel_work_sync(&priv->update_stats_work);
5069 }
5070
5071 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5072 {
5073         const struct mlx5e_profile *profile = priv->profile;
5074         struct net_device *netdev = priv->netdev;
5075
5076         if (profile->cleanup)
5077                 profile->cleanup(priv);
5078         free_netdev(netdev);
5079 }
5080
5081 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
5082  * hardware contexts and to connect it to the current netdev.
5083  */
5084 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
5085 {
5086         struct mlx5e_priv *priv = vpriv;
5087         struct net_device *netdev = priv->netdev;
5088         int err;
5089
5090         if (netif_device_present(netdev))
5091                 return 0;
5092
5093         err = mlx5e_create_mdev_resources(mdev);
5094         if (err)
5095                 return err;
5096
5097         err = mlx5e_attach_netdev(priv);
5098         if (err) {
5099                 mlx5e_destroy_mdev_resources(mdev);
5100                 return err;
5101         }
5102
5103         return 0;
5104 }
5105
5106 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
5107 {
5108         struct mlx5e_priv *priv = vpriv;
5109         struct net_device *netdev = priv->netdev;
5110
5111         if (!netif_device_present(netdev))
5112                 return;
5113
5114         mlx5e_detach_netdev(priv);
5115         mlx5e_destroy_mdev_resources(mdev);
5116 }
5117
5118 static void *mlx5e_add(struct mlx5_core_dev *mdev)
5119 {
5120         struct net_device *netdev;
5121         void *priv;
5122         int err;
5123         int nch;
5124
5125         err = mlx5e_check_required_hca_cap(mdev);
5126         if (err)
5127                 return NULL;
5128
5129 #ifdef CONFIG_MLX5_ESWITCH
5130         if (MLX5_ESWITCH_MANAGER(mdev) &&
5131             mlx5_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
5132                 mlx5e_rep_register_vport_reps(mdev);
5133                 return mdev;
5134         }
5135 #endif
5136
5137         nch = mlx5e_get_max_num_channels(mdev);
5138         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, nch, NULL);
5139         if (!netdev) {
5140                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5141                 return NULL;
5142         }
5143
5144         priv = netdev_priv(netdev);
5145
5146         err = mlx5e_attach(mdev, priv);
5147         if (err) {
5148                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
5149                 goto err_destroy_netdev;
5150         }
5151
5152         err = register_netdev(netdev);
5153         if (err) {
5154                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5155                 goto err_detach;
5156         }
5157
5158 #ifdef CONFIG_MLX5_CORE_EN_DCB
5159         mlx5e_dcbnl_init_app(priv);
5160 #endif
5161         return priv;
5162
5163 err_detach:
5164         mlx5e_detach(mdev, priv);
5165 err_destroy_netdev:
5166         mlx5e_destroy_netdev(priv);
5167         return NULL;
5168 }
5169
5170 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5171 {
5172         struct mlx5e_priv *priv;
5173
5174 #ifdef CONFIG_MLX5_ESWITCH
5175         if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev) {
5176                 mlx5e_rep_unregister_vport_reps(mdev);
5177                 return;
5178         }
5179 #endif
5180         priv = vpriv;
5181 #ifdef CONFIG_MLX5_CORE_EN_DCB
5182         mlx5e_dcbnl_delete_app(priv);
5183 #endif
5184         unregister_netdev(priv->netdev);
5185         mlx5e_detach(mdev, vpriv);
5186         mlx5e_destroy_netdev(priv);
5187 }
5188
5189 static struct mlx5_interface mlx5e_interface = {
5190         .add       = mlx5e_add,
5191         .remove    = mlx5e_remove,
5192         .attach    = mlx5e_attach,
5193         .detach    = mlx5e_detach,
5194         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
5195 };
5196
5197 void mlx5e_init(void)
5198 {
5199         mlx5e_ipsec_build_inverse_table();
5200         mlx5e_build_ptys2ethtool_map();
5201         mlx5_register_interface(&mlx5e_interface);
5202 }
5203
5204 void mlx5e_cleanup(void)
5205 {
5206         mlx5_unregister_interface(&mlx5e_interface);
5207 }