2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
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21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
43 MLX5_EN_QP_FLUSH_TIMEOUT_MS = 5000,
44 MLX5_EN_QP_FLUSH_MSLEEP_QUANT = 20,
45 MLX5_EN_QP_FLUSH_MAX_ITER = MLX5_EN_QP_FLUSH_TIMEOUT_MS /
46 MLX5_EN_QP_FLUSH_MSLEEP_QUANT,
49 struct mlx5e_rq_param {
50 u32 rqc[MLX5_ST_SZ_DW(rqc)];
51 struct mlx5_wq_param wq;
55 struct mlx5e_sq_param {
56 u32 sqc[MLX5_ST_SZ_DW(sqc)];
57 struct mlx5_wq_param wq;
63 struct mlx5e_cq_param {
64 u32 cqc[MLX5_ST_SZ_DW(cqc)];
65 struct mlx5_wq_param wq;
70 struct mlx5e_channel_param {
71 struct mlx5e_rq_param rq;
72 struct mlx5e_sq_param sq;
73 struct mlx5e_sq_param icosq;
74 struct mlx5e_cq_param rx_cq;
75 struct mlx5e_cq_param tx_cq;
76 struct mlx5e_cq_param icosq_cq;
79 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
81 struct mlx5_core_dev *mdev = priv->mdev;
84 port_state = mlx5_query_vport_state(mdev,
85 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
87 if (port_state == VPORT_STATE_UP) {
88 netdev_info(priv->netdev, "Link up\n");
89 netif_carrier_on(priv->netdev);
91 netdev_info(priv->netdev, "Link down\n");
92 netif_carrier_off(priv->netdev);
96 static void mlx5e_update_carrier_work(struct work_struct *work)
98 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
101 mutex_lock(&priv->state_lock);
102 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
103 mlx5e_update_carrier(priv);
104 mutex_unlock(&priv->state_lock);
107 static void mlx5e_tx_timeout_work(struct work_struct *work)
109 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
114 mutex_lock(&priv->state_lock);
115 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
117 mlx5e_close_locked(priv->netdev);
118 err = mlx5e_open_locked(priv->netdev);
120 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
123 mutex_unlock(&priv->state_lock);
127 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
129 struct mlx5e_sw_stats *s = &priv->stats.sw;
130 struct mlx5e_rq_stats *rq_stats;
131 struct mlx5e_sq_stats *sq_stats;
132 u64 tx_offload_none = 0;
135 memset(s, 0, sizeof(*s));
136 for (i = 0; i < priv->params.num_channels; i++) {
137 rq_stats = &priv->channel[i]->rq.stats;
139 s->rx_packets += rq_stats->packets;
140 s->rx_bytes += rq_stats->bytes;
141 s->rx_lro_packets += rq_stats->lro_packets;
142 s->rx_lro_bytes += rq_stats->lro_bytes;
143 s->rx_csum_none += rq_stats->csum_none;
144 s->rx_csum_complete += rq_stats->csum_complete;
145 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
146 s->rx_wqe_err += rq_stats->wqe_err;
147 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
148 s->rx_mpwqe_frag += rq_stats->mpwqe_frag;
149 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
150 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
151 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
153 for (j = 0; j < priv->params.num_tc; j++) {
154 sq_stats = &priv->channel[i]->sq[j].stats;
156 s->tx_packets += sq_stats->packets;
157 s->tx_bytes += sq_stats->bytes;
158 s->tx_tso_packets += sq_stats->tso_packets;
159 s->tx_tso_bytes += sq_stats->tso_bytes;
160 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
161 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
162 s->tx_queue_stopped += sq_stats->stopped;
163 s->tx_queue_wake += sq_stats->wake;
164 s->tx_queue_dropped += sq_stats->dropped;
165 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
166 tx_offload_none += sq_stats->csum_none;
170 /* Update calculated offload counters */
171 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
172 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
174 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
175 priv->stats.pport.phy_counters,
176 counter_set.phys_layer_cntrs.link_down_events);
179 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
181 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
182 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
183 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
184 struct mlx5_core_dev *mdev = priv->mdev;
186 memset(in, 0, sizeof(in));
188 MLX5_SET(query_vport_counter_in, in, opcode,
189 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
190 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
191 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
193 memset(out, 0, outlen);
195 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
198 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
200 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
201 struct mlx5_core_dev *mdev = priv->mdev;
202 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
207 in = mlx5_vzalloc(sz);
211 MLX5_SET(ppcnt_reg, in, local_port, 1);
213 out = pstats->IEEE_802_3_counters;
214 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
215 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
217 out = pstats->RFC_2863_counters;
218 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
219 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
221 out = pstats->RFC_2819_counters;
222 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
223 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
225 out = pstats->phy_counters;
226 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
227 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
229 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
230 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
231 out = pstats->per_prio_counters[prio];
232 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
233 mlx5_core_access_reg(mdev, in, sz, out, sz,
234 MLX5_REG_PPCNT, 0, 0);
241 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
243 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
245 if (!priv->q_counter)
248 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
249 &qcnt->rx_out_of_buffer);
252 void mlx5e_update_stats(struct mlx5e_priv *priv)
254 mlx5e_update_q_counter(priv);
255 mlx5e_update_vport_counters(priv);
256 mlx5e_update_pport_counters(priv);
257 mlx5e_update_sw_counters(priv);
260 void mlx5e_update_stats_work(struct work_struct *work)
262 struct delayed_work *dwork = to_delayed_work(work);
263 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
265 mutex_lock(&priv->state_lock);
266 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
267 priv->profile->update_stats(priv);
268 queue_delayed_work(priv->wq, dwork,
269 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
271 mutex_unlock(&priv->state_lock);
274 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
275 enum mlx5_dev_event event, unsigned long param)
277 struct mlx5e_priv *priv = vpriv;
279 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
283 case MLX5_DEV_EVENT_PORT_UP:
284 case MLX5_DEV_EVENT_PORT_DOWN:
285 queue_work(priv->wq, &priv->update_carrier_work);
293 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
295 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
298 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
300 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
301 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
304 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
305 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
307 static int mlx5e_create_rq(struct mlx5e_channel *c,
308 struct mlx5e_rq_param *param,
311 struct mlx5e_priv *priv = c->priv;
312 struct mlx5_core_dev *mdev = priv->mdev;
313 void *rqc = param->rqc;
314 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
320 param->wq.db_numa_node = cpu_to_node(c->cpu);
322 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
327 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
329 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
331 switch (priv->params.rq_wq_type) {
332 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
333 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
334 GFP_KERNEL, cpu_to_node(c->cpu));
337 goto err_rq_wq_destroy;
339 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
340 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
341 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
343 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
344 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
345 rq->wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
346 byte_count = rq->wqe_sz;
348 default: /* MLX5_WQ_TYPE_LINKED_LIST */
349 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
350 cpu_to_node(c->cpu));
353 goto err_rq_wq_destroy;
355 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
356 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
357 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
359 rq->wqe_sz = (priv->params.lro_en) ?
360 priv->params.lro_wqe_sz :
361 MLX5E_SW2HW_MTU(priv->netdev->mtu);
362 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
363 byte_count = rq->wqe_sz;
364 byte_count |= MLX5_HW_START_PADDING;
367 for (i = 0; i < wq_sz; i++) {
368 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
370 wqe->data.byte_count = cpu_to_be32(byte_count);
373 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
374 rq->am.mode = priv->params.rx_cq_period_mode;
376 rq->wq_type = priv->params.rq_wq_type;
378 rq->netdev = c->netdev;
379 rq->tstamp = &priv->tstamp;
383 rq->mkey_be = c->mkey_be;
384 rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
389 mlx5_wq_destroy(&rq->wq_ctrl);
394 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
396 switch (rq->wq_type) {
397 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
400 default: /* MLX5_WQ_TYPE_LINKED_LIST */
404 mlx5_wq_destroy(&rq->wq_ctrl);
407 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
409 struct mlx5e_priv *priv = rq->priv;
410 struct mlx5_core_dev *mdev = priv->mdev;
418 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
419 sizeof(u64) * rq->wq_ctrl.buf.npages;
420 in = mlx5_vzalloc(inlen);
424 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
425 wq = MLX5_ADDR_OF(rqc, rqc, wq);
427 memcpy(rqc, param->rqc, sizeof(param->rqc));
429 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
430 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
431 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
432 MLX5_SET(rqc, rqc, vsd, priv->params.vlan_strip_disable);
433 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
434 MLX5_ADAPTER_PAGE_SHIFT);
435 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
437 mlx5_fill_page_array(&rq->wq_ctrl.buf,
438 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
440 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
447 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
450 struct mlx5e_channel *c = rq->channel;
451 struct mlx5e_priv *priv = c->priv;
452 struct mlx5_core_dev *mdev = priv->mdev;
459 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
460 in = mlx5_vzalloc(inlen);
464 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
466 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
467 MLX5_SET(rqc, rqc, state, next_state);
469 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
476 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
478 struct mlx5e_channel *c = rq->channel;
479 struct mlx5e_priv *priv = c->priv;
480 struct mlx5_core_dev *mdev = priv->mdev;
487 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
488 in = mlx5_vzalloc(inlen);
492 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
494 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
495 MLX5_SET64(modify_rq_in, in, modify_bitmask, MLX5_RQ_BITMASK_VSD);
496 MLX5_SET(rqc, rqc, vsd, vsd);
497 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
499 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
506 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
508 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
511 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
513 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
514 struct mlx5e_channel *c = rq->channel;
515 struct mlx5e_priv *priv = c->priv;
516 struct mlx5_wq_ll *wq = &rq->wq;
518 while (time_before(jiffies, exp_time)) {
519 if (wq->cur_sz >= priv->params.min_rx_wqes)
528 static int mlx5e_open_rq(struct mlx5e_channel *c,
529 struct mlx5e_rq_param *param,
532 struct mlx5e_sq *sq = &c->icosq;
533 u16 pi = sq->pc & sq->wq.sz_m1;
536 err = mlx5e_create_rq(c, param, rq);
540 err = mlx5e_enable_rq(rq, param);
544 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
548 if (param->am_enabled)
549 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
551 set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
553 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_NOP;
554 sq->ico_wqe_info[pi].num_wqebbs = 1;
555 mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
560 mlx5e_disable_rq(rq);
562 mlx5e_destroy_rq(rq);
567 static void mlx5e_close_rq(struct mlx5e_rq *rq)
572 clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
573 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
575 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
576 while (!mlx5_wq_ll_is_empty(&rq->wq) && !err &&
577 tout++ < MLX5_EN_QP_FLUSH_MAX_ITER)
578 msleep(MLX5_EN_QP_FLUSH_MSLEEP_QUANT);
580 if (err || tout == MLX5_EN_QP_FLUSH_MAX_ITER)
581 set_bit(MLX5E_RQ_STATE_FLUSH_TIMEOUT, &rq->state);
583 /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
584 napi_synchronize(&rq->channel->napi);
586 cancel_work_sync(&rq->am.work);
588 mlx5e_disable_rq(rq);
589 mlx5e_free_rx_descs(rq);
590 mlx5e_destroy_rq(rq);
593 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
600 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
602 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
603 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
605 sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
606 sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
608 sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
611 if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
612 mlx5e_free_sq_db(sq);
616 sq->dma_fifo_mask = df_sz - 1;
621 static int mlx5e_create_sq(struct mlx5e_channel *c,
623 struct mlx5e_sq_param *param,
626 struct mlx5e_priv *priv = c->priv;
627 struct mlx5_core_dev *mdev = priv->mdev;
629 void *sqc = param->sqc;
630 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
633 err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
637 param->wq.db_numa_node = cpu_to_node(c->cpu);
639 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq,
642 goto err_unmap_free_uar;
644 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
645 if (sq->uar.bf_map) {
646 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
647 sq->uar_map = sq->uar.bf_map;
649 sq->uar_map = sq->uar.map;
651 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
652 sq->max_inline = param->max_inline;
653 sq->min_inline_mode =
654 MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5E_INLINE_MODE_VPORT_CONTEXT ?
655 param->min_inline_mode : 0;
657 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
659 goto err_sq_wq_destroy;
662 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
664 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
667 cpu_to_node(c->cpu));
668 if (!sq->ico_wqe_info) {
675 txq_ix = c->ix + tc * priv->params.num_channels;
676 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
677 priv->txq_to_sq_map[txq_ix] = sq;
681 sq->tstamp = &priv->tstamp;
682 sq->mkey_be = c->mkey_be;
685 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
686 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
691 mlx5e_free_sq_db(sq);
694 mlx5_wq_destroy(&sq->wq_ctrl);
697 mlx5_unmap_free_uar(mdev, &sq->uar);
702 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
704 struct mlx5e_channel *c = sq->channel;
705 struct mlx5e_priv *priv = c->priv;
707 kfree(sq->ico_wqe_info);
708 mlx5e_free_sq_db(sq);
709 mlx5_wq_destroy(&sq->wq_ctrl);
710 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
713 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
715 struct mlx5e_channel *c = sq->channel;
716 struct mlx5e_priv *priv = c->priv;
717 struct mlx5_core_dev *mdev = priv->mdev;
725 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
726 sizeof(u64) * sq->wq_ctrl.buf.npages;
727 in = mlx5_vzalloc(inlen);
731 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
732 wq = MLX5_ADDR_OF(sqc, sqc, wq);
734 memcpy(sqc, param->sqc, sizeof(param->sqc));
736 MLX5_SET(sqc, sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
737 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
738 MLX5_SET(sqc, sqc, min_wqe_inline_mode, sq->min_inline_mode);
739 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
740 MLX5_SET(sqc, sqc, tis_lst_sz, param->icosq ? 0 : 1);
741 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
743 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
744 MLX5_SET(wq, wq, uar_page, sq->uar.index);
745 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
746 MLX5_ADAPTER_PAGE_SHIFT);
747 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
749 mlx5_fill_page_array(&sq->wq_ctrl.buf,
750 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
752 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
759 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
760 int next_state, bool update_rl, int rl_index)
762 struct mlx5e_channel *c = sq->channel;
763 struct mlx5e_priv *priv = c->priv;
764 struct mlx5_core_dev *mdev = priv->mdev;
771 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
772 in = mlx5_vzalloc(inlen);
776 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
778 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
779 MLX5_SET(sqc, sqc, state, next_state);
780 if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
781 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
782 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
785 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
792 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
794 struct mlx5e_channel *c = sq->channel;
795 struct mlx5e_priv *priv = c->priv;
796 struct mlx5_core_dev *mdev = priv->mdev;
798 mlx5_core_destroy_sq(mdev, sq->sqn);
800 mlx5_rl_remove_rate(mdev, sq->rate_limit);
803 static int mlx5e_open_sq(struct mlx5e_channel *c,
805 struct mlx5e_sq_param *param,
810 err = mlx5e_create_sq(c, tc, param, sq);
814 err = mlx5e_enable_sq(sq, param);
818 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
824 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
825 netdev_tx_reset_queue(sq->txq);
826 netif_tx_start_queue(sq->txq);
832 mlx5e_disable_sq(sq);
834 mlx5e_destroy_sq(sq);
839 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
841 __netif_tx_lock_bh(txq);
842 netif_tx_stop_queue(txq);
843 __netif_tx_unlock_bh(txq);
846 static void mlx5e_close_sq(struct mlx5e_sq *sq)
852 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
853 /* prevent netif_tx_wake_queue */
854 napi_synchronize(&sq->channel->napi);
855 netif_tx_disable_queue(sq->txq);
857 /* ensure hw is notified of all pending wqes */
858 if (mlx5e_sq_has_room_for(sq, 1))
859 mlx5e_send_nop(sq, true);
861 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
862 MLX5_SQC_STATE_ERR, false, 0);
864 set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
867 /* wait till sq is empty, unless a TX timeout occurred on this SQ */
868 while (sq->cc != sq->pc &&
869 !test_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state)) {
870 msleep(MLX5_EN_QP_FLUSH_MSLEEP_QUANT);
871 if (tout++ > MLX5_EN_QP_FLUSH_MAX_ITER)
872 set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
875 /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
876 napi_synchronize(&sq->channel->napi);
878 mlx5e_free_tx_descs(sq);
879 mlx5e_disable_sq(sq);
880 mlx5e_destroy_sq(sq);
883 static int mlx5e_create_cq(struct mlx5e_channel *c,
884 struct mlx5e_cq_param *param,
887 struct mlx5e_priv *priv = c->priv;
888 struct mlx5_core_dev *mdev = priv->mdev;
889 struct mlx5_core_cq *mcq = &cq->mcq;
895 param->wq.buf_numa_node = cpu_to_node(c->cpu);
896 param->wq.db_numa_node = cpu_to_node(c->cpu);
897 param->eq_ix = c->ix;
899 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
904 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
909 mcq->set_ci_db = cq->wq_ctrl.db.db;
910 mcq->arm_db = cq->wq_ctrl.db.db + 1;
913 mcq->vector = param->eq_ix;
914 mcq->comp = mlx5e_completion_event;
915 mcq->event = mlx5e_cq_error_event;
917 mcq->uar = &mdev->mlx5e_res.cq_uar;
919 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
920 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
931 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
933 mlx5_wq_destroy(&cq->wq_ctrl);
936 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
938 struct mlx5e_priv *priv = cq->priv;
939 struct mlx5_core_dev *mdev = priv->mdev;
940 struct mlx5_core_cq *mcq = &cq->mcq;
945 unsigned int irqn_not_used;
949 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
950 sizeof(u64) * cq->wq_ctrl.buf.npages;
951 in = mlx5_vzalloc(inlen);
955 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
957 memcpy(cqc, param->cqc, sizeof(param->cqc));
959 mlx5_fill_page_array(&cq->wq_ctrl.buf,
960 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
962 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
964 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
965 MLX5_SET(cqc, cqc, c_eqn, eqn);
966 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
967 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
968 MLX5_ADAPTER_PAGE_SHIFT);
969 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
971 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
983 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
985 struct mlx5e_priv *priv = cq->priv;
986 struct mlx5_core_dev *mdev = priv->mdev;
988 mlx5_core_destroy_cq(mdev, &cq->mcq);
991 static int mlx5e_open_cq(struct mlx5e_channel *c,
992 struct mlx5e_cq_param *param,
994 struct mlx5e_cq_moder moderation)
997 struct mlx5e_priv *priv = c->priv;
998 struct mlx5_core_dev *mdev = priv->mdev;
1000 err = mlx5e_create_cq(c, param, cq);
1004 err = mlx5e_enable_cq(cq, param);
1006 goto err_destroy_cq;
1008 if (MLX5_CAP_GEN(mdev, cq_moderation))
1009 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
1015 mlx5e_destroy_cq(cq);
1020 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1022 mlx5e_disable_cq(cq);
1023 mlx5e_destroy_cq(cq);
1026 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1028 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1031 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1032 struct mlx5e_channel_param *cparam)
1034 struct mlx5e_priv *priv = c->priv;
1038 for (tc = 0; tc < c->num_tc; tc++) {
1039 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
1040 priv->params.tx_cq_moderation);
1042 goto err_close_tx_cqs;
1048 for (tc--; tc >= 0; tc--)
1049 mlx5e_close_cq(&c->sq[tc].cq);
1054 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1058 for (tc = 0; tc < c->num_tc; tc++)
1059 mlx5e_close_cq(&c->sq[tc].cq);
1062 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1063 struct mlx5e_channel_param *cparam)
1068 for (tc = 0; tc < c->num_tc; tc++) {
1069 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1077 for (tc--; tc >= 0; tc--)
1078 mlx5e_close_sq(&c->sq[tc]);
1083 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1087 for (tc = 0; tc < c->num_tc; tc++)
1088 mlx5e_close_sq(&c->sq[tc]);
1091 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1095 for (i = 0; i < priv->profile->max_tc; i++)
1096 priv->channeltc_to_txq_map[ix][i] =
1097 ix + i * priv->params.num_channels;
1100 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1101 struct mlx5e_sq *sq, u32 rate)
1103 struct mlx5e_priv *priv = netdev_priv(dev);
1104 struct mlx5_core_dev *mdev = priv->mdev;
1108 if (rate == sq->rate_limit)
1113 /* remove current rl index to free space to next ones */
1114 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1119 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1121 netdev_err(dev, "Failed configuring rate %u: %d\n",
1127 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1128 MLX5_SQC_STATE_RDY, true, rl_index);
1130 netdev_err(dev, "Failed configuring rate %u: %d\n",
1132 /* remove the rate from the table */
1134 mlx5_rl_remove_rate(mdev, rate);
1138 sq->rate_limit = rate;
1142 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1144 struct mlx5e_priv *priv = netdev_priv(dev);
1145 struct mlx5_core_dev *mdev = priv->mdev;
1146 struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1149 if (!mlx5_rl_is_supported(mdev)) {
1150 netdev_err(dev, "Rate limiting is not supported on this device\n");
1154 /* rate is given in Mb/sec, HW config is in Kb/sec */
1157 /* Check whether rate in valid range, 0 is always valid */
1158 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1159 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1163 mutex_lock(&priv->state_lock);
1164 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1165 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1167 priv->tx_rates[index] = rate;
1168 mutex_unlock(&priv->state_lock);
1173 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1174 struct mlx5e_channel_param *cparam,
1175 struct mlx5e_channel **cp)
1177 struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
1178 struct net_device *netdev = priv->netdev;
1179 struct mlx5e_cq_moder rx_cq_profile;
1180 int cpu = mlx5e_get_cpu(priv, ix);
1181 struct mlx5e_channel *c;
1182 struct mlx5e_sq *sq;
1186 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1193 c->pdev = &priv->mdev->pdev->dev;
1194 c->netdev = priv->netdev;
1195 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1196 c->num_tc = priv->params.num_tc;
1198 if (priv->params.rx_am_enabled)
1199 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1201 rx_cq_profile = priv->params.rx_cq_moderation;
1203 mlx5e_build_channeltc_to_txq_map(priv, ix);
1205 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1207 err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
1211 err = mlx5e_open_tx_cqs(c, cparam);
1213 goto err_close_icosq_cq;
1215 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1218 goto err_close_tx_cqs;
1220 napi_enable(&c->napi);
1222 err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1224 goto err_disable_napi;
1226 err = mlx5e_open_sqs(c, cparam);
1228 goto err_close_icosq;
1230 for (i = 0; i < priv->params.num_tc; i++) {
1231 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1233 if (priv->tx_rates[txq_ix]) {
1234 sq = priv->txq_to_sq_map[txq_ix];
1235 mlx5e_set_sq_maxrate(priv->netdev, sq,
1236 priv->tx_rates[txq_ix]);
1240 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1244 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1253 mlx5e_close_sq(&c->icosq);
1256 napi_disable(&c->napi);
1257 mlx5e_close_cq(&c->rq.cq);
1260 mlx5e_close_tx_cqs(c);
1263 mlx5e_close_cq(&c->icosq.cq);
1266 netif_napi_del(&c->napi);
1267 napi_hash_del(&c->napi);
1273 static void mlx5e_close_channel(struct mlx5e_channel *c)
1275 mlx5e_close_rq(&c->rq);
1277 mlx5e_close_sq(&c->icosq);
1278 napi_disable(&c->napi);
1279 mlx5e_close_cq(&c->rq.cq);
1280 mlx5e_close_tx_cqs(c);
1281 mlx5e_close_cq(&c->icosq.cq);
1282 netif_napi_del(&c->napi);
1284 napi_hash_del(&c->napi);
1290 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1291 struct mlx5e_rq_param *param)
1293 void *rqc = param->rqc;
1294 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1296 switch (priv->params.rq_wq_type) {
1297 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1298 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1299 priv->params.mpwqe_log_num_strides - 9);
1300 MLX5_SET(wq, wq, log_wqe_stride_size,
1301 priv->params.mpwqe_log_stride_sz - 6);
1302 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1304 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1305 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1308 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1309 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1310 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1311 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
1312 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1314 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1315 param->wq.linear = 1;
1317 param->am_enabled = priv->params.rx_am_enabled;
1320 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1322 void *rqc = param->rqc;
1323 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1325 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1326 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1329 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1330 struct mlx5e_sq_param *param)
1332 void *sqc = param->sqc;
1333 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1335 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1336 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
1338 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1341 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1342 struct mlx5e_sq_param *param)
1344 void *sqc = param->sqc;
1345 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1347 mlx5e_build_sq_param_common(priv, param);
1348 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1350 param->max_inline = priv->params.tx_max_inline;
1351 param->min_inline_mode = priv->params.tx_min_inline_mode;
1354 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1355 struct mlx5e_cq_param *param)
1357 void *cqc = param->cqc;
1359 MLX5_SET(cqc, cqc, uar_page, priv->mdev->mlx5e_res.cq_uar.index);
1362 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1363 struct mlx5e_cq_param *param)
1365 void *cqc = param->cqc;
1368 switch (priv->params.rq_wq_type) {
1369 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1370 log_cq_size = priv->params.log_rq_size +
1371 priv->params.mpwqe_log_num_strides;
1373 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1374 log_cq_size = priv->params.log_rq_size;
1377 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1378 if (priv->params.rx_cqe_compress) {
1379 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1380 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1383 mlx5e_build_common_cq_param(priv, param);
1385 param->cq_period_mode = priv->params.rx_cq_period_mode;
1388 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1389 struct mlx5e_cq_param *param)
1391 void *cqc = param->cqc;
1393 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1395 mlx5e_build_common_cq_param(priv, param);
1397 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1400 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1401 struct mlx5e_cq_param *param,
1404 void *cqc = param->cqc;
1406 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1408 mlx5e_build_common_cq_param(priv, param);
1410 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1413 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1414 struct mlx5e_sq_param *param,
1417 void *sqc = param->sqc;
1418 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1420 mlx5e_build_sq_param_common(priv, param);
1422 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1423 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1425 param->icosq = true;
1428 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1430 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1432 mlx5e_build_rq_param(priv, &cparam->rq);
1433 mlx5e_build_sq_param(priv, &cparam->sq);
1434 mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1435 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1436 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1437 mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1440 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1442 struct mlx5e_channel_param *cparam;
1443 int nch = priv->params.num_channels;
1448 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1451 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1452 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1454 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1456 if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1457 goto err_free_txq_to_sq_map;
1459 mlx5e_build_channel_param(priv, cparam);
1461 for (i = 0; i < nch; i++) {
1462 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1464 goto err_close_channels;
1467 for (j = 0; j < nch; j++) {
1468 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1470 goto err_close_channels;
1473 /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1474 * polling for inactive tx queues.
1476 netif_tx_start_all_queues(priv->netdev);
1482 for (i--; i >= 0; i--)
1483 mlx5e_close_channel(priv->channel[i]);
1485 err_free_txq_to_sq_map:
1486 kfree(priv->txq_to_sq_map);
1487 kfree(priv->channel);
1493 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1497 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1498 * polling for inactive tx queues.
1500 netif_tx_stop_all_queues(priv->netdev);
1501 netif_tx_disable(priv->netdev);
1503 for (i = 0; i < priv->params.num_channels; i++)
1504 mlx5e_close_channel(priv->channel[i]);
1506 kfree(priv->txq_to_sq_map);
1507 kfree(priv->channel);
1510 static int mlx5e_rx_hash_fn(int hfunc)
1512 return (hfunc == ETH_RSS_HASH_TOP) ?
1513 MLX5_RX_HASH_FN_TOEPLITZ :
1514 MLX5_RX_HASH_FN_INVERTED_XOR8;
1517 static int mlx5e_bits_invert(unsigned long a, int size)
1522 for (i = 0; i < size; i++)
1523 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1528 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1532 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1536 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1537 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1539 ix = priv->params.indirection_rqt[ix];
1540 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1541 priv->channel[ix]->rq.rqn :
1543 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1547 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1550 u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1551 priv->channel[ix]->rq.rqn :
1554 MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1557 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1558 int ix, struct mlx5e_rqt *rqt)
1560 struct mlx5_core_dev *mdev = priv->mdev;
1566 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1567 in = mlx5_vzalloc(inlen);
1571 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1573 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1574 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1576 if (sz > 1) /* RSS */
1577 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1579 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1581 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1583 rqt->enabled = true;
1589 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1591 rqt->enabled = false;
1592 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1595 static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1597 struct mlx5e_rqt *rqt = &priv->indir_rqt;
1599 return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1602 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1604 struct mlx5e_rqt *rqt;
1608 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1609 rqt = &priv->direct_tir[ix].rqt;
1610 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1612 goto err_destroy_rqts;
1618 for (ix--; ix >= 0; ix--)
1619 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1624 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
1626 struct mlx5_core_dev *mdev = priv->mdev;
1632 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1633 in = mlx5_vzalloc(inlen);
1637 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1639 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1640 if (sz > 1) /* RSS */
1641 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1643 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1645 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1647 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
1654 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1659 if (priv->indir_rqt.enabled) {
1660 rqtn = priv->indir_rqt.rqtn;
1661 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1664 for (ix = 0; ix < priv->params.num_channels; ix++) {
1665 if (!priv->direct_tir[ix].rqt.enabled)
1667 rqtn = priv->direct_tir[ix].rqt.rqtn;
1668 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1672 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1674 if (!priv->params.lro_en)
1677 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1679 MLX5_SET(tirc, tirc, lro_enable_mask,
1680 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1681 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1682 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1683 (priv->params.lro_wqe_sz -
1684 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1685 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1686 MLX5_CAP_ETH(priv->mdev,
1687 lro_timer_supported_periods[2]));
1690 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1692 MLX5_SET(tirc, tirc, rx_hash_fn,
1693 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1694 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1695 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1696 rx_hash_toeplitz_key);
1697 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1698 rx_hash_toeplitz_key);
1700 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1701 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1705 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1707 struct mlx5_core_dev *mdev = priv->mdev;
1716 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1717 in = mlx5_vzalloc(inlen);
1721 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1722 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1724 mlx5e_build_tir_ctx_lro(tirc, priv);
1726 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1727 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1733 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1734 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
1746 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
1748 struct mlx5_core_dev *mdev = priv->mdev;
1749 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
1752 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
1756 /* Update vport context MTU */
1757 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
1761 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
1763 struct mlx5_core_dev *mdev = priv->mdev;
1767 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
1768 if (err || !hw_mtu) /* fallback to port oper mtu */
1769 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1771 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
1774 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1776 struct mlx5e_priv *priv = netdev_priv(netdev);
1780 err = mlx5e_set_mtu(priv, netdev->mtu);
1784 mlx5e_query_mtu(priv, &mtu);
1785 if (mtu != netdev->mtu)
1786 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
1787 __func__, mtu, netdev->mtu);
1793 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1795 struct mlx5e_priv *priv = netdev_priv(netdev);
1796 int nch = priv->params.num_channels;
1797 int ntc = priv->params.num_tc;
1800 netdev_reset_tc(netdev);
1805 netdev_set_num_tc(netdev, ntc);
1807 /* Map netdev TCs to offset 0
1808 * We have our own UP to TXQ mapping for QoS
1810 for (tc = 0; tc < ntc; tc++)
1811 netdev_set_tc_queue(netdev, tc, nch, 0);
1814 int mlx5e_open_locked(struct net_device *netdev)
1816 struct mlx5e_priv *priv = netdev_priv(netdev);
1817 struct mlx5_core_dev *mdev = priv->mdev;
1821 set_bit(MLX5E_STATE_OPENED, &priv->state);
1823 mlx5e_netdev_set_tcs(netdev);
1825 num_txqs = priv->params.num_channels * priv->params.num_tc;
1826 netif_set_real_num_tx_queues(netdev, num_txqs);
1827 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1829 err = mlx5e_set_dev_port_mtu(netdev);
1831 goto err_clear_state_opened_flag;
1833 err = mlx5e_open_channels(priv);
1835 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1837 goto err_clear_state_opened_flag;
1840 err = mlx5e_refresh_tirs_self_loopback_enable(priv->mdev);
1842 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1844 goto err_close_channels;
1847 mlx5e_redirect_rqts(priv);
1848 mlx5e_update_carrier(priv);
1849 mlx5e_timestamp_init(priv);
1850 #ifdef CONFIG_RFS_ACCEL
1851 priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
1853 if (priv->profile->update_stats)
1854 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
1856 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
1857 err = mlx5e_add_sqs_fwd_rules(priv);
1859 goto err_close_channels;
1864 mlx5e_close_channels(priv);
1865 err_clear_state_opened_flag:
1866 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1870 int mlx5e_open(struct net_device *netdev)
1872 struct mlx5e_priv *priv = netdev_priv(netdev);
1875 mutex_lock(&priv->state_lock);
1876 err = mlx5e_open_locked(netdev);
1877 mutex_unlock(&priv->state_lock);
1882 int mlx5e_close_locked(struct net_device *netdev)
1884 struct mlx5e_priv *priv = netdev_priv(netdev);
1885 struct mlx5_core_dev *mdev = priv->mdev;
1887 /* May already be CLOSED in case a previous configuration operation
1888 * (e.g RX/TX queue size change) that involves close&open failed.
1890 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1893 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1895 if (MLX5_CAP_GEN(mdev, vport_group_manager))
1896 mlx5e_remove_sqs_fwd_rules(priv);
1898 mlx5e_timestamp_cleanup(priv);
1899 netif_carrier_off(priv->netdev);
1900 mlx5e_redirect_rqts(priv);
1901 mlx5e_close_channels(priv);
1906 int mlx5e_close(struct net_device *netdev)
1908 struct mlx5e_priv *priv = netdev_priv(netdev);
1911 mutex_lock(&priv->state_lock);
1912 err = mlx5e_close_locked(netdev);
1913 mutex_unlock(&priv->state_lock);
1918 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1919 struct mlx5e_rq *rq,
1920 struct mlx5e_rq_param *param)
1922 struct mlx5_core_dev *mdev = priv->mdev;
1923 void *rqc = param->rqc;
1924 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1927 param->wq.db_numa_node = param->wq.buf_numa_node;
1929 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
1939 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1940 struct mlx5e_cq *cq,
1941 struct mlx5e_cq_param *param)
1943 struct mlx5_core_dev *mdev = priv->mdev;
1944 struct mlx5_core_cq *mcq = &cq->mcq;
1949 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1954 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1957 mcq->set_ci_db = cq->wq_ctrl.db.db;
1958 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1959 *mcq->set_ci_db = 0;
1961 mcq->vector = param->eq_ix;
1962 mcq->comp = mlx5e_completion_event;
1963 mcq->event = mlx5e_cq_error_event;
1965 mcq->uar = &mdev->mlx5e_res.cq_uar;
1972 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1974 struct mlx5e_cq_param cq_param;
1975 struct mlx5e_rq_param rq_param;
1976 struct mlx5e_rq *rq = &priv->drop_rq;
1977 struct mlx5e_cq *cq = &priv->drop_rq.cq;
1980 memset(&cq_param, 0, sizeof(cq_param));
1981 memset(&rq_param, 0, sizeof(rq_param));
1982 mlx5e_build_drop_rq_param(&rq_param);
1984 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1988 err = mlx5e_enable_cq(cq, &cq_param);
1990 goto err_destroy_cq;
1992 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1994 goto err_disable_cq;
1996 err = mlx5e_enable_rq(rq, &rq_param);
1998 goto err_destroy_rq;
2003 mlx5e_destroy_rq(&priv->drop_rq);
2006 mlx5e_disable_cq(&priv->drop_rq.cq);
2009 mlx5e_destroy_cq(&priv->drop_rq.cq);
2014 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
2016 mlx5e_disable_rq(&priv->drop_rq);
2017 mlx5e_destroy_rq(&priv->drop_rq);
2018 mlx5e_disable_cq(&priv->drop_rq.cq);
2019 mlx5e_destroy_cq(&priv->drop_rq.cq);
2022 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2024 struct mlx5_core_dev *mdev = priv->mdev;
2025 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2026 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2028 memset(in, 0, sizeof(in));
2030 MLX5_SET(tisc, tisc, prio, tc << 1);
2031 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2033 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2036 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2038 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2041 int mlx5e_create_tises(struct mlx5e_priv *priv)
2046 for (tc = 0; tc < priv->profile->max_tc; tc++) {
2047 err = mlx5e_create_tis(priv, tc);
2049 goto err_close_tises;
2055 for (tc--; tc >= 0; tc--)
2056 mlx5e_destroy_tis(priv, tc);
2061 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2065 for (tc = 0; tc < priv->profile->max_tc; tc++)
2066 mlx5e_destroy_tis(priv, tc);
2069 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2070 enum mlx5e_traffic_types tt)
2072 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2074 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2076 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2077 MLX5_HASH_FIELD_SEL_DST_IP)
2079 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2080 MLX5_HASH_FIELD_SEL_DST_IP |\
2081 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2082 MLX5_HASH_FIELD_SEL_L4_DPORT)
2084 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2085 MLX5_HASH_FIELD_SEL_DST_IP |\
2086 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2088 mlx5e_build_tir_ctx_lro(tirc, priv);
2090 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2091 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2092 mlx5e_build_tir_ctx_hash(tirc, priv);
2095 case MLX5E_TT_IPV4_TCP:
2096 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2097 MLX5_L3_PROT_TYPE_IPV4);
2098 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2099 MLX5_L4_PROT_TYPE_TCP);
2100 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2101 MLX5_HASH_IP_L4PORTS);
2104 case MLX5E_TT_IPV6_TCP:
2105 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2106 MLX5_L3_PROT_TYPE_IPV6);
2107 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2108 MLX5_L4_PROT_TYPE_TCP);
2109 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2110 MLX5_HASH_IP_L4PORTS);
2113 case MLX5E_TT_IPV4_UDP:
2114 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2115 MLX5_L3_PROT_TYPE_IPV4);
2116 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2117 MLX5_L4_PROT_TYPE_UDP);
2118 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2119 MLX5_HASH_IP_L4PORTS);
2122 case MLX5E_TT_IPV6_UDP:
2123 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2124 MLX5_L3_PROT_TYPE_IPV6);
2125 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2126 MLX5_L4_PROT_TYPE_UDP);
2127 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2128 MLX5_HASH_IP_L4PORTS);
2131 case MLX5E_TT_IPV4_IPSEC_AH:
2132 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2133 MLX5_L3_PROT_TYPE_IPV4);
2134 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2135 MLX5_HASH_IP_IPSEC_SPI);
2138 case MLX5E_TT_IPV6_IPSEC_AH:
2139 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2140 MLX5_L3_PROT_TYPE_IPV6);
2141 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2142 MLX5_HASH_IP_IPSEC_SPI);
2145 case MLX5E_TT_IPV4_IPSEC_ESP:
2146 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2147 MLX5_L3_PROT_TYPE_IPV4);
2148 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2149 MLX5_HASH_IP_IPSEC_SPI);
2152 case MLX5E_TT_IPV6_IPSEC_ESP:
2153 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2154 MLX5_L3_PROT_TYPE_IPV6);
2155 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2156 MLX5_HASH_IP_IPSEC_SPI);
2160 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2161 MLX5_L3_PROT_TYPE_IPV4);
2162 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2167 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2168 MLX5_L3_PROT_TYPE_IPV6);
2169 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2174 "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2178 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2181 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2183 mlx5e_build_tir_ctx_lro(tirc, priv);
2185 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2186 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2187 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2190 static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2192 struct mlx5e_tir *tir;
2199 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2200 in = mlx5_vzalloc(inlen);
2204 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2205 memset(in, 0, inlen);
2206 tir = &priv->indir_tir[tt];
2207 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2208 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2209 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2211 goto err_destroy_tirs;
2219 for (tt--; tt >= 0; tt--)
2220 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2227 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2229 int nch = priv->profile->max_nch(priv->mdev);
2230 struct mlx5e_tir *tir;
2237 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2238 in = mlx5_vzalloc(inlen);
2242 for (ix = 0; ix < nch; ix++) {
2243 memset(in, 0, inlen);
2244 tir = &priv->direct_tir[ix];
2245 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2246 mlx5e_build_direct_tir_ctx(priv, tirc,
2247 priv->direct_tir[ix].rqt.rqtn);
2248 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2250 goto err_destroy_ch_tirs;
2257 err_destroy_ch_tirs:
2258 for (ix--; ix >= 0; ix--)
2259 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2266 static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
2270 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2271 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
2274 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
2276 int nch = priv->profile->max_nch(priv->mdev);
2279 for (i = 0; i < nch; i++)
2280 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2283 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2288 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2291 for (i = 0; i < priv->params.num_channels; i++) {
2292 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2300 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2302 struct mlx5e_priv *priv = netdev_priv(netdev);
2306 if (tc && tc != MLX5E_MAX_NUM_TC)
2309 mutex_lock(&priv->state_lock);
2311 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2313 mlx5e_close_locked(priv->netdev);
2315 priv->params.num_tc = tc ? tc : 1;
2318 err = mlx5e_open_locked(priv->netdev);
2320 mutex_unlock(&priv->state_lock);
2325 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2326 __be16 proto, struct tc_to_netdev *tc)
2328 struct mlx5e_priv *priv = netdev_priv(dev);
2330 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2334 case TC_SETUP_CLSFLOWER:
2335 switch (tc->cls_flower->command) {
2336 case TC_CLSFLOWER_REPLACE:
2337 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2338 case TC_CLSFLOWER_DESTROY:
2339 return mlx5e_delete_flower(priv, tc->cls_flower);
2340 case TC_CLSFLOWER_STATS:
2341 return mlx5e_stats_flower(priv, tc->cls_flower);
2348 if (tc->type != TC_SETUP_MQPRIO)
2351 return mlx5e_setup_tc(dev, tc->tc);
2354 struct rtnl_link_stats64 *
2355 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2357 struct mlx5e_priv *priv = netdev_priv(dev);
2358 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2359 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2360 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2362 stats->rx_packets = sstats->rx_packets;
2363 stats->rx_bytes = sstats->rx_bytes;
2364 stats->tx_packets = sstats->tx_packets;
2365 stats->tx_bytes = sstats->tx_bytes;
2367 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2368 stats->tx_dropped = sstats->tx_queue_dropped;
2370 stats->rx_length_errors =
2371 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2372 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2373 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2374 stats->rx_crc_errors =
2375 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2376 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2377 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2378 stats->tx_carrier_errors =
2379 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2380 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2381 stats->rx_frame_errors;
2382 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2384 /* vport multicast also counts packets that are dropped due to steering
2385 * or rx out of buffer
2388 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2393 static void mlx5e_set_rx_mode(struct net_device *dev)
2395 struct mlx5e_priv *priv = netdev_priv(dev);
2397 queue_work(priv->wq, &priv->set_rx_mode_work);
2400 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2402 struct mlx5e_priv *priv = netdev_priv(netdev);
2403 struct sockaddr *saddr = addr;
2405 if (!is_valid_ether_addr(saddr->sa_data))
2406 return -EADDRNOTAVAIL;
2408 netif_addr_lock_bh(netdev);
2409 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2410 netif_addr_unlock_bh(netdev);
2412 queue_work(priv->wq, &priv->set_rx_mode_work);
2417 #define MLX5E_SET_FEATURE(netdev, feature, enable) \
2420 netdev->features |= feature; \
2422 netdev->features &= ~feature; \
2425 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2427 static int set_feature_lro(struct net_device *netdev, bool enable)
2429 struct mlx5e_priv *priv = netdev_priv(netdev);
2430 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2433 mutex_lock(&priv->state_lock);
2435 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2436 mlx5e_close_locked(priv->netdev);
2438 priv->params.lro_en = enable;
2439 err = mlx5e_modify_tirs_lro(priv);
2441 netdev_err(netdev, "lro modify failed, %d\n", err);
2442 priv->params.lro_en = !enable;
2445 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2446 mlx5e_open_locked(priv->netdev);
2448 mutex_unlock(&priv->state_lock);
2453 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2455 struct mlx5e_priv *priv = netdev_priv(netdev);
2458 mlx5e_enable_vlan_filter(priv);
2460 mlx5e_disable_vlan_filter(priv);
2465 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2467 struct mlx5e_priv *priv = netdev_priv(netdev);
2469 if (!enable && mlx5e_tc_num_filters(priv)) {
2471 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2478 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2480 struct mlx5e_priv *priv = netdev_priv(netdev);
2481 struct mlx5_core_dev *mdev = priv->mdev;
2483 return mlx5_set_port_fcs(mdev, !enable);
2486 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2488 struct mlx5e_priv *priv = netdev_priv(netdev);
2491 mutex_lock(&priv->state_lock);
2493 priv->params.vlan_strip_disable = !enable;
2494 err = mlx5e_modify_rqs_vsd(priv, !enable);
2496 priv->params.vlan_strip_disable = enable;
2498 mutex_unlock(&priv->state_lock);
2503 #ifdef CONFIG_RFS_ACCEL
2504 static int set_feature_arfs(struct net_device *netdev, bool enable)
2506 struct mlx5e_priv *priv = netdev_priv(netdev);
2510 err = mlx5e_arfs_enable(priv);
2512 err = mlx5e_arfs_disable(priv);
2518 static int mlx5e_handle_feature(struct net_device *netdev,
2519 netdev_features_t wanted_features,
2520 netdev_features_t feature,
2521 mlx5e_feature_handler feature_handler)
2523 netdev_features_t changes = wanted_features ^ netdev->features;
2524 bool enable = !!(wanted_features & feature);
2527 if (!(changes & feature))
2530 err = feature_handler(netdev, enable);
2532 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2533 enable ? "Enable" : "Disable", feature, err);
2537 MLX5E_SET_FEATURE(netdev, feature, enable);
2541 static int mlx5e_set_features(struct net_device *netdev,
2542 netdev_features_t features)
2546 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2548 err |= mlx5e_handle_feature(netdev, features,
2549 NETIF_F_HW_VLAN_CTAG_FILTER,
2550 set_feature_vlan_filter);
2551 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2552 set_feature_tc_num_filters);
2553 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2554 set_feature_rx_all);
2555 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2556 set_feature_rx_vlan);
2557 #ifdef CONFIG_RFS_ACCEL
2558 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2562 return err ? -EINVAL : 0;
2565 #define MXL5_HW_MIN_MTU 64
2566 #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2568 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2570 struct mlx5e_priv *priv = netdev_priv(netdev);
2571 struct mlx5_core_dev *mdev = priv->mdev;
2577 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2579 max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2580 min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
2582 if (new_mtu > max_mtu || new_mtu < min_mtu) {
2584 "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2585 __func__, new_mtu, min_mtu, max_mtu);
2589 mutex_lock(&priv->state_lock);
2591 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2593 mlx5e_close_locked(netdev);
2595 netdev->mtu = new_mtu;
2598 err = mlx5e_open_locked(netdev);
2600 mutex_unlock(&priv->state_lock);
2605 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2609 return mlx5e_hwstamp_set(dev, ifr);
2611 return mlx5e_hwstamp_get(dev, ifr);
2617 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2619 struct mlx5e_priv *priv = netdev_priv(dev);
2620 struct mlx5_core_dev *mdev = priv->mdev;
2622 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2625 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2627 struct mlx5e_priv *priv = netdev_priv(dev);
2628 struct mlx5_core_dev *mdev = priv->mdev;
2630 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2634 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2636 struct mlx5e_priv *priv = netdev_priv(dev);
2637 struct mlx5_core_dev *mdev = priv->mdev;
2639 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2642 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2644 struct mlx5e_priv *priv = netdev_priv(dev);
2645 struct mlx5_core_dev *mdev = priv->mdev;
2647 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2649 static int mlx5_vport_link2ifla(u8 esw_link)
2652 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2653 return IFLA_VF_LINK_STATE_DISABLE;
2654 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2655 return IFLA_VF_LINK_STATE_ENABLE;
2657 return IFLA_VF_LINK_STATE_AUTO;
2660 static int mlx5_ifla_link2vport(u8 ifla_link)
2662 switch (ifla_link) {
2663 case IFLA_VF_LINK_STATE_DISABLE:
2664 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2665 case IFLA_VF_LINK_STATE_ENABLE:
2666 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2668 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2671 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2674 struct mlx5e_priv *priv = netdev_priv(dev);
2675 struct mlx5_core_dev *mdev = priv->mdev;
2677 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2678 mlx5_ifla_link2vport(link_state));
2681 static int mlx5e_get_vf_config(struct net_device *dev,
2682 int vf, struct ifla_vf_info *ivi)
2684 struct mlx5e_priv *priv = netdev_priv(dev);
2685 struct mlx5_core_dev *mdev = priv->mdev;
2688 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2691 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2695 static int mlx5e_get_vf_stats(struct net_device *dev,
2696 int vf, struct ifla_vf_stats *vf_stats)
2698 struct mlx5e_priv *priv = netdev_priv(dev);
2699 struct mlx5_core_dev *mdev = priv->mdev;
2701 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2705 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2706 struct udp_tunnel_info *ti)
2708 struct mlx5e_priv *priv = netdev_priv(netdev);
2710 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2713 if (!mlx5e_vxlan_allowed(priv->mdev))
2716 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
2719 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2720 struct udp_tunnel_info *ti)
2722 struct mlx5e_priv *priv = netdev_priv(netdev);
2724 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2727 if (!mlx5e_vxlan_allowed(priv->mdev))
2730 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
2733 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2734 struct sk_buff *skb,
2735 netdev_features_t features)
2737 struct udphdr *udph;
2741 switch (vlan_get_protocol(skb)) {
2742 case htons(ETH_P_IP):
2743 proto = ip_hdr(skb)->protocol;
2745 case htons(ETH_P_IPV6):
2746 proto = ipv6_hdr(skb)->nexthdr;
2752 if (proto == IPPROTO_UDP) {
2753 udph = udp_hdr(skb);
2754 port = be16_to_cpu(udph->dest);
2757 /* Verify if UDP port is being offloaded by HW */
2758 if (port && mlx5e_vxlan_lookup_port(priv, port))
2762 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2763 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2766 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2767 struct net_device *netdev,
2768 netdev_features_t features)
2770 struct mlx5e_priv *priv = netdev_priv(netdev);
2772 features = vlan_features_check(skb, features);
2773 features = vxlan_features_check(skb, features);
2775 /* Validate if the tunneled packet is being offloaded by HW */
2776 if (skb->encapsulation &&
2777 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2778 return mlx5e_vxlan_features_check(priv, skb, features);
2783 static void mlx5e_tx_timeout(struct net_device *dev)
2785 struct mlx5e_priv *priv = netdev_priv(dev);
2786 bool sched_work = false;
2789 netdev_err(dev, "TX timeout detected\n");
2791 for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
2792 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
2794 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
2797 set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
2798 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
2799 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
2802 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
2803 schedule_work(&priv->tx_timeout_work);
2806 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2807 .ndo_open = mlx5e_open,
2808 .ndo_stop = mlx5e_close,
2809 .ndo_start_xmit = mlx5e_xmit,
2810 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2811 .ndo_select_queue = mlx5e_select_queue,
2812 .ndo_get_stats64 = mlx5e_get_stats,
2813 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2814 .ndo_set_mac_address = mlx5e_set_mac,
2815 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2816 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2817 .ndo_set_features = mlx5e_set_features,
2818 .ndo_change_mtu = mlx5e_change_mtu,
2819 .ndo_do_ioctl = mlx5e_ioctl,
2820 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
2821 #ifdef CONFIG_RFS_ACCEL
2822 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
2824 .ndo_tx_timeout = mlx5e_tx_timeout,
2827 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2828 .ndo_open = mlx5e_open,
2829 .ndo_stop = mlx5e_close,
2830 .ndo_start_xmit = mlx5e_xmit,
2831 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2832 .ndo_select_queue = mlx5e_select_queue,
2833 .ndo_get_stats64 = mlx5e_get_stats,
2834 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2835 .ndo_set_mac_address = mlx5e_set_mac,
2836 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2837 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2838 .ndo_set_features = mlx5e_set_features,
2839 .ndo_change_mtu = mlx5e_change_mtu,
2840 .ndo_do_ioctl = mlx5e_ioctl,
2841 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
2842 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
2843 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
2844 .ndo_features_check = mlx5e_features_check,
2845 #ifdef CONFIG_RFS_ACCEL
2846 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
2848 .ndo_set_vf_mac = mlx5e_set_vf_mac,
2849 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
2850 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
2851 .ndo_set_vf_trust = mlx5e_set_vf_trust,
2852 .ndo_get_vf_config = mlx5e_get_vf_config,
2853 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
2854 .ndo_get_vf_stats = mlx5e_get_vf_stats,
2855 .ndo_tx_timeout = mlx5e_tx_timeout,
2858 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2860 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2862 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2863 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2864 !MLX5_CAP_ETH(mdev, csum_cap) ||
2865 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2866 !MLX5_CAP_ETH(mdev, vlan_cap) ||
2867 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2868 MLX5_CAP_FLOWTABLE(mdev,
2869 flow_table_properties_nic_receive.max_ft_level)
2871 mlx5_core_warn(mdev,
2872 "Not creating net device, some required device capabilities are missing\n");
2875 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2876 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2877 if (!MLX5_CAP_GEN(mdev, cq_moderation))
2878 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2883 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2885 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2887 return bf_buf_size -
2888 sizeof(struct mlx5e_tx_wqe) +
2889 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2892 #ifdef CONFIG_MLX5_CORE_EN_DCB
2893 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2897 priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2898 for (i = 0; i < priv->params.ets.ets_cap; i++) {
2899 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2900 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2901 priv->params.ets.prio_tc[i] = i;
2904 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2905 priv->params.ets.prio_tc[0] = 1;
2906 priv->params.ets.prio_tc[1] = 0;
2910 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2911 u32 *indirection_rqt, int len,
2914 int node = mdev->priv.numa_node;
2915 int node_num_of_cores;
2919 node = first_online_node;
2921 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2923 if (node_num_of_cores)
2924 num_channels = min_t(int, num_channels, node_num_of_cores);
2926 for (i = 0; i < len; i++)
2927 indirection_rqt[i] = i % num_channels;
2930 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2932 return MLX5_CAP_GEN(mdev, striding_rq) &&
2933 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2934 MLX5_CAP_ETH(mdev, reg_umr_sq);
2937 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
2939 enum pcie_link_width width;
2940 enum pci_bus_speed speed;
2943 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
2947 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
2951 case PCIE_SPEED_2_5GT:
2952 *pci_bw = 2500 * width;
2954 case PCIE_SPEED_5_0GT:
2955 *pci_bw = 5000 * width;
2957 case PCIE_SPEED_8_0GT:
2958 *pci_bw = 8000 * width;
2967 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
2969 return (link_speed && pci_bw &&
2970 (pci_bw < 40000) && (pci_bw < link_speed));
2973 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
2975 params->rx_cq_period_mode = cq_period_mode;
2977 params->rx_cq_moderation.pkts =
2978 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2979 params->rx_cq_moderation.usec =
2980 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2982 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
2983 params->rx_cq_moderation.usec =
2984 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
2987 static void mlx5e_query_min_inline(struct mlx5_core_dev *mdev,
2988 u8 *min_inline_mode)
2990 switch (MLX5_CAP_ETH(mdev, wqe_inline_mode)) {
2991 case MLX5E_INLINE_MODE_L2:
2992 *min_inline_mode = MLX5_INLINE_MODE_L2;
2994 case MLX5E_INLINE_MODE_VPORT_CONTEXT:
2995 mlx5_query_nic_vport_min_inline(mdev,
2998 case MLX5_INLINE_MODE_NOT_REQUIRED:
2999 *min_inline_mode = MLX5_INLINE_MODE_NONE;
3004 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3005 struct net_device *netdev,
3006 const struct mlx5e_profile *profile,
3009 struct mlx5e_priv *priv = netdev_priv(netdev);
3012 u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3013 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3014 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3016 priv->params.log_sq_size =
3017 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3018 priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
3019 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
3020 MLX5_WQ_TYPE_LINKED_LIST;
3022 /* set CQE compression */
3023 priv->params.rx_cqe_compress_admin = false;
3024 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3025 MLX5_CAP_GEN(mdev, vport_group_manager)) {
3026 mlx5e_get_max_linkspeed(mdev, &link_speed);
3027 mlx5e_get_pci_bw(mdev, &pci_bw);
3028 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3029 link_speed, pci_bw);
3030 priv->params.rx_cqe_compress_admin =
3031 cqe_compress_heuristic(link_speed, pci_bw);
3034 priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
3036 switch (priv->params.rq_wq_type) {
3037 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
3038 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
3039 priv->params.mpwqe_log_stride_sz =
3040 priv->params.rx_cqe_compress ?
3041 MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
3042 MLX5_MPWRQ_LOG_STRIDE_SIZE;
3043 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
3044 priv->params.mpwqe_log_stride_sz;
3045 priv->params.lro_en = true;
3047 default: /* MLX5_WQ_TYPE_LINKED_LIST */
3048 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3051 mlx5_core_info(mdev,
3052 "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
3053 priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
3054 BIT(priv->params.log_rq_size),
3055 BIT(priv->params.mpwqe_log_stride_sz),
3056 priv->params.rx_cqe_compress_admin);
3058 priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
3059 BIT(priv->params.log_rq_size));
3061 priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3062 mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
3064 priv->params.tx_cq_moderation.usec =
3065 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3066 priv->params.tx_cq_moderation.pkts =
3067 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3068 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3069 mlx5e_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3070 priv->params.num_tc = 1;
3071 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
3073 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
3074 sizeof(priv->params.toeplitz_hash_key));
3076 mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
3077 MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
3079 priv->params.lro_wqe_sz =
3080 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3082 /* Initialize pflags */
3083 MLX5E_SET_PRIV_FLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3084 priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3087 priv->netdev = netdev;
3088 priv->params.num_channels = profile->max_nch(mdev);
3089 priv->profile = profile;
3090 priv->ppriv = ppriv;
3092 #ifdef CONFIG_MLX5_CORE_EN_DCB
3093 mlx5e_ets_init(priv);
3096 mutex_init(&priv->state_lock);
3098 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3099 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3100 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
3101 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3104 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3106 struct mlx5e_priv *priv = netdev_priv(netdev);
3108 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
3109 if (is_zero_ether_addr(netdev->dev_addr) &&
3110 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3111 eth_hw_addr_random(netdev);
3112 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3116 static const struct switchdev_ops mlx5e_switchdev_ops = {
3117 .switchdev_port_attr_get = mlx5e_attr_get,
3120 static void mlx5e_build_nic_netdev(struct net_device *netdev)
3122 struct mlx5e_priv *priv = netdev_priv(netdev);
3123 struct mlx5_core_dev *mdev = priv->mdev;
3127 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3129 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3130 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
3131 #ifdef CONFIG_MLX5_CORE_EN_DCB
3132 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
3135 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
3138 netdev->watchdog_timeo = 15 * HZ;
3140 netdev->ethtool_ops = &mlx5e_ethtool_ops;
3142 netdev->vlan_features |= NETIF_F_SG;
3143 netdev->vlan_features |= NETIF_F_IP_CSUM;
3144 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
3145 netdev->vlan_features |= NETIF_F_GRO;
3146 netdev->vlan_features |= NETIF_F_TSO;
3147 netdev->vlan_features |= NETIF_F_TSO6;
3148 netdev->vlan_features |= NETIF_F_RXCSUM;
3149 netdev->vlan_features |= NETIF_F_RXHASH;
3151 if (!!MLX5_CAP_ETH(mdev, lro_cap))
3152 netdev->vlan_features |= NETIF_F_LRO;
3154 netdev->hw_features = netdev->vlan_features;
3155 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
3156 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
3157 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3159 if (mlx5e_vxlan_allowed(mdev)) {
3160 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3161 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3162 NETIF_F_GSO_PARTIAL;
3163 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
3164 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
3165 netdev->hw_enc_features |= NETIF_F_TSO;
3166 netdev->hw_enc_features |= NETIF_F_TSO6;
3167 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
3168 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3169 NETIF_F_GSO_PARTIAL;
3170 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
3173 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3176 netdev->hw_features |= NETIF_F_RXALL;
3178 netdev->features = netdev->hw_features;
3179 if (!priv->params.lro_en)
3180 netdev->features &= ~NETIF_F_LRO;
3183 netdev->features &= ~NETIF_F_RXALL;
3185 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3186 if (FT_CAP(flow_modify_en) &&
3187 FT_CAP(modify_root) &&
3188 FT_CAP(identified_miss_table_mode) &&
3189 FT_CAP(flow_table_modify)) {
3190 netdev->hw_features |= NETIF_F_HW_TC;
3191 #ifdef CONFIG_RFS_ACCEL
3192 netdev->hw_features |= NETIF_F_NTUPLE;
3196 netdev->features |= NETIF_F_HIGHDMA;
3198 netdev->priv_flags |= IFF_UNICAST_FLT;
3200 mlx5e_set_netdev_dev_addr(netdev);
3202 #ifdef CONFIG_NET_SWITCHDEV
3203 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3204 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3208 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3210 struct mlx5_core_dev *mdev = priv->mdev;
3213 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3215 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3216 priv->q_counter = 0;
3220 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3222 if (!priv->q_counter)
3225 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3228 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
3230 struct mlx5_core_dev *mdev = priv->mdev;
3231 struct mlx5_create_mkey_mbox_in *in;
3232 struct mlx5_mkey_seg *mkc;
3233 int inlen = sizeof(*in);
3235 priv->profile->max_nch(mdev) * MLX5_CHANNEL_MAX_NUM_MTTS;
3238 in = mlx5_vzalloc(inlen);
3243 mkc->status = MLX5_MKEY_STATUS_FREE;
3244 mkc->flags = MLX5_PERM_UMR_EN |
3245 MLX5_PERM_LOCAL_READ |
3246 MLX5_PERM_LOCAL_WRITE |
3247 MLX5_ACCESS_MODE_MTT;
3249 mkc->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
3250 mkc->flags_pd = cpu_to_be32(mdev->mlx5e_res.pdn);
3251 mkc->len = cpu_to_be64(npages << PAGE_SHIFT);
3252 mkc->xlt_oct_size = cpu_to_be32(mlx5e_get_mtt_octw(npages));
3253 mkc->log2_page_size = PAGE_SHIFT;
3255 err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen, NULL,
3263 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3264 struct net_device *netdev,
3265 const struct mlx5e_profile *profile,
3268 struct mlx5e_priv *priv = netdev_priv(netdev);
3270 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
3271 mlx5e_build_nic_netdev(netdev);
3272 mlx5e_vxlan_init(priv);
3275 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3277 struct mlx5_core_dev *mdev = priv->mdev;
3278 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3280 mlx5e_vxlan_cleanup(priv);
3282 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3283 mlx5_eswitch_unregister_vport_rep(esw, 0);
3286 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3288 struct mlx5_core_dev *mdev = priv->mdev;
3292 err = mlx5e_create_indirect_rqts(priv);
3294 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3298 err = mlx5e_create_direct_rqts(priv);
3300 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3301 goto err_destroy_indirect_rqts;
3304 err = mlx5e_create_indirect_tirs(priv);
3306 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3307 goto err_destroy_direct_rqts;
3310 err = mlx5e_create_direct_tirs(priv);
3312 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3313 goto err_destroy_indirect_tirs;
3316 err = mlx5e_create_flow_steering(priv);
3318 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3319 goto err_destroy_direct_tirs;
3322 err = mlx5e_tc_init(priv);
3324 goto err_destroy_flow_steering;
3328 err_destroy_flow_steering:
3329 mlx5e_destroy_flow_steering(priv);
3330 err_destroy_direct_tirs:
3331 mlx5e_destroy_direct_tirs(priv);
3332 err_destroy_indirect_tirs:
3333 mlx5e_destroy_indirect_tirs(priv);
3334 err_destroy_direct_rqts:
3335 for (i = 0; i < priv->profile->max_nch(mdev); i++)
3336 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3337 err_destroy_indirect_rqts:
3338 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3342 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
3346 mlx5e_tc_cleanup(priv);
3347 mlx5e_destroy_flow_steering(priv);
3348 mlx5e_destroy_direct_tirs(priv);
3349 mlx5e_destroy_indirect_tirs(priv);
3350 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
3351 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3352 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3355 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
3359 err = mlx5e_create_tises(priv);
3361 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
3365 #ifdef CONFIG_MLX5_CORE_EN_DCB
3366 mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3371 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
3373 struct net_device *netdev = priv->netdev;
3374 struct mlx5_core_dev *mdev = priv->mdev;
3375 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3376 struct mlx5_eswitch_rep rep;
3378 if (mlx5e_vxlan_allowed(mdev)) {
3380 udp_tunnel_get_rx_info(netdev);
3384 mlx5e_enable_async_events(priv);
3385 queue_work(priv->wq, &priv->set_rx_mode_work);
3387 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3388 rep.load = mlx5e_nic_rep_load;
3389 rep.unload = mlx5e_nic_rep_unload;
3391 rep.priv_data = priv;
3392 mlx5_eswitch_register_vport_rep(esw, &rep);
3396 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
3398 queue_work(priv->wq, &priv->set_rx_mode_work);
3399 mlx5e_disable_async_events(priv);
3402 static const struct mlx5e_profile mlx5e_nic_profile = {
3403 .init = mlx5e_nic_init,
3404 .cleanup = mlx5e_nic_cleanup,
3405 .init_rx = mlx5e_init_nic_rx,
3406 .cleanup_rx = mlx5e_cleanup_nic_rx,
3407 .init_tx = mlx5e_init_nic_tx,
3408 .cleanup_tx = mlx5e_cleanup_nic_tx,
3409 .enable = mlx5e_nic_enable,
3410 .disable = mlx5e_nic_disable,
3411 .update_stats = mlx5e_update_stats,
3412 .max_nch = mlx5e_get_max_num_channels,
3413 .max_tc = MLX5E_MAX_NUM_TC,
3416 void *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
3417 const struct mlx5e_profile *profile, void *ppriv)
3419 struct net_device *netdev;
3420 struct mlx5e_priv *priv;
3421 int nch = profile->max_nch(mdev);
3424 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
3425 nch * profile->max_tc,
3428 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3432 profile->init(mdev, netdev, profile, ppriv);
3434 netif_carrier_off(netdev);
3436 priv = netdev_priv(netdev);
3438 priv->wq = create_singlethread_workqueue("mlx5e");
3440 goto err_free_netdev;
3442 err = mlx5e_create_umr_mkey(priv);
3444 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
3445 goto err_destroy_wq;
3448 err = profile->init_tx(priv);
3450 goto err_destroy_umr_mkey;
3452 err = mlx5e_open_drop_rq(priv);
3454 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
3455 goto err_cleanup_tx;
3458 err = profile->init_rx(priv);
3460 goto err_close_drop_rq;
3462 mlx5e_create_q_counter(priv);
3464 mlx5e_init_l2_addr(priv);
3466 err = register_netdev(netdev);
3468 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
3469 goto err_dealloc_q_counters;
3472 if (profile->enable)
3473 profile->enable(priv);
3477 err_dealloc_q_counters:
3478 mlx5e_destroy_q_counter(priv);
3479 profile->cleanup_rx(priv);
3482 mlx5e_close_drop_rq(priv);
3485 profile->cleanup_tx(priv);
3487 err_destroy_umr_mkey:
3488 mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3491 destroy_workqueue(priv->wq);
3494 free_netdev(netdev);
3499 static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
3501 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3502 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3505 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3508 for (vport = 1; vport < total_vfs; vport++) {
3509 struct mlx5_eswitch_rep rep;
3511 rep.load = mlx5e_vport_rep_load;
3512 rep.unload = mlx5e_vport_rep_unload;
3514 mlx5_eswitch_register_vport_rep(esw, &rep);
3518 static void *mlx5e_add(struct mlx5_core_dev *mdev)
3520 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3524 if (mlx5e_check_required_hca_cap(mdev))
3527 if (mlx5e_create_mdev_resources(mdev))
3530 mlx5e_register_vport_rep(mdev);
3532 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3533 ppriv = &esw->offloads.vport_reps[0];
3535 ret = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
3537 mlx5e_destroy_mdev_resources(mdev);
3543 void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
3545 const struct mlx5e_profile *profile = priv->profile;
3546 struct net_device *netdev = priv->netdev;
3548 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3549 if (profile->disable)
3550 profile->disable(priv);
3552 flush_workqueue(priv->wq);
3553 if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) {
3554 netif_device_detach(netdev);
3555 mlx5e_close(netdev);
3557 unregister_netdev(netdev);
3560 mlx5e_destroy_q_counter(priv);
3561 profile->cleanup_rx(priv);
3562 mlx5e_close_drop_rq(priv);
3563 profile->cleanup_tx(priv);
3564 mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3565 cancel_delayed_work_sync(&priv->update_stats_work);
3566 destroy_workqueue(priv->wq);
3567 if (profile->cleanup)
3568 profile->cleanup(priv);
3570 if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state))
3571 free_netdev(netdev);
3574 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
3576 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3577 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3578 struct mlx5e_priv *priv = vpriv;
3581 mlx5e_destroy_netdev(mdev, priv);
3583 for (vport = 1; vport < total_vfs; vport++)
3584 mlx5_eswitch_unregister_vport_rep(esw, vport);
3586 mlx5e_destroy_mdev_resources(mdev);
3589 static void *mlx5e_get_netdev(void *vpriv)
3591 struct mlx5e_priv *priv = vpriv;
3593 return priv->netdev;
3596 static struct mlx5_interface mlx5e_interface = {
3598 .remove = mlx5e_remove,
3599 .event = mlx5e_async_event,
3600 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3601 .get_dev = mlx5e_get_netdev,
3604 void mlx5e_init(void)
3606 mlx5e_build_ptys2ethtool_map();
3607 mlx5_register_interface(&mlx5e_interface);
3610 void mlx5e_cleanup(void)
3612 mlx5_unregister_interface(&mlx5e_interface);