2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <net/geneve.h>
38 #include <linux/bpf.h>
39 #include <linux/if_bridge.h>
40 #include <net/page_pool.h>
45 #include "en_accel/ipsec.h"
46 #include "en_accel/ipsec_rxtx.h"
47 #include "en_accel/en_accel.h"
48 #include "en_accel/tls.h"
49 #include "accel/ipsec.h"
50 #include "accel/tls.h"
51 #include "lib/vxlan.h"
52 #include "lib/clock.h"
56 #include "en/monitor_stats.h"
57 #include "en/reporter.h"
58 #include "en/params.h"
60 struct mlx5e_rq_param {
61 u32 rqc[MLX5_ST_SZ_DW(rqc)];
62 struct mlx5_wq_param wq;
63 struct mlx5e_rq_frags_info frags_info;
66 struct mlx5e_sq_param {
67 u32 sqc[MLX5_ST_SZ_DW(sqc)];
68 struct mlx5_wq_param wq;
72 struct mlx5e_cq_param {
73 u32 cqc[MLX5_ST_SZ_DW(cqc)];
74 struct mlx5_wq_param wq;
79 struct mlx5e_channel_param {
80 struct mlx5e_rq_param rq;
81 struct mlx5e_sq_param sq;
82 struct mlx5e_sq_param xdp_sq;
83 struct mlx5e_sq_param icosq;
84 struct mlx5e_cq_param rx_cq;
85 struct mlx5e_cq_param tx_cq;
86 struct mlx5e_cq_param icosq_cq;
89 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
91 bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
92 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
93 MLX5_CAP_ETH(mdev, reg_umr_sq);
94 u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
95 bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
100 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
101 (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
107 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
108 struct mlx5e_params *params)
110 params->log_rq_mtu_frames = is_kdump_kernel() ?
111 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
112 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
114 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
115 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
116 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
117 BIT(mlx5e_mpwqe_get_log_rq_size(params)) :
118 BIT(params->log_rq_mtu_frames),
119 BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)),
120 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
123 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
124 struct mlx5e_params *params)
126 return mlx5e_check_fragmented_striding_rq_cap(mdev) &&
127 !MLX5_IPSEC_DEV(mdev) &&
128 !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params));
131 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
133 params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
134 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
135 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
139 void mlx5e_update_carrier(struct mlx5e_priv *priv)
141 struct mlx5_core_dev *mdev = priv->mdev;
144 port_state = mlx5_query_vport_state(mdev,
145 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
148 if (port_state == VPORT_STATE_UP) {
149 netdev_info(priv->netdev, "Link up\n");
150 netif_carrier_on(priv->netdev);
152 netdev_info(priv->netdev, "Link down\n");
153 netif_carrier_off(priv->netdev);
157 static void mlx5e_update_carrier_work(struct work_struct *work)
159 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
160 update_carrier_work);
162 mutex_lock(&priv->state_lock);
163 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
164 if (priv->profile->update_carrier)
165 priv->profile->update_carrier(priv);
166 mutex_unlock(&priv->state_lock);
169 void mlx5e_update_stats(struct mlx5e_priv *priv)
173 for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
174 if (mlx5e_stats_grps[i].update_stats)
175 mlx5e_stats_grps[i].update_stats(priv);
178 void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
182 for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
183 if (mlx5e_stats_grps[i].update_stats_mask &
184 MLX5E_NDO_UPDATE_STATS)
185 mlx5e_stats_grps[i].update_stats(priv);
188 static void mlx5e_update_stats_work(struct work_struct *work)
190 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
193 mutex_lock(&priv->state_lock);
194 priv->profile->update_stats(priv);
195 mutex_unlock(&priv->state_lock);
198 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
200 if (!priv->profile->update_stats)
203 if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
206 queue_work(priv->wq, &priv->update_stats_work);
209 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
211 struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
212 struct mlx5_eqe *eqe = data;
214 if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
217 switch (eqe->sub_type) {
218 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
219 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
220 queue_work(priv->wq, &priv->update_carrier_work);
229 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
231 priv->events_nb.notifier_call = async_event;
232 mlx5_notifier_register(priv->mdev, &priv->events_nb);
235 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
237 mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
240 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
241 struct mlx5e_icosq *sq,
242 struct mlx5e_umr_wqe *wqe)
244 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
245 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
246 u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
248 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
250 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
251 cseg->imm = rq->mkey_be;
253 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
254 ucseg->xlt_octowords =
255 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
256 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
259 static u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq)
261 switch (rq->wq_type) {
262 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
263 return mlx5_wq_ll_get_size(&rq->mpwqe.wq);
265 return mlx5_wq_cyc_get_size(&rq->wqe.wq);
269 static u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq)
271 switch (rq->wq_type) {
272 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
273 return rq->mpwqe.wq.cur_sz;
275 return rq->wqe.wq.cur_sz;
279 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
280 struct mlx5e_channel *c)
282 int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
284 rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
285 sizeof(*rq->mpwqe.info)),
286 GFP_KERNEL, cpu_to_node(c->cpu));
290 mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
295 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
296 u64 npages, u8 page_shift,
297 struct mlx5_core_mkey *umr_mkey)
299 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
304 in = kvzalloc(inlen, GFP_KERNEL);
308 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
310 MLX5_SET(mkc, mkc, free, 1);
311 MLX5_SET(mkc, mkc, umr_en, 1);
312 MLX5_SET(mkc, mkc, lw, 1);
313 MLX5_SET(mkc, mkc, lr, 1);
314 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
316 MLX5_SET(mkc, mkc, qpn, 0xffffff);
317 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
318 MLX5_SET64(mkc, mkc, len, npages << page_shift);
319 MLX5_SET(mkc, mkc, translations_octword_size,
320 MLX5_MTT_OCTW(npages));
321 MLX5_SET(mkc, mkc, log_page_size, page_shift);
323 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
329 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
331 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
333 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
336 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
338 return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
341 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
343 struct mlx5e_wqe_frag_info next_frag, *prev;
346 next_frag.di = &rq->wqe.di[0];
347 next_frag.offset = 0;
350 for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
351 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
352 struct mlx5e_wqe_frag_info *frag =
353 &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
356 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
357 if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
359 next_frag.offset = 0;
361 prev->last_in_page = true;
366 next_frag.offset += frag_info[f].frag_stride;
372 prev->last_in_page = true;
375 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
378 int len = wq_sz << rq->wqe.info.log_num_frags;
380 rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
381 GFP_KERNEL, cpu_to_node(cpu));
385 mlx5e_init_frags_partition(rq);
390 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
395 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
396 struct mlx5e_params *params,
397 struct mlx5e_rq_param *rqp,
400 struct page_pool_params pp_params = { 0 };
401 struct mlx5_core_dev *mdev = c->mdev;
402 void *rqc = rqp->rqc;
403 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
409 rqp->wq.db_numa_node = cpu_to_node(c->cpu);
411 rq->wq_type = params->rq_wq_type;
413 rq->netdev = c->netdev;
414 rq->tstamp = c->tstamp;
415 rq->clock = &mdev->clock;
419 rq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
420 rq->stats = &c->priv->channel_stats[c->ix].rq;
422 rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
423 if (IS_ERR(rq->xdp_prog)) {
424 err = PTR_ERR(rq->xdp_prog);
426 goto err_rq_wq_destroy;
429 err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
431 goto err_rq_wq_destroy;
433 rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
434 rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params);
435 pool_size = 1 << params->log_rq_mtu_frames;
437 switch (rq->wq_type) {
438 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
439 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
444 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
446 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
448 pool_size = MLX5_MPWRQ_PAGES_PER_WQE << mlx5e_mpwqe_get_log_rq_size(params);
450 rq->post_wqes = mlx5e_post_rx_mpwqes;
451 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
453 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
454 #ifdef CONFIG_MLX5_EN_IPSEC
455 if (MLX5_IPSEC_DEV(mdev)) {
457 netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
458 goto err_rq_wq_destroy;
461 if (!rq->handle_rx_cqe) {
463 netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
464 goto err_rq_wq_destroy;
467 rq->mpwqe.skb_from_cqe_mpwrq =
468 mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ?
469 mlx5e_skb_from_cqe_mpwrq_linear :
470 mlx5e_skb_from_cqe_mpwrq_nonlinear;
471 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params);
472 rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params));
474 err = mlx5e_create_rq_umr_mkey(mdev, rq);
476 goto err_rq_wq_destroy;
477 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
479 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
483 default: /* MLX5_WQ_TYPE_CYCLIC */
484 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
489 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
491 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
493 rq->wqe.info = rqp->frags_info;
495 kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
496 (wq_sz << rq->wqe.info.log_num_frags)),
497 GFP_KERNEL, cpu_to_node(c->cpu));
498 if (!rq->wqe.frags) {
503 err = mlx5e_init_di_list(rq, wq_sz, c->cpu);
506 rq->post_wqes = mlx5e_post_rx_wqes;
507 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
509 #ifdef CONFIG_MLX5_EN_IPSEC
511 rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
514 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
515 if (!rq->handle_rx_cqe) {
517 netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
521 rq->wqe.skb_from_cqe = mlx5e_rx_is_linear_skb(params) ?
522 mlx5e_skb_from_cqe_linear :
523 mlx5e_skb_from_cqe_nonlinear;
524 rq->mkey_be = c->mkey_be;
527 /* Create a page_pool and register it with rxq */
529 pp_params.flags = 0; /* No-internal DMA mapping in page_pool */
530 pp_params.pool_size = pool_size;
531 pp_params.nid = cpu_to_node(c->cpu);
532 pp_params.dev = c->pdev;
533 pp_params.dma_dir = rq->buff.map_dir;
535 /* page_pool can be used even when there is no rq->xdp_prog,
536 * given page_pool does not handle DMA mapping there is no
537 * required state to clear. And page_pool gracefully handle
540 rq->page_pool = page_pool_create(&pp_params);
541 if (IS_ERR(rq->page_pool)) {
542 err = PTR_ERR(rq->page_pool);
543 rq->page_pool = NULL;
546 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
547 MEM_TYPE_PAGE_POOL, rq->page_pool);
549 page_pool_free(rq->page_pool);
553 for (i = 0; i < wq_sz; i++) {
554 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
555 struct mlx5e_rx_wqe_ll *wqe =
556 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
558 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
559 u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
561 wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
562 wqe->data[0].byte_count = cpu_to_be32(byte_count);
563 wqe->data[0].lkey = rq->mkey_be;
565 struct mlx5e_rx_wqe_cyc *wqe =
566 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
569 for (f = 0; f < rq->wqe.info.num_frags; f++) {
570 u32 frag_size = rq->wqe.info.arr[f].frag_size |
571 MLX5_HW_START_PADDING;
573 wqe->data[f].byte_count = cpu_to_be32(frag_size);
574 wqe->data[f].lkey = rq->mkey_be;
576 /* check if num_frags is not a pow of two */
577 if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
578 wqe->data[f].byte_count = 0;
579 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
580 wqe->data[f].addr = 0;
585 INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
587 switch (params->rx_cq_moderation.cq_period_mode) {
588 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
589 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
591 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
593 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
596 rq->page_cache.head = 0;
597 rq->page_cache.tail = 0;
602 switch (rq->wq_type) {
603 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
604 kvfree(rq->mpwqe.info);
605 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
607 default: /* MLX5_WQ_TYPE_CYCLIC */
608 kvfree(rq->wqe.frags);
609 mlx5e_free_di_list(rq);
614 bpf_prog_put(rq->xdp_prog);
615 xdp_rxq_info_unreg(&rq->xdp_rxq);
616 mlx5_wq_destroy(&rq->wq_ctrl);
621 static void mlx5e_free_rq(struct mlx5e_rq *rq)
626 bpf_prog_put(rq->xdp_prog);
628 switch (rq->wq_type) {
629 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
630 kvfree(rq->mpwqe.info);
631 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
633 default: /* MLX5_WQ_TYPE_CYCLIC */
634 kvfree(rq->wqe.frags);
635 mlx5e_free_di_list(rq);
638 for (i = rq->page_cache.head; i != rq->page_cache.tail;
639 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
640 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
642 mlx5e_page_release(rq, dma_info, false);
645 xdp_rxq_info_unreg(&rq->xdp_rxq);
646 mlx5_wq_destroy(&rq->wq_ctrl);
649 static int mlx5e_create_rq(struct mlx5e_rq *rq,
650 struct mlx5e_rq_param *param)
652 struct mlx5_core_dev *mdev = rq->mdev;
660 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
661 sizeof(u64) * rq->wq_ctrl.buf.npages;
662 in = kvzalloc(inlen, GFP_KERNEL);
666 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
667 wq = MLX5_ADDR_OF(rqc, rqc, wq);
669 memcpy(rqc, param->rqc, sizeof(param->rqc));
671 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
672 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
673 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
674 MLX5_ADAPTER_PAGE_SHIFT);
675 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
677 mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
678 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
680 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
687 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
690 struct mlx5_core_dev *mdev = rq->mdev;
697 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
698 in = kvzalloc(inlen, GFP_KERNEL);
702 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
704 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
705 MLX5_SET(rqc, rqc, state, next_state);
707 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
714 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
716 struct mlx5e_channel *c = rq->channel;
717 struct mlx5e_priv *priv = c->priv;
718 struct mlx5_core_dev *mdev = priv->mdev;
725 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
726 in = kvzalloc(inlen, GFP_KERNEL);
730 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
732 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
733 MLX5_SET64(modify_rq_in, in, modify_bitmask,
734 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
735 MLX5_SET(rqc, rqc, scatter_fcs, enable);
736 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
738 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
745 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
747 struct mlx5e_channel *c = rq->channel;
748 struct mlx5_core_dev *mdev = c->mdev;
754 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
755 in = kvzalloc(inlen, GFP_KERNEL);
759 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
761 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
762 MLX5_SET64(modify_rq_in, in, modify_bitmask,
763 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
764 MLX5_SET(rqc, rqc, vsd, vsd);
765 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
767 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
774 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
776 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
779 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
781 unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
782 struct mlx5e_channel *c = rq->channel;
784 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
787 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
791 } while (time_before(jiffies, exp_time));
793 netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
794 c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
799 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
804 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
805 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
809 /* Outstanding UMR WQEs (in progress) start at wq->head */
810 for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
811 rq->dealloc_wqe(rq, head);
812 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
815 while (!mlx5_wq_ll_is_empty(wq)) {
816 struct mlx5e_rx_wqe_ll *wqe;
818 wqe_ix_be = *wq->tail_next;
819 wqe_ix = be16_to_cpu(wqe_ix_be);
820 wqe = mlx5_wq_ll_get_wqe(wq, wqe_ix);
821 rq->dealloc_wqe(rq, wqe_ix);
822 mlx5_wq_ll_pop(wq, wqe_ix_be,
823 &wqe->next.next_wqe_index);
826 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
828 while (!mlx5_wq_cyc_is_empty(wq)) {
829 wqe_ix = mlx5_wq_cyc_get_tail(wq);
830 rq->dealloc_wqe(rq, wqe_ix);
837 static int mlx5e_open_rq(struct mlx5e_channel *c,
838 struct mlx5e_params *params,
839 struct mlx5e_rq_param *param,
844 err = mlx5e_alloc_rq(c, params, param, rq);
848 err = mlx5e_create_rq(rq, param);
852 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
856 if (params->rx_dim_enabled)
857 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
859 /* We disable csum_complete when XDP is enabled since
860 * XDP programs might manipulate packets which will render
861 * skb->checksum incorrect.
863 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || c->xdp)
864 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
869 mlx5e_destroy_rq(rq);
876 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
878 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
879 mlx5e_trigger_irq(&rq->channel->icosq);
882 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
884 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
885 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
888 static void mlx5e_close_rq(struct mlx5e_rq *rq)
890 cancel_work_sync(&rq->dim.work);
891 mlx5e_destroy_rq(rq);
892 mlx5e_free_rx_descs(rq);
896 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
898 kvfree(sq->db.xdpi_fifo.xi);
899 kvfree(sq->db.wqe_info);
902 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
904 struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
905 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
906 int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
908 xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq,
913 xdpi_fifo->pc = &sq->xdpi_fifo_pc;
914 xdpi_fifo->cc = &sq->xdpi_fifo_cc;
915 xdpi_fifo->mask = dsegs_per_wq - 1;
920 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
922 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
925 sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz,
927 if (!sq->db.wqe_info)
930 err = mlx5e_alloc_xdpsq_fifo(sq, numa);
932 mlx5e_free_xdpsq_db(sq);
939 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
940 struct mlx5e_params *params,
941 struct mlx5e_sq_param *param,
942 struct mlx5e_xdpsq *sq,
945 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
946 struct mlx5_core_dev *mdev = c->mdev;
947 struct mlx5_wq_cyc *wq = &sq->wq;
951 sq->mkey_be = c->mkey_be;
953 sq->uar_map = mdev->mlx5e_res.bfreg.map;
954 sq->min_inline_mode = params->tx_min_inline_mode;
955 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
956 sq->stats = is_redirect ?
957 &c->priv->channel_stats[c->ix].xdpsq :
958 &c->priv->channel_stats[c->ix].rq_xdpsq;
960 param->wq.db_numa_node = cpu_to_node(c->cpu);
961 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
964 wq->db = &wq->db[MLX5_SND_DBR];
966 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
968 goto err_sq_wq_destroy;
973 mlx5_wq_destroy(&sq->wq_ctrl);
978 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
980 mlx5e_free_xdpsq_db(sq);
981 mlx5_wq_destroy(&sq->wq_ctrl);
984 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
986 kvfree(sq->db.ico_wqe);
989 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
991 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
993 sq->db.ico_wqe = kvzalloc_node(array_size(wq_sz,
994 sizeof(*sq->db.ico_wqe)),
1002 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1003 struct mlx5e_sq_param *param,
1004 struct mlx5e_icosq *sq)
1006 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1007 struct mlx5_core_dev *mdev = c->mdev;
1008 struct mlx5_wq_cyc *wq = &sq->wq;
1012 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1014 param->wq.db_numa_node = cpu_to_node(c->cpu);
1015 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1018 wq->db = &wq->db[MLX5_SND_DBR];
1020 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1022 goto err_sq_wq_destroy;
1027 mlx5_wq_destroy(&sq->wq_ctrl);
1032 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1034 mlx5e_free_icosq_db(sq);
1035 mlx5_wq_destroy(&sq->wq_ctrl);
1038 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1040 kvfree(sq->db.wqe_info);
1041 kvfree(sq->db.dma_fifo);
1044 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1046 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1047 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1049 sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1050 sizeof(*sq->db.dma_fifo)),
1052 sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1053 sizeof(*sq->db.wqe_info)),
1055 if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1056 mlx5e_free_txqsq_db(sq);
1060 sq->dma_fifo_mask = df_sz - 1;
1065 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1066 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1068 struct mlx5e_params *params,
1069 struct mlx5e_sq_param *param,
1070 struct mlx5e_txqsq *sq,
1073 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1074 struct mlx5_core_dev *mdev = c->mdev;
1075 struct mlx5_wq_cyc *wq = &sq->wq;
1079 sq->tstamp = c->tstamp;
1080 sq->clock = &mdev->clock;
1081 sq->mkey_be = c->mkey_be;
1084 sq->txq_ix = txq_ix;
1085 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1086 sq->min_inline_mode = params->tx_min_inline_mode;
1087 sq->stats = &c->priv->channel_stats[c->ix].sq[tc];
1088 INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1089 if (MLX5_IPSEC_DEV(c->priv->mdev))
1090 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1091 if (mlx5_accel_is_tls_device(c->priv->mdev))
1092 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1094 param->wq.db_numa_node = cpu_to_node(c->cpu);
1095 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1098 wq->db = &wq->db[MLX5_SND_DBR];
1100 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1102 goto err_sq_wq_destroy;
1104 INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1105 sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1110 mlx5_wq_destroy(&sq->wq_ctrl);
1115 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1117 mlx5e_free_txqsq_db(sq);
1118 mlx5_wq_destroy(&sq->wq_ctrl);
1121 struct mlx5e_create_sq_param {
1122 struct mlx5_wq_ctrl *wq_ctrl;
1129 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1130 struct mlx5e_sq_param *param,
1131 struct mlx5e_create_sq_param *csp,
1140 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1141 sizeof(u64) * csp->wq_ctrl->buf.npages;
1142 in = kvzalloc(inlen, GFP_KERNEL);
1146 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1147 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1149 memcpy(sqc, param->sqc, sizeof(param->sqc));
1150 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1151 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1152 MLX5_SET(sqc, sqc, cqn, csp->cqn);
1154 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1155 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
1157 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1158 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1160 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1161 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
1162 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
1163 MLX5_ADAPTER_PAGE_SHIFT);
1164 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
1166 mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1167 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1169 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1176 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1177 struct mlx5e_modify_sq_param *p)
1184 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1185 in = kvzalloc(inlen, GFP_KERNEL);
1189 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1191 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1192 MLX5_SET(sqc, sqc, state, p->next_state);
1193 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1194 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1195 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1198 err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1205 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1207 mlx5_core_destroy_sq(mdev, sqn);
1210 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1211 struct mlx5e_sq_param *param,
1212 struct mlx5e_create_sq_param *csp,
1215 struct mlx5e_modify_sq_param msp = {0};
1218 err = mlx5e_create_sq(mdev, param, csp, sqn);
1222 msp.curr_state = MLX5_SQC_STATE_RST;
1223 msp.next_state = MLX5_SQC_STATE_RDY;
1224 err = mlx5e_modify_sq(mdev, *sqn, &msp);
1226 mlx5e_destroy_sq(mdev, *sqn);
1231 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1232 struct mlx5e_txqsq *sq, u32 rate);
1234 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1237 struct mlx5e_params *params,
1238 struct mlx5e_sq_param *param,
1239 struct mlx5e_txqsq *sq,
1242 struct mlx5e_create_sq_param csp = {};
1246 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1252 csp.cqn = sq->cq.mcq.cqn;
1253 csp.wq_ctrl = &sq->wq_ctrl;
1254 csp.min_inline_mode = sq->min_inline_mode;
1255 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1257 goto err_free_txqsq;
1259 tx_rate = c->priv->tx_rates[sq->txq_ix];
1261 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1263 if (params->tx_dim_enabled)
1264 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1269 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1270 mlx5e_free_txqsq(sq);
1275 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1277 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1278 clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
1279 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1280 netdev_tx_reset_queue(sq->txq);
1281 netif_tx_start_queue(sq->txq);
1284 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1286 __netif_tx_lock_bh(txq);
1287 netif_tx_stop_queue(txq);
1288 __netif_tx_unlock_bh(txq);
1291 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1293 struct mlx5e_channel *c = sq->channel;
1294 struct mlx5_wq_cyc *wq = &sq->wq;
1296 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1297 /* prevent netif_tx_wake_queue */
1298 napi_synchronize(&c->napi);
1300 mlx5e_tx_disable_queue(sq->txq);
1302 /* last doorbell out, godspeed .. */
1303 if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1304 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1305 struct mlx5e_tx_wqe *nop;
1307 sq->db.wqe_info[pi].skb = NULL;
1308 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1309 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1313 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1315 struct mlx5e_channel *c = sq->channel;
1316 struct mlx5_core_dev *mdev = c->mdev;
1317 struct mlx5_rate_limit rl = {0};
1319 cancel_work_sync(&sq->dim.work);
1320 cancel_work_sync(&sq->recover_work);
1321 mlx5e_destroy_sq(mdev, sq->sqn);
1322 if (sq->rate_limit) {
1323 rl.rate = sq->rate_limit;
1324 mlx5_rl_remove_rate(mdev, &rl);
1326 mlx5e_free_txqsq_descs(sq);
1327 mlx5e_free_txqsq(sq);
1330 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1332 struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1335 mlx5e_tx_reporter_err_cqe(sq);
1338 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1339 struct mlx5e_params *params,
1340 struct mlx5e_sq_param *param,
1341 struct mlx5e_icosq *sq)
1343 struct mlx5e_create_sq_param csp = {};
1346 err = mlx5e_alloc_icosq(c, param, sq);
1350 csp.cqn = sq->cq.mcq.cqn;
1351 csp.wq_ctrl = &sq->wq_ctrl;
1352 csp.min_inline_mode = params->tx_min_inline_mode;
1353 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1354 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1356 goto err_free_icosq;
1361 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1362 mlx5e_free_icosq(sq);
1367 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1369 struct mlx5e_channel *c = sq->channel;
1371 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1372 napi_synchronize(&c->napi);
1374 mlx5e_destroy_sq(c->mdev, sq->sqn);
1375 mlx5e_free_icosq(sq);
1378 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1379 struct mlx5e_params *params,
1380 struct mlx5e_sq_param *param,
1381 struct mlx5e_xdpsq *sq,
1384 struct mlx5e_create_sq_param csp = {};
1387 err = mlx5e_alloc_xdpsq(c, params, param, sq, is_redirect);
1392 csp.tisn = c->priv->tisn[0]; /* tc = 0 */
1393 csp.cqn = sq->cq.mcq.cqn;
1394 csp.wq_ctrl = &sq->wq_ctrl;
1395 csp.min_inline_mode = sq->min_inline_mode;
1396 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1397 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1399 goto err_free_xdpsq;
1401 mlx5e_set_xmit_fp(sq, param->is_mpw);
1403 if (!param->is_mpw) {
1404 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1405 unsigned int inline_hdr_sz = 0;
1408 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1409 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1413 /* Pre initialize fixed WQE fields */
1414 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1415 struct mlx5e_xdp_wqe_info *wi = &sq->db.wqe_info[i];
1416 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1417 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1418 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1419 struct mlx5_wqe_data_seg *dseg;
1421 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1422 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1424 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1425 dseg->lkey = sq->mkey_be;
1435 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1436 mlx5e_free_xdpsq(sq);
1441 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq, struct mlx5e_rq *rq)
1443 struct mlx5e_channel *c = sq->channel;
1445 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1446 napi_synchronize(&c->napi);
1448 mlx5e_destroy_sq(c->mdev, sq->sqn);
1449 mlx5e_free_xdpsq_descs(sq, rq);
1450 mlx5e_free_xdpsq(sq);
1453 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1454 struct mlx5e_cq_param *param,
1455 struct mlx5e_cq *cq)
1457 struct mlx5_core_cq *mcq = &cq->mcq;
1463 err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1467 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1473 mcq->set_ci_db = cq->wq_ctrl.db.db;
1474 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1475 *mcq->set_ci_db = 0;
1477 mcq->vector = param->eq_ix;
1478 mcq->comp = mlx5e_completion_event;
1479 mcq->event = mlx5e_cq_error_event;
1482 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1483 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1493 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1494 struct mlx5e_cq_param *param,
1495 struct mlx5e_cq *cq)
1497 struct mlx5_core_dev *mdev = c->priv->mdev;
1500 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1501 param->wq.db_numa_node = cpu_to_node(c->cpu);
1502 param->eq_ix = c->ix;
1504 err = mlx5e_alloc_cq_common(mdev, param, cq);
1506 cq->napi = &c->napi;
1512 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1514 mlx5_wq_destroy(&cq->wq_ctrl);
1517 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1519 struct mlx5_core_dev *mdev = cq->mdev;
1520 struct mlx5_core_cq *mcq = &cq->mcq;
1525 unsigned int irqn_not_used;
1529 err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1533 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1534 sizeof(u64) * cq->wq_ctrl.buf.npages;
1535 in = kvzalloc(inlen, GFP_KERNEL);
1539 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1541 memcpy(cqc, param->cqc, sizeof(param->cqc));
1543 mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1544 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1546 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
1547 MLX5_SET(cqc, cqc, c_eqn, eqn);
1548 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1549 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1550 MLX5_ADAPTER_PAGE_SHIFT);
1551 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1553 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1565 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1567 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1570 static int mlx5e_open_cq(struct mlx5e_channel *c,
1571 struct net_dim_cq_moder moder,
1572 struct mlx5e_cq_param *param,
1573 struct mlx5e_cq *cq)
1575 struct mlx5_core_dev *mdev = c->mdev;
1578 err = mlx5e_alloc_cq(c, param, cq);
1582 err = mlx5e_create_cq(cq, param);
1586 if (MLX5_CAP_GEN(mdev, cq_moderation))
1587 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1596 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1598 mlx5e_destroy_cq(cq);
1602 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1603 struct mlx5e_params *params,
1604 struct mlx5e_channel_param *cparam)
1609 for (tc = 0; tc < c->num_tc; tc++) {
1610 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1611 &cparam->tx_cq, &c->sq[tc].cq);
1613 goto err_close_tx_cqs;
1619 for (tc--; tc >= 0; tc--)
1620 mlx5e_close_cq(&c->sq[tc].cq);
1625 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1629 for (tc = 0; tc < c->num_tc; tc++)
1630 mlx5e_close_cq(&c->sq[tc].cq);
1633 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1634 struct mlx5e_params *params,
1635 struct mlx5e_channel_param *cparam)
1637 struct mlx5e_priv *priv = c->priv;
1638 int err, tc, max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
1640 for (tc = 0; tc < params->num_tc; tc++) {
1641 int txq_ix = c->ix + tc * max_nch;
1643 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1644 params, &cparam->sq, &c->sq[tc], tc);
1652 for (tc--; tc >= 0; tc--)
1653 mlx5e_close_txqsq(&c->sq[tc]);
1658 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1662 for (tc = 0; tc < c->num_tc; tc++)
1663 mlx5e_close_txqsq(&c->sq[tc]);
1666 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1667 struct mlx5e_txqsq *sq, u32 rate)
1669 struct mlx5e_priv *priv = netdev_priv(dev);
1670 struct mlx5_core_dev *mdev = priv->mdev;
1671 struct mlx5e_modify_sq_param msp = {0};
1672 struct mlx5_rate_limit rl = {0};
1676 if (rate == sq->rate_limit)
1680 if (sq->rate_limit) {
1681 rl.rate = sq->rate_limit;
1682 /* remove current rl index to free space to next ones */
1683 mlx5_rl_remove_rate(mdev, &rl);
1690 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1692 netdev_err(dev, "Failed configuring rate %u: %d\n",
1698 msp.curr_state = MLX5_SQC_STATE_RDY;
1699 msp.next_state = MLX5_SQC_STATE_RDY;
1700 msp.rl_index = rl_index;
1701 msp.rl_update = true;
1702 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1704 netdev_err(dev, "Failed configuring rate %u: %d\n",
1706 /* remove the rate from the table */
1708 mlx5_rl_remove_rate(mdev, &rl);
1712 sq->rate_limit = rate;
1716 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1718 struct mlx5e_priv *priv = netdev_priv(dev);
1719 struct mlx5_core_dev *mdev = priv->mdev;
1720 struct mlx5e_txqsq *sq = priv->txq2sq[index];
1723 if (!mlx5_rl_is_supported(mdev)) {
1724 netdev_err(dev, "Rate limiting is not supported on this device\n");
1728 /* rate is given in Mb/sec, HW config is in Kb/sec */
1731 /* Check whether rate in valid range, 0 is always valid */
1732 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1733 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1737 mutex_lock(&priv->state_lock);
1738 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1739 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1741 priv->tx_rates[index] = rate;
1742 mutex_unlock(&priv->state_lock);
1747 static int mlx5e_alloc_xps_cpumask(struct mlx5e_channel *c,
1748 struct mlx5e_params *params)
1750 int num_comp_vectors = mlx5_comp_vectors_count(c->mdev);
1753 if (!zalloc_cpumask_var(&c->xps_cpumask, GFP_KERNEL))
1756 for (irq = c->ix; irq < num_comp_vectors; irq += params->num_channels) {
1757 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(c->mdev, irq));
1759 cpumask_set_cpu(cpu, c->xps_cpumask);
1765 static void mlx5e_free_xps_cpumask(struct mlx5e_channel *c)
1767 free_cpumask_var(c->xps_cpumask);
1770 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1771 struct mlx5e_params *params,
1772 struct mlx5e_channel_param *cparam,
1773 struct mlx5e_channel **cp)
1775 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1776 struct net_dim_cq_moder icocq_moder = {0, 0};
1777 struct net_device *netdev = priv->netdev;
1778 struct mlx5e_channel *c;
1783 err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1787 c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1792 c->mdev = priv->mdev;
1793 c->tstamp = &priv->tstamp;
1796 c->pdev = priv->mdev->device;
1797 c->netdev = priv->netdev;
1798 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1799 c->num_tc = params->num_tc;
1800 c->xdp = !!params->xdp_prog;
1801 c->stats = &priv->channel_stats[ix].ch;
1802 c->irq_desc = irq_to_desc(irq);
1804 err = mlx5e_alloc_xps_cpumask(c, params);
1806 goto err_free_channel;
1808 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1810 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1814 err = mlx5e_open_tx_cqs(c, params, cparam);
1816 goto err_close_icosq_cq;
1818 err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->tx_cq, &c->xdpsq.cq);
1820 goto err_close_tx_cqs;
1822 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1824 goto err_close_xdp_tx_cqs;
1826 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1827 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1828 &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1830 goto err_close_rx_cq;
1832 napi_enable(&c->napi);
1834 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1836 goto err_disable_napi;
1838 err = mlx5e_open_sqs(c, params, cparam);
1840 goto err_close_icosq;
1842 err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq, false) : 0;
1846 err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1848 goto err_close_xdp_sq;
1850 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->xdpsq, true);
1859 mlx5e_close_rq(&c->rq);
1863 mlx5e_close_xdpsq(&c->rq.xdpsq, &c->rq);
1869 mlx5e_close_icosq(&c->icosq);
1872 napi_disable(&c->napi);
1874 mlx5e_close_cq(&c->rq.xdpsq.cq);
1877 mlx5e_close_cq(&c->rq.cq);
1879 err_close_xdp_tx_cqs:
1880 mlx5e_close_cq(&c->xdpsq.cq);
1883 mlx5e_close_tx_cqs(c);
1886 mlx5e_close_cq(&c->icosq.cq);
1889 netif_napi_del(&c->napi);
1890 mlx5e_free_xps_cpumask(c);
1898 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1902 for (tc = 0; tc < c->num_tc; tc++)
1903 mlx5e_activate_txqsq(&c->sq[tc]);
1904 mlx5e_activate_rq(&c->rq);
1905 netif_set_xps_queue(c->netdev, c->xps_cpumask, c->ix);
1908 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1912 mlx5e_deactivate_rq(&c->rq);
1913 for (tc = 0; tc < c->num_tc; tc++)
1914 mlx5e_deactivate_txqsq(&c->sq[tc]);
1917 static void mlx5e_close_channel(struct mlx5e_channel *c)
1919 mlx5e_close_xdpsq(&c->xdpsq, NULL);
1920 mlx5e_close_rq(&c->rq);
1922 mlx5e_close_xdpsq(&c->rq.xdpsq, &c->rq);
1924 mlx5e_close_icosq(&c->icosq);
1925 napi_disable(&c->napi);
1927 mlx5e_close_cq(&c->rq.xdpsq.cq);
1928 mlx5e_close_cq(&c->rq.cq);
1929 mlx5e_close_cq(&c->xdpsq.cq);
1930 mlx5e_close_tx_cqs(c);
1931 mlx5e_close_cq(&c->icosq.cq);
1932 netif_napi_del(&c->napi);
1933 mlx5e_free_xps_cpumask(c);
1938 #define DEFAULT_FRAG_SIZE (2048)
1940 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
1941 struct mlx5e_params *params,
1942 struct mlx5e_rq_frags_info *info)
1944 u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1945 int frag_size_max = DEFAULT_FRAG_SIZE;
1949 #ifdef CONFIG_MLX5_EN_IPSEC
1950 if (MLX5_IPSEC_DEV(mdev))
1951 byte_count += MLX5E_METADATA_ETHER_LEN;
1954 if (mlx5e_rx_is_linear_skb(params)) {
1957 frag_stride = mlx5e_rx_get_linear_frag_sz(params);
1958 frag_stride = roundup_pow_of_two(frag_stride);
1960 info->arr[0].frag_size = byte_count;
1961 info->arr[0].frag_stride = frag_stride;
1962 info->num_frags = 1;
1963 info->wqe_bulk = PAGE_SIZE / frag_stride;
1967 if (byte_count > PAGE_SIZE +
1968 (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
1969 frag_size_max = PAGE_SIZE;
1972 while (buf_size < byte_count) {
1973 int frag_size = byte_count - buf_size;
1975 if (i < MLX5E_MAX_RX_FRAGS - 1)
1976 frag_size = min(frag_size, frag_size_max);
1978 info->arr[i].frag_size = frag_size;
1979 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
1981 buf_size += frag_size;
1984 info->num_frags = i;
1985 /* number of different wqes sharing a page */
1986 info->wqe_bulk = 1 + (info->num_frags % 2);
1989 info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
1990 info->log_num_frags = order_base_2(info->num_frags);
1993 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
1995 int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
1998 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1999 sz += sizeof(struct mlx5e_rx_wqe_ll);
2001 default: /* MLX5_WQ_TYPE_CYCLIC */
2002 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2005 return order_base_2(sz);
2008 static u8 mlx5e_get_rq_log_wq_sz(void *rqc)
2010 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2012 return MLX5_GET(wq, wq, log_wq_sz);
2015 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2016 struct mlx5e_params *params,
2017 struct mlx5e_rq_param *param)
2019 struct mlx5_core_dev *mdev = priv->mdev;
2020 void *rqc = param->rqc;
2021 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2024 switch (params->rq_wq_type) {
2025 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2026 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2027 mlx5e_mpwqe_get_log_num_strides(mdev, params) -
2028 MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2029 MLX5_SET(wq, wq, log_wqe_stride_size,
2030 mlx5e_mpwqe_get_log_stride_size(mdev, params) -
2031 MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2032 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params));
2034 default: /* MLX5_WQ_TYPE_CYCLIC */
2035 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2036 mlx5e_build_rq_frags_info(mdev, params, ¶m->frags_info);
2037 ndsegs = param->frags_info.num_frags;
2040 MLX5_SET(wq, wq, wq_type, params->rq_wq_type);
2041 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2042 MLX5_SET(wq, wq, log_wq_stride,
2043 mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2044 MLX5_SET(wq, wq, pd, mdev->mlx5e_res.pdn);
2045 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2046 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
2047 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
2049 param->wq.buf_numa_node = dev_to_node(mdev->device);
2052 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2053 struct mlx5e_rq_param *param)
2055 struct mlx5_core_dev *mdev = priv->mdev;
2056 void *rqc = param->rqc;
2057 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2059 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2060 MLX5_SET(wq, wq, log_wq_stride,
2061 mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2062 MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2064 param->wq.buf_numa_node = dev_to_node(mdev->device);
2067 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2068 struct mlx5e_sq_param *param)
2070 void *sqc = param->sqc;
2071 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2073 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2074 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
2076 param->wq.buf_numa_node = dev_to_node(priv->mdev->device);
2079 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2080 struct mlx5e_params *params,
2081 struct mlx5e_sq_param *param)
2083 void *sqc = param->sqc;
2084 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2087 allow_swp = mlx5_geneve_tx_allowed(priv->mdev) ||
2088 !!MLX5_IPSEC_DEV(priv->mdev);
2089 mlx5e_build_sq_param_common(priv, param);
2090 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2091 MLX5_SET(sqc, sqc, allow_swp, allow_swp);
2094 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2095 struct mlx5e_cq_param *param)
2097 void *cqc = param->cqc;
2099 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2100 if (MLX5_CAP_GEN(priv->mdev, cqe_128_always) && cache_line_size() >= 128)
2101 MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD);
2104 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2105 struct mlx5e_params *params,
2106 struct mlx5e_cq_param *param)
2108 struct mlx5_core_dev *mdev = priv->mdev;
2109 void *cqc = param->cqc;
2112 switch (params->rq_wq_type) {
2113 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2114 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) +
2115 mlx5e_mpwqe_get_log_num_strides(mdev, params);
2117 default: /* MLX5_WQ_TYPE_CYCLIC */
2118 log_cq_size = params->log_rq_mtu_frames;
2121 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2122 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2123 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2124 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2127 mlx5e_build_common_cq_param(priv, param);
2128 param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2131 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2132 struct mlx5e_params *params,
2133 struct mlx5e_cq_param *param)
2135 void *cqc = param->cqc;
2137 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2139 mlx5e_build_common_cq_param(priv, param);
2140 param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2143 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2145 struct mlx5e_cq_param *param)
2147 void *cqc = param->cqc;
2149 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2151 mlx5e_build_common_cq_param(priv, param);
2153 param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2156 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2158 struct mlx5e_sq_param *param)
2160 void *sqc = param->sqc;
2161 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2163 mlx5e_build_sq_param_common(priv, param);
2165 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2166 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2169 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2170 struct mlx5e_params *params,
2171 struct mlx5e_sq_param *param)
2173 void *sqc = param->sqc;
2174 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2176 mlx5e_build_sq_param_common(priv, param);
2177 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2178 param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE);
2181 static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5e_params *params,
2182 struct mlx5e_rq_param *rqp)
2184 switch (params->rq_wq_type) {
2185 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2186 return order_base_2(MLX5E_UMR_WQEBBS) +
2187 mlx5e_get_rq_log_wq_sz(rqp->rqc);
2188 default: /* MLX5_WQ_TYPE_CYCLIC */
2189 return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2193 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2194 struct mlx5e_params *params,
2195 struct mlx5e_channel_param *cparam)
2199 mlx5e_build_rq_param(priv, params, &cparam->rq);
2201 icosq_log_wq_sz = mlx5e_build_icosq_log_wq_sz(params, &cparam->rq);
2203 mlx5e_build_sq_param(priv, params, &cparam->sq);
2204 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2205 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2206 mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2207 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2208 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2211 int mlx5e_open_channels(struct mlx5e_priv *priv,
2212 struct mlx5e_channels *chs)
2214 struct mlx5e_channel_param *cparam;
2218 chs->num = chs->params.num_channels;
2220 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2221 cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2222 if (!chs->c || !cparam)
2225 mlx5e_build_channel_param(priv, &chs->params, cparam);
2226 for (i = 0; i < chs->num; i++) {
2227 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2229 goto err_close_channels;
2232 if (!IS_ERR_OR_NULL(priv->tx_reporter))
2233 devlink_health_reporter_state_update(priv->tx_reporter,
2234 DEVLINK_HEALTH_REPORTER_STATE_HEALTHY);
2240 for (i--; i >= 0; i--)
2241 mlx5e_close_channel(chs->c[i]);
2250 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2254 for (i = 0; i < chs->num; i++)
2255 mlx5e_activate_channel(chs->c[i]);
2258 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2260 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2265 for (i = 0; i < chs->num; i++) {
2266 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2268 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2271 return err ? -ETIMEDOUT : 0;
2274 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2278 for (i = 0; i < chs->num; i++)
2279 mlx5e_deactivate_channel(chs->c[i]);
2282 void mlx5e_close_channels(struct mlx5e_channels *chs)
2286 for (i = 0; i < chs->num; i++)
2287 mlx5e_close_channel(chs->c[i]);
2294 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2296 struct mlx5_core_dev *mdev = priv->mdev;
2303 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2304 in = kvzalloc(inlen, GFP_KERNEL);
2308 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2310 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2311 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2313 for (i = 0; i < sz; i++)
2314 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2316 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2318 rqt->enabled = true;
2324 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2326 rqt->enabled = false;
2327 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2330 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2332 struct mlx5e_rqt *rqt = &priv->indir_rqt;
2335 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2337 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2341 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2343 struct mlx5e_rqt *rqt;
2347 for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
2348 rqt = &priv->direct_tir[ix].rqt;
2349 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2351 goto err_destroy_rqts;
2357 mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2358 for (ix--; ix >= 0; ix--)
2359 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2364 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2368 for (i = 0; i < mlx5e_get_netdev_max_channels(priv->netdev); i++)
2369 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2372 static int mlx5e_rx_hash_fn(int hfunc)
2374 return (hfunc == ETH_RSS_HASH_TOP) ?
2375 MLX5_RX_HASH_FN_TOEPLITZ :
2376 MLX5_RX_HASH_FN_INVERTED_XOR8;
2379 int mlx5e_bits_invert(unsigned long a, int size)
2384 for (i = 0; i < size; i++)
2385 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2390 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2391 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2395 for (i = 0; i < sz; i++) {
2401 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2402 ix = mlx5e_bits_invert(i, ilog2(sz));
2404 ix = priv->rss_params.indirection_rqt[ix];
2405 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2409 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2413 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2414 struct mlx5e_redirect_rqt_param rrp)
2416 struct mlx5_core_dev *mdev = priv->mdev;
2422 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2423 in = kvzalloc(inlen, GFP_KERNEL);
2427 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2429 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2430 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2431 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2432 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2438 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2439 struct mlx5e_redirect_rqt_param rrp)
2444 if (ix >= rrp.rss.channels->num)
2445 return priv->drop_rq.rqn;
2447 return rrp.rss.channels->c[ix]->rq.rqn;
2450 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2451 struct mlx5e_redirect_rqt_param rrp)
2456 if (priv->indir_rqt.enabled) {
2458 rqtn = priv->indir_rqt.rqtn;
2459 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2462 for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
2463 struct mlx5e_redirect_rqt_param direct_rrp = {
2466 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2470 /* Direct RQ Tables */
2471 if (!priv->direct_tir[ix].rqt.enabled)
2474 rqtn = priv->direct_tir[ix].rqt.rqtn;
2475 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2479 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2480 struct mlx5e_channels *chs)
2482 struct mlx5e_redirect_rqt_param rrp = {
2487 .hfunc = priv->rss_params.hfunc,
2492 mlx5e_redirect_rqts(priv, rrp);
2495 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2497 struct mlx5e_redirect_rqt_param drop_rrp = {
2500 .rqn = priv->drop_rq.rqn,
2504 mlx5e_redirect_rqts(priv, drop_rrp);
2507 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {
2508 [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2509 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2510 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2512 [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2513 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2514 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2516 [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2517 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2518 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2520 [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2521 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2522 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2524 [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2526 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2528 [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2530 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2532 [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2534 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2536 [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2538 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2540 [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2542 .rx_hash_fields = MLX5_HASH_IP,
2544 [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2546 .rx_hash_fields = MLX5_HASH_IP,
2550 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)
2552 return tirc_default_config[tt];
2555 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2557 if (!params->lro_en)
2560 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2562 MLX5_SET(tirc, tirc, lro_enable_mask,
2563 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2564 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2565 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2566 (MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2567 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2570 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
2571 const struct mlx5e_tirc_config *ttconfig,
2572 void *tirc, bool inner)
2574 void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2575 MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2577 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc));
2578 if (rss_params->hfunc == ETH_RSS_HASH_TOP) {
2579 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2580 rx_hash_toeplitz_key);
2581 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2582 rx_hash_toeplitz_key);
2584 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2585 memcpy(rss_key, rss_params->toeplitz_hash_key, len);
2587 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2588 ttconfig->l3_prot_type);
2589 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2590 ttconfig->l4_prot_type);
2591 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2592 ttconfig->rx_hash_fields);
2595 static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig,
2596 enum mlx5e_traffic_types tt,
2599 *ttconfig = tirc_default_config[tt];
2600 ttconfig->rx_hash_fields = rx_hash_fields;
2603 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
2605 void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2606 struct mlx5e_rss_params *rss = &priv->rss_params;
2607 struct mlx5_core_dev *mdev = priv->mdev;
2608 int ctxlen = MLX5_ST_SZ_BYTES(tirc);
2609 struct mlx5e_tirc_config ttconfig;
2612 MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
2614 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2615 memset(tirc, 0, ctxlen);
2616 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2617 rss->rx_hash_fields[tt]);
2618 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false);
2619 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);
2622 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2625 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2626 memset(tirc, 0, ctxlen);
2627 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2628 rss->rx_hash_fields[tt]);
2629 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true);
2630 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in,
2635 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2637 struct mlx5_core_dev *mdev = priv->mdev;
2646 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2647 in = kvzalloc(inlen, GFP_KERNEL);
2651 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2652 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2654 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2656 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2657 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2663 for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
2664 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2676 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2677 struct mlx5e_params *params, u16 mtu)
2679 u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2682 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2686 /* Update vport context MTU */
2687 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2691 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2692 struct mlx5e_params *params, u16 *mtu)
2697 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2698 if (err || !hw_mtu) /* fallback to port oper mtu */
2699 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2701 *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2704 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2706 struct mlx5e_params *params = &priv->channels.params;
2707 struct net_device *netdev = priv->netdev;
2708 struct mlx5_core_dev *mdev = priv->mdev;
2712 err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2716 mlx5e_query_mtu(mdev, params, &mtu);
2717 if (mtu != params->sw_mtu)
2718 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2719 __func__, mtu, params->sw_mtu);
2721 params->sw_mtu = mtu;
2725 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2727 struct mlx5e_params *params = &priv->channels.params;
2728 struct net_device *netdev = priv->netdev;
2729 struct mlx5_core_dev *mdev = priv->mdev;
2732 /* MTU range: 68 - hw-specific max */
2733 netdev->min_mtu = ETH_MIN_MTU;
2735 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2736 netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2740 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2742 struct mlx5e_priv *priv = netdev_priv(netdev);
2743 int nch = priv->channels.params.num_channels;
2744 int ntc = priv->channels.params.num_tc;
2747 netdev_reset_tc(netdev);
2752 netdev_set_num_tc(netdev, ntc);
2754 /* Map netdev TCs to offset 0
2755 * We have our own UP to TXQ mapping for QoS
2757 for (tc = 0; tc < ntc; tc++)
2758 netdev_set_tc_queue(netdev, tc, nch, 0);
2761 static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv)
2763 int max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
2766 for (i = 0; i < max_nch; i++)
2767 for (tc = 0; tc < priv->profile->max_tc; tc++)
2768 priv->channel_tc2txq[i][tc] = i + tc * max_nch;
2771 static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv)
2773 struct mlx5e_channel *c;
2774 struct mlx5e_txqsq *sq;
2777 for (i = 0; i < priv->channels.num; i++) {
2778 c = priv->channels.c[i];
2779 for (tc = 0; tc < c->num_tc; tc++) {
2781 priv->txq2sq[sq->txq_ix] = sq;
2786 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2788 int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2789 struct net_device *netdev = priv->netdev;
2791 mlx5e_netdev_set_tcs(netdev);
2792 netif_set_real_num_tx_queues(netdev, num_txqs);
2793 netif_set_real_num_rx_queues(netdev, priv->channels.num);
2795 mlx5e_build_tx2sq_maps(priv);
2796 mlx5e_activate_channels(&priv->channels);
2797 mlx5e_xdp_tx_enable(priv);
2798 netif_tx_start_all_queues(priv->netdev);
2800 if (mlx5e_is_vport_rep(priv))
2801 mlx5e_add_sqs_fwd_rules(priv);
2803 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2804 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2807 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2809 mlx5e_redirect_rqts_to_drop(priv);
2811 if (mlx5e_is_vport_rep(priv))
2812 mlx5e_remove_sqs_fwd_rules(priv);
2814 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2815 * polling for inactive tx queues.
2817 netif_tx_stop_all_queues(priv->netdev);
2818 netif_tx_disable(priv->netdev);
2819 mlx5e_xdp_tx_disable(priv);
2820 mlx5e_deactivate_channels(&priv->channels);
2823 static void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2824 struct mlx5e_channels *new_chs,
2825 mlx5e_fp_hw_modify hw_modify)
2827 struct net_device *netdev = priv->netdev;
2831 new_num_txqs = new_chs->num * new_chs->params.num_tc;
2833 carrier_ok = netif_carrier_ok(netdev);
2834 netif_carrier_off(netdev);
2836 if (new_num_txqs < netdev->real_num_tx_queues)
2837 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2839 mlx5e_deactivate_priv_channels(priv);
2840 mlx5e_close_channels(&priv->channels);
2842 priv->channels = *new_chs;
2844 /* New channels are ready to roll, modify HW settings if needed */
2848 mlx5e_refresh_tirs(priv, false);
2849 mlx5e_activate_priv_channels(priv);
2851 /* return carrier back if needed */
2853 netif_carrier_on(netdev);
2856 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
2857 struct mlx5e_channels *new_chs,
2858 mlx5e_fp_hw_modify hw_modify)
2862 err = mlx5e_open_channels(priv, new_chs);
2866 mlx5e_switch_priv_channels(priv, new_chs, hw_modify);
2870 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
2872 struct mlx5e_channels new_channels = {};
2874 new_channels.params = priv->channels.params;
2875 return mlx5e_safe_switch_channels(priv, &new_channels, NULL);
2878 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2880 priv->tstamp.tx_type = HWTSTAMP_TX_OFF;
2881 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2884 int mlx5e_open_locked(struct net_device *netdev)
2886 struct mlx5e_priv *priv = netdev_priv(netdev);
2889 set_bit(MLX5E_STATE_OPENED, &priv->state);
2891 err = mlx5e_open_channels(priv, &priv->channels);
2893 goto err_clear_state_opened_flag;
2895 mlx5e_refresh_tirs(priv, false);
2896 mlx5e_activate_priv_channels(priv);
2897 if (priv->profile->update_carrier)
2898 priv->profile->update_carrier(priv);
2900 mlx5e_queue_update_stats(priv);
2903 err_clear_state_opened_flag:
2904 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2908 int mlx5e_open(struct net_device *netdev)
2910 struct mlx5e_priv *priv = netdev_priv(netdev);
2913 mutex_lock(&priv->state_lock);
2914 err = mlx5e_open_locked(netdev);
2916 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2917 mutex_unlock(&priv->state_lock);
2919 if (mlx5_vxlan_allowed(priv->mdev->vxlan))
2920 udp_tunnel_get_rx_info(netdev);
2925 int mlx5e_close_locked(struct net_device *netdev)
2927 struct mlx5e_priv *priv = netdev_priv(netdev);
2929 /* May already be CLOSED in case a previous configuration operation
2930 * (e.g RX/TX queue size change) that involves close&open failed.
2932 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2935 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2937 netif_carrier_off(priv->netdev);
2938 mlx5e_deactivate_priv_channels(priv);
2939 mlx5e_close_channels(&priv->channels);
2944 int mlx5e_close(struct net_device *netdev)
2946 struct mlx5e_priv *priv = netdev_priv(netdev);
2949 if (!netif_device_present(netdev))
2952 mutex_lock(&priv->state_lock);
2953 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
2954 err = mlx5e_close_locked(netdev);
2955 mutex_unlock(&priv->state_lock);
2960 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2961 struct mlx5e_rq *rq,
2962 struct mlx5e_rq_param *param)
2964 void *rqc = param->rqc;
2965 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2968 param->wq.db_numa_node = param->wq.buf_numa_node;
2970 err = mlx5_wq_cyc_create(mdev, ¶m->wq, rqc_wq, &rq->wqe.wq,
2975 /* Mark as unused given "Drop-RQ" packets never reach XDP */
2976 xdp_rxq_info_unused(&rq->xdp_rxq);
2983 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
2984 struct mlx5e_cq *cq,
2985 struct mlx5e_cq_param *param)
2987 param->wq.buf_numa_node = dev_to_node(mdev->device);
2988 param->wq.db_numa_node = dev_to_node(mdev->device);
2990 return mlx5e_alloc_cq_common(mdev, param, cq);
2993 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
2994 struct mlx5e_rq *drop_rq)
2996 struct mlx5_core_dev *mdev = priv->mdev;
2997 struct mlx5e_cq_param cq_param = {};
2998 struct mlx5e_rq_param rq_param = {};
2999 struct mlx5e_cq *cq = &drop_rq->cq;
3002 mlx5e_build_drop_rq_param(priv, &rq_param);
3004 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3008 err = mlx5e_create_cq(cq, &cq_param);
3012 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3014 goto err_destroy_cq;
3016 err = mlx5e_create_rq(drop_rq, &rq_param);
3020 err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3022 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3027 mlx5e_free_rq(drop_rq);
3030 mlx5e_destroy_cq(cq);
3038 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3040 mlx5e_destroy_rq(drop_rq);
3041 mlx5e_free_rq(drop_rq);
3042 mlx5e_destroy_cq(&drop_rq->cq);
3043 mlx5e_free_cq(&drop_rq->cq);
3046 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
3047 u32 underlay_qpn, u32 *tisn)
3049 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
3050 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3052 MLX5_SET(tisc, tisc, prio, tc << 1);
3053 MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
3054 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3056 if (mlx5_lag_is_lacp_owner(mdev))
3057 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3059 return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
3062 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3064 mlx5_core_destroy_tis(mdev, tisn);
3067 int mlx5e_create_tises(struct mlx5e_priv *priv)
3072 for (tc = 0; tc < priv->profile->max_tc; tc++) {
3073 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
3075 goto err_close_tises;
3081 for (tc--; tc >= 0; tc--)
3082 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3087 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3091 mlx5e_tx_reporter_destroy(priv);
3092 for (tc = 0; tc < priv->profile->max_tc; tc++)
3093 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3096 static void mlx5e_build_indir_tir_ctx_common(struct mlx5e_priv *priv,
3097 u32 rqtn, u32 *tirc)
3099 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3100 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3101 MLX5_SET(tirc, tirc, indirect_table, rqtn);
3102 MLX5_SET(tirc, tirc, tunneled_offload_en,
3103 priv->channels.params.tunneled_offload_en);
3105 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3108 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3109 enum mlx5e_traffic_types tt,
3112 mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3113 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3114 &tirc_default_config[tt], tirc, false);
3117 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3119 mlx5e_build_indir_tir_ctx_common(priv, rqtn, tirc);
3120 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3123 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
3124 enum mlx5e_traffic_types tt,
3127 mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3128 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3129 &tirc_default_config[tt], tirc, true);
3132 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3134 struct mlx5e_tir *tir;
3142 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3143 in = kvzalloc(inlen, GFP_KERNEL);
3147 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3148 memset(in, 0, inlen);
3149 tir = &priv->indir_tir[tt];
3150 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3151 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3152 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3154 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3155 goto err_destroy_inner_tirs;
3159 if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3162 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3163 memset(in, 0, inlen);
3164 tir = &priv->inner_indir_tir[i];
3165 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3166 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3167 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3169 mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3170 goto err_destroy_inner_tirs;
3179 err_destroy_inner_tirs:
3180 for (i--; i >= 0; i--)
3181 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3183 for (tt--; tt >= 0; tt--)
3184 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3191 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
3193 int nch = mlx5e_get_netdev_max_channels(priv->netdev);
3194 struct mlx5e_tir *tir;
3201 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3202 in = kvzalloc(inlen, GFP_KERNEL);
3206 for (ix = 0; ix < nch; ix++) {
3207 memset(in, 0, inlen);
3208 tir = &priv->direct_tir[ix];
3209 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3210 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
3211 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3213 goto err_destroy_ch_tirs;
3220 err_destroy_ch_tirs:
3221 mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
3222 for (ix--; ix >= 0; ix--)
3223 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
3230 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3234 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3235 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3237 if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3240 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3241 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3244 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3246 int nch = mlx5e_get_netdev_max_channels(priv->netdev);
3249 for (i = 0; i < nch; i++)
3250 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3253 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3258 for (i = 0; i < chs->num; i++) {
3259 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3267 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3272 for (i = 0; i < chs->num; i++) {
3273 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3281 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3282 struct tc_mqprio_qopt *mqprio)
3284 struct mlx5e_priv *priv = netdev_priv(netdev);
3285 struct mlx5e_channels new_channels = {};
3286 u8 tc = mqprio->num_tc;
3289 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3291 if (tc && tc != MLX5E_MAX_NUM_TC)
3294 mutex_lock(&priv->state_lock);
3296 new_channels.params = priv->channels.params;
3297 new_channels.params.num_tc = tc ? tc : 1;
3299 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3300 priv->channels.params = new_channels.params;
3304 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
3308 priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3309 new_channels.params.num_tc);
3311 mutex_unlock(&priv->state_lock);
3315 #ifdef CONFIG_MLX5_ESWITCH
3316 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3317 struct tc_cls_flower_offload *cls_flower,
3320 switch (cls_flower->command) {
3321 case TC_CLSFLOWER_REPLACE:
3322 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
3324 case TC_CLSFLOWER_DESTROY:
3325 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
3327 case TC_CLSFLOWER_STATS:
3328 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
3335 static int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3338 struct mlx5e_priv *priv = cb_priv;
3341 case TC_SETUP_CLSFLOWER:
3342 return mlx5e_setup_tc_cls_flower(priv, type_data, MLX5E_TC_INGRESS |
3343 MLX5E_TC_NIC_OFFLOAD);
3349 static int mlx5e_setup_tc_block(struct net_device *dev,
3350 struct tc_block_offload *f)
3352 struct mlx5e_priv *priv = netdev_priv(dev);
3354 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3357 switch (f->command) {
3359 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
3360 priv, priv, f->extack);
3361 case TC_BLOCK_UNBIND:
3362 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3371 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3375 #ifdef CONFIG_MLX5_ESWITCH
3376 case TC_SETUP_BLOCK:
3377 return mlx5e_setup_tc_block(dev, type_data);
3379 case TC_SETUP_QDISC_MQPRIO:
3380 return mlx5e_setup_tc_mqprio(dev, type_data);
3386 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3390 for (i = 0; i < mlx5e_get_netdev_max_channels(priv->netdev); i++) {
3391 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3392 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3395 s->rx_packets += rq_stats->packets;
3396 s->rx_bytes += rq_stats->bytes;
3398 for (j = 0; j < priv->max_opened_tc; j++) {
3399 struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3401 s->tx_packets += sq_stats->packets;
3402 s->tx_bytes += sq_stats->bytes;
3403 s->tx_dropped += sq_stats->dropped;
3409 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3411 struct mlx5e_priv *priv = netdev_priv(dev);
3412 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3413 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3415 if (!mlx5e_monitor_counter_supported(priv)) {
3416 /* update HW stats in background for next time */
3417 mlx5e_queue_update_stats(priv);
3420 if (mlx5e_is_uplink_rep(priv)) {
3421 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3422 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3423 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3424 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3426 mlx5e_fold_sw_stats64(priv, stats);
3429 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3431 stats->rx_length_errors =
3432 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3433 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3434 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3435 stats->rx_crc_errors =
3436 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3437 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3438 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3439 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3440 stats->rx_frame_errors;
3441 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3443 /* vport multicast also counts packets that are dropped due to steering
3444 * or rx out of buffer
3447 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3450 static void mlx5e_set_rx_mode(struct net_device *dev)
3452 struct mlx5e_priv *priv = netdev_priv(dev);
3454 queue_work(priv->wq, &priv->set_rx_mode_work);
3457 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3459 struct mlx5e_priv *priv = netdev_priv(netdev);
3460 struct sockaddr *saddr = addr;
3462 if (!is_valid_ether_addr(saddr->sa_data))
3463 return -EADDRNOTAVAIL;
3465 netif_addr_lock_bh(netdev);
3466 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3467 netif_addr_unlock_bh(netdev);
3469 queue_work(priv->wq, &priv->set_rx_mode_work);
3474 #define MLX5E_SET_FEATURE(features, feature, enable) \
3477 *features |= feature; \
3479 *features &= ~feature; \
3482 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3484 static int set_feature_lro(struct net_device *netdev, bool enable)
3486 struct mlx5e_priv *priv = netdev_priv(netdev);
3487 struct mlx5_core_dev *mdev = priv->mdev;
3488 struct mlx5e_channels new_channels = {};
3489 struct mlx5e_params *old_params;
3493 mutex_lock(&priv->state_lock);
3495 old_params = &priv->channels.params;
3496 if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3497 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3502 reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3504 new_channels.params = *old_params;
3505 new_channels.params.lro_en = enable;
3507 if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3508 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params) ==
3509 mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params))
3514 *old_params = new_channels.params;
3515 err = mlx5e_modify_tirs_lro(priv);
3519 err = mlx5e_safe_switch_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3521 mutex_unlock(&priv->state_lock);
3525 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3527 struct mlx5e_priv *priv = netdev_priv(netdev);
3530 mlx5e_enable_cvlan_filter(priv);
3532 mlx5e_disable_cvlan_filter(priv);
3537 #ifdef CONFIG_MLX5_ESWITCH
3538 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3540 struct mlx5e_priv *priv = netdev_priv(netdev);
3542 if (!enable && mlx5e_tc_num_filters(priv, MLX5E_TC_NIC_OFFLOAD)) {
3544 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3552 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3554 struct mlx5e_priv *priv = netdev_priv(netdev);
3555 struct mlx5_core_dev *mdev = priv->mdev;
3557 return mlx5_set_port_fcs(mdev, !enable);
3560 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3562 struct mlx5e_priv *priv = netdev_priv(netdev);
3565 mutex_lock(&priv->state_lock);
3567 priv->channels.params.scatter_fcs_en = enable;
3568 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3570 priv->channels.params.scatter_fcs_en = !enable;
3572 mutex_unlock(&priv->state_lock);
3577 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3579 struct mlx5e_priv *priv = netdev_priv(netdev);
3582 mutex_lock(&priv->state_lock);
3584 priv->channels.params.vlan_strip_disable = !enable;
3585 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3588 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3590 priv->channels.params.vlan_strip_disable = enable;
3593 mutex_unlock(&priv->state_lock);
3598 #ifdef CONFIG_MLX5_EN_ARFS
3599 static int set_feature_arfs(struct net_device *netdev, bool enable)
3601 struct mlx5e_priv *priv = netdev_priv(netdev);
3605 err = mlx5e_arfs_enable(priv);
3607 err = mlx5e_arfs_disable(priv);
3613 static int mlx5e_handle_feature(struct net_device *netdev,
3614 netdev_features_t *features,
3615 netdev_features_t wanted_features,
3616 netdev_features_t feature,
3617 mlx5e_feature_handler feature_handler)
3619 netdev_features_t changes = wanted_features ^ netdev->features;
3620 bool enable = !!(wanted_features & feature);
3623 if (!(changes & feature))
3626 err = feature_handler(netdev, enable);
3628 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3629 enable ? "Enable" : "Disable", &feature, err);
3633 MLX5E_SET_FEATURE(features, feature, enable);
3637 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3639 netdev_features_t oper_features = netdev->features;
3642 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3643 mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3645 err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3646 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3647 set_feature_cvlan_filter);
3648 #ifdef CONFIG_MLX5_ESWITCH
3649 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3651 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3652 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3653 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3654 #ifdef CONFIG_MLX5_EN_ARFS
3655 err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3659 netdev->features = oper_features;
3666 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3667 netdev_features_t features)
3669 struct mlx5e_priv *priv = netdev_priv(netdev);
3670 struct mlx5e_params *params;
3672 mutex_lock(&priv->state_lock);
3673 params = &priv->channels.params;
3674 if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3675 /* HW strips the outer C-tag header, this is a problem
3676 * for S-tag traffic.
3678 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3679 if (!params->vlan_strip_disable)
3680 netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3682 if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3683 features &= ~NETIF_F_LRO;
3685 netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3688 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3689 features &= ~NETIF_F_RXHASH;
3690 if (netdev->features & NETIF_F_RXHASH)
3691 netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3694 mutex_unlock(&priv->state_lock);
3699 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3700 change_hw_mtu_cb set_mtu_cb)
3702 struct mlx5e_priv *priv = netdev_priv(netdev);
3703 struct mlx5e_channels new_channels = {};
3704 struct mlx5e_params *params;
3708 mutex_lock(&priv->state_lock);
3710 params = &priv->channels.params;
3712 reset = !params->lro_en;
3713 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3715 new_channels.params = *params;
3716 new_channels.params.sw_mtu = new_mtu;
3718 if (params->xdp_prog &&
3719 !mlx5e_rx_is_linear_skb(&new_channels.params)) {
3720 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3721 new_mtu, mlx5e_xdp_max_mtu(params));
3726 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3727 bool is_linear = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, &new_channels.params);
3728 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params);
3729 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params);
3731 reset = reset && (is_linear || (ppw_old != ppw_new));
3735 params->sw_mtu = new_mtu;
3738 netdev->mtu = params->sw_mtu;
3742 err = mlx5e_safe_switch_channels(priv, &new_channels, set_mtu_cb);
3746 netdev->mtu = new_channels.params.sw_mtu;
3749 mutex_unlock(&priv->state_lock);
3753 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3755 return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu);
3758 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3760 struct hwtstamp_config config;
3763 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
3764 (mlx5_clock_get_ptp_index(priv->mdev) == -1))
3767 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3770 /* TX HW timestamp */
3771 switch (config.tx_type) {
3772 case HWTSTAMP_TX_OFF:
3773 case HWTSTAMP_TX_ON:
3779 mutex_lock(&priv->state_lock);
3780 /* RX HW timestamp */
3781 switch (config.rx_filter) {
3782 case HWTSTAMP_FILTER_NONE:
3783 /* Reset CQE compression to Admin default */
3784 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3786 case HWTSTAMP_FILTER_ALL:
3787 case HWTSTAMP_FILTER_SOME:
3788 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3789 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3790 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3791 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3792 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3793 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3794 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3795 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3796 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3797 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3798 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3799 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3800 case HWTSTAMP_FILTER_NTP_ALL:
3801 /* Disable CQE compression */
3802 netdev_warn(priv->netdev, "Disabling cqe compression");
3803 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3805 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3806 mutex_unlock(&priv->state_lock);
3809 config.rx_filter = HWTSTAMP_FILTER_ALL;
3812 mutex_unlock(&priv->state_lock);
3816 memcpy(&priv->tstamp, &config, sizeof(config));
3817 mutex_unlock(&priv->state_lock);
3819 /* might need to fix some features */
3820 netdev_update_features(priv->netdev);
3822 return copy_to_user(ifr->ifr_data, &config,
3823 sizeof(config)) ? -EFAULT : 0;
3826 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3828 struct hwtstamp_config *cfg = &priv->tstamp;
3830 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3833 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3836 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3838 struct mlx5e_priv *priv = netdev_priv(dev);
3842 return mlx5e_hwstamp_set(priv, ifr);
3844 return mlx5e_hwstamp_get(priv, ifr);
3850 #ifdef CONFIG_MLX5_ESWITCH
3851 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3853 struct mlx5e_priv *priv = netdev_priv(dev);
3854 struct mlx5_core_dev *mdev = priv->mdev;
3856 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3859 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3862 struct mlx5e_priv *priv = netdev_priv(dev);
3863 struct mlx5_core_dev *mdev = priv->mdev;
3865 if (vlan_proto != htons(ETH_P_8021Q))
3866 return -EPROTONOSUPPORT;
3868 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3872 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3874 struct mlx5e_priv *priv = netdev_priv(dev);
3875 struct mlx5_core_dev *mdev = priv->mdev;
3877 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3880 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3882 struct mlx5e_priv *priv = netdev_priv(dev);
3883 struct mlx5_core_dev *mdev = priv->mdev;
3885 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3888 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3891 struct mlx5e_priv *priv = netdev_priv(dev);
3892 struct mlx5_core_dev *mdev = priv->mdev;
3894 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3895 max_tx_rate, min_tx_rate);
3898 static int mlx5_vport_link2ifla(u8 esw_link)
3901 case MLX5_VPORT_ADMIN_STATE_DOWN:
3902 return IFLA_VF_LINK_STATE_DISABLE;
3903 case MLX5_VPORT_ADMIN_STATE_UP:
3904 return IFLA_VF_LINK_STATE_ENABLE;
3906 return IFLA_VF_LINK_STATE_AUTO;
3909 static int mlx5_ifla_link2vport(u8 ifla_link)
3911 switch (ifla_link) {
3912 case IFLA_VF_LINK_STATE_DISABLE:
3913 return MLX5_VPORT_ADMIN_STATE_DOWN;
3914 case IFLA_VF_LINK_STATE_ENABLE:
3915 return MLX5_VPORT_ADMIN_STATE_UP;
3917 return MLX5_VPORT_ADMIN_STATE_AUTO;
3920 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3923 struct mlx5e_priv *priv = netdev_priv(dev);
3924 struct mlx5_core_dev *mdev = priv->mdev;
3926 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3927 mlx5_ifla_link2vport(link_state));
3930 int mlx5e_get_vf_config(struct net_device *dev,
3931 int vf, struct ifla_vf_info *ivi)
3933 struct mlx5e_priv *priv = netdev_priv(dev);
3934 struct mlx5_core_dev *mdev = priv->mdev;
3937 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3940 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3944 int mlx5e_get_vf_stats(struct net_device *dev,
3945 int vf, struct ifla_vf_stats *vf_stats)
3947 struct mlx5e_priv *priv = netdev_priv(dev);
3948 struct mlx5_core_dev *mdev = priv->mdev;
3950 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3955 struct mlx5e_vxlan_work {
3956 struct work_struct work;
3957 struct mlx5e_priv *priv;
3961 static void mlx5e_vxlan_add_work(struct work_struct *work)
3963 struct mlx5e_vxlan_work *vxlan_work =
3964 container_of(work, struct mlx5e_vxlan_work, work);
3965 struct mlx5e_priv *priv = vxlan_work->priv;
3966 u16 port = vxlan_work->port;
3968 mutex_lock(&priv->state_lock);
3969 mlx5_vxlan_add_port(priv->mdev->vxlan, port);
3970 mutex_unlock(&priv->state_lock);
3975 static void mlx5e_vxlan_del_work(struct work_struct *work)
3977 struct mlx5e_vxlan_work *vxlan_work =
3978 container_of(work, struct mlx5e_vxlan_work, work);
3979 struct mlx5e_priv *priv = vxlan_work->priv;
3980 u16 port = vxlan_work->port;
3982 mutex_lock(&priv->state_lock);
3983 mlx5_vxlan_del_port(priv->mdev->vxlan, port);
3984 mutex_unlock(&priv->state_lock);
3988 static void mlx5e_vxlan_queue_work(struct mlx5e_priv *priv, u16 port, int add)
3990 struct mlx5e_vxlan_work *vxlan_work;
3992 vxlan_work = kmalloc(sizeof(*vxlan_work), GFP_ATOMIC);
3997 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_add_work);
3999 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_del_work);
4001 vxlan_work->priv = priv;
4002 vxlan_work->port = port;
4003 queue_work(priv->wq, &vxlan_work->work);
4006 void mlx5e_add_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4008 struct mlx5e_priv *priv = netdev_priv(netdev);
4010 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4013 if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4016 mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 1);
4019 void mlx5e_del_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4021 struct mlx5e_priv *priv = netdev_priv(netdev);
4023 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4026 if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4029 mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 0);
4032 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4033 struct sk_buff *skb,
4034 netdev_features_t features)
4036 unsigned int offset = 0;
4037 struct udphdr *udph;
4041 switch (vlan_get_protocol(skb)) {
4042 case htons(ETH_P_IP):
4043 proto = ip_hdr(skb)->protocol;
4045 case htons(ETH_P_IPV6):
4046 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4056 udph = udp_hdr(skb);
4057 port = be16_to_cpu(udph->dest);
4059 /* Verify if UDP port is being offloaded by HW */
4060 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4063 #if IS_ENABLED(CONFIG_GENEVE)
4064 /* Support Geneve offload for default UDP port */
4065 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4071 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4072 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4075 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4076 struct net_device *netdev,
4077 netdev_features_t features)
4079 struct mlx5e_priv *priv = netdev_priv(netdev);
4081 features = vlan_features_check(skb, features);
4082 features = vxlan_features_check(skb, features);
4084 #ifdef CONFIG_MLX5_EN_IPSEC
4085 if (mlx5e_ipsec_feature_check(skb, netdev, features))
4089 /* Validate if the tunneled packet is being offloaded by HW */
4090 if (skb->encapsulation &&
4091 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4092 return mlx5e_tunnel_features_check(priv, skb, features);
4097 static void mlx5e_tx_timeout_work(struct work_struct *work)
4099 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4101 bool report_failed = false;
4106 mutex_lock(&priv->state_lock);
4108 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4111 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
4112 struct netdev_queue *dev_queue =
4113 netdev_get_tx_queue(priv->netdev, i);
4114 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4116 if (!netif_xmit_stopped(dev_queue))
4119 if (mlx5e_tx_reporter_timeout(sq))
4120 report_failed = true;
4126 err = mlx5e_safe_reopen_channels(priv);
4128 netdev_err(priv->netdev,
4129 "mlx5e_safe_reopen_channels failed recovering from a tx_timeout, err(%d).\n",
4133 mutex_unlock(&priv->state_lock);
4137 static void mlx5e_tx_timeout(struct net_device *dev)
4139 struct mlx5e_priv *priv = netdev_priv(dev);
4141 netdev_err(dev, "TX timeout detected\n");
4142 queue_work(priv->wq, &priv->tx_timeout_work);
4145 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4147 struct net_device *netdev = priv->netdev;
4148 struct mlx5e_channels new_channels = {};
4150 if (priv->channels.params.lro_en) {
4151 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4155 if (MLX5_IPSEC_DEV(priv->mdev)) {
4156 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4160 new_channels.params = priv->channels.params;
4161 new_channels.params.xdp_prog = prog;
4163 if (!mlx5e_rx_is_linear_skb(&new_channels.params)) {
4164 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4165 new_channels.params.sw_mtu,
4166 mlx5e_xdp_max_mtu(&new_channels.params));
4173 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4175 struct mlx5e_priv *priv = netdev_priv(netdev);
4176 struct bpf_prog *old_prog;
4177 bool reset, was_opened;
4181 mutex_lock(&priv->state_lock);
4184 err = mlx5e_xdp_allowed(priv, prog);
4189 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4190 /* no need for full reset when exchanging programs */
4191 reset = (!priv->channels.params.xdp_prog || !prog);
4193 if (was_opened && reset)
4194 mlx5e_close_locked(netdev);
4195 if (was_opened && !reset) {
4196 /* num_channels is invariant here, so we can take the
4197 * batched reference right upfront.
4199 prog = bpf_prog_add(prog, priv->channels.num);
4201 err = PTR_ERR(prog);
4206 /* exchange programs, extra prog reference we got from caller
4207 * as long as we don't fail from this point onwards.
4209 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4211 bpf_prog_put(old_prog);
4213 if (reset) /* change RQ type according to priv->xdp_prog */
4214 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4216 if (was_opened && reset)
4217 err = mlx5e_open_locked(netdev);
4219 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4222 /* exchanging programs w/o reset, we update ref counts on behalf
4223 * of the channels RQs here.
4225 for (i = 0; i < priv->channels.num; i++) {
4226 struct mlx5e_channel *c = priv->channels.c[i];
4228 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4229 napi_synchronize(&c->napi);
4230 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4232 old_prog = xchg(&c->rq.xdp_prog, prog);
4234 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4235 /* napi_schedule in case we have missed anything */
4236 napi_schedule(&c->napi);
4239 bpf_prog_put(old_prog);
4243 mutex_unlock(&priv->state_lock);
4247 static u32 mlx5e_xdp_query(struct net_device *dev)
4249 struct mlx5e_priv *priv = netdev_priv(dev);
4250 const struct bpf_prog *xdp_prog;
4253 mutex_lock(&priv->state_lock);
4254 xdp_prog = priv->channels.params.xdp_prog;
4256 prog_id = xdp_prog->aux->id;
4257 mutex_unlock(&priv->state_lock);
4262 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4264 switch (xdp->command) {
4265 case XDP_SETUP_PROG:
4266 return mlx5e_xdp_set(dev, xdp->prog);
4267 case XDP_QUERY_PROG:
4268 xdp->prog_id = mlx5e_xdp_query(dev);
4275 #ifdef CONFIG_MLX5_ESWITCH
4276 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4277 struct net_device *dev, u32 filter_mask,
4280 struct mlx5e_priv *priv = netdev_priv(dev);
4281 struct mlx5_core_dev *mdev = priv->mdev;
4285 err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4288 mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4289 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4291 0, 0, nlflags, filter_mask, NULL);
4294 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4295 u16 flags, struct netlink_ext_ack *extack)
4297 struct mlx5e_priv *priv = netdev_priv(dev);
4298 struct mlx5_core_dev *mdev = priv->mdev;
4299 struct nlattr *attr, *br_spec;
4300 u16 mode = BRIDGE_MODE_UNDEF;
4304 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4308 nla_for_each_nested(attr, br_spec, rem) {
4309 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4312 if (nla_len(attr) < sizeof(mode))
4315 mode = nla_get_u16(attr);
4316 if (mode > BRIDGE_MODE_VEPA)
4322 if (mode == BRIDGE_MODE_UNDEF)
4325 setting = (mode == BRIDGE_MODE_VEPA) ? 1 : 0;
4326 return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4330 const struct net_device_ops mlx5e_netdev_ops = {
4331 .ndo_open = mlx5e_open,
4332 .ndo_stop = mlx5e_close,
4333 .ndo_start_xmit = mlx5e_xmit,
4334 .ndo_setup_tc = mlx5e_setup_tc,
4335 .ndo_select_queue = mlx5e_select_queue,
4336 .ndo_get_stats64 = mlx5e_get_stats,
4337 .ndo_set_rx_mode = mlx5e_set_rx_mode,
4338 .ndo_set_mac_address = mlx5e_set_mac,
4339 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
4340 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
4341 .ndo_set_features = mlx5e_set_features,
4342 .ndo_fix_features = mlx5e_fix_features,
4343 .ndo_change_mtu = mlx5e_change_nic_mtu,
4344 .ndo_do_ioctl = mlx5e_ioctl,
4345 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
4346 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
4347 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
4348 .ndo_features_check = mlx5e_features_check,
4349 .ndo_tx_timeout = mlx5e_tx_timeout,
4350 .ndo_bpf = mlx5e_xdp,
4351 .ndo_xdp_xmit = mlx5e_xdp_xmit,
4352 #ifdef CONFIG_MLX5_EN_ARFS
4353 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
4355 #ifdef CONFIG_MLX5_ESWITCH
4356 .ndo_bridge_setlink = mlx5e_bridge_setlink,
4357 .ndo_bridge_getlink = mlx5e_bridge_getlink,
4359 /* SRIOV E-Switch NDOs */
4360 .ndo_set_vf_mac = mlx5e_set_vf_mac,
4361 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
4362 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
4363 .ndo_set_vf_trust = mlx5e_set_vf_trust,
4364 .ndo_set_vf_rate = mlx5e_set_vf_rate,
4365 .ndo_get_vf_config = mlx5e_get_vf_config,
4366 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
4367 .ndo_get_vf_stats = mlx5e_get_vf_stats,
4371 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4373 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4375 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4376 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4377 !MLX5_CAP_ETH(mdev, csum_cap) ||
4378 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4379 !MLX5_CAP_ETH(mdev, vlan_cap) ||
4380 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4381 MLX5_CAP_FLOWTABLE(mdev,
4382 flow_table_properties_nic_receive.max_ft_level)
4384 mlx5_core_warn(mdev,
4385 "Not creating net device, some required device capabilities are missing\n");
4388 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4389 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4390 if (!MLX5_CAP_GEN(mdev, cq_moderation))
4391 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4396 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4401 for (i = 0; i < len; i++)
4402 indirection_rqt[i] = i % num_channels;
4405 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4410 mlx5e_port_max_linkspeed(mdev, &link_speed);
4411 pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4412 mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4413 link_speed, pci_bw);
4415 #define MLX5E_SLOW_PCI_RATIO (2)
4417 return link_speed && pci_bw &&
4418 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4421 static struct net_dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4423 struct net_dim_cq_moder moder;
4425 moder.cq_period_mode = cq_period_mode;
4426 moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4427 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4428 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4429 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4434 static struct net_dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4436 struct net_dim_cq_moder moder;
4438 moder.cq_period_mode = cq_period_mode;
4439 moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4440 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4441 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4442 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4447 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4449 return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4450 NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4451 NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4454 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4456 if (params->tx_dim_enabled) {
4457 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4459 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4461 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4464 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4465 params->tx_cq_moderation.cq_period_mode ==
4466 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4469 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4471 if (params->rx_dim_enabled) {
4472 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4474 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4476 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4479 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4480 params->rx_cq_moderation.cq_period_mode ==
4481 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4484 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4488 /* The supported periods are organized in ascending order */
4489 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4490 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4493 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4496 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
4497 struct mlx5e_params *params)
4499 /* Prefer Striding RQ, unless any of the following holds:
4500 * - Striding RQ configuration is not possible/supported.
4501 * - Slow PCI heuristic.
4502 * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4504 if (!slow_pci_heuristic(mdev) &&
4505 mlx5e_striding_rq_possible(mdev, params) &&
4506 (mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ||
4507 !mlx5e_rx_is_linear_skb(params)))
4508 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4509 mlx5e_set_rq_type(mdev, params);
4510 mlx5e_init_rq_type_params(mdev, params);
4513 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
4516 enum mlx5e_traffic_types tt;
4518 rss_params->hfunc = ETH_RSS_HASH_TOP;
4519 netdev_rss_key_fill(rss_params->toeplitz_hash_key,
4520 sizeof(rss_params->toeplitz_hash_key));
4521 mlx5e_build_default_indir_rqt(rss_params->indirection_rqt,
4522 MLX5E_INDIR_RQT_SIZE, num_channels);
4523 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
4524 rss_params->rx_hash_fields[tt] =
4525 tirc_default_config[tt].rx_hash_fields;
4528 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4529 struct mlx5e_rss_params *rss_params,
4530 struct mlx5e_params *params,
4531 u16 max_channels, u16 mtu)
4533 u8 rx_cq_period_mode;
4535 params->sw_mtu = mtu;
4536 params->hard_mtu = MLX5E_ETH_HARD_MTU;
4537 params->num_channels = max_channels;
4541 params->log_sq_size = is_kdump_kernel() ?
4542 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4543 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4546 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE,
4547 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
4549 /* set CQE compression */
4550 params->rx_cqe_compress_def = false;
4551 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4552 MLX5_CAP_GEN(mdev, vport_group_manager))
4553 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4555 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4556 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4559 mlx5e_build_rq_params(mdev, params);
4563 /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4564 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
4565 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
4566 params->lro_en = !slow_pci_heuristic(mdev);
4567 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4569 /* CQ moderation params */
4570 rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4571 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4572 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4573 params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4574 params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4575 mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4576 mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4579 params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
4582 mlx5e_build_rss_params(rss_params, params->num_channels);
4583 params->tunneled_offload_en =
4584 mlx5e_tunnel_inner_ft_supported(mdev);
4587 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4589 struct mlx5e_priv *priv = netdev_priv(netdev);
4591 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
4592 if (is_zero_ether_addr(netdev->dev_addr) &&
4593 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4594 eth_hw_addr_random(netdev);
4595 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4599 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4601 struct mlx5e_priv *priv = netdev_priv(netdev);
4602 struct mlx5_core_dev *mdev = priv->mdev;
4606 SET_NETDEV_DEV(netdev, mdev->device);
4608 netdev->netdev_ops = &mlx5e_netdev_ops;
4610 #ifdef CONFIG_MLX5_CORE_EN_DCB
4611 if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4612 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4615 netdev->watchdog_timeo = 15 * HZ;
4617 netdev->ethtool_ops = &mlx5e_ethtool_ops;
4619 netdev->vlan_features |= NETIF_F_SG;
4620 netdev->vlan_features |= NETIF_F_IP_CSUM;
4621 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
4622 netdev->vlan_features |= NETIF_F_GRO;
4623 netdev->vlan_features |= NETIF_F_TSO;
4624 netdev->vlan_features |= NETIF_F_TSO6;
4625 netdev->vlan_features |= NETIF_F_RXCSUM;
4626 netdev->vlan_features |= NETIF_F_RXHASH;
4628 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_TX;
4629 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_RX;
4631 if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4632 mlx5e_check_fragmented_striding_rq_cap(mdev))
4633 netdev->vlan_features |= NETIF_F_LRO;
4635 netdev->hw_features = netdev->vlan_features;
4636 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
4637 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4638 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4639 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
4641 if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev) ||
4642 MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4643 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
4644 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
4645 netdev->hw_enc_features |= NETIF_F_TSO;
4646 netdev->hw_enc_features |= NETIF_F_TSO6;
4647 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4650 if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4651 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
4652 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4653 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4654 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4655 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4658 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4659 netdev->hw_features |= NETIF_F_GSO_GRE |
4660 NETIF_F_GSO_GRE_CSUM;
4661 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4662 NETIF_F_GSO_GRE_CSUM;
4663 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4664 NETIF_F_GSO_GRE_CSUM;
4667 netdev->hw_features |= NETIF_F_GSO_PARTIAL;
4668 netdev->gso_partial_features |= NETIF_F_GSO_UDP_L4;
4669 netdev->hw_features |= NETIF_F_GSO_UDP_L4;
4670 netdev->features |= NETIF_F_GSO_UDP_L4;
4672 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4675 netdev->hw_features |= NETIF_F_RXALL;
4677 if (MLX5_CAP_ETH(mdev, scatter_fcs))
4678 netdev->hw_features |= NETIF_F_RXFCS;
4680 netdev->features = netdev->hw_features;
4681 if (!priv->channels.params.lro_en)
4682 netdev->features &= ~NETIF_F_LRO;
4685 netdev->features &= ~NETIF_F_RXALL;
4687 if (!priv->channels.params.scatter_fcs_en)
4688 netdev->features &= ~NETIF_F_RXFCS;
4690 /* prefere CQE compression over rxhash */
4691 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4692 netdev->features &= ~NETIF_F_RXHASH;
4694 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4695 if (FT_CAP(flow_modify_en) &&
4696 FT_CAP(modify_root) &&
4697 FT_CAP(identified_miss_table_mode) &&
4698 FT_CAP(flow_table_modify)) {
4699 #ifdef CONFIG_MLX5_ESWITCH
4700 netdev->hw_features |= NETIF_F_HW_TC;
4702 #ifdef CONFIG_MLX5_EN_ARFS
4703 netdev->hw_features |= NETIF_F_NTUPLE;
4707 netdev->features |= NETIF_F_HIGHDMA;
4708 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
4710 netdev->priv_flags |= IFF_UNICAST_FLT;
4712 mlx5e_set_netdev_dev_addr(netdev);
4713 mlx5e_ipsec_build_netdev(priv);
4714 mlx5e_tls_build_netdev(priv);
4717 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4719 struct mlx5_core_dev *mdev = priv->mdev;
4722 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4724 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4725 priv->q_counter = 0;
4728 err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4730 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4731 priv->drop_rq_q_counter = 0;
4735 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4737 if (priv->q_counter)
4738 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4740 if (priv->drop_rq_q_counter)
4741 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
4744 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
4745 struct net_device *netdev,
4746 const struct mlx5e_profile *profile,
4749 struct mlx5e_priv *priv = netdev_priv(netdev);
4750 struct mlx5e_rss_params *rss = &priv->rss_params;
4753 err = mlx5e_netdev_init(netdev, priv, mdev, profile, ppriv);
4757 mlx5e_build_nic_params(mdev, rss, &priv->channels.params,
4758 mlx5e_get_netdev_max_channels(netdev),
4761 mlx5e_timestamp_init(priv);
4763 err = mlx5e_ipsec_init(priv);
4765 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4766 err = mlx5e_tls_init(priv);
4768 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4769 mlx5e_build_nic_netdev(netdev);
4770 mlx5e_build_tc2txq_maps(priv);
4775 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4777 mlx5e_tls_cleanup(priv);
4778 mlx5e_ipsec_cleanup(priv);
4779 mlx5e_netdev_cleanup(priv->netdev, priv);
4782 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4784 struct mlx5_core_dev *mdev = priv->mdev;
4787 mlx5e_create_q_counters(priv);
4789 err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4791 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4792 goto err_destroy_q_counters;
4795 err = mlx5e_create_indirect_rqt(priv);
4797 goto err_close_drop_rq;
4799 err = mlx5e_create_direct_rqts(priv);
4801 goto err_destroy_indirect_rqts;
4803 err = mlx5e_create_indirect_tirs(priv, true);
4805 goto err_destroy_direct_rqts;
4807 err = mlx5e_create_direct_tirs(priv);
4809 goto err_destroy_indirect_tirs;
4811 err = mlx5e_create_flow_steering(priv);
4813 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4814 goto err_destroy_direct_tirs;
4817 err = mlx5e_tc_nic_init(priv);
4819 goto err_destroy_flow_steering;
4823 err_destroy_flow_steering:
4824 mlx5e_destroy_flow_steering(priv);
4825 err_destroy_direct_tirs:
4826 mlx5e_destroy_direct_tirs(priv);
4827 err_destroy_indirect_tirs:
4828 mlx5e_destroy_indirect_tirs(priv, true);
4829 err_destroy_direct_rqts:
4830 mlx5e_destroy_direct_rqts(priv);
4831 err_destroy_indirect_rqts:
4832 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4834 mlx5e_close_drop_rq(&priv->drop_rq);
4835 err_destroy_q_counters:
4836 mlx5e_destroy_q_counters(priv);
4840 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4842 mlx5e_tc_nic_cleanup(priv);
4843 mlx5e_destroy_flow_steering(priv);
4844 mlx5e_destroy_direct_tirs(priv);
4845 mlx5e_destroy_indirect_tirs(priv, true);
4846 mlx5e_destroy_direct_rqts(priv);
4847 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4848 mlx5e_close_drop_rq(&priv->drop_rq);
4849 mlx5e_destroy_q_counters(priv);
4852 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4856 err = mlx5e_create_tises(priv);
4858 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4862 #ifdef CONFIG_MLX5_CORE_EN_DCB
4863 mlx5e_dcbnl_initialize(priv);
4865 mlx5e_tx_reporter_create(priv);
4869 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4871 struct net_device *netdev = priv->netdev;
4872 struct mlx5_core_dev *mdev = priv->mdev;
4874 mlx5e_init_l2_addr(priv);
4876 /* Marking the link as currently not needed by the Driver */
4877 if (!netif_running(netdev))
4878 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4880 mlx5e_set_netdev_mtu_boundaries(priv);
4881 mlx5e_set_dev_port_mtu(priv);
4883 mlx5_lag_add(mdev, netdev);
4885 mlx5e_enable_async_events(priv);
4886 if (mlx5e_monitor_counter_supported(priv))
4887 mlx5e_monitor_counter_init(priv);
4889 if (netdev->reg_state != NETREG_REGISTERED)
4891 #ifdef CONFIG_MLX5_CORE_EN_DCB
4892 mlx5e_dcbnl_init_app(priv);
4895 queue_work(priv->wq, &priv->set_rx_mode_work);
4898 if (netif_running(netdev))
4900 netif_device_attach(netdev);
4904 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4906 struct mlx5_core_dev *mdev = priv->mdev;
4908 #ifdef CONFIG_MLX5_CORE_EN_DCB
4909 if (priv->netdev->reg_state == NETREG_REGISTERED)
4910 mlx5e_dcbnl_delete_app(priv);
4914 if (netif_running(priv->netdev))
4915 mlx5e_close(priv->netdev);
4916 netif_device_detach(priv->netdev);
4919 queue_work(priv->wq, &priv->set_rx_mode_work);
4921 if (mlx5e_monitor_counter_supported(priv))
4922 mlx5e_monitor_counter_cleanup(priv);
4924 mlx5e_disable_async_events(priv);
4925 mlx5_lag_remove(mdev);
4928 static const struct mlx5e_profile mlx5e_nic_profile = {
4929 .init = mlx5e_nic_init,
4930 .cleanup = mlx5e_nic_cleanup,
4931 .init_rx = mlx5e_init_nic_rx,
4932 .cleanup_rx = mlx5e_cleanup_nic_rx,
4933 .init_tx = mlx5e_init_nic_tx,
4934 .cleanup_tx = mlx5e_cleanup_nic_tx,
4935 .enable = mlx5e_nic_enable,
4936 .disable = mlx5e_nic_disable,
4937 .update_stats = mlx5e_update_ndo_stats,
4938 .update_carrier = mlx5e_update_carrier,
4939 .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe,
4940 .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
4941 .max_tc = MLX5E_MAX_NUM_TC,
4944 /* mlx5e generic netdev management API (move to en_common.c) */
4946 /* mlx5e_netdev_init/cleanup must be called from profile->init/cleanup callbacks */
4947 int mlx5e_netdev_init(struct net_device *netdev,
4948 struct mlx5e_priv *priv,
4949 struct mlx5_core_dev *mdev,
4950 const struct mlx5e_profile *profile,
4955 priv->netdev = netdev;
4956 priv->profile = profile;
4957 priv->ppriv = ppriv;
4958 priv->msglevel = MLX5E_MSG_LEVEL;
4959 priv->max_opened_tc = 1;
4961 mutex_init(&priv->state_lock);
4962 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4963 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
4964 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
4965 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
4967 priv->wq = create_singlethread_workqueue("mlx5e");
4972 netif_carrier_off(netdev);
4974 #ifdef CONFIG_MLX5_EN_ARFS
4975 netdev->rx_cpu_rmap = mlx5_eq_table_get_rmap(mdev);
4981 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv)
4983 destroy_workqueue(priv->wq);
4986 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4987 const struct mlx5e_profile *profile,
4991 struct net_device *netdev;
4994 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
4995 nch * profile->max_tc,
4998 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5002 err = profile->init(mdev, netdev, profile, ppriv);
5004 mlx5_core_err(mdev, "failed to init mlx5e profile %d\n", err);
5005 goto err_free_netdev;
5011 free_netdev(netdev);
5016 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5018 const struct mlx5e_profile *profile;
5022 profile = priv->profile;
5023 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5025 /* max number of channels may have changed */
5026 max_nch = mlx5e_get_max_num_channels(priv->mdev);
5027 if (priv->channels.params.num_channels > max_nch) {
5028 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5029 priv->channels.params.num_channels = max_nch;
5030 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
5031 MLX5E_INDIR_RQT_SIZE, max_nch);
5034 err = profile->init_tx(priv);
5038 err = profile->init_rx(priv);
5040 goto err_cleanup_tx;
5042 if (profile->enable)
5043 profile->enable(priv);
5048 profile->cleanup_tx(priv);
5054 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5056 const struct mlx5e_profile *profile = priv->profile;
5058 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5060 if (profile->disable)
5061 profile->disable(priv);
5062 flush_workqueue(priv->wq);
5064 profile->cleanup_rx(priv);
5065 profile->cleanup_tx(priv);
5066 cancel_work_sync(&priv->update_stats_work);
5069 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5071 const struct mlx5e_profile *profile = priv->profile;
5072 struct net_device *netdev = priv->netdev;
5074 if (profile->cleanup)
5075 profile->cleanup(priv);
5076 free_netdev(netdev);
5079 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
5080 * hardware contexts and to connect it to the current netdev.
5082 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
5084 struct mlx5e_priv *priv = vpriv;
5085 struct net_device *netdev = priv->netdev;
5088 if (netif_device_present(netdev))
5091 err = mlx5e_create_mdev_resources(mdev);
5095 err = mlx5e_attach_netdev(priv);
5097 mlx5e_destroy_mdev_resources(mdev);
5104 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
5106 struct mlx5e_priv *priv = vpriv;
5107 struct net_device *netdev = priv->netdev;
5109 #ifdef CONFIG_MLX5_ESWITCH
5110 if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev)
5114 if (!netif_device_present(netdev))
5117 mlx5e_detach_netdev(priv);
5118 mlx5e_destroy_mdev_resources(mdev);
5121 static void *mlx5e_add(struct mlx5_core_dev *mdev)
5123 struct net_device *netdev;
5128 err = mlx5e_check_required_hca_cap(mdev);
5132 #ifdef CONFIG_MLX5_ESWITCH
5133 if (MLX5_ESWITCH_MANAGER(mdev) &&
5134 mlx5_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
5135 mlx5e_rep_register_vport_reps(mdev);
5140 nch = mlx5e_get_max_num_channels(mdev);
5141 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, nch, NULL);
5143 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5147 priv = netdev_priv(netdev);
5149 err = mlx5e_attach(mdev, priv);
5151 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
5152 goto err_destroy_netdev;
5155 err = register_netdev(netdev);
5157 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5161 #ifdef CONFIG_MLX5_CORE_EN_DCB
5162 mlx5e_dcbnl_init_app(priv);
5167 mlx5e_detach(mdev, priv);
5169 mlx5e_destroy_netdev(priv);
5173 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5175 struct mlx5e_priv *priv;
5177 #ifdef CONFIG_MLX5_ESWITCH
5178 if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev) {
5179 mlx5e_rep_unregister_vport_reps(mdev);
5184 #ifdef CONFIG_MLX5_CORE_EN_DCB
5185 mlx5e_dcbnl_delete_app(priv);
5187 unregister_netdev(priv->netdev);
5188 mlx5e_detach(mdev, vpriv);
5189 mlx5e_destroy_netdev(priv);
5192 static struct mlx5_interface mlx5e_interface = {
5194 .remove = mlx5e_remove,
5195 .attach = mlx5e_attach,
5196 .detach = mlx5e_detach,
5197 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
5200 void mlx5e_init(void)
5202 mlx5e_ipsec_build_inverse_table();
5203 mlx5e_build_ptys2ethtool_map();
5204 mlx5_register_interface(&mlx5e_interface);
5207 void mlx5e_cleanup(void)
5209 mlx5_unregister_interface(&mlx5e_interface);