2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
43 MLX5_EN_QP_FLUSH_TIMEOUT_MS = 5000,
44 MLX5_EN_QP_FLUSH_MSLEEP_QUANT = 20,
45 MLX5_EN_QP_FLUSH_MAX_ITER = MLX5_EN_QP_FLUSH_TIMEOUT_MS /
46 MLX5_EN_QP_FLUSH_MSLEEP_QUANT,
49 struct mlx5e_rq_param {
50 u32 rqc[MLX5_ST_SZ_DW(rqc)];
51 struct mlx5_wq_param wq;
54 struct mlx5e_sq_param {
55 u32 sqc[MLX5_ST_SZ_DW(sqc)];
56 struct mlx5_wq_param wq;
61 struct mlx5e_cq_param {
62 u32 cqc[MLX5_ST_SZ_DW(cqc)];
63 struct mlx5_wq_param wq;
67 struct mlx5e_channel_param {
68 struct mlx5e_rq_param rq;
69 struct mlx5e_sq_param sq;
70 struct mlx5e_sq_param icosq;
71 struct mlx5e_cq_param rx_cq;
72 struct mlx5e_cq_param tx_cq;
73 struct mlx5e_cq_param icosq_cq;
76 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
78 struct mlx5_core_dev *mdev = priv->mdev;
81 port_state = mlx5_query_vport_state(mdev,
82 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
84 if (port_state == VPORT_STATE_UP) {
85 netdev_info(priv->netdev, "Link up\n");
86 netif_carrier_on(priv->netdev);
88 netdev_info(priv->netdev, "Link down\n");
89 netif_carrier_off(priv->netdev);
93 static void mlx5e_update_carrier_work(struct work_struct *work)
95 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
98 mutex_lock(&priv->state_lock);
99 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
100 mlx5e_update_carrier(priv);
101 mutex_unlock(&priv->state_lock);
104 static void mlx5e_tx_timeout_work(struct work_struct *work)
106 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
111 mutex_lock(&priv->state_lock);
112 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
114 mlx5e_close_locked(priv->netdev);
115 err = mlx5e_open_locked(priv->netdev);
117 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
120 mutex_unlock(&priv->state_lock);
124 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
126 struct mlx5e_sw_stats *s = &priv->stats.sw;
127 struct mlx5e_rq_stats *rq_stats;
128 struct mlx5e_sq_stats *sq_stats;
129 u64 tx_offload_none = 0;
132 memset(s, 0, sizeof(*s));
133 for (i = 0; i < priv->params.num_channels; i++) {
134 rq_stats = &priv->channel[i]->rq.stats;
136 s->rx_packets += rq_stats->packets;
137 s->rx_bytes += rq_stats->bytes;
138 s->rx_lro_packets += rq_stats->lro_packets;
139 s->rx_lro_bytes += rq_stats->lro_bytes;
140 s->rx_csum_none += rq_stats->csum_none;
141 s->rx_csum_complete += rq_stats->csum_complete;
142 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
143 s->rx_wqe_err += rq_stats->wqe_err;
144 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
145 s->rx_mpwqe_frag += rq_stats->mpwqe_frag;
146 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
147 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
148 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
150 for (j = 0; j < priv->params.num_tc; j++) {
151 sq_stats = &priv->channel[i]->sq[j].stats;
153 s->tx_packets += sq_stats->packets;
154 s->tx_bytes += sq_stats->bytes;
155 s->tx_tso_packets += sq_stats->tso_packets;
156 s->tx_tso_bytes += sq_stats->tso_bytes;
157 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
158 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
159 s->tx_queue_stopped += sq_stats->stopped;
160 s->tx_queue_wake += sq_stats->wake;
161 s->tx_queue_dropped += sq_stats->dropped;
162 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
163 tx_offload_none += sq_stats->csum_none;
167 /* Update calculated offload counters */
168 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
169 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
171 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
172 priv->stats.pport.phy_counters,
173 counter_set.phys_layer_cntrs.link_down_events);
176 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
178 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
179 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
180 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
181 struct mlx5_core_dev *mdev = priv->mdev;
183 memset(in, 0, sizeof(in));
185 MLX5_SET(query_vport_counter_in, in, opcode,
186 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
187 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
188 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
190 memset(out, 0, outlen);
192 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
195 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
197 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
198 struct mlx5_core_dev *mdev = priv->mdev;
199 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
204 in = mlx5_vzalloc(sz);
208 MLX5_SET(ppcnt_reg, in, local_port, 1);
210 out = pstats->IEEE_802_3_counters;
211 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
212 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
214 out = pstats->RFC_2863_counters;
215 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
216 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
218 out = pstats->RFC_2819_counters;
219 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
220 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
222 out = pstats->phy_counters;
223 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
224 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
226 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
227 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
228 out = pstats->per_prio_counters[prio];
229 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
230 mlx5_core_access_reg(mdev, in, sz, out, sz,
231 MLX5_REG_PPCNT, 0, 0);
238 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
240 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
242 if (!priv->q_counter)
245 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
246 &qcnt->rx_out_of_buffer);
249 void mlx5e_update_stats(struct mlx5e_priv *priv)
251 mlx5e_update_q_counter(priv);
252 mlx5e_update_vport_counters(priv);
253 mlx5e_update_pport_counters(priv);
254 mlx5e_update_sw_counters(priv);
257 static void mlx5e_update_stats_work(struct work_struct *work)
259 struct delayed_work *dwork = to_delayed_work(work);
260 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
262 mutex_lock(&priv->state_lock);
263 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
264 mlx5e_update_stats(priv);
265 queue_delayed_work(priv->wq, dwork,
266 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
268 mutex_unlock(&priv->state_lock);
271 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
272 enum mlx5_dev_event event, unsigned long param)
274 struct mlx5e_priv *priv = vpriv;
276 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
280 case MLX5_DEV_EVENT_PORT_UP:
281 case MLX5_DEV_EVENT_PORT_DOWN:
282 queue_work(priv->wq, &priv->update_carrier_work);
290 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
292 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
295 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
297 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
298 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
301 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
302 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
304 static int mlx5e_create_rq(struct mlx5e_channel *c,
305 struct mlx5e_rq_param *param,
308 struct mlx5e_priv *priv = c->priv;
309 struct mlx5_core_dev *mdev = priv->mdev;
310 void *rqc = param->rqc;
311 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
317 param->wq.db_numa_node = cpu_to_node(c->cpu);
319 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
324 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
326 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
328 switch (priv->params.rq_wq_type) {
329 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
330 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
331 GFP_KERNEL, cpu_to_node(c->cpu));
334 goto err_rq_wq_destroy;
336 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
337 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
338 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
340 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
341 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
342 rq->wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
343 byte_count = rq->wqe_sz;
345 default: /* MLX5_WQ_TYPE_LINKED_LIST */
346 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
347 cpu_to_node(c->cpu));
350 goto err_rq_wq_destroy;
352 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
353 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
354 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
356 rq->wqe_sz = (priv->params.lro_en) ?
357 priv->params.lro_wqe_sz :
358 MLX5E_SW2HW_MTU(priv->netdev->mtu);
359 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
360 byte_count = rq->wqe_sz;
361 byte_count |= MLX5_HW_START_PADDING;
364 for (i = 0; i < wq_sz; i++) {
365 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
367 wqe->data.byte_count = cpu_to_be32(byte_count);
370 rq->wq_type = priv->params.rq_wq_type;
372 rq->netdev = c->netdev;
373 rq->tstamp = &priv->tstamp;
377 rq->mkey_be = c->mkey_be;
378 rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
383 mlx5_wq_destroy(&rq->wq_ctrl);
388 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
390 switch (rq->wq_type) {
391 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
394 default: /* MLX5_WQ_TYPE_LINKED_LIST */
398 mlx5_wq_destroy(&rq->wq_ctrl);
401 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
403 struct mlx5e_priv *priv = rq->priv;
404 struct mlx5_core_dev *mdev = priv->mdev;
412 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
413 sizeof(u64) * rq->wq_ctrl.buf.npages;
414 in = mlx5_vzalloc(inlen);
418 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
419 wq = MLX5_ADDR_OF(rqc, rqc, wq);
421 memcpy(rqc, param->rqc, sizeof(param->rqc));
423 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
424 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
425 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
426 MLX5_SET(rqc, rqc, vsd, priv->params.vlan_strip_disable);
427 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
428 MLX5_ADAPTER_PAGE_SHIFT);
429 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
431 mlx5_fill_page_array(&rq->wq_ctrl.buf,
432 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
434 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
441 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
444 struct mlx5e_channel *c = rq->channel;
445 struct mlx5e_priv *priv = c->priv;
446 struct mlx5_core_dev *mdev = priv->mdev;
453 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
454 in = mlx5_vzalloc(inlen);
458 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
460 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
461 MLX5_SET(rqc, rqc, state, next_state);
463 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
470 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
472 struct mlx5e_channel *c = rq->channel;
473 struct mlx5e_priv *priv = c->priv;
474 struct mlx5_core_dev *mdev = priv->mdev;
481 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
482 in = mlx5_vzalloc(inlen);
486 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
488 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
489 MLX5_SET64(modify_rq_in, in, modify_bitmask, MLX5_RQ_BITMASK_VSD);
490 MLX5_SET(rqc, rqc, vsd, vsd);
491 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
493 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
500 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
502 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
505 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
507 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
508 struct mlx5e_channel *c = rq->channel;
509 struct mlx5e_priv *priv = c->priv;
510 struct mlx5_wq_ll *wq = &rq->wq;
512 while (time_before(jiffies, exp_time)) {
513 if (wq->cur_sz >= priv->params.min_rx_wqes)
522 static int mlx5e_open_rq(struct mlx5e_channel *c,
523 struct mlx5e_rq_param *param,
526 struct mlx5e_sq *sq = &c->icosq;
527 u16 pi = sq->pc & sq->wq.sz_m1;
530 err = mlx5e_create_rq(c, param, rq);
534 err = mlx5e_enable_rq(rq, param);
538 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
542 set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
544 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_NOP;
545 sq->ico_wqe_info[pi].num_wqebbs = 1;
546 mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
551 mlx5e_disable_rq(rq);
553 mlx5e_destroy_rq(rq);
558 static void mlx5e_close_rq(struct mlx5e_rq *rq)
563 clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
564 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
566 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
567 while (!mlx5_wq_ll_is_empty(&rq->wq) && !err &&
568 tout++ < MLX5_EN_QP_FLUSH_MAX_ITER)
569 msleep(MLX5_EN_QP_FLUSH_MSLEEP_QUANT);
571 if (err || tout == MLX5_EN_QP_FLUSH_MAX_ITER)
572 set_bit(MLX5E_RQ_STATE_FLUSH_TIMEOUT, &rq->state);
574 /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
575 napi_synchronize(&rq->channel->napi);
577 mlx5e_disable_rq(rq);
578 mlx5e_free_rx_descs(rq);
579 mlx5e_destroy_rq(rq);
582 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
589 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
591 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
592 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
594 sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
595 sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
597 sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
600 if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
601 mlx5e_free_sq_db(sq);
605 sq->dma_fifo_mask = df_sz - 1;
610 static int mlx5e_create_sq(struct mlx5e_channel *c,
612 struct mlx5e_sq_param *param,
615 struct mlx5e_priv *priv = c->priv;
616 struct mlx5_core_dev *mdev = priv->mdev;
618 void *sqc = param->sqc;
619 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
622 err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
626 param->wq.db_numa_node = cpu_to_node(c->cpu);
628 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq,
631 goto err_unmap_free_uar;
633 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
634 if (sq->uar.bf_map) {
635 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
636 sq->uar_map = sq->uar.bf_map;
638 sq->uar_map = sq->uar.map;
640 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
641 sq->max_inline = param->max_inline;
643 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
645 goto err_sq_wq_destroy;
648 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
650 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
653 cpu_to_node(c->cpu));
654 if (!sq->ico_wqe_info) {
661 txq_ix = c->ix + tc * priv->params.num_channels;
662 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
663 priv->txq_to_sq_map[txq_ix] = sq;
667 sq->tstamp = &priv->tstamp;
668 sq->mkey_be = c->mkey_be;
671 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
672 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
677 mlx5e_free_sq_db(sq);
680 mlx5_wq_destroy(&sq->wq_ctrl);
683 mlx5_unmap_free_uar(mdev, &sq->uar);
688 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
690 struct mlx5e_channel *c = sq->channel;
691 struct mlx5e_priv *priv = c->priv;
693 kfree(sq->ico_wqe_info);
694 mlx5e_free_sq_db(sq);
695 mlx5_wq_destroy(&sq->wq_ctrl);
696 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
699 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
701 struct mlx5e_channel *c = sq->channel;
702 struct mlx5e_priv *priv = c->priv;
703 struct mlx5_core_dev *mdev = priv->mdev;
711 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
712 sizeof(u64) * sq->wq_ctrl.buf.npages;
713 in = mlx5_vzalloc(inlen);
717 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
718 wq = MLX5_ADDR_OF(sqc, sqc, wq);
720 memcpy(sqc, param->sqc, sizeof(param->sqc));
722 MLX5_SET(sqc, sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
723 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
724 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
725 MLX5_SET(sqc, sqc, tis_lst_sz, param->icosq ? 0 : 1);
726 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
728 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
729 MLX5_SET(wq, wq, uar_page, sq->uar.index);
730 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
731 MLX5_ADAPTER_PAGE_SHIFT);
732 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
734 mlx5_fill_page_array(&sq->wq_ctrl.buf,
735 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
737 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
744 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
746 struct mlx5e_channel *c = sq->channel;
747 struct mlx5e_priv *priv = c->priv;
748 struct mlx5_core_dev *mdev = priv->mdev;
755 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
756 in = mlx5_vzalloc(inlen);
760 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
762 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
763 MLX5_SET(sqc, sqc, state, next_state);
765 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
772 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
774 struct mlx5e_channel *c = sq->channel;
775 struct mlx5e_priv *priv = c->priv;
776 struct mlx5_core_dev *mdev = priv->mdev;
778 mlx5_core_destroy_sq(mdev, sq->sqn);
781 static int mlx5e_open_sq(struct mlx5e_channel *c,
783 struct mlx5e_sq_param *param,
788 err = mlx5e_create_sq(c, tc, param, sq);
792 err = mlx5e_enable_sq(sq, param);
796 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
801 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
802 netdev_tx_reset_queue(sq->txq);
803 netif_tx_start_queue(sq->txq);
809 mlx5e_disable_sq(sq);
811 mlx5e_destroy_sq(sq);
816 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
818 __netif_tx_lock_bh(txq);
819 netif_tx_stop_queue(txq);
820 __netif_tx_unlock_bh(txq);
823 static void mlx5e_close_sq(struct mlx5e_sq *sq)
829 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
830 /* prevent netif_tx_wake_queue */
831 napi_synchronize(&sq->channel->napi);
832 netif_tx_disable_queue(sq->txq);
834 /* ensure hw is notified of all pending wqes */
835 if (mlx5e_sq_has_room_for(sq, 1))
836 mlx5e_send_nop(sq, true);
838 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
841 set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
844 /* wait till sq is empty, unless a TX timeout occurred on this SQ */
845 while (sq->cc != sq->pc &&
846 !test_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state)) {
847 msleep(MLX5_EN_QP_FLUSH_MSLEEP_QUANT);
848 if (tout++ > MLX5_EN_QP_FLUSH_MAX_ITER)
849 set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
852 /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
853 napi_synchronize(&sq->channel->napi);
855 mlx5e_free_tx_descs(sq);
856 mlx5e_disable_sq(sq);
857 mlx5e_destroy_sq(sq);
860 static int mlx5e_create_cq(struct mlx5e_channel *c,
861 struct mlx5e_cq_param *param,
864 struct mlx5e_priv *priv = c->priv;
865 struct mlx5_core_dev *mdev = priv->mdev;
866 struct mlx5_core_cq *mcq = &cq->mcq;
872 param->wq.buf_numa_node = cpu_to_node(c->cpu);
873 param->wq.db_numa_node = cpu_to_node(c->cpu);
874 param->eq_ix = c->ix;
876 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
881 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
886 mcq->set_ci_db = cq->wq_ctrl.db.db;
887 mcq->arm_db = cq->wq_ctrl.db.db + 1;
890 mcq->vector = param->eq_ix;
891 mcq->comp = mlx5e_completion_event;
892 mcq->event = mlx5e_cq_error_event;
894 mcq->uar = &priv->cq_uar;
896 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
897 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
908 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
910 mlx5_wq_destroy(&cq->wq_ctrl);
913 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
915 struct mlx5e_priv *priv = cq->priv;
916 struct mlx5_core_dev *mdev = priv->mdev;
917 struct mlx5_core_cq *mcq = &cq->mcq;
922 unsigned int irqn_not_used;
926 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
927 sizeof(u64) * cq->wq_ctrl.buf.npages;
928 in = mlx5_vzalloc(inlen);
932 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
934 memcpy(cqc, param->cqc, sizeof(param->cqc));
936 mlx5_fill_page_array(&cq->wq_ctrl.buf,
937 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
939 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
941 MLX5_SET(cqc, cqc, c_eqn, eqn);
942 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
943 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
944 MLX5_ADAPTER_PAGE_SHIFT);
945 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
947 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
959 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
961 struct mlx5e_priv *priv = cq->priv;
962 struct mlx5_core_dev *mdev = priv->mdev;
964 mlx5_core_destroy_cq(mdev, &cq->mcq);
967 static int mlx5e_open_cq(struct mlx5e_channel *c,
968 struct mlx5e_cq_param *param,
970 u16 moderation_usecs,
971 u16 moderation_frames)
974 struct mlx5e_priv *priv = c->priv;
975 struct mlx5_core_dev *mdev = priv->mdev;
977 err = mlx5e_create_cq(c, param, cq);
981 err = mlx5e_enable_cq(cq, param);
985 if (MLX5_CAP_GEN(mdev, cq_moderation))
986 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
992 mlx5e_destroy_cq(cq);
997 static void mlx5e_close_cq(struct mlx5e_cq *cq)
999 mlx5e_disable_cq(cq);
1000 mlx5e_destroy_cq(cq);
1003 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1005 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1008 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1009 struct mlx5e_channel_param *cparam)
1011 struct mlx5e_priv *priv = c->priv;
1015 for (tc = 0; tc < c->num_tc; tc++) {
1016 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
1017 priv->params.tx_cq_moderation_usec,
1018 priv->params.tx_cq_moderation_pkts);
1020 goto err_close_tx_cqs;
1026 for (tc--; tc >= 0; tc--)
1027 mlx5e_close_cq(&c->sq[tc].cq);
1032 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1036 for (tc = 0; tc < c->num_tc; tc++)
1037 mlx5e_close_cq(&c->sq[tc].cq);
1040 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1041 struct mlx5e_channel_param *cparam)
1046 for (tc = 0; tc < c->num_tc; tc++) {
1047 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1055 for (tc--; tc >= 0; tc--)
1056 mlx5e_close_sq(&c->sq[tc]);
1061 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1065 for (tc = 0; tc < c->num_tc; tc++)
1066 mlx5e_close_sq(&c->sq[tc]);
1069 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1073 for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
1074 priv->channeltc_to_txq_map[ix][i] =
1075 ix + i * priv->params.num_channels;
1078 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1079 struct mlx5e_channel_param *cparam,
1080 struct mlx5e_channel **cp)
1082 struct net_device *netdev = priv->netdev;
1083 int cpu = mlx5e_get_cpu(priv, ix);
1084 struct mlx5e_channel *c;
1087 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1094 c->pdev = &priv->mdev->pdev->dev;
1095 c->netdev = priv->netdev;
1096 c->mkey_be = cpu_to_be32(priv->mkey.key);
1097 c->num_tc = priv->params.num_tc;
1099 mlx5e_build_channeltc_to_txq_map(priv, ix);
1101 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1103 err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, 0, 0);
1107 err = mlx5e_open_tx_cqs(c, cparam);
1109 goto err_close_icosq_cq;
1111 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1112 priv->params.rx_cq_moderation_usec,
1113 priv->params.rx_cq_moderation_pkts);
1115 goto err_close_tx_cqs;
1117 napi_enable(&c->napi);
1119 err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1121 goto err_disable_napi;
1123 err = mlx5e_open_sqs(c, cparam);
1125 goto err_close_icosq;
1127 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1131 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1140 mlx5e_close_sq(&c->icosq);
1143 napi_disable(&c->napi);
1144 mlx5e_close_cq(&c->rq.cq);
1147 mlx5e_close_tx_cqs(c);
1150 mlx5e_close_cq(&c->icosq.cq);
1153 netif_napi_del(&c->napi);
1154 napi_hash_del(&c->napi);
1160 static void mlx5e_close_channel(struct mlx5e_channel *c)
1162 mlx5e_close_rq(&c->rq);
1164 mlx5e_close_sq(&c->icosq);
1165 napi_disable(&c->napi);
1166 mlx5e_close_cq(&c->rq.cq);
1167 mlx5e_close_tx_cqs(c);
1168 mlx5e_close_cq(&c->icosq.cq);
1169 netif_napi_del(&c->napi);
1171 napi_hash_del(&c->napi);
1177 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1178 struct mlx5e_rq_param *param)
1180 void *rqc = param->rqc;
1181 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1183 switch (priv->params.rq_wq_type) {
1184 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1185 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1186 priv->params.mpwqe_log_num_strides - 9);
1187 MLX5_SET(wq, wq, log_wqe_stride_size,
1188 priv->params.mpwqe_log_stride_sz - 6);
1189 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1191 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1192 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1195 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1196 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1197 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1198 MLX5_SET(wq, wq, pd, priv->pdn);
1199 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1201 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1202 param->wq.linear = 1;
1205 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1207 void *rqc = param->rqc;
1208 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1210 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1211 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1214 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1215 struct mlx5e_sq_param *param)
1217 void *sqc = param->sqc;
1218 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1220 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1221 MLX5_SET(wq, wq, pd, priv->pdn);
1223 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1226 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1227 struct mlx5e_sq_param *param)
1229 void *sqc = param->sqc;
1230 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1232 mlx5e_build_sq_param_common(priv, param);
1233 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1235 param->max_inline = priv->params.tx_max_inline;
1238 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1239 struct mlx5e_cq_param *param)
1241 void *cqc = param->cqc;
1243 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1246 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1247 struct mlx5e_cq_param *param)
1249 void *cqc = param->cqc;
1252 switch (priv->params.rq_wq_type) {
1253 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1254 log_cq_size = priv->params.log_rq_size +
1255 priv->params.mpwqe_log_num_strides;
1257 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1258 log_cq_size = priv->params.log_rq_size;
1261 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1262 if (priv->params.rx_cqe_compress) {
1263 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1264 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1267 mlx5e_build_common_cq_param(priv, param);
1270 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1271 struct mlx5e_cq_param *param)
1273 void *cqc = param->cqc;
1275 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1277 mlx5e_build_common_cq_param(priv, param);
1280 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1281 struct mlx5e_cq_param *param,
1284 void *cqc = param->cqc;
1286 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1288 mlx5e_build_common_cq_param(priv, param);
1291 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1292 struct mlx5e_sq_param *param,
1295 void *sqc = param->sqc;
1296 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1298 mlx5e_build_sq_param_common(priv, param);
1300 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1301 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1303 param->icosq = true;
1306 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1308 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1310 mlx5e_build_rq_param(priv, &cparam->rq);
1311 mlx5e_build_sq_param(priv, &cparam->sq);
1312 mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1313 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1314 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1315 mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1318 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1320 struct mlx5e_channel_param *cparam;
1321 int nch = priv->params.num_channels;
1326 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1329 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1330 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1332 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1334 if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1335 goto err_free_txq_to_sq_map;
1337 mlx5e_build_channel_param(priv, cparam);
1339 for (i = 0; i < nch; i++) {
1340 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1342 goto err_close_channels;
1345 for (j = 0; j < nch; j++) {
1346 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1348 goto err_close_channels;
1351 /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1352 * polling for inactive tx queues.
1354 netif_tx_start_all_queues(priv->netdev);
1360 for (i--; i >= 0; i--)
1361 mlx5e_close_channel(priv->channel[i]);
1363 err_free_txq_to_sq_map:
1364 kfree(priv->txq_to_sq_map);
1365 kfree(priv->channel);
1371 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1375 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1376 * polling for inactive tx queues.
1378 netif_tx_stop_all_queues(priv->netdev);
1379 netif_tx_disable(priv->netdev);
1381 for (i = 0; i < priv->params.num_channels; i++)
1382 mlx5e_close_channel(priv->channel[i]);
1384 kfree(priv->txq_to_sq_map);
1385 kfree(priv->channel);
1388 static int mlx5e_rx_hash_fn(int hfunc)
1390 return (hfunc == ETH_RSS_HASH_TOP) ?
1391 MLX5_RX_HASH_FN_TOEPLITZ :
1392 MLX5_RX_HASH_FN_INVERTED_XOR8;
1395 static int mlx5e_bits_invert(unsigned long a, int size)
1400 for (i = 0; i < size; i++)
1401 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1406 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1410 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1414 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1415 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1417 ix = priv->params.indirection_rqt[ix];
1418 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1419 priv->channel[ix]->rq.rqn :
1421 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1425 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1428 u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1429 priv->channel[ix]->rq.rqn :
1432 MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1435 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, int ix, u32 *rqtn)
1437 struct mlx5_core_dev *mdev = priv->mdev;
1443 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1444 in = mlx5_vzalloc(inlen);
1448 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1450 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1451 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1453 if (sz > 1) /* RSS */
1454 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1456 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1458 err = mlx5_core_create_rqt(mdev, in, inlen, rqtn);
1464 static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, u32 rqtn)
1466 mlx5_core_destroy_rqt(priv->mdev, rqtn);
1469 static int mlx5e_create_rqts(struct mlx5e_priv *priv)
1471 int nch = mlx5e_get_max_num_channels(priv->mdev);
1477 rqtn = &priv->indir_rqtn;
1478 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqtn);
1483 for (ix = 0; ix < nch; ix++) {
1484 rqtn = &priv->direct_tir[ix].rqtn;
1485 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqtn);
1487 goto err_destroy_rqts;
1493 for (ix--; ix >= 0; ix--)
1494 mlx5e_destroy_rqt(priv, priv->direct_tir[ix].rqtn);
1496 mlx5e_destroy_rqt(priv, priv->indir_rqtn);
1501 static void mlx5e_destroy_rqts(struct mlx5e_priv *priv)
1503 int nch = mlx5e_get_max_num_channels(priv->mdev);
1506 for (i = 0; i < nch; i++)
1507 mlx5e_destroy_rqt(priv, priv->direct_tir[i].rqtn);
1509 mlx5e_destroy_rqt(priv, priv->indir_rqtn);
1512 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
1514 struct mlx5_core_dev *mdev = priv->mdev;
1520 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1521 in = mlx5_vzalloc(inlen);
1525 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1527 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1528 if (sz > 1) /* RSS */
1529 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1531 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1533 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1535 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
1542 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1547 rqtn = priv->indir_rqtn;
1548 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1549 for (ix = 0; ix < priv->params.num_channels; ix++) {
1550 rqtn = priv->direct_tir[ix].rqtn;
1551 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1555 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1557 if (!priv->params.lro_en)
1560 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1562 MLX5_SET(tirc, tirc, lro_enable_mask,
1563 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1564 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1565 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1566 (priv->params.lro_wqe_sz -
1567 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1568 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1569 MLX5_CAP_ETH(priv->mdev,
1570 lro_timer_supported_periods[2]));
1573 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1575 MLX5_SET(tirc, tirc, rx_hash_fn,
1576 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1577 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1578 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1579 rx_hash_toeplitz_key);
1580 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1581 rx_hash_toeplitz_key);
1583 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1584 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1588 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1590 struct mlx5_core_dev *mdev = priv->mdev;
1599 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1600 in = mlx5_vzalloc(inlen);
1604 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1605 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1607 mlx5e_build_tir_ctx_lro(tirc, priv);
1609 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1610 err = mlx5_core_modify_tir(mdev, priv->indir_tirn[tt], in,
1616 for (ix = 0; ix < mlx5e_get_max_num_channels(mdev); ix++) {
1617 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
1629 static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1636 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1637 in = mlx5_vzalloc(inlen);
1641 MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1643 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
1644 err = mlx5_core_modify_tir(priv->mdev, priv->indir_tirn[i], in,
1650 for (i = 0; i < priv->params.num_channels; i++) {
1651 err = mlx5_core_modify_tir(priv->mdev,
1652 priv->direct_tir[i].tirn, in,
1663 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
1665 struct mlx5_core_dev *mdev = priv->mdev;
1666 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
1669 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
1673 /* Update vport context MTU */
1674 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
1678 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
1680 struct mlx5_core_dev *mdev = priv->mdev;
1684 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
1685 if (err || !hw_mtu) /* fallback to port oper mtu */
1686 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1688 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
1691 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1693 struct mlx5e_priv *priv = netdev_priv(netdev);
1697 err = mlx5e_set_mtu(priv, netdev->mtu);
1701 mlx5e_query_mtu(priv, &mtu);
1702 if (mtu != netdev->mtu)
1703 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
1704 __func__, mtu, netdev->mtu);
1710 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1712 struct mlx5e_priv *priv = netdev_priv(netdev);
1713 int nch = priv->params.num_channels;
1714 int ntc = priv->params.num_tc;
1717 netdev_reset_tc(netdev);
1722 netdev_set_num_tc(netdev, ntc);
1724 /* Map netdev TCs to offset 0
1725 * We have our own UP to TXQ mapping for QoS
1727 for (tc = 0; tc < ntc; tc++)
1728 netdev_set_tc_queue(netdev, tc, nch, 0);
1731 int mlx5e_open_locked(struct net_device *netdev)
1733 struct mlx5e_priv *priv = netdev_priv(netdev);
1737 set_bit(MLX5E_STATE_OPENED, &priv->state);
1739 mlx5e_netdev_set_tcs(netdev);
1741 num_txqs = priv->params.num_channels * priv->params.num_tc;
1742 netif_set_real_num_tx_queues(netdev, num_txqs);
1743 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1745 err = mlx5e_set_dev_port_mtu(netdev);
1747 goto err_clear_state_opened_flag;
1749 err = mlx5e_open_channels(priv);
1751 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1753 goto err_clear_state_opened_flag;
1756 err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1758 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1760 goto err_close_channels;
1763 mlx5e_redirect_rqts(priv);
1764 mlx5e_update_carrier(priv);
1765 mlx5e_timestamp_init(priv);
1766 #ifdef CONFIG_RFS_ACCEL
1767 priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
1770 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
1775 mlx5e_close_channels(priv);
1776 err_clear_state_opened_flag:
1777 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1781 static int mlx5e_open(struct net_device *netdev)
1783 struct mlx5e_priv *priv = netdev_priv(netdev);
1786 mutex_lock(&priv->state_lock);
1787 err = mlx5e_open_locked(netdev);
1788 mutex_unlock(&priv->state_lock);
1793 int mlx5e_close_locked(struct net_device *netdev)
1795 struct mlx5e_priv *priv = netdev_priv(netdev);
1797 /* May already be CLOSED in case a previous configuration operation
1798 * (e.g RX/TX queue size change) that involves close&open failed.
1800 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1803 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1805 mlx5e_timestamp_cleanup(priv);
1806 netif_carrier_off(priv->netdev);
1807 mlx5e_redirect_rqts(priv);
1808 mlx5e_close_channels(priv);
1813 static int mlx5e_close(struct net_device *netdev)
1815 struct mlx5e_priv *priv = netdev_priv(netdev);
1818 mutex_lock(&priv->state_lock);
1819 err = mlx5e_close_locked(netdev);
1820 mutex_unlock(&priv->state_lock);
1825 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1826 struct mlx5e_rq *rq,
1827 struct mlx5e_rq_param *param)
1829 struct mlx5_core_dev *mdev = priv->mdev;
1830 void *rqc = param->rqc;
1831 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1834 param->wq.db_numa_node = param->wq.buf_numa_node;
1836 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
1846 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1847 struct mlx5e_cq *cq,
1848 struct mlx5e_cq_param *param)
1850 struct mlx5_core_dev *mdev = priv->mdev;
1851 struct mlx5_core_cq *mcq = &cq->mcq;
1856 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1861 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1864 mcq->set_ci_db = cq->wq_ctrl.db.db;
1865 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1866 *mcq->set_ci_db = 0;
1868 mcq->vector = param->eq_ix;
1869 mcq->comp = mlx5e_completion_event;
1870 mcq->event = mlx5e_cq_error_event;
1872 mcq->uar = &priv->cq_uar;
1879 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1881 struct mlx5e_cq_param cq_param;
1882 struct mlx5e_rq_param rq_param;
1883 struct mlx5e_rq *rq = &priv->drop_rq;
1884 struct mlx5e_cq *cq = &priv->drop_rq.cq;
1887 memset(&cq_param, 0, sizeof(cq_param));
1888 memset(&rq_param, 0, sizeof(rq_param));
1889 mlx5e_build_drop_rq_param(&rq_param);
1891 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1895 err = mlx5e_enable_cq(cq, &cq_param);
1897 goto err_destroy_cq;
1899 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1901 goto err_disable_cq;
1903 err = mlx5e_enable_rq(rq, &rq_param);
1905 goto err_destroy_rq;
1910 mlx5e_destroy_rq(&priv->drop_rq);
1913 mlx5e_disable_cq(&priv->drop_rq.cq);
1916 mlx5e_destroy_cq(&priv->drop_rq.cq);
1921 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1923 mlx5e_disable_rq(&priv->drop_rq);
1924 mlx5e_destroy_rq(&priv->drop_rq);
1925 mlx5e_disable_cq(&priv->drop_rq.cq);
1926 mlx5e_destroy_cq(&priv->drop_rq.cq);
1929 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1931 struct mlx5_core_dev *mdev = priv->mdev;
1932 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1933 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1935 memset(in, 0, sizeof(in));
1937 MLX5_SET(tisc, tisc, prio, tc << 1);
1938 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1940 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1943 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1945 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1948 static int mlx5e_create_tises(struct mlx5e_priv *priv)
1953 for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
1954 err = mlx5e_create_tis(priv, tc);
1956 goto err_close_tises;
1962 for (tc--; tc >= 0; tc--)
1963 mlx5e_destroy_tis(priv, tc);
1968 static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1972 for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
1973 mlx5e_destroy_tis(priv, tc);
1976 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
1977 enum mlx5e_traffic_types tt)
1979 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1981 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1983 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
1984 MLX5_HASH_FIELD_SEL_DST_IP)
1986 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
1987 MLX5_HASH_FIELD_SEL_DST_IP |\
1988 MLX5_HASH_FIELD_SEL_L4_SPORT |\
1989 MLX5_HASH_FIELD_SEL_L4_DPORT)
1991 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
1992 MLX5_HASH_FIELD_SEL_DST_IP |\
1993 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1995 mlx5e_build_tir_ctx_lro(tirc, priv);
1997 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1998 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqtn);
1999 mlx5e_build_tir_ctx_hash(tirc, priv);
2002 case MLX5E_TT_IPV4_TCP:
2003 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2004 MLX5_L3_PROT_TYPE_IPV4);
2005 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2006 MLX5_L4_PROT_TYPE_TCP);
2007 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2008 MLX5_HASH_IP_L4PORTS);
2011 case MLX5E_TT_IPV6_TCP:
2012 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2013 MLX5_L3_PROT_TYPE_IPV6);
2014 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2015 MLX5_L4_PROT_TYPE_TCP);
2016 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2017 MLX5_HASH_IP_L4PORTS);
2020 case MLX5E_TT_IPV4_UDP:
2021 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2022 MLX5_L3_PROT_TYPE_IPV4);
2023 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2024 MLX5_L4_PROT_TYPE_UDP);
2025 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2026 MLX5_HASH_IP_L4PORTS);
2029 case MLX5E_TT_IPV6_UDP:
2030 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2031 MLX5_L3_PROT_TYPE_IPV6);
2032 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2033 MLX5_L4_PROT_TYPE_UDP);
2034 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2035 MLX5_HASH_IP_L4PORTS);
2038 case MLX5E_TT_IPV4_IPSEC_AH:
2039 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2040 MLX5_L3_PROT_TYPE_IPV4);
2041 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2042 MLX5_HASH_IP_IPSEC_SPI);
2045 case MLX5E_TT_IPV6_IPSEC_AH:
2046 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2047 MLX5_L3_PROT_TYPE_IPV6);
2048 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2049 MLX5_HASH_IP_IPSEC_SPI);
2052 case MLX5E_TT_IPV4_IPSEC_ESP:
2053 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2054 MLX5_L3_PROT_TYPE_IPV4);
2055 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2056 MLX5_HASH_IP_IPSEC_SPI);
2059 case MLX5E_TT_IPV6_IPSEC_ESP:
2060 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2061 MLX5_L3_PROT_TYPE_IPV6);
2062 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2063 MLX5_HASH_IP_IPSEC_SPI);
2067 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2068 MLX5_L3_PROT_TYPE_IPV4);
2069 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2074 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2075 MLX5_L3_PROT_TYPE_IPV6);
2076 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2081 "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2085 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2088 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2090 mlx5e_build_tir_ctx_lro(tirc, priv);
2092 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2093 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2094 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2097 static int mlx5e_create_tirs(struct mlx5e_priv *priv)
2099 int nch = mlx5e_get_max_num_channels(priv->mdev);
2108 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2109 in = mlx5_vzalloc(inlen);
2114 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2115 memset(in, 0, inlen);
2116 tirn = &priv->indir_tirn[tt];
2117 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2118 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2119 err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn);
2121 goto err_destroy_tirs;
2125 for (ix = 0; ix < nch; ix++) {
2126 memset(in, 0, inlen);
2127 tirn = &priv->direct_tir[ix].tirn;
2128 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2129 mlx5e_build_direct_tir_ctx(priv, tirc,
2130 priv->direct_tir[ix].rqtn);
2131 err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn);
2133 goto err_destroy_ch_tirs;
2140 err_destroy_ch_tirs:
2141 for (ix--; ix >= 0; ix--)
2142 mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[ix].tirn);
2145 for (tt--; tt >= 0; tt--)
2146 mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[tt]);
2153 static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
2155 int nch = mlx5e_get_max_num_channels(priv->mdev);
2158 for (i = 0; i < nch; i++)
2159 mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[i].tirn);
2161 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2162 mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[i]);
2165 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2170 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2173 for (i = 0; i < priv->params.num_channels; i++) {
2174 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2182 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2184 struct mlx5e_priv *priv = netdev_priv(netdev);
2188 if (tc && tc != MLX5E_MAX_NUM_TC)
2191 mutex_lock(&priv->state_lock);
2193 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2195 mlx5e_close_locked(priv->netdev);
2197 priv->params.num_tc = tc ? tc : 1;
2200 err = mlx5e_open_locked(priv->netdev);
2202 mutex_unlock(&priv->state_lock);
2207 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2208 __be16 proto, struct tc_to_netdev *tc)
2210 struct mlx5e_priv *priv = netdev_priv(dev);
2212 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2216 case TC_SETUP_CLSFLOWER:
2217 switch (tc->cls_flower->command) {
2218 case TC_CLSFLOWER_REPLACE:
2219 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2220 case TC_CLSFLOWER_DESTROY:
2221 return mlx5e_delete_flower(priv, tc->cls_flower);
2222 case TC_CLSFLOWER_STATS:
2223 return mlx5e_stats_flower(priv, tc->cls_flower);
2230 if (tc->type != TC_SETUP_MQPRIO)
2233 return mlx5e_setup_tc(dev, tc->tc);
2236 static struct rtnl_link_stats64 *
2237 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2239 struct mlx5e_priv *priv = netdev_priv(dev);
2240 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2241 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2242 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2244 stats->rx_packets = sstats->rx_packets;
2245 stats->rx_bytes = sstats->rx_bytes;
2246 stats->tx_packets = sstats->tx_packets;
2247 stats->tx_bytes = sstats->tx_bytes;
2249 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2250 stats->tx_dropped = sstats->tx_queue_dropped;
2252 stats->rx_length_errors =
2253 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2254 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2255 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2256 stats->rx_crc_errors =
2257 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2258 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2259 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2260 stats->tx_carrier_errors =
2261 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2262 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2263 stats->rx_frame_errors;
2264 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2266 /* vport multicast also counts packets that are dropped due to steering
2267 * or rx out of buffer
2270 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2275 static void mlx5e_set_rx_mode(struct net_device *dev)
2277 struct mlx5e_priv *priv = netdev_priv(dev);
2279 queue_work(priv->wq, &priv->set_rx_mode_work);
2282 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2284 struct mlx5e_priv *priv = netdev_priv(netdev);
2285 struct sockaddr *saddr = addr;
2287 if (!is_valid_ether_addr(saddr->sa_data))
2288 return -EADDRNOTAVAIL;
2290 netif_addr_lock_bh(netdev);
2291 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2292 netif_addr_unlock_bh(netdev);
2294 queue_work(priv->wq, &priv->set_rx_mode_work);
2299 #define MLX5E_SET_FEATURE(netdev, feature, enable) \
2302 netdev->features |= feature; \
2304 netdev->features &= ~feature; \
2307 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2309 static int set_feature_lro(struct net_device *netdev, bool enable)
2311 struct mlx5e_priv *priv = netdev_priv(netdev);
2312 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2315 mutex_lock(&priv->state_lock);
2317 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2318 mlx5e_close_locked(priv->netdev);
2320 priv->params.lro_en = enable;
2321 err = mlx5e_modify_tirs_lro(priv);
2323 netdev_err(netdev, "lro modify failed, %d\n", err);
2324 priv->params.lro_en = !enable;
2327 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2328 mlx5e_open_locked(priv->netdev);
2330 mutex_unlock(&priv->state_lock);
2335 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2337 struct mlx5e_priv *priv = netdev_priv(netdev);
2340 mlx5e_enable_vlan_filter(priv);
2342 mlx5e_disable_vlan_filter(priv);
2347 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2349 struct mlx5e_priv *priv = netdev_priv(netdev);
2351 if (!enable && mlx5e_tc_num_filters(priv)) {
2353 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2360 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2362 struct mlx5e_priv *priv = netdev_priv(netdev);
2363 struct mlx5_core_dev *mdev = priv->mdev;
2365 return mlx5_set_port_fcs(mdev, !enable);
2368 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2370 struct mlx5e_priv *priv = netdev_priv(netdev);
2373 mutex_lock(&priv->state_lock);
2375 priv->params.vlan_strip_disable = !enable;
2376 err = mlx5e_modify_rqs_vsd(priv, !enable);
2378 priv->params.vlan_strip_disable = enable;
2380 mutex_unlock(&priv->state_lock);
2385 #ifdef CONFIG_RFS_ACCEL
2386 static int set_feature_arfs(struct net_device *netdev, bool enable)
2388 struct mlx5e_priv *priv = netdev_priv(netdev);
2392 err = mlx5e_arfs_enable(priv);
2394 err = mlx5e_arfs_disable(priv);
2400 static int mlx5e_handle_feature(struct net_device *netdev,
2401 netdev_features_t wanted_features,
2402 netdev_features_t feature,
2403 mlx5e_feature_handler feature_handler)
2405 netdev_features_t changes = wanted_features ^ netdev->features;
2406 bool enable = !!(wanted_features & feature);
2409 if (!(changes & feature))
2412 err = feature_handler(netdev, enable);
2414 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2415 enable ? "Enable" : "Disable", feature, err);
2419 MLX5E_SET_FEATURE(netdev, feature, enable);
2423 static int mlx5e_set_features(struct net_device *netdev,
2424 netdev_features_t features)
2428 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2430 err |= mlx5e_handle_feature(netdev, features,
2431 NETIF_F_HW_VLAN_CTAG_FILTER,
2432 set_feature_vlan_filter);
2433 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2434 set_feature_tc_num_filters);
2435 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2436 set_feature_rx_all);
2437 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2438 set_feature_rx_vlan);
2439 #ifdef CONFIG_RFS_ACCEL
2440 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2444 return err ? -EINVAL : 0;
2447 #define MXL5_HW_MIN_MTU 64
2448 #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2450 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2452 struct mlx5e_priv *priv = netdev_priv(netdev);
2453 struct mlx5_core_dev *mdev = priv->mdev;
2459 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2461 max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2462 min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
2464 if (new_mtu > max_mtu || new_mtu < min_mtu) {
2466 "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2467 __func__, new_mtu, min_mtu, max_mtu);
2471 mutex_lock(&priv->state_lock);
2473 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2475 mlx5e_close_locked(netdev);
2477 netdev->mtu = new_mtu;
2480 err = mlx5e_open_locked(netdev);
2482 mutex_unlock(&priv->state_lock);
2487 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2491 return mlx5e_hwstamp_set(dev, ifr);
2493 return mlx5e_hwstamp_get(dev, ifr);
2499 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2501 struct mlx5e_priv *priv = netdev_priv(dev);
2502 struct mlx5_core_dev *mdev = priv->mdev;
2504 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2507 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2509 struct mlx5e_priv *priv = netdev_priv(dev);
2510 struct mlx5_core_dev *mdev = priv->mdev;
2512 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2516 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2518 struct mlx5e_priv *priv = netdev_priv(dev);
2519 struct mlx5_core_dev *mdev = priv->mdev;
2521 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2524 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2526 struct mlx5e_priv *priv = netdev_priv(dev);
2527 struct mlx5_core_dev *mdev = priv->mdev;
2529 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2531 static int mlx5_vport_link2ifla(u8 esw_link)
2534 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2535 return IFLA_VF_LINK_STATE_DISABLE;
2536 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2537 return IFLA_VF_LINK_STATE_ENABLE;
2539 return IFLA_VF_LINK_STATE_AUTO;
2542 static int mlx5_ifla_link2vport(u8 ifla_link)
2544 switch (ifla_link) {
2545 case IFLA_VF_LINK_STATE_DISABLE:
2546 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2547 case IFLA_VF_LINK_STATE_ENABLE:
2548 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2550 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2553 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2556 struct mlx5e_priv *priv = netdev_priv(dev);
2557 struct mlx5_core_dev *mdev = priv->mdev;
2559 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2560 mlx5_ifla_link2vport(link_state));
2563 static int mlx5e_get_vf_config(struct net_device *dev,
2564 int vf, struct ifla_vf_info *ivi)
2566 struct mlx5e_priv *priv = netdev_priv(dev);
2567 struct mlx5_core_dev *mdev = priv->mdev;
2570 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2573 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2577 static int mlx5e_get_vf_stats(struct net_device *dev,
2578 int vf, struct ifla_vf_stats *vf_stats)
2580 struct mlx5e_priv *priv = netdev_priv(dev);
2581 struct mlx5_core_dev *mdev = priv->mdev;
2583 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2587 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2588 sa_family_t sa_family, __be16 port)
2590 struct mlx5e_priv *priv = netdev_priv(netdev);
2592 if (!mlx5e_vxlan_allowed(priv->mdev))
2595 mlx5e_vxlan_queue_work(priv, sa_family, be16_to_cpu(port), 1);
2598 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2599 sa_family_t sa_family, __be16 port)
2601 struct mlx5e_priv *priv = netdev_priv(netdev);
2603 if (!mlx5e_vxlan_allowed(priv->mdev))
2606 mlx5e_vxlan_queue_work(priv, sa_family, be16_to_cpu(port), 0);
2609 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2610 struct sk_buff *skb,
2611 netdev_features_t features)
2613 struct udphdr *udph;
2617 switch (vlan_get_protocol(skb)) {
2618 case htons(ETH_P_IP):
2619 proto = ip_hdr(skb)->protocol;
2621 case htons(ETH_P_IPV6):
2622 proto = ipv6_hdr(skb)->nexthdr;
2628 if (proto == IPPROTO_UDP) {
2629 udph = udp_hdr(skb);
2630 port = be16_to_cpu(udph->dest);
2633 /* Verify if UDP port is being offloaded by HW */
2634 if (port && mlx5e_vxlan_lookup_port(priv, port))
2638 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2639 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2642 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2643 struct net_device *netdev,
2644 netdev_features_t features)
2646 struct mlx5e_priv *priv = netdev_priv(netdev);
2648 features = vlan_features_check(skb, features);
2649 features = vxlan_features_check(skb, features);
2651 /* Validate if the tunneled packet is being offloaded by HW */
2652 if (skb->encapsulation &&
2653 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2654 return mlx5e_vxlan_features_check(priv, skb, features);
2659 static void mlx5e_tx_timeout(struct net_device *dev)
2661 struct mlx5e_priv *priv = netdev_priv(dev);
2662 bool sched_work = false;
2665 netdev_err(dev, "TX timeout detected\n");
2667 for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
2668 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
2670 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
2673 set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
2674 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
2675 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
2678 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
2679 schedule_work(&priv->tx_timeout_work);
2682 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2683 .ndo_open = mlx5e_open,
2684 .ndo_stop = mlx5e_close,
2685 .ndo_start_xmit = mlx5e_xmit,
2686 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2687 .ndo_select_queue = mlx5e_select_queue,
2688 .ndo_get_stats64 = mlx5e_get_stats,
2689 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2690 .ndo_set_mac_address = mlx5e_set_mac,
2691 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2692 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2693 .ndo_set_features = mlx5e_set_features,
2694 .ndo_change_mtu = mlx5e_change_mtu,
2695 .ndo_do_ioctl = mlx5e_ioctl,
2696 #ifdef CONFIG_RFS_ACCEL
2697 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
2699 .ndo_tx_timeout = mlx5e_tx_timeout,
2702 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2703 .ndo_open = mlx5e_open,
2704 .ndo_stop = mlx5e_close,
2705 .ndo_start_xmit = mlx5e_xmit,
2706 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2707 .ndo_select_queue = mlx5e_select_queue,
2708 .ndo_get_stats64 = mlx5e_get_stats,
2709 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2710 .ndo_set_mac_address = mlx5e_set_mac,
2711 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2712 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2713 .ndo_set_features = mlx5e_set_features,
2714 .ndo_change_mtu = mlx5e_change_mtu,
2715 .ndo_do_ioctl = mlx5e_ioctl,
2716 .ndo_add_vxlan_port = mlx5e_add_vxlan_port,
2717 .ndo_del_vxlan_port = mlx5e_del_vxlan_port,
2718 .ndo_features_check = mlx5e_features_check,
2719 #ifdef CONFIG_RFS_ACCEL
2720 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
2722 .ndo_set_vf_mac = mlx5e_set_vf_mac,
2723 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
2724 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
2725 .ndo_set_vf_trust = mlx5e_set_vf_trust,
2726 .ndo_get_vf_config = mlx5e_get_vf_config,
2727 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
2728 .ndo_get_vf_stats = mlx5e_get_vf_stats,
2729 .ndo_tx_timeout = mlx5e_tx_timeout,
2732 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2734 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2736 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2737 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2738 !MLX5_CAP_ETH(mdev, csum_cap) ||
2739 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2740 !MLX5_CAP_ETH(mdev, vlan_cap) ||
2741 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2742 MLX5_CAP_FLOWTABLE(mdev,
2743 flow_table_properties_nic_receive.max_ft_level)
2745 mlx5_core_warn(mdev,
2746 "Not creating net device, some required device capabilities are missing\n");
2749 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2750 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2751 if (!MLX5_CAP_GEN(mdev, cq_moderation))
2752 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2757 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2759 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2761 return bf_buf_size -
2762 sizeof(struct mlx5e_tx_wqe) +
2763 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2766 #ifdef CONFIG_MLX5_CORE_EN_DCB
2767 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2771 priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2772 for (i = 0; i < priv->params.ets.ets_cap; i++) {
2773 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2774 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2775 priv->params.ets.prio_tc[i] = i;
2778 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2779 priv->params.ets.prio_tc[0] = 1;
2780 priv->params.ets.prio_tc[1] = 0;
2784 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2785 u32 *indirection_rqt, int len,
2788 int node = mdev->priv.numa_node;
2789 int node_num_of_cores;
2793 node = first_online_node;
2795 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2797 if (node_num_of_cores)
2798 num_channels = min_t(int, num_channels, node_num_of_cores);
2800 for (i = 0; i < len; i++)
2801 indirection_rqt[i] = i % num_channels;
2804 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2806 return MLX5_CAP_GEN(mdev, striding_rq) &&
2807 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2808 MLX5_CAP_ETH(mdev, reg_umr_sq);
2811 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
2813 enum pcie_link_width width;
2814 enum pci_bus_speed speed;
2817 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
2821 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
2825 case PCIE_SPEED_2_5GT:
2826 *pci_bw = 2500 * width;
2828 case PCIE_SPEED_5_0GT:
2829 *pci_bw = 5000 * width;
2831 case PCIE_SPEED_8_0GT:
2832 *pci_bw = 8000 * width;
2841 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
2843 return (link_speed && pci_bw &&
2844 (pci_bw < 40000) && (pci_bw < link_speed));
2847 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2848 struct net_device *netdev,
2851 struct mlx5e_priv *priv = netdev_priv(netdev);
2855 priv->params.log_sq_size =
2856 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2857 priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
2858 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
2859 MLX5_WQ_TYPE_LINKED_LIST;
2861 /* set CQE compression */
2862 priv->params.rx_cqe_compress_admin = false;
2863 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
2864 MLX5_CAP_GEN(mdev, vport_group_manager)) {
2865 mlx5e_get_max_linkspeed(mdev, &link_speed);
2866 mlx5e_get_pci_bw(mdev, &pci_bw);
2867 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
2868 link_speed, pci_bw);
2869 priv->params.rx_cqe_compress_admin =
2870 cqe_compress_heuristic(link_speed, pci_bw);
2873 priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
2875 switch (priv->params.rq_wq_type) {
2876 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2877 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
2878 priv->params.mpwqe_log_stride_sz =
2879 priv->params.rx_cqe_compress ?
2880 MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
2881 MLX5_MPWRQ_LOG_STRIDE_SIZE;
2882 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
2883 priv->params.mpwqe_log_stride_sz;
2884 priv->params.lro_en = true;
2886 default: /* MLX5_WQ_TYPE_LINKED_LIST */
2887 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2890 mlx5_core_info(mdev,
2891 "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
2892 priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
2893 BIT(priv->params.log_rq_size),
2894 BIT(priv->params.mpwqe_log_stride_sz),
2895 priv->params.rx_cqe_compress_admin);
2897 priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
2898 BIT(priv->params.log_rq_size));
2899 priv->params.rx_cq_moderation_usec =
2900 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2901 priv->params.rx_cq_moderation_pkts =
2902 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2903 priv->params.tx_cq_moderation_usec =
2904 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2905 priv->params.tx_cq_moderation_pkts =
2906 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2907 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
2908 priv->params.num_tc = 1;
2909 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
2911 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2912 sizeof(priv->params.toeplitz_hash_key));
2914 mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
2915 MLX5E_INDIR_RQT_SIZE, num_channels);
2917 priv->params.lro_wqe_sz =
2918 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2921 priv->netdev = netdev;
2922 priv->params.num_channels = num_channels;
2924 #ifdef CONFIG_MLX5_CORE_EN_DCB
2925 mlx5e_ets_init(priv);
2928 mutex_init(&priv->state_lock);
2930 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2931 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2932 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
2933 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2936 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2938 struct mlx5e_priv *priv = netdev_priv(netdev);
2940 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
2941 if (is_zero_ether_addr(netdev->dev_addr) &&
2942 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2943 eth_hw_addr_random(netdev);
2944 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2948 static void mlx5e_build_netdev(struct net_device *netdev)
2950 struct mlx5e_priv *priv = netdev_priv(netdev);
2951 struct mlx5_core_dev *mdev = priv->mdev;
2955 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2957 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2958 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
2959 #ifdef CONFIG_MLX5_CORE_EN_DCB
2960 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2963 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
2966 netdev->watchdog_timeo = 15 * HZ;
2968 netdev->ethtool_ops = &mlx5e_ethtool_ops;
2970 netdev->vlan_features |= NETIF_F_SG;
2971 netdev->vlan_features |= NETIF_F_IP_CSUM;
2972 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
2973 netdev->vlan_features |= NETIF_F_GRO;
2974 netdev->vlan_features |= NETIF_F_TSO;
2975 netdev->vlan_features |= NETIF_F_TSO6;
2976 netdev->vlan_features |= NETIF_F_RXCSUM;
2977 netdev->vlan_features |= NETIF_F_RXHASH;
2979 if (!!MLX5_CAP_ETH(mdev, lro_cap))
2980 netdev->vlan_features |= NETIF_F_LRO;
2982 netdev->hw_features = netdev->vlan_features;
2983 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
2984 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
2985 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2987 if (mlx5e_vxlan_allowed(mdev)) {
2988 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
2989 NETIF_F_GSO_UDP_TUNNEL_CSUM |
2990 NETIF_F_GSO_PARTIAL;
2991 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
2992 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
2993 netdev->hw_enc_features |= NETIF_F_TSO;
2994 netdev->hw_enc_features |= NETIF_F_TSO6;
2995 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
2996 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
2997 NETIF_F_GSO_PARTIAL;
2998 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
3001 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3004 netdev->hw_features |= NETIF_F_RXALL;
3006 netdev->features = netdev->hw_features;
3007 if (!priv->params.lro_en)
3008 netdev->features &= ~NETIF_F_LRO;
3011 netdev->features &= ~NETIF_F_RXALL;
3013 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3014 if (FT_CAP(flow_modify_en) &&
3015 FT_CAP(modify_root) &&
3016 FT_CAP(identified_miss_table_mode) &&
3017 FT_CAP(flow_table_modify)) {
3018 netdev->hw_features |= NETIF_F_HW_TC;
3019 #ifdef CONFIG_RFS_ACCEL
3020 netdev->hw_features |= NETIF_F_NTUPLE;
3024 netdev->features |= NETIF_F_HIGHDMA;
3026 netdev->priv_flags |= IFF_UNICAST_FLT;
3028 mlx5e_set_netdev_dev_addr(netdev);
3031 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3032 struct mlx5_core_mkey *mkey)
3034 struct mlx5_core_dev *mdev = priv->mdev;
3035 struct mlx5_create_mkey_mbox_in *in;
3038 in = mlx5_vzalloc(sizeof(*in));
3042 in->seg.flags = MLX5_PERM_LOCAL_WRITE |
3043 MLX5_PERM_LOCAL_READ |
3044 MLX5_ACCESS_MODE_PA;
3045 in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
3046 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
3048 err = mlx5_core_create_mkey(mdev, mkey, in, sizeof(*in), NULL, NULL,
3056 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3058 struct mlx5_core_dev *mdev = priv->mdev;
3061 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3063 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3064 priv->q_counter = 0;
3068 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3070 if (!priv->q_counter)
3073 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3076 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
3078 struct mlx5_core_dev *mdev = priv->mdev;
3079 struct mlx5_create_mkey_mbox_in *in;
3080 struct mlx5_mkey_seg *mkc;
3081 int inlen = sizeof(*in);
3083 mlx5e_get_max_num_channels(mdev) * MLX5_CHANNEL_MAX_NUM_MTTS;
3086 in = mlx5_vzalloc(inlen);
3091 mkc->status = MLX5_MKEY_STATUS_FREE;
3092 mkc->flags = MLX5_PERM_UMR_EN |
3093 MLX5_PERM_LOCAL_READ |
3094 MLX5_PERM_LOCAL_WRITE |
3095 MLX5_ACCESS_MODE_MTT;
3097 mkc->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
3098 mkc->flags_pd = cpu_to_be32(priv->pdn);
3099 mkc->len = cpu_to_be64(npages << PAGE_SHIFT);
3100 mkc->xlt_oct_size = cpu_to_be32(mlx5e_get_mtt_octw(npages));
3101 mkc->log2_page_size = PAGE_SHIFT;
3103 err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen, NULL,
3111 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
3113 struct net_device *netdev;
3114 struct mlx5e_priv *priv;
3115 int nch = mlx5e_get_max_num_channels(mdev);
3118 if (mlx5e_check_required_hca_cap(mdev))
3121 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
3122 nch * MLX5E_MAX_NUM_TC,
3125 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3129 mlx5e_build_netdev_priv(mdev, netdev, nch);
3130 mlx5e_build_netdev(netdev);
3132 netif_carrier_off(netdev);
3134 priv = netdev_priv(netdev);
3136 priv->wq = create_singlethread_workqueue("mlx5e");
3138 goto err_free_netdev;
3140 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false);
3142 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
3143 goto err_destroy_wq;
3146 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3148 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
3149 goto err_unmap_free_uar;
3152 err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
3154 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
3155 goto err_dealloc_pd;
3158 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mkey);
3160 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
3161 goto err_dealloc_transport_domain;
3164 err = mlx5e_create_umr_mkey(priv);
3166 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
3167 goto err_destroy_mkey;
3170 err = mlx5e_create_tises(priv);
3172 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
3173 goto err_destroy_umr_mkey;
3176 err = mlx5e_open_drop_rq(priv);
3178 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
3179 goto err_destroy_tises;
3182 err = mlx5e_create_rqts(priv);
3184 mlx5_core_warn(mdev, "create rqts failed, %d\n", err);
3185 goto err_close_drop_rq;
3188 err = mlx5e_create_tirs(priv);
3190 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
3191 goto err_destroy_rqts;
3194 err = mlx5e_create_flow_steering(priv);
3196 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3197 goto err_destroy_tirs;
3200 mlx5e_create_q_counter(priv);
3202 mlx5e_init_l2_addr(priv);
3204 mlx5e_vxlan_init(priv);
3206 err = mlx5e_tc_init(priv);
3208 goto err_dealloc_q_counters;
3210 #ifdef CONFIG_MLX5_CORE_EN_DCB
3211 mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3214 err = register_netdev(netdev);
3216 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
3217 goto err_tc_cleanup;
3220 if (mlx5e_vxlan_allowed(mdev)) {
3222 vxlan_get_rx_port(netdev);
3226 mlx5e_enable_async_events(priv);
3227 queue_work(priv->wq, &priv->set_rx_mode_work);
3232 mlx5e_tc_cleanup(priv);
3234 err_dealloc_q_counters:
3235 mlx5e_destroy_q_counter(priv);
3236 mlx5e_destroy_flow_steering(priv);
3239 mlx5e_destroy_tirs(priv);
3242 mlx5e_destroy_rqts(priv);
3245 mlx5e_close_drop_rq(priv);
3248 mlx5e_destroy_tises(priv);
3250 err_destroy_umr_mkey:
3251 mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3254 mlx5_core_destroy_mkey(mdev, &priv->mkey);
3256 err_dealloc_transport_domain:
3257 mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
3260 mlx5_core_dealloc_pd(mdev, priv->pdn);
3263 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3266 destroy_workqueue(priv->wq);
3269 free_netdev(netdev);
3274 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
3276 struct mlx5e_priv *priv = vpriv;
3277 struct net_device *netdev = priv->netdev;
3279 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3281 queue_work(priv->wq, &priv->set_rx_mode_work);
3282 mlx5e_disable_async_events(priv);
3283 flush_workqueue(priv->wq);
3284 if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) {
3285 netif_device_detach(netdev);
3286 mlx5e_close(netdev);
3288 unregister_netdev(netdev);
3291 mlx5e_tc_cleanup(priv);
3292 mlx5e_vxlan_cleanup(priv);
3293 mlx5e_destroy_q_counter(priv);
3294 mlx5e_destroy_flow_steering(priv);
3295 mlx5e_destroy_tirs(priv);
3296 mlx5e_destroy_rqts(priv);
3297 mlx5e_close_drop_rq(priv);
3298 mlx5e_destroy_tises(priv);
3299 mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3300 mlx5_core_destroy_mkey(priv->mdev, &priv->mkey);
3301 mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
3302 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3303 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3304 cancel_delayed_work_sync(&priv->update_stats_work);
3305 destroy_workqueue(priv->wq);
3307 if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state))
3308 free_netdev(netdev);
3311 static void *mlx5e_get_netdev(void *vpriv)
3313 struct mlx5e_priv *priv = vpriv;
3315 return priv->netdev;
3318 static struct mlx5_interface mlx5e_interface = {
3319 .add = mlx5e_create_netdev,
3320 .remove = mlx5e_destroy_netdev,
3321 .event = mlx5e_async_event,
3322 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3323 .get_dev = mlx5e_get_netdev,
3326 void mlx5e_init(void)
3328 mlx5_register_interface(&mlx5e_interface);
3331 void mlx5e_cleanup(void)
3333 mlx5_unregister_interface(&mlx5e_interface);