drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <net/geneve.h>
  38 #include <linux/bpf.h>
  39 #include <linux/if_bridge.h>
  40 #include <net/page_pool.h>
  41 #include <net/xdp_sock_drv.h>
  42 #include "eswitch.h"
  43 #include "en.h"
  44 #include "en/txrx.h"
  45 #include "en_tc.h"
  46 #include "en_rep.h"
  47 #include "en_accel/ipsec.h"
  48 #include "en_accel/en_accel.h"
  49 #include "en_accel/tls.h"
  50 #include "accel/ipsec.h"
  51 #include "accel/tls.h"
  52 #include "lib/vxlan.h"
  53 #include "lib/clock.h"
  54 #include "en/port.h"
  55 #include "en/xdp.h"
  56 #include "lib/eq.h"
  57 #include "en/monitor_stats.h"
  58 #include "en/health.h"
  59 #include "en/params.h"
  60 #include "en/xsk/pool.h"
  61 #include "en/xsk/setup.h"
  62 #include "en/xsk/rx.h"
  63 #include "en/xsk/tx.h"
  64 #include "en/hv_vhca_stats.h"
  65 #include "en/devlink.h"
  66 #include "lib/mlx5.h"
  67 #include "en/ptp.h"
  68 #include "qos.h"
  69 #include "en/trap.h"
  70 #include "fpga/ipsec.h"
  71
  72 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  73 {
  74         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  75                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  76                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  77         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  78         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  79
  80         if (!striding_rq_umr)
  81                 return false;
  82         if (!inline_umr) {
  83                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  84                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  85                 return false;
  86         }
  87         return true;
  88 }
  89
  90 void mlx5e_update_carrier(struct mlx5e_priv *priv)
  91 {
  92         struct mlx5_core_dev *mdev = priv->mdev;
  93         u8 port_state;
  94         bool up;
  95
  96         port_state = mlx5_query_vport_state(mdev,
  97                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
  98                                             0);
  99
 100         up = port_state == VPORT_STATE_UP;
 101         if (up == netif_carrier_ok(priv->netdev))
 102                 netif_carrier_event(priv->netdev);
 103         if (up) {
 104                 netdev_info(priv->netdev, "Link up\n");
 105                 netif_carrier_on(priv->netdev);
 106         } else {
 107                 netdev_info(priv->netdev, "Link down\n");
 108                 netif_carrier_off(priv->netdev);
 109         }
 110 }
 111
 112 static void mlx5e_update_carrier_work(struct work_struct *work)
 113 {
 114         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 115                                                update_carrier_work);
 116
 117         mutex_lock(&priv->state_lock);
 118         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 119                 if (priv->profile->update_carrier)
 120                         priv->profile->update_carrier(priv);
 121         mutex_unlock(&priv->state_lock);
 122 }
 123
 124 static void mlx5e_update_stats_work(struct work_struct *work)
 125 {
 126         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 127                                                update_stats_work);
 128
 129         mutex_lock(&priv->state_lock);
 130         priv->profile->update_stats(priv);
 131         mutex_unlock(&priv->state_lock);
 132 }
 133
 134 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
 135 {
 136         if (!priv->profile->update_stats)
 137                 return;
 138
 139         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
 140                 return;
 141
 142         queue_work(priv->wq, &priv->update_stats_work);
 143 }
 144
 145 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
 146 {
 147         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
 148         struct mlx5_eqe   *eqe = data;
 149
 150         if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
 151                 return NOTIFY_DONE;
 152
 153         switch (eqe->sub_type) {
 154         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 155         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 156                 queue_work(priv->wq, &priv->update_carrier_work);
 157                 break;
 158         default:
 159                 return NOTIFY_DONE;
 160         }
 161
 162         return NOTIFY_OK;
 163 }
 164
 165 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 166 {
 167         priv->events_nb.notifier_call = async_event;
 168         mlx5_notifier_register(priv->mdev, &priv->events_nb);
 169 }
 170
 171 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 172 {
 173         mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
 174 }
 175
 176 static int blocking_event(struct notifier_block *nb, unsigned long event, void *data)
 177 {
 178         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, blocking_events_nb);
 179         int err;
 180
 181         switch (event) {
 182         case MLX5_DRIVER_EVENT_TYPE_TRAP:
 183                 err = mlx5e_handle_trap_event(priv, data);
 184                 break;
 185         default:
 186                 netdev_warn(priv->netdev, "Sync event: Unknown event %ld\n", event);
 187                 err = -EINVAL;
 188         }
 189         return err;
 190 }
 191
 192 static void mlx5e_enable_blocking_events(struct mlx5e_priv *priv)
 193 {
 194         priv->blocking_events_nb.notifier_call = blocking_event;
 195         mlx5_blocking_notifier_register(priv->mdev, &priv->blocking_events_nb);
 196 }
 197
 198 static void mlx5e_disable_blocking_events(struct mlx5e_priv *priv)
 199 {
 200         mlx5_blocking_notifier_unregister(priv->mdev, &priv->blocking_events_nb);
 201 }
 202
 203 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 204                                        struct mlx5e_icosq *sq,
 205                                        struct mlx5e_umr_wqe *wqe)
 206 {
 207         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 208         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 209         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 210
 211         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 212                                       ds_cnt);
 213         cseg->umr_mkey  = rq->mkey_be;
 214
 215         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 216         ucseg->xlt_octowords =
 217                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 218         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 219 }
 220
 221 static int mlx5e_rq_shampo_hd_alloc(struct mlx5e_rq *rq, int node)
 222 {
 223         rq->mpwqe.shampo = kvzalloc_node(sizeof(*rq->mpwqe.shampo),
 224                                          GFP_KERNEL, node);
 225         if (!rq->mpwqe.shampo)
 226                 return -ENOMEM;
 227         return 0;
 228 }
 229
 230 static void mlx5e_rq_shampo_hd_free(struct mlx5e_rq *rq)
 231 {
 232         kvfree(rq->mpwqe.shampo);
 233 }
 234
 235 static int mlx5e_rq_shampo_hd_info_alloc(struct mlx5e_rq *rq, int node)
 236 {
 237         struct mlx5e_shampo_hd *shampo = rq->mpwqe.shampo;
 238
 239         shampo->bitmap = bitmap_zalloc_node(shampo->hd_per_wq, GFP_KERNEL,
 240                                             node);
 241         if (!shampo->bitmap)
 242                 return -ENOMEM;
 243
 244         shampo->info = kvzalloc_node(array_size(shampo->hd_per_wq,
 245                                                 sizeof(*shampo->info)),
 246                                      GFP_KERNEL, node);
 247         if (!shampo->info) {
 248                 kvfree(shampo->bitmap);
 249                 return -ENOMEM;
 250         }
 251         return 0;
 252 }
 253
 254 static void mlx5e_rq_shampo_hd_info_free(struct mlx5e_rq *rq)
 255 {
 256         kvfree(rq->mpwqe.shampo->bitmap);
 257         kvfree(rq->mpwqe.shampo->info);
 258 }
 259
 260 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, int node)
 261 {
 262         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 263
 264         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 265                                                   sizeof(*rq->mpwqe.info)),
 266                                        GFP_KERNEL, node);
 267         if (!rq->mpwqe.info)
 268                 return -ENOMEM;
 269
 270         mlx5e_build_umr_wqe(rq, rq->icosq, &rq->mpwqe.umr_wqe);
 271
 272         return 0;
 273 }
 274
 275 static int mlx5e_create_umr_mtt_mkey(struct mlx5_core_dev *mdev,
 276                                      u64 npages, u8 page_shift, u32 *umr_mkey,
 277                                      dma_addr_t filler_addr)
 278 {
 279         struct mlx5_mtt *mtt;
 280         int inlen;
 281         void *mkc;
 282         u32 *in;
 283         int err;
 284         int i;
 285
 286         inlen = MLX5_ST_SZ_BYTES(create_mkey_in) + sizeof(*mtt) * npages;
 287
 288         in = kvzalloc(inlen, GFP_KERNEL);
 289         if (!in)
 290                 return -ENOMEM;
 291
 292         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 293
 294         MLX5_SET(mkc, mkc, free, 1);
 295         MLX5_SET(mkc, mkc, umr_en, 1);
 296         MLX5_SET(mkc, mkc, lw, 1);
 297         MLX5_SET(mkc, mkc, lr, 1);
 298         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 299         mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
 300         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 301         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
 302         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 303         MLX5_SET(mkc, mkc, translations_octword_size,
 304                  MLX5_MTT_OCTW(npages));
 305         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 306         MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
 307                  MLX5_MTT_OCTW(npages));
 308
 309         /* Initialize the mkey with all MTTs pointing to a default
 310          * page (filler_addr). When the channels are activated, UMR
 311          * WQEs will redirect the RX WQEs to the actual memory from
 312          * the RQ's pool, while the gaps (wqe_overflow) remain mapped
 313          * to the default page.
 314          */
 315         mtt = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
 316         for (i = 0 ; i < npages ; i++)
 317                 mtt[i].ptag = cpu_to_be64(filler_addr);
 318
 319         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 320
 321         kvfree(in);
 322         return err;
 323 }
 324
 325 static int mlx5e_create_umr_klm_mkey(struct mlx5_core_dev *mdev,
 326                                      u64 nentries,
 327                                      u32 *umr_mkey)
 328 {
 329         int inlen;
 330         void *mkc;
 331         u32 *in;
 332         int err;
 333
 334         inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 335
 336         in = kvzalloc(inlen, GFP_KERNEL);
 337         if (!in)
 338                 return -ENOMEM;
 339
 340         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 341
 342         MLX5_SET(mkc, mkc, free, 1);
 343         MLX5_SET(mkc, mkc, umr_en, 1);
 344         MLX5_SET(mkc, mkc, lw, 1);
 345         MLX5_SET(mkc, mkc, lr, 1);
 346         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_KLMS);
 347         mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
 348         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 349         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
 350         MLX5_SET(mkc, mkc, translations_octword_size, nentries);
 351         MLX5_SET(mkc, mkc, length64, 1);
 352         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 353
 354         kvfree(in);
 355         return err;
 356 }
 357
 358 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 359 {
 360         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 361
 362         return mlx5e_create_umr_mtt_mkey(mdev, num_mtts, PAGE_SHIFT,
 363                                          &rq->umr_mkey, rq->wqe_overflow.addr);
 364 }
 365
 366 static int mlx5e_create_rq_hd_umr_mkey(struct mlx5_core_dev *mdev,
 367                                        struct mlx5e_rq *rq)
 368 {
 369         u32 max_klm_size = BIT(MLX5_CAP_GEN(mdev, log_max_klm_list_size));
 370
 371         if (max_klm_size < rq->mpwqe.shampo->hd_per_wq) {
 372                 mlx5_core_err(mdev, "max klm list size 0x%x is smaller than shampo header buffer list size 0x%x\n",
 373                               max_klm_size, rq->mpwqe.shampo->hd_per_wq);
 374                 return -EINVAL;
 375         }
 376         return mlx5e_create_umr_klm_mkey(mdev, rq->mpwqe.shampo->hd_per_wq,
 377                                          &rq->mpwqe.shampo->mkey);
 378 }
 379
 380 static u64 mlx5e_get_mpwqe_offset(u16 wqe_ix)
 381 {
 382         return MLX5E_REQUIRED_MTTS(wqe_ix) << PAGE_SHIFT;
 383 }
 384
 385 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 386 {
 387         struct mlx5e_wqe_frag_info next_frag = {};
 388         struct mlx5e_wqe_frag_info *prev = NULL;
 389         int i;
 390
 391         next_frag.di = &rq->wqe.di[0];
 392
 393         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 394                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 395                 struct mlx5e_wqe_frag_info *frag =
 396                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 397                 int f;
 398
 399                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 400                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 401                                 next_frag.di++;
 402                                 next_frag.offset = 0;
 403                                 if (prev)
 404                                         prev->last_in_page = true;
 405                         }
 406                         *frag = next_frag;
 407
 408                         /* prepare next */
 409                         next_frag.offset += frag_info[f].frag_stride;
 410                         prev = frag;
 411                 }
 412         }
 413
 414         if (prev)
 415                 prev->last_in_page = true;
 416 }
 417
 418 int mlx5e_init_di_list(struct mlx5e_rq *rq, int wq_sz, int node)
 419 {
 420         int len = wq_sz << rq->wqe.info.log_num_frags;
 421
 422         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)), GFP_KERNEL, node);
 423         if (!rq->wqe.di)
 424                 return -ENOMEM;
 425
 426         mlx5e_init_frags_partition(rq);
 427
 428         return 0;
 429 }
 430
 431 void mlx5e_free_di_list(struct mlx5e_rq *rq)
 432 {
 433         kvfree(rq->wqe.di);
 434 }
 435
 436 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
 437 {
 438         struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
 439
 440         mlx5e_reporter_rq_cqe_err(rq);
 441 }
 442
 443 static int mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
 444 {
 445         rq->wqe_overflow.page = alloc_page(GFP_KERNEL);
 446         if (!rq->wqe_overflow.page)
 447                 return -ENOMEM;
 448
 449         rq->wqe_overflow.addr = dma_map_page(rq->pdev, rq->wqe_overflow.page, 0,
 450                                              PAGE_SIZE, rq->buff.map_dir);
 451         if (dma_mapping_error(rq->pdev, rq->wqe_overflow.addr)) {
 452                 __free_page(rq->wqe_overflow.page);
 453                 return -ENOMEM;
 454         }
 455         return 0;
 456 }
 457
 458 static void mlx5e_free_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
 459 {
 460          dma_unmap_page(rq->pdev, rq->wqe_overflow.addr, PAGE_SIZE,
 461                         rq->buff.map_dir);
 462          __free_page(rq->wqe_overflow.page);
 463 }
 464
 465 static int mlx5e_init_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
 466                              struct mlx5e_rq *rq)
 467 {
 468         struct mlx5_core_dev *mdev = c->mdev;
 469         int err;
 470
 471         rq->wq_type      = params->rq_wq_type;
 472         rq->pdev         = c->pdev;
 473         rq->netdev       = c->netdev;
 474         rq->priv         = c->priv;
 475         rq->tstamp       = c->tstamp;
 476         rq->clock        = &mdev->clock;
 477         rq->icosq        = &c->icosq;
 478         rq->ix           = c->ix;
 479         rq->mdev         = mdev;
 480         rq->hw_mtu       = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 481         rq->xdpsq        = &c->rq_xdpsq;
 482         rq->stats        = &c->priv->channel_stats[c->ix].rq;
 483         rq->ptp_cyc2time = mlx5_rq_ts_translator(mdev);
 484         err = mlx5e_rq_set_handlers(rq, params, NULL);
 485         if (err)
 486                 return err;
 487
 488         return xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix, 0);
 489 }
 490
 491 static int mlx5_rq_shampo_alloc(struct mlx5_core_dev *mdev,
 492                                 struct mlx5e_params *params,
 493                                 struct mlx5e_rq_param *rqp,
 494                                 struct mlx5e_rq *rq,
 495                                 u32 *pool_size,
 496                                 int node)
 497 {
 498         void *wqc = MLX5_ADDR_OF(rqc, rqp->rqc, wq);
 499         int wq_size;
 500         int err;
 501
 502         if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
 503                 return 0;
 504         err = mlx5e_rq_shampo_hd_alloc(rq, node);
 505         if (err)
 506                 goto out;
 507         rq->mpwqe.shampo->hd_per_wq =
 508                 mlx5e_shampo_hd_per_wq(mdev, params, rqp);
 509         err = mlx5e_create_rq_hd_umr_mkey(mdev, rq);
 510         if (err)
 511                 goto err_shampo_hd;
 512         err = mlx5e_rq_shampo_hd_info_alloc(rq, node);
 513         if (err)
 514                 goto err_shampo_info;
 515         rq->hw_gro_data = kvzalloc_node(sizeof(*rq->hw_gro_data), GFP_KERNEL, node);
 516         if (!rq->hw_gro_data) {
 517                 err = -ENOMEM;
 518                 goto err_hw_gro_data;
 519         }
 520         rq->mpwqe.shampo->key =
 521                 cpu_to_be32(rq->mpwqe.shampo->mkey);
 522         rq->mpwqe.shampo->hd_per_wqe =
 523                 mlx5e_shampo_hd_per_wqe(mdev, params, rqp);
 524         wq_size = BIT(MLX5_GET(wq, wqc, log_wq_sz));
 525         *pool_size += (rq->mpwqe.shampo->hd_per_wqe * wq_size) /
 526                      MLX5E_SHAMPO_WQ_HEADER_PER_PAGE;
 527         return 0;
 528
 529 err_hw_gro_data:
 530         mlx5e_rq_shampo_hd_info_free(rq);
 531 err_shampo_info:
 532         mlx5_core_destroy_mkey(mdev, rq->mpwqe.shampo->mkey);
 533 err_shampo_hd:
 534         mlx5e_rq_shampo_hd_free(rq);
 535 out:
 536         return err;
 537 }
 538
 539 static void mlx5e_rq_free_shampo(struct mlx5e_rq *rq)
 540 {
 541         if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
 542                 return;
 543
 544         kvfree(rq->hw_gro_data);
 545         mlx5e_rq_shampo_hd_info_free(rq);
 546         mlx5_core_destroy_mkey(rq->mdev, rq->mpwqe.shampo->mkey);
 547         mlx5e_rq_shampo_hd_free(rq);
 548 }
 549
 550 static int mlx5e_alloc_rq(struct mlx5e_params *params,
 551                           struct mlx5e_xsk_param *xsk,
 552                           struct mlx5e_rq_param *rqp,
 553                           int node, struct mlx5e_rq *rq)
 554 {
 555         struct page_pool_params pp_params = { 0 };
 556         struct mlx5_core_dev *mdev = rq->mdev;
 557         void *rqc = rqp->rqc;
 558         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 559         u32 pool_size;
 560         int wq_sz;
 561         int err;
 562         int i;
 563
 564         rqp->wq.db_numa_node = node;
 565         INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
 566
 567         if (params->xdp_prog)
 568                 bpf_prog_inc(params->xdp_prog);
 569         RCU_INIT_POINTER(rq->xdp_prog, params->xdp_prog);
 570
 571         rq->buff.map_dir = params->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 572         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
 573         pool_size = 1 << params->log_rq_mtu_frames;
 574
 575         switch (rq->wq_type) {
 576         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 577                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 578                                         &rq->wq_ctrl);
 579                 if (err)
 580                         goto err_rq_xdp_prog;
 581
 582                 err = mlx5e_alloc_mpwqe_rq_drop_page(rq);
 583                 if (err)
 584                         goto err_rq_wq_destroy;
 585
 586                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 587
 588                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 589
 590                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
 591                         mlx5e_mpwqe_get_log_rq_size(params, xsk);
 592
 593                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
 594                 rq->mpwqe.num_strides =
 595                         BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
 596
 597                 rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz);
 598
 599                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 600                 if (err)
 601                         goto err_rq_drop_page;
 602                 rq->mkey_be = cpu_to_be32(rq->umr_mkey);
 603
 604                 err = mlx5e_rq_alloc_mpwqe_info(rq, node);
 605                 if (err)
 606                         goto err_rq_mkey;
 607
 608                 err = mlx5_rq_shampo_alloc(mdev, params, rqp, rq, &pool_size, node);
 609                 if (err)
 610                         goto err_free_by_rq_type;
 611
 612                 break;
 613         default: /* MLX5_WQ_TYPE_CYCLIC */
 614                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 615                                          &rq->wq_ctrl);
 616                 if (err)
 617                         goto err_rq_xdp_prog;
 618
 619                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 620
 621                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 622
 623                 rq->wqe.info = rqp->frags_info;
 624                 rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride;
 625
 626                 rq->wqe.frags =
 627                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 628                                         (wq_sz << rq->wqe.info.log_num_frags)),
 629                                       GFP_KERNEL, node);
 630                 if (!rq->wqe.frags) {
 631                         err = -ENOMEM;
 632                         goto err_rq_wq_destroy;
 633                 }
 634
 635                 err = mlx5e_init_di_list(rq, wq_sz, node);
 636                 if (err)
 637                         goto err_rq_frags;
 638
 639                 rq->mkey_be = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey);
 640         }
 641
 642         if (xsk) {
 643                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 644                                                  MEM_TYPE_XSK_BUFF_POOL, NULL);
 645                 xsk_pool_set_rxq_info(rq->xsk_pool, &rq->xdp_rxq);
 646         } else {
 647                 /* Create a page_pool and register it with rxq */
 648                 pp_params.order     = 0;
 649                 pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 650                 pp_params.pool_size = pool_size;
 651                 pp_params.nid       = node;
 652                 pp_params.dev       = rq->pdev;
 653                 pp_params.dma_dir   = rq->buff.map_dir;
 654
 655                 /* page_pool can be used even when there is no rq->xdp_prog,
 656                  * given page_pool does not handle DMA mapping there is no
 657                  * required state to clear. And page_pool gracefully handle
 658                  * elevated refcnt.
 659                  */
 660                 rq->page_pool = page_pool_create(&pp_params);
 661                 if (IS_ERR(rq->page_pool)) {
 662                         err = PTR_ERR(rq->page_pool);
 663                         rq->page_pool = NULL;
 664                         goto err_free_shampo;
 665                 }
 666                 if (xdp_rxq_info_is_reg(&rq->xdp_rxq))
 667                         err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 668                                                          MEM_TYPE_PAGE_POOL, rq->page_pool);
 669         }
 670         if (err)
 671                 goto err_free_shampo;
 672
 673         for (i = 0; i < wq_sz; i++) {
 674                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 675                         struct mlx5e_rx_wqe_ll *wqe =
 676                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 677                         u32 byte_count =
 678                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 679                         u64 dma_offset = mlx5e_get_mpwqe_offset(i);
 680                         u16 headroom = test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state) ?
 681                                        0 : rq->buff.headroom;
 682
 683                         wqe->data[0].addr = cpu_to_be64(dma_offset + headroom);
 684                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 685                         wqe->data[0].lkey = rq->mkey_be;
 686                 } else {
 687                         struct mlx5e_rx_wqe_cyc *wqe =
 688                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 689                         int f;
 690
 691                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 692                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 693                                         MLX5_HW_START_PADDING;
 694
 695                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 696                                 wqe->data[f].lkey = rq->mkey_be;
 697                         }
 698                         /* check if num_frags is not a pow of two */
 699                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 700                                 wqe->data[f].byte_count = 0;
 701                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 702                                 wqe->data[f].addr = 0;
 703                         }
 704                 }
 705         }
 706
 707         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 708
 709         switch (params->rx_cq_moderation.cq_period_mode) {
 710         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 711                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 712                 break;
 713         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 714         default:
 715                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 716         }
 717
 718         rq->page_cache.head = 0;
 719         rq->page_cache.tail = 0;
 720
 721         return 0;
 722
 723 err_free_shampo:
 724         mlx5e_rq_free_shampo(rq);
 725 err_free_by_rq_type:
 726         switch (rq->wq_type) {
 727         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 728                 kvfree(rq->mpwqe.info);
 729 err_rq_mkey:
 730                 mlx5_core_destroy_mkey(mdev, rq->umr_mkey);
 731 err_rq_drop_page:
 732                 mlx5e_free_mpwqe_rq_drop_page(rq);
 733                 break;
 734         default: /* MLX5_WQ_TYPE_CYCLIC */
 735                 mlx5e_free_di_list(rq);
 736 err_rq_frags:
 737                 kvfree(rq->wqe.frags);
 738         }
 739 err_rq_wq_destroy:
 740         mlx5_wq_destroy(&rq->wq_ctrl);
 741 err_rq_xdp_prog:
 742         if (params->xdp_prog)
 743                 bpf_prog_put(params->xdp_prog);
 744
 745         return err;
 746 }
 747
 748 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 749 {
 750         struct bpf_prog *old_prog;
 751         int i;
 752
 753         if (xdp_rxq_info_is_reg(&rq->xdp_rxq)) {
 754                 old_prog = rcu_dereference_protected(rq->xdp_prog,
 755                                                      lockdep_is_held(&rq->priv->state_lock));
 756                 if (old_prog)
 757                         bpf_prog_put(old_prog);
 758         }
 759
 760         switch (rq->wq_type) {
 761         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 762                 kvfree(rq->mpwqe.info);
 763                 mlx5_core_destroy_mkey(rq->mdev, rq->umr_mkey);
 764                 mlx5e_free_mpwqe_rq_drop_page(rq);
 765                 mlx5e_rq_free_shampo(rq);
 766                 break;
 767         default: /* MLX5_WQ_TYPE_CYCLIC */
 768                 kvfree(rq->wqe.frags);
 769                 mlx5e_free_di_list(rq);
 770         }
 771
 772         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 773              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 774                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 775
 776                 /* With AF_XDP, page_cache is not used, so this loop is not
 777                  * entered, and it's safe to call mlx5e_page_release_dynamic
 778                  * directly.
 779                  */
 780                 mlx5e_page_release_dynamic(rq, dma_info, false);
 781         }
 782
 783         xdp_rxq_info_unreg(&rq->xdp_rxq);
 784         page_pool_destroy(rq->page_pool);
 785         mlx5_wq_destroy(&rq->wq_ctrl);
 786 }
 787
 788 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 789 {
 790         struct mlx5_core_dev *mdev = rq->mdev;
 791         u8 ts_format;
 792         void *in;
 793         void *rqc;
 794         void *wq;
 795         int inlen;
 796         int err;
 797
 798         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 799                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 800         in = kvzalloc(inlen, GFP_KERNEL);
 801         if (!in)
 802                 return -ENOMEM;
 803
 804         ts_format = mlx5_is_real_time_rq(mdev) ?
 805                             MLX5_TIMESTAMP_FORMAT_REAL_TIME :
 806                             MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
 807         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 808         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 809
 810         memcpy(rqc, param->rqc, sizeof(param->rqc));
 811
 812         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 813         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 814         MLX5_SET(rqc,  rqc, ts_format,          ts_format);
 815         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 816                                                 MLX5_ADAPTER_PAGE_SHIFT);
 817         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 818
 819         if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) {
 820                 MLX5_SET(wq, wq, log_headers_buffer_entry_num,
 821                          order_base_2(rq->mpwqe.shampo->hd_per_wq));
 822                 MLX5_SET(wq, wq, headers_mkey, rq->mpwqe.shampo->mkey);
 823         }
 824
 825         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 826                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 827
 828         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 829
 830         kvfree(in);
 831
 832         return err;
 833 }
 834
 835 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
 836 {
 837         struct mlx5_core_dev *mdev = rq->mdev;
 838
 839         void *in;
 840         void *rqc;
 841         int inlen;
 842         int err;
 843
 844         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 845         in = kvzalloc(inlen, GFP_KERNEL);
 846         if (!in)
 847                 return -ENOMEM;
 848
 849         if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY)
 850                 mlx5e_rqwq_reset(rq);
 851
 852         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 853
 854         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 855         MLX5_SET(rqc, rqc, state, next_state);
 856
 857         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 858
 859         kvfree(in);
 860
 861         return err;
 862 }
 863
 864 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 865 {
 866         struct mlx5_core_dev *mdev = rq->mdev;
 867
 868         void *in;
 869         void *rqc;
 870         int inlen;
 871         int err;
 872
 873         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 874         in = kvzalloc(inlen, GFP_KERNEL);
 875         if (!in)
 876                 return -ENOMEM;
 877
 878         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 879
 880         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 881         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 882                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 883         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 884         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 885
 886         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 887
 888         kvfree(in);
 889
 890         return err;
 891 }
 892
 893 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 894 {
 895         struct mlx5_core_dev *mdev = rq->mdev;
 896         void *in;
 897         void *rqc;
 898         int inlen;
 899         int err;
 900
 901         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 902         in = kvzalloc(inlen, GFP_KERNEL);
 903         if (!in)
 904                 return -ENOMEM;
 905
 906         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 907
 908         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 909         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 910                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 911         MLX5_SET(rqc, rqc, vsd, vsd);
 912         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 913
 914         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 915
 916         kvfree(in);
 917
 918         return err;
 919 }
 920
 921 void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 922 {
 923         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 924 }
 925
 926 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 927 {
 928         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 929
 930         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 931
 932         do {
 933                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 934                         return 0;
 935
 936                 msleep(20);
 937         } while (time_before(jiffies, exp_time));
 938
 939         netdev_warn(rq->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 940                     rq->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 941
 942         mlx5e_reporter_rx_timeout(rq);
 943         return -ETIMEDOUT;
 944 }
 945
 946 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq *rq)
 947 {
 948         struct mlx5_wq_ll *wq;
 949         u16 head;
 950         int i;
 951
 952         if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 953                 return;
 954
 955         wq = &rq->mpwqe.wq;
 956         head = wq->head;
 957
 958         /* Outstanding UMR WQEs (in progress) start at wq->head */
 959         for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
 960                 rq->dealloc_wqe(rq, head);
 961                 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
 962         }
 963
 964         if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) {
 965                 u16 len;
 966
 967                 len = (rq->mpwqe.shampo->pi - rq->mpwqe.shampo->ci) &
 968                       (rq->mpwqe.shampo->hd_per_wq - 1);
 969                 mlx5e_shampo_dealloc_hd(rq, len, rq->mpwqe.shampo->ci, false);
 970                 rq->mpwqe.shampo->pi = rq->mpwqe.shampo->ci;
 971         }
 972
 973         rq->mpwqe.actual_wq_head = wq->head;
 974         rq->mpwqe.umr_in_progress = 0;
 975         rq->mpwqe.umr_completed = 0;
 976 }
 977
 978 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 979 {
 980         __be16 wqe_ix_be;
 981         u16 wqe_ix;
 982
 983         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 984                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 985
 986                 mlx5e_free_rx_in_progress_descs(rq);
 987
 988                 while (!mlx5_wq_ll_is_empty(wq)) {
 989                         struct mlx5e_rx_wqe_ll *wqe;
 990
 991                         wqe_ix_be = *wq->tail_next;
 992                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 993                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 994                         rq->dealloc_wqe(rq, wqe_ix);
 995                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 996                                        &wqe->next.next_wqe_index);
 997                 }
 998
 999                 if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
1000                         mlx5e_shampo_dealloc_hd(rq, rq->mpwqe.shampo->hd_per_wq,
1001                                                 0, true);
1002         } else {
1003                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1004
1005                 while (!mlx5_wq_cyc_is_empty(wq)) {
1006                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
1007                         rq->dealloc_wqe(rq, wqe_ix);
1008                         mlx5_wq_cyc_pop(wq);
1009                 }
1010         }
1011
1012 }
1013
1014 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
1015                   struct mlx5e_xsk_param *xsk, int node,
1016                   struct mlx5e_rq *rq)
1017 {
1018         struct mlx5_core_dev *mdev = rq->mdev;
1019         int err;
1020
1021         if (params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO)
1022                 __set_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state);
1023
1024         err = mlx5e_alloc_rq(params, xsk, param, node, rq);
1025         if (err)
1026                 return err;
1027
1028         err = mlx5e_create_rq(rq, param);
1029         if (err)
1030                 goto err_free_rq;
1031
1032         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1033         if (err)
1034                 goto err_destroy_rq;
1035
1036         if (mlx5e_is_tls_on(rq->priv) && !mlx5e_accel_is_ktls_device(mdev))
1037                 __set_bit(MLX5E_RQ_STATE_FPGA_TLS, &rq->state); /* must be FPGA */
1038
1039         if (MLX5_CAP_ETH(mdev, cqe_checksum_full))
1040                 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state);
1041
1042         if (params->rx_dim_enabled)
1043                 __set_bit(MLX5E_RQ_STATE_AM, &rq->state);
1044
1045         /* We disable csum_complete when XDP is enabled since
1046          * XDP programs might manipulate packets which will render
1047          * skb->checksum incorrect.
1048          */
1049         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || params->xdp_prog)
1050                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state);
1051
1052         /* For CQE compression on striding RQ, use stride index provided by
1053          * HW if capability is supported.
1054          */
1055         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) &&
1056             MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index))
1057                 __set_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &rq->state);
1058
1059         return 0;
1060
1061 err_destroy_rq:
1062         mlx5e_destroy_rq(rq);
1063 err_free_rq:
1064         mlx5e_free_rq(rq);
1065
1066         return err;
1067 }
1068
1069 void mlx5e_activate_rq(struct mlx5e_rq *rq)
1070 {
1071         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
1072         if (rq->icosq) {
1073                 mlx5e_trigger_irq(rq->icosq);
1074         } else {
1075                 local_bh_disable();
1076                 napi_schedule(rq->cq.napi);
1077                 local_bh_enable();
1078         }
1079 }
1080
1081 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
1082 {
1083         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
1084         synchronize_net(); /* Sync with NAPI to prevent mlx5e_post_rx_wqes. */
1085 }
1086
1087 void mlx5e_close_rq(struct mlx5e_rq *rq)
1088 {
1089         cancel_work_sync(&rq->dim.work);
1090         cancel_work_sync(&rq->recover_work);
1091         mlx5e_destroy_rq(rq);
1092         mlx5e_free_rx_descs(rq);
1093         mlx5e_free_rq(rq);
1094 }
1095
1096 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
1097 {
1098         kvfree(sq->db.xdpi_fifo.xi);
1099         kvfree(sq->db.wqe_info);
1100 }
1101
1102 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
1103 {
1104         struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
1105         int wq_sz        = mlx5_wq_cyc_get_size(&sq->wq);
1106         int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1107         size_t size;
1108
1109         size = array_size(sizeof(*xdpi_fifo->xi), dsegs_per_wq);
1110         xdpi_fifo->xi = kvzalloc_node(size, GFP_KERNEL, numa);
1111         if (!xdpi_fifo->xi)
1112                 return -ENOMEM;
1113
1114         xdpi_fifo->pc   = &sq->xdpi_fifo_pc;
1115         xdpi_fifo->cc   = &sq->xdpi_fifo_cc;
1116         xdpi_fifo->mask = dsegs_per_wq - 1;
1117
1118         return 0;
1119 }
1120
1121 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
1122 {
1123         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1124         size_t size;
1125         int err;
1126
1127         size = array_size(sizeof(*sq->db.wqe_info), wq_sz);
1128         sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1129         if (!sq->db.wqe_info)
1130                 return -ENOMEM;
1131
1132         err = mlx5e_alloc_xdpsq_fifo(sq, numa);
1133         if (err) {
1134                 mlx5e_free_xdpsq_db(sq);
1135                 return err;
1136         }
1137
1138         return 0;
1139 }
1140
1141 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
1142                              struct mlx5e_params *params,
1143                              struct xsk_buff_pool *xsk_pool,
1144                              struct mlx5e_sq_param *param,
1145                              struct mlx5e_xdpsq *sq,
1146                              bool is_redirect)
1147 {
1148         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1149         struct mlx5_core_dev *mdev = c->mdev;
1150         struct mlx5_wq_cyc *wq = &sq->wq;
1151         int err;
1152
1153         sq->pdev      = c->pdev;
1154         sq->mkey_be   = c->mkey_be;
1155         sq->channel   = c;
1156         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1157         sq->min_inline_mode = params->tx_min_inline_mode;
1158         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1159         sq->xsk_pool  = xsk_pool;
1160
1161         sq->stats = sq->xsk_pool ?
1162                 &c->priv->channel_stats[c->ix].xsksq :
1163                 is_redirect ?
1164                         &c->priv->channel_stats[c->ix].xdpsq :
1165                         &c->priv->channel_stats[c->ix].rq_xdpsq;
1166
1167         param->wq.db_numa_node = cpu_to_node(c->cpu);
1168         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1169         if (err)
1170                 return err;
1171         wq->db = &wq->db[MLX5_SND_DBR];
1172
1173         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1174         if (err)
1175                 goto err_sq_wq_destroy;
1176
1177         return 0;
1178
1179 err_sq_wq_destroy:
1180         mlx5_wq_destroy(&sq->wq_ctrl);
1181
1182         return err;
1183 }
1184
1185 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1186 {
1187         mlx5e_free_xdpsq_db(sq);
1188         mlx5_wq_destroy(&sq->wq_ctrl);
1189 }
1190
1191 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1192 {
1193         kvfree(sq->db.wqe_info);
1194 }
1195
1196 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1197 {
1198         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1199         size_t size;
1200
1201         size = array_size(wq_sz, sizeof(*sq->db.wqe_info));
1202         sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1203         if (!sq->db.wqe_info)
1204                 return -ENOMEM;
1205
1206         return 0;
1207 }
1208
1209 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1210 {
1211         struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1212                                               recover_work);
1213
1214         mlx5e_reporter_icosq_cqe_err(sq);
1215 }
1216
1217 static void mlx5e_async_icosq_err_cqe_work(struct work_struct *recover_work)
1218 {
1219         struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1220                                               recover_work);
1221
1222         /* Not implemented yet. */
1223
1224         netdev_warn(sq->channel->netdev, "async_icosq recovery is not implemented\n");
1225 }
1226
1227 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1228                              struct mlx5e_sq_param *param,
1229                              struct mlx5e_icosq *sq,
1230                              work_func_t recover_work_func)
1231 {
1232         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1233         struct mlx5_core_dev *mdev = c->mdev;
1234         struct mlx5_wq_cyc *wq = &sq->wq;
1235         int err;
1236
1237         sq->channel   = c;
1238         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1239         sq->reserved_room = param->stop_room;
1240
1241         param->wq.db_numa_node = cpu_to_node(c->cpu);
1242         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1243         if (err)
1244                 return err;
1245         wq->db = &wq->db[MLX5_SND_DBR];
1246
1247         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1248         if (err)
1249                 goto err_sq_wq_destroy;
1250
1251         INIT_WORK(&sq->recover_work, recover_work_func);
1252
1253         return 0;
1254
1255 err_sq_wq_destroy:
1256         mlx5_wq_destroy(&sq->wq_ctrl);
1257
1258         return err;
1259 }
1260
1261 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1262 {
1263         mlx5e_free_icosq_db(sq);
1264         mlx5_wq_destroy(&sq->wq_ctrl);
1265 }
1266
1267 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1268 {
1269         kvfree(sq->db.wqe_info);
1270         kvfree(sq->db.skb_fifo.fifo);
1271         kvfree(sq->db.dma_fifo);
1272 }
1273
1274 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1275 {
1276         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1277         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1278
1279         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1280                                                    sizeof(*sq->db.dma_fifo)),
1281                                         GFP_KERNEL, numa);
1282         sq->db.skb_fifo.fifo = kvzalloc_node(array_size(df_sz,
1283                                                         sizeof(*sq->db.skb_fifo.fifo)),
1284                                         GFP_KERNEL, numa);
1285         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1286                                                    sizeof(*sq->db.wqe_info)),
1287                                         GFP_KERNEL, numa);
1288         if (!sq->db.dma_fifo || !sq->db.skb_fifo.fifo || !sq->db.wqe_info) {
1289                 mlx5e_free_txqsq_db(sq);
1290                 return -ENOMEM;
1291         }
1292
1293         sq->dma_fifo_mask = df_sz - 1;
1294
1295         sq->db.skb_fifo.pc   = &sq->skb_fifo_pc;
1296         sq->db.skb_fifo.cc   = &sq->skb_fifo_cc;
1297         sq->db.skb_fifo.mask = df_sz - 1;
1298
1299         return 0;
1300 }
1301
1302 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1303                              int txq_ix,
1304                              struct mlx5e_params *params,
1305                              struct mlx5e_sq_param *param,
1306                              struct mlx5e_txqsq *sq,
1307                              int tc)
1308 {
1309         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1310         struct mlx5_core_dev *mdev = c->mdev;
1311         struct mlx5_wq_cyc *wq = &sq->wq;
1312         int err;
1313
1314         sq->pdev      = c->pdev;
1315         sq->tstamp    = c->tstamp;
1316         sq->clock     = &mdev->clock;
1317         sq->mkey_be   = c->mkey_be;
1318         sq->netdev    = c->netdev;
1319         sq->mdev      = c->mdev;
1320         sq->priv      = c->priv;
1321         sq->ch_ix     = c->ix;
1322         sq->txq_ix    = txq_ix;
1323         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1324         sq->min_inline_mode = params->tx_min_inline_mode;
1325         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1326         INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1327         if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1328                 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1329         if (MLX5_IPSEC_DEV(c->priv->mdev))
1330                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1331         if (param->is_mpw)
1332                 set_bit(MLX5E_SQ_STATE_MPWQE, &sq->state);
1333         sq->stop_room = param->stop_room;
1334         sq->ptp_cyc2time = mlx5_sq_ts_translator(mdev);
1335
1336         param->wq.db_numa_node = cpu_to_node(c->cpu);
1337         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1338         if (err)
1339                 return err;
1340         wq->db    = &wq->db[MLX5_SND_DBR];
1341
1342         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1343         if (err)
1344                 goto err_sq_wq_destroy;
1345
1346         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1347         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1348
1349         return 0;
1350
1351 err_sq_wq_destroy:
1352         mlx5_wq_destroy(&sq->wq_ctrl);
1353
1354         return err;
1355 }
1356
1357 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1358 {
1359         mlx5e_free_txqsq_db(sq);
1360         mlx5_wq_destroy(&sq->wq_ctrl);
1361 }
1362
1363 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1364                            struct mlx5e_sq_param *param,
1365                            struct mlx5e_create_sq_param *csp,
1366                            u32 *sqn)
1367 {
1368         u8 ts_format;
1369         void *in;
1370         void *sqc;
1371         void *wq;
1372         int inlen;
1373         int err;
1374
1375         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1376                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1377         in = kvzalloc(inlen, GFP_KERNEL);
1378         if (!in)
1379                 return -ENOMEM;
1380
1381         ts_format = mlx5_is_real_time_sq(mdev) ?
1382                             MLX5_TIMESTAMP_FORMAT_REAL_TIME :
1383                             MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
1384         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1385         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1386
1387         memcpy(sqc, param->sqc, sizeof(param->sqc));
1388         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1389         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1390         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1391         MLX5_SET(sqc,  sqc, ts_cqe_to_dest_cqn, csp->ts_cqe_to_dest_cqn);
1392         MLX5_SET(sqc,  sqc, ts_format, ts_format);
1393
1394
1395         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1396                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1397
1398         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1399         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1400
1401         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1402         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.hw_objs.bfreg.index);
1403         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1404                                           MLX5_ADAPTER_PAGE_SHIFT);
1405         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1406
1407         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1408                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1409
1410         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1411
1412         kvfree(in);
1413
1414         return err;
1415 }
1416
1417 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1418                     struct mlx5e_modify_sq_param *p)
1419 {
1420         u64 bitmask = 0;
1421         void *in;
1422         void *sqc;
1423         int inlen;
1424         int err;
1425
1426         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1427         in = kvzalloc(inlen, GFP_KERNEL);
1428         if (!in)
1429                 return -ENOMEM;
1430
1431         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1432
1433         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1434         MLX5_SET(sqc, sqc, state, p->next_state);
1435         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1436                 bitmask |= 1;
1437                 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1438         }
1439         if (p->qos_update && p->next_state == MLX5_SQC_STATE_RDY) {
1440                 bitmask |= 1 << 2;
1441                 MLX5_SET(sqc, sqc, qos_queue_group_id, p->qos_queue_group_id);
1442         }
1443         MLX5_SET64(modify_sq_in, in, modify_bitmask, bitmask);
1444
1445         err = mlx5_core_modify_sq(mdev, sqn, in);
1446
1447         kvfree(in);
1448
1449         return err;
1450 }
1451
1452 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1453 {
1454         mlx5_core_destroy_sq(mdev, sqn);
1455 }
1456
1457 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1458                         struct mlx5e_sq_param *param,
1459                         struct mlx5e_create_sq_param *csp,
1460                         u16 qos_queue_group_id,
1461                         u32 *sqn)
1462 {
1463         struct mlx5e_modify_sq_param msp = {0};
1464         int err;
1465
1466         err = mlx5e_create_sq(mdev, param, csp, sqn);
1467         if (err)
1468                 return err;
1469
1470         msp.curr_state = MLX5_SQC_STATE_RST;
1471         msp.next_state = MLX5_SQC_STATE_RDY;
1472         if (qos_queue_group_id) {
1473                 msp.qos_update = true;
1474                 msp.qos_queue_group_id = qos_queue_group_id;
1475         }
1476         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1477         if (err)
1478                 mlx5e_destroy_sq(mdev, *sqn);
1479
1480         return err;
1481 }
1482
1483 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1484                                 struct mlx5e_txqsq *sq, u32 rate);
1485
1486 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1487                      struct mlx5e_params *params, struct mlx5e_sq_param *param,
1488                      struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id,
1489                      struct mlx5e_sq_stats *sq_stats)
1490 {
1491         struct mlx5e_create_sq_param csp = {};
1492         u32 tx_rate;
1493         int err;
1494
1495         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1496         if (err)
1497                 return err;
1498
1499         sq->stats = sq_stats;
1500
1501         csp.tisn            = tisn;
1502         csp.tis_lst_sz      = 1;
1503         csp.cqn             = sq->cq.mcq.cqn;
1504         csp.wq_ctrl         = &sq->wq_ctrl;
1505         csp.min_inline_mode = sq->min_inline_mode;
1506         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, qos_queue_group_id, &sq->sqn);
1507         if (err)
1508                 goto err_free_txqsq;
1509
1510         tx_rate = c->priv->tx_rates[sq->txq_ix];
1511         if (tx_rate)
1512                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1513
1514         if (params->tx_dim_enabled)
1515                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1516
1517         return 0;
1518
1519 err_free_txqsq:
1520         mlx5e_free_txqsq(sq);
1521
1522         return err;
1523 }
1524
1525 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1526 {
1527         sq->txq = netdev_get_tx_queue(sq->netdev, sq->txq_ix);
1528         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1529         netdev_tx_reset_queue(sq->txq);
1530         netif_tx_start_queue(sq->txq);
1531 }
1532
1533 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1534 {
1535         __netif_tx_lock_bh(txq);
1536         netif_tx_stop_queue(txq);
1537         __netif_tx_unlock_bh(txq);
1538 }
1539
1540 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1541 {
1542         struct mlx5_wq_cyc *wq = &sq->wq;
1543
1544         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1545         synchronize_net(); /* Sync with NAPI to prevent netif_tx_wake_queue. */
1546
1547         mlx5e_tx_disable_queue(sq->txq);
1548
1549         /* last doorbell out, godspeed .. */
1550         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1551                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1552                 struct mlx5e_tx_wqe *nop;
1553
1554                 sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) {
1555                         .num_wqebbs = 1,
1556                 };
1557
1558                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1559                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1560         }
1561 }
1562
1563 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1564 {
1565         struct mlx5_core_dev *mdev = sq->mdev;
1566         struct mlx5_rate_limit rl = {0};
1567
1568         cancel_work_sync(&sq->dim.work);
1569         cancel_work_sync(&sq->recover_work);
1570         mlx5e_destroy_sq(mdev, sq->sqn);
1571         if (sq->rate_limit) {
1572                 rl.rate = sq->rate_limit;
1573                 mlx5_rl_remove_rate(mdev, &rl);
1574         }
1575         mlx5e_free_txqsq_descs(sq);
1576         mlx5e_free_txqsq(sq);
1577 }
1578
1579 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1580 {
1581         struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1582                                               recover_work);
1583
1584         mlx5e_reporter_tx_err_cqe(sq);
1585 }
1586
1587 static int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1588                             struct mlx5e_sq_param *param, struct mlx5e_icosq *sq,
1589                             work_func_t recover_work_func)
1590 {
1591         struct mlx5e_create_sq_param csp = {};
1592         int err;
1593
1594         err = mlx5e_alloc_icosq(c, param, sq, recover_work_func);
1595         if (err)
1596                 return err;
1597
1598         csp.cqn             = sq->cq.mcq.cqn;
1599         csp.wq_ctrl         = &sq->wq_ctrl;
1600         csp.min_inline_mode = params->tx_min_inline_mode;
1601         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1602         if (err)
1603                 goto err_free_icosq;
1604
1605         if (param->is_tls) {
1606                 sq->ktls_resync = mlx5e_ktls_rx_resync_create_resp_list();
1607                 if (IS_ERR(sq->ktls_resync)) {
1608                         err = PTR_ERR(sq->ktls_resync);
1609                         goto err_destroy_icosq;
1610                 }
1611         }
1612         return 0;
1613
1614 err_destroy_icosq:
1615         mlx5e_destroy_sq(c->mdev, sq->sqn);
1616 err_free_icosq:
1617         mlx5e_free_icosq(sq);
1618
1619         return err;
1620 }
1621
1622 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1623 {
1624         set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1625 }
1626
1627 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1628 {
1629         clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1630         synchronize_net(); /* Sync with NAPI. */
1631 }
1632
1633 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1634 {
1635         struct mlx5e_channel *c = sq->channel;
1636
1637         if (sq->ktls_resync)
1638                 mlx5e_ktls_rx_resync_destroy_resp_list(sq->ktls_resync);
1639         mlx5e_destroy_sq(c->mdev, sq->sqn);
1640         mlx5e_free_icosq_descs(sq);
1641         mlx5e_free_icosq(sq);
1642 }
1643
1644 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1645                      struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
1646                      struct mlx5e_xdpsq *sq, bool is_redirect)
1647 {
1648         struct mlx5e_create_sq_param csp = {};
1649         int err;
1650
1651         err = mlx5e_alloc_xdpsq(c, params, xsk_pool, param, sq, is_redirect);
1652         if (err)
1653                 return err;
1654
1655         csp.tis_lst_sz      = 1;
1656         csp.tisn            = c->priv->tisn[c->lag_port][0]; /* tc = 0 */
1657         csp.cqn             = sq->cq.mcq.cqn;
1658         csp.wq_ctrl         = &sq->wq_ctrl;
1659         csp.min_inline_mode = sq->min_inline_mode;
1660         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1661         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1662         if (err)
1663                 goto err_free_xdpsq;
1664
1665         mlx5e_set_xmit_fp(sq, param->is_mpw);
1666
1667         if (!param->is_mpw) {
1668                 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1669                 unsigned int inline_hdr_sz = 0;
1670                 int i;
1671
1672                 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1673                         inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1674                         ds_cnt++;
1675                 }
1676
1677                 /* Pre initialize fixed WQE fields */
1678                 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1679                         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1680                         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1681                         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1682                         struct mlx5_wqe_data_seg *dseg;
1683
1684                         sq->db.wqe_info[i] = (struct mlx5e_xdp_wqe_info) {
1685                                 .num_wqebbs = 1,
1686                                 .num_pkts   = 1,
1687                         };
1688
1689                         cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1690                         eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1691
1692                         dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1693                         dseg->lkey = sq->mkey_be;
1694                 }
1695         }
1696
1697         return 0;
1698
1699 err_free_xdpsq:
1700         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1701         mlx5e_free_xdpsq(sq);
1702
1703         return err;
1704 }
1705
1706 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1707 {
1708         struct mlx5e_channel *c = sq->channel;
1709
1710         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1711         synchronize_net(); /* Sync with NAPI. */
1712
1713         mlx5e_destroy_sq(c->mdev, sq->sqn);
1714         mlx5e_free_xdpsq_descs(sq);
1715         mlx5e_free_xdpsq(sq);
1716 }
1717
1718 static int mlx5e_alloc_cq_common(struct mlx5e_priv *priv,
1719                                  struct mlx5e_cq_param *param,
1720                                  struct mlx5e_cq *cq)
1721 {
1722         struct mlx5_core_dev *mdev = priv->mdev;
1723         struct mlx5_core_cq *mcq = &cq->mcq;
1724         int err;
1725         u32 i;
1726
1727         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1728                                &cq->wq_ctrl);
1729         if (err)
1730                 return err;
1731
1732         mcq->cqe_sz     = 64;
1733         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1734         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1735         *mcq->set_ci_db = 0;
1736         *mcq->arm_db    = 0;
1737         mcq->vector     = param->eq_ix;
1738         mcq->comp       = mlx5e_completion_event;
1739         mcq->event      = mlx5e_cq_error_event;
1740
1741         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1742                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1743
1744                 cqe->op_own = 0xf1;
1745         }
1746
1747         cq->mdev = mdev;
1748         cq->netdev = priv->netdev;
1749         cq->priv = priv;
1750
1751         return 0;
1752 }
1753
1754 static int mlx5e_alloc_cq(struct mlx5e_priv *priv,
1755                           struct mlx5e_cq_param *param,
1756                           struct mlx5e_create_cq_param *ccp,
1757                           struct mlx5e_cq *cq)
1758 {
1759         int err;
1760
1761         param->wq.buf_numa_node = ccp->node;
1762         param->wq.db_numa_node  = ccp->node;
1763         param->eq_ix            = ccp->ix;
1764
1765         err = mlx5e_alloc_cq_common(priv, param, cq);
1766
1767         cq->napi     = ccp->napi;
1768         cq->ch_stats = ccp->ch_stats;
1769
1770         return err;
1771 }
1772
1773 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1774 {
1775         mlx5_wq_destroy(&cq->wq_ctrl);
1776 }
1777
1778 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1779 {
1780         u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1781         struct mlx5_core_dev *mdev = cq->mdev;
1782         struct mlx5_core_cq *mcq = &cq->mcq;
1783
1784         void *in;
1785         void *cqc;
1786         int inlen;
1787         int eqn;
1788         int err;
1789
1790         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn);
1791         if (err)
1792                 return err;
1793
1794         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1795                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1796         in = kvzalloc(inlen, GFP_KERNEL);
1797         if (!in)
1798                 return -ENOMEM;
1799
1800         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1801
1802         memcpy(cqc, param->cqc, sizeof(param->cqc));
1803
1804         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1805                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1806
1807         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1808         MLX5_SET(cqc,   cqc, c_eqn_or_apu_element, eqn);
1809         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1810         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1811                                             MLX5_ADAPTER_PAGE_SHIFT);
1812         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1813
1814         err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1815
1816         kvfree(in);
1817
1818         if (err)
1819                 return err;
1820
1821         mlx5e_cq_arm(cq);
1822
1823         return 0;
1824 }
1825
1826 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1827 {
1828         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1829 }
1830
1831 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder,
1832                   struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
1833                   struct mlx5e_cq *cq)
1834 {
1835         struct mlx5_core_dev *mdev = priv->mdev;
1836         int err;
1837
1838         err = mlx5e_alloc_cq(priv, param, ccp, cq);
1839         if (err)
1840                 return err;
1841
1842         err = mlx5e_create_cq(cq, param);
1843         if (err)
1844                 goto err_free_cq;
1845
1846         if (MLX5_CAP_GEN(mdev, cq_moderation))
1847                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1848         return 0;
1849
1850 err_free_cq:
1851         mlx5e_free_cq(cq);
1852
1853         return err;
1854 }
1855
1856 void mlx5e_close_cq(struct mlx5e_cq *cq)
1857 {
1858         mlx5e_destroy_cq(cq);
1859         mlx5e_free_cq(cq);
1860 }
1861
1862 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1863                              struct mlx5e_params *params,
1864                              struct mlx5e_create_cq_param *ccp,
1865                              struct mlx5e_channel_param *cparam)
1866 {
1867         int err;
1868         int tc;
1869
1870         for (tc = 0; tc < c->num_tc; tc++) {
1871                 err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->txq_sq.cqp,
1872                                     ccp, &c->sq[tc].cq);
1873                 if (err)
1874                         goto err_close_tx_cqs;
1875         }
1876
1877         return 0;
1878
1879 err_close_tx_cqs:
1880         for (tc--; tc >= 0; tc--)
1881                 mlx5e_close_cq(&c->sq[tc].cq);
1882
1883         return err;
1884 }
1885
1886 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1887 {
1888         int tc;
1889
1890         for (tc = 0; tc < c->num_tc; tc++)
1891                 mlx5e_close_cq(&c->sq[tc].cq);
1892 }
1893
1894 static int mlx5e_mqprio_txq_to_tc(struct netdev_tc_txq *tc_to_txq, unsigned int txq)
1895 {
1896         int tc;
1897
1898         for (tc = 0; tc < TC_MAX_QUEUE; tc++)
1899                 if (txq - tc_to_txq[tc].offset < tc_to_txq[tc].count)
1900                         return tc;
1901
1902         WARN(1, "Unexpected TCs configuration. No match found for txq %u", txq);
1903         return -ENOENT;
1904 }
1905
1906 static int mlx5e_txq_get_qos_node_hw_id(struct mlx5e_params *params, int txq_ix,
1907                                         u32 *hw_id)
1908 {
1909         int tc;
1910
1911         if (params->mqprio.mode != TC_MQPRIO_MODE_CHANNEL ||
1912             !params->mqprio.channel.rl) {
1913                 *hw_id = 0;
1914                 return 0;
1915         }
1916
1917         tc = mlx5e_mqprio_txq_to_tc(params->mqprio.tc_to_txq, txq_ix);
1918         if (tc < 0)
1919                 return tc;
1920
1921         return mlx5e_mqprio_rl_get_node_hw_id(params->mqprio.channel.rl, tc, hw_id);
1922 }
1923
1924 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1925                           struct mlx5e_params *params,
1926                           struct mlx5e_channel_param *cparam)
1927 {
1928         int err, tc;
1929
1930         for (tc = 0; tc < mlx5e_get_dcb_num_tc(params); tc++) {
1931                 int txq_ix = c->ix + tc * params->num_channels;
1932                 u32 qos_queue_group_id;
1933
1934                 err = mlx5e_txq_get_qos_node_hw_id(params, txq_ix, &qos_queue_group_id);
1935                 if (err)
1936                         goto err_close_sqs;
1937
1938                 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
1939                                        params, &cparam->txq_sq, &c->sq[tc], tc,
1940                                        qos_queue_group_id,
1941                                        &c->priv->channel_stats[c->ix].sq[tc]);
1942                 if (err)
1943                         goto err_close_sqs;
1944         }
1945
1946         return 0;
1947
1948 err_close_sqs:
1949         for (tc--; tc >= 0; tc--)
1950                 mlx5e_close_txqsq(&c->sq[tc]);
1951
1952         return err;
1953 }
1954
1955 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1956 {
1957         int tc;
1958
1959         for (tc = 0; tc < c->num_tc; tc++)
1960                 mlx5e_close_txqsq(&c->sq[tc]);
1961 }
1962
1963 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1964                                 struct mlx5e_txqsq *sq, u32 rate)
1965 {
1966         struct mlx5e_priv *priv = netdev_priv(dev);
1967         struct mlx5_core_dev *mdev = priv->mdev;
1968         struct mlx5e_modify_sq_param msp = {0};
1969         struct mlx5_rate_limit rl = {0};
1970         u16 rl_index = 0;
1971         int err;
1972
1973         if (rate == sq->rate_limit)
1974                 /* nothing to do */
1975                 return 0;
1976
1977         if (sq->rate_limit) {
1978                 rl.rate = sq->rate_limit;
1979                 /* remove current rl index to free space to next ones */
1980                 mlx5_rl_remove_rate(mdev, &rl);
1981         }
1982
1983         sq->rate_limit = 0;
1984
1985         if (rate) {
1986                 rl.rate = rate;
1987                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1988                 if (err) {
1989                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1990                                    rate, err);
1991                         return err;
1992                 }
1993         }
1994
1995         msp.curr_state = MLX5_SQC_STATE_RDY;
1996         msp.next_state = MLX5_SQC_STATE_RDY;
1997         msp.rl_index   = rl_index;
1998         msp.rl_update  = true;
1999         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
2000         if (err) {
2001                 netdev_err(dev, "Failed configuring rate %u: %d\n",
2002                            rate, err);
2003                 /* remove the rate from the table */
2004                 if (rate)
2005                         mlx5_rl_remove_rate(mdev, &rl);
2006                 return err;
2007         }
2008
2009         sq->rate_limit = rate;
2010         return 0;
2011 }
2012
2013 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
2014 {
2015         struct mlx5e_priv *priv = netdev_priv(dev);
2016         struct mlx5_core_dev *mdev = priv->mdev;
2017         struct mlx5e_txqsq *sq = priv->txq2sq[index];
2018         int err = 0;
2019
2020         if (!mlx5_rl_is_supported(mdev)) {
2021                 netdev_err(dev, "Rate limiting is not supported on this device\n");
2022                 return -EINVAL;
2023         }
2024
2025         /* rate is given in Mb/sec, HW config is in Kb/sec */
2026         rate = rate << 10;
2027
2028         /* Check whether rate in valid range, 0 is always valid */
2029         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
2030                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
2031                 return -ERANGE;
2032         }
2033
2034         mutex_lock(&priv->state_lock);
2035         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
2036                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
2037         if (!err)
2038                 priv->tx_rates[index] = rate;
2039         mutex_unlock(&priv->state_lock);
2040
2041         return err;
2042 }
2043
2044 static int mlx5e_open_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
2045                              struct mlx5e_rq_param *rq_params)
2046 {
2047         int err;
2048
2049         err = mlx5e_init_rxq_rq(c, params, &c->rq);
2050         if (err)
2051                 return err;
2052
2053         return mlx5e_open_rq(params, rq_params, NULL, cpu_to_node(c->cpu), &c->rq);
2054 }
2055
2056 static int mlx5e_open_queues(struct mlx5e_channel *c,
2057                              struct mlx5e_params *params,
2058                              struct mlx5e_channel_param *cparam)
2059 {
2060         struct dim_cq_moder icocq_moder = {0, 0};
2061         struct mlx5e_create_cq_param ccp;
2062         int err;
2063
2064         mlx5e_build_create_cq_param(&ccp, c);
2065
2066         err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->async_icosq.cqp, &ccp,
2067                             &c->async_icosq.cq);
2068         if (err)
2069                 return err;
2070
2071         err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->icosq.cqp, &ccp,
2072                             &c->icosq.cq);
2073         if (err)
2074                 goto err_close_async_icosq_cq;
2075
2076         err = mlx5e_open_tx_cqs(c, params, &ccp, cparam);
2077         if (err)
2078                 goto err_close_icosq_cq;
2079
2080         err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp, &ccp,
2081                             &c->xdpsq.cq);
2082         if (err)
2083                 goto err_close_tx_cqs;
2084
2085         err = mlx5e_open_cq(c->priv, params->rx_cq_moderation, &cparam->rq.cqp, &ccp,
2086                             &c->rq.cq);
2087         if (err)
2088                 goto err_close_xdp_tx_cqs;
2089
2090         err = c->xdp ? mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp,
2091                                      &ccp, &c->rq_xdpsq.cq) : 0;
2092         if (err)
2093                 goto err_close_rx_cq;
2094
2095         spin_lock_init(&c->async_icosq_lock);
2096
2097         err = mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq,
2098                                mlx5e_async_icosq_err_cqe_work);
2099         if (err)
2100                 goto err_close_xdpsq_cq;
2101
2102         mutex_init(&c->icosq_recovery_lock);
2103
2104         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq,
2105                                mlx5e_icosq_err_cqe_work);
2106         if (err)
2107                 goto err_close_async_icosq;
2108
2109         err = mlx5e_open_sqs(c, params, cparam);
2110         if (err)
2111                 goto err_close_icosq;
2112
2113         err = mlx5e_open_rxq_rq(c, params, &cparam->rq);
2114         if (err)
2115                 goto err_close_sqs;
2116
2117         if (c->xdp) {
2118                 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
2119                                        &c->rq_xdpsq, false);
2120                 if (err)
2121                         goto err_close_rq;
2122         }
2123
2124         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
2125         if (err)
2126                 goto err_close_xdp_sq;
2127
2128         return 0;
2129
2130 err_close_xdp_sq:
2131         if (c->xdp)
2132                 mlx5e_close_xdpsq(&c->rq_xdpsq);
2133
2134 err_close_rq:
2135         mlx5e_close_rq(&c->rq);
2136
2137 err_close_sqs:
2138         mlx5e_close_sqs(c);
2139
2140 err_close_icosq:
2141         mlx5e_close_icosq(&c->icosq);
2142
2143 err_close_async_icosq:
2144         mlx5e_close_icosq(&c->async_icosq);
2145
2146 err_close_xdpsq_cq:
2147         if (c->xdp)
2148                 mlx5e_close_cq(&c->rq_xdpsq.cq);
2149
2150 err_close_rx_cq:
2151         mlx5e_close_cq(&c->rq.cq);
2152
2153 err_close_xdp_tx_cqs:
2154         mlx5e_close_cq(&c->xdpsq.cq);
2155
2156 err_close_tx_cqs:
2157         mlx5e_close_tx_cqs(c);
2158
2159 err_close_icosq_cq:
2160         mlx5e_close_cq(&c->icosq.cq);
2161
2162 err_close_async_icosq_cq:
2163         mlx5e_close_cq(&c->async_icosq.cq);
2164
2165         return err;
2166 }
2167
2168 static void mlx5e_close_queues(struct mlx5e_channel *c)
2169 {
2170         mlx5e_close_xdpsq(&c->xdpsq);
2171         if (c->xdp)
2172                 mlx5e_close_xdpsq(&c->rq_xdpsq);
2173         /* The same ICOSQ is used for UMRs for both RQ and XSKRQ. */
2174         cancel_work_sync(&c->icosq.recover_work);
2175         mlx5e_close_rq(&c->rq);
2176         mlx5e_close_sqs(c);
2177         mlx5e_close_icosq(&c->icosq);
2178         mutex_destroy(&c->icosq_recovery_lock);
2179         mlx5e_close_icosq(&c->async_icosq);
2180         if (c->xdp)
2181                 mlx5e_close_cq(&c->rq_xdpsq.cq);
2182         mlx5e_close_cq(&c->rq.cq);
2183         mlx5e_close_cq(&c->xdpsq.cq);
2184         mlx5e_close_tx_cqs(c);
2185         mlx5e_close_cq(&c->icosq.cq);
2186         mlx5e_close_cq(&c->async_icosq.cq);
2187 }
2188
2189 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
2190 {
2191         u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
2192
2193         return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
2194 }
2195
2196 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
2197                               struct mlx5e_params *params,
2198                               struct mlx5e_channel_param *cparam,
2199                               struct xsk_buff_pool *xsk_pool,
2200                               struct mlx5e_channel **cp)
2201 {
2202         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
2203         struct net_device *netdev = priv->netdev;
2204         struct mlx5e_xsk_param xsk;
2205         struct mlx5e_channel *c;
2206         unsigned int irq;
2207         int err;
2208
2209         err = mlx5_vector2irqn(priv->mdev, ix, &irq);
2210         if (err)
2211                 return err;
2212
2213         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
2214         if (!c)
2215                 return -ENOMEM;
2216
2217         c->priv     = priv;
2218         c->mdev     = priv->mdev;
2219         c->tstamp   = &priv->tstamp;
2220         c->ix       = ix;
2221         c->cpu      = cpu;
2222         c->pdev     = mlx5_core_dma_dev(priv->mdev);
2223         c->netdev   = priv->netdev;
2224         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.hw_objs.mkey);
2225         c->num_tc   = mlx5e_get_dcb_num_tc(params);
2226         c->xdp      = !!params->xdp_prog;
2227         c->stats    = &priv->channel_stats[ix].ch;
2228         c->aff_mask = irq_get_effective_affinity_mask(irq);
2229         c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix);
2230
2231         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
2232
2233         err = mlx5e_open_queues(c, params, cparam);
2234         if (unlikely(err))
2235                 goto err_napi_del;
2236
2237         if (xsk_pool) {
2238                 mlx5e_build_xsk_param(xsk_pool, &xsk);
2239                 err = mlx5e_open_xsk(priv, params, &xsk, xsk_pool, c);
2240                 if (unlikely(err))
2241                         goto err_close_queues;
2242         }
2243
2244         *cp = c;
2245
2246         return 0;
2247
2248 err_close_queues:
2249         mlx5e_close_queues(c);
2250
2251 err_napi_del:
2252         netif_napi_del(&c->napi);
2253
2254         kvfree(c);
2255
2256         return err;
2257 }
2258
2259 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2260 {
2261         int tc;
2262
2263         napi_enable(&c->napi);
2264
2265         for (tc = 0; tc < c->num_tc; tc++)
2266                 mlx5e_activate_txqsq(&c->sq[tc]);
2267         mlx5e_activate_icosq(&c->icosq);
2268         mlx5e_activate_icosq(&c->async_icosq);
2269         mlx5e_activate_rq(&c->rq);
2270
2271         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2272                 mlx5e_activate_xsk(c);
2273 }
2274
2275 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2276 {
2277         int tc;
2278
2279         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2280                 mlx5e_deactivate_xsk(c);
2281
2282         mlx5e_deactivate_rq(&c->rq);
2283         mlx5e_deactivate_icosq(&c->async_icosq);
2284         mlx5e_deactivate_icosq(&c->icosq);
2285         for (tc = 0; tc < c->num_tc; tc++)
2286                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2287         mlx5e_qos_deactivate_queues(c);
2288
2289         napi_disable(&c->napi);
2290 }
2291
2292 static void mlx5e_close_channel(struct mlx5e_channel *c)
2293 {
2294         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2295                 mlx5e_close_xsk(c);
2296         mlx5e_close_queues(c);
2297         mlx5e_qos_close_queues(c);
2298         netif_napi_del(&c->napi);
2299
2300         kvfree(c);
2301 }
2302
2303 int mlx5e_open_channels(struct mlx5e_priv *priv,
2304                         struct mlx5e_channels *chs)
2305 {
2306         struct mlx5e_channel_param *cparam;
2307         int err = -ENOMEM;
2308         int i;
2309
2310         chs->num = chs->params.num_channels;
2311
2312         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2313         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2314         if (!chs->c || !cparam)
2315                 goto err_free;
2316
2317         err = mlx5e_build_channel_param(priv->mdev, &chs->params, priv->q_counter, cparam);
2318         if (err)
2319                 goto err_free;
2320
2321         for (i = 0; i < chs->num; i++) {
2322                 struct xsk_buff_pool *xsk_pool = NULL;
2323
2324                 if (chs->params.xdp_prog)
2325                         xsk_pool = mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, i);
2326
2327                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, xsk_pool, &chs->c[i]);
2328                 if (err)
2329                         goto err_close_channels;
2330         }
2331
2332         if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS) || chs->params.ptp_rx) {
2333                 err = mlx5e_ptp_open(priv, &chs->params, chs->c[0]->lag_port, &chs->ptp);
2334                 if (err)
2335                         goto err_close_channels;
2336         }
2337
2338         err = mlx5e_qos_open_queues(priv, chs);
2339         if (err)
2340                 goto err_close_ptp;
2341
2342         mlx5e_health_channels_update(priv);
2343         kvfree(cparam);
2344         return 0;
2345
2346 err_close_ptp:
2347         if (chs->ptp)
2348                 mlx5e_ptp_close(chs->ptp);
2349
2350 err_close_channels:
2351         for (i--; i >= 0; i--)
2352                 mlx5e_close_channel(chs->c[i]);
2353
2354 err_free:
2355         kfree(chs->c);
2356         kvfree(cparam);
2357         chs->num = 0;
2358         return err;
2359 }
2360
2361 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2362 {
2363         int i;
2364
2365         for (i = 0; i < chs->num; i++)
2366                 mlx5e_activate_channel(chs->c[i]);
2367
2368         if (chs->ptp)
2369                 mlx5e_ptp_activate_channel(chs->ptp);
2370 }
2371
2372 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2373
2374 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2375 {
2376         int err = 0;
2377         int i;
2378
2379         for (i = 0; i < chs->num; i++) {
2380                 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2381
2382                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2383
2384                 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2385                  * doesn't provide any Fill Ring entries at the setup stage.
2386                  */
2387         }
2388
2389         return err ? -ETIMEDOUT : 0;
2390 }
2391
2392 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2393 {
2394         int i;
2395
2396         if (chs->ptp)
2397                 mlx5e_ptp_deactivate_channel(chs->ptp);
2398
2399         for (i = 0; i < chs->num; i++)
2400                 mlx5e_deactivate_channel(chs->c[i]);
2401 }
2402
2403 void mlx5e_close_channels(struct mlx5e_channels *chs)
2404 {
2405         int i;
2406
2407         if (chs->ptp) {
2408                 mlx5e_ptp_close(chs->ptp);
2409                 chs->ptp = NULL;
2410         }
2411         for (i = 0; i < chs->num; i++)
2412                 mlx5e_close_channel(chs->c[i]);
2413
2414         kfree(chs->c);
2415         chs->num = 0;
2416 }
2417
2418 static int mlx5e_modify_tirs_packet_merge(struct mlx5e_priv *priv)
2419 {
2420         struct mlx5e_rx_res *res = priv->rx_res;
2421
2422         return mlx5e_rx_res_packet_merge_set_param(res, &priv->channels.params.packet_merge);
2423 }
2424
2425 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_packet_merge);
2426
2427 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2428                          struct mlx5e_params *params, u16 mtu)
2429 {
2430         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2431         int err;
2432
2433         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2434         if (err)
2435                 return err;
2436
2437         /* Update vport context MTU */
2438         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2439         return 0;
2440 }
2441
2442 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2443                             struct mlx5e_params *params, u16 *mtu)
2444 {
2445         u16 hw_mtu = 0;
2446         int err;
2447
2448         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2449         if (err || !hw_mtu) /* fallback to port oper mtu */
2450                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2451
2452         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2453 }
2454
2455 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2456 {
2457         struct mlx5e_params *params = &priv->channels.params;
2458         struct net_device *netdev = priv->netdev;
2459         struct mlx5_core_dev *mdev = priv->mdev;
2460         u16 mtu;
2461         int err;
2462
2463         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2464         if (err)
2465                 return err;
2466
2467         mlx5e_query_mtu(mdev, params, &mtu);
2468         if (mtu != params->sw_mtu)
2469                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2470                             __func__, mtu, params->sw_mtu);
2471
2472         params->sw_mtu = mtu;
2473         return 0;
2474 }
2475
2476 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu);
2477
2478 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2479 {
2480         struct mlx5e_params *params = &priv->channels.params;
2481         struct net_device *netdev   = priv->netdev;
2482         struct mlx5_core_dev *mdev  = priv->mdev;
2483         u16 max_mtu;
2484
2485         /* MTU range: 68 - hw-specific max */
2486         netdev->min_mtu = ETH_MIN_MTU;
2487
2488         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2489         netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2490                                 ETH_MAX_MTU);
2491 }
2492
2493 static int mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc,
2494                                 struct netdev_tc_txq *tc_to_txq)
2495 {
2496         int tc, err;
2497
2498         netdev_reset_tc(netdev);
2499
2500         if (ntc == 1)
2501                 return 0;
2502
2503         err = netdev_set_num_tc(netdev, ntc);
2504         if (err) {
2505                 netdev_WARN(netdev, "netdev_set_num_tc failed (%d), ntc = %d\n", err, ntc);
2506                 return err;
2507         }
2508
2509         for (tc = 0; tc < ntc; tc++) {
2510                 u16 count, offset;
2511
2512                 count = tc_to_txq[tc].count;
2513                 offset = tc_to_txq[tc].offset;
2514                 netdev_set_tc_queue(netdev, tc, count, offset);
2515         }
2516
2517         return 0;
2518 }
2519
2520 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv)
2521 {
2522         int qos_queues, nch, ntc, num_txqs, err;
2523
2524         qos_queues = mlx5e_qos_cur_leaf_nodes(priv);
2525
2526         nch = priv->channels.params.num_channels;
2527         ntc = mlx5e_get_dcb_num_tc(&priv->channels.params);
2528         num_txqs = nch * ntc + qos_queues;
2529         if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_TX_PORT_TS))
2530                 num_txqs += ntc;
2531
2532         mlx5e_dbg(DRV, priv, "Setting num_txqs %d\n", num_txqs);
2533         err = netif_set_real_num_tx_queues(priv->netdev, num_txqs);
2534         if (err)
2535                 netdev_warn(priv->netdev, "netif_set_real_num_tx_queues failed, %d\n", err);
2536
2537         return err;
2538 }
2539
2540 static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv)
2541 {
2542         struct netdev_tc_txq old_tc_to_txq[TC_MAX_QUEUE], *tc_to_txq;
2543         struct net_device *netdev = priv->netdev;
2544         int old_num_txqs, old_ntc;
2545         int num_rxqs, nch, ntc;
2546         int err;
2547         int i;
2548
2549         old_num_txqs = netdev->real_num_tx_queues;
2550         old_ntc = netdev->num_tc ? : 1;
2551         for (i = 0; i < ARRAY_SIZE(old_tc_to_txq); i++)
2552                 old_tc_to_txq[i] = netdev->tc_to_txq[i];
2553
2554         nch = priv->channels.params.num_channels;
2555         ntc = priv->channels.params.mqprio.num_tc;
2556         num_rxqs = nch * priv->profile->rq_groups;
2557         tc_to_txq = priv->channels.params.mqprio.tc_to_txq;
2558
2559         err = mlx5e_netdev_set_tcs(netdev, nch, ntc, tc_to_txq);
2560         if (err)
2561                 goto err_out;
2562         err = mlx5e_update_tx_netdev_queues(priv);
2563         if (err)
2564                 goto err_tcs;
2565         err = netif_set_real_num_rx_queues(netdev, num_rxqs);
2566         if (err) {
2567                 netdev_warn(netdev, "netif_set_real_num_rx_queues failed, %d\n", err);
2568                 goto err_txqs;
2569         }
2570         if (priv->mqprio_rl != priv->channels.params.mqprio.channel.rl) {
2571                 if (priv->mqprio_rl) {
2572                         mlx5e_mqprio_rl_cleanup(priv->mqprio_rl);
2573                         mlx5e_mqprio_rl_free(priv->mqprio_rl);
2574                 }
2575                 priv->mqprio_rl = priv->channels.params.mqprio.channel.rl;
2576         }
2577
2578         return 0;
2579
2580 err_txqs:
2581         /* netif_set_real_num_rx_queues could fail only when nch increased. Only
2582          * one of nch and ntc is changed in this function. That means, the call
2583          * to netif_set_real_num_tx_queues below should not fail, because it
2584          * decreases the number of TX queues.
2585          */
2586         WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs));
2587
2588 err_tcs:
2589         WARN_ON_ONCE(mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc,
2590                                           old_tc_to_txq));
2591 err_out:
2592         return err;
2593 }
2594
2595 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_update_netdev_queues);
2596
2597 static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv,
2598                                            struct mlx5e_params *params)
2599 {
2600         struct mlx5_core_dev *mdev = priv->mdev;
2601         int num_comp_vectors, ix, irq;
2602
2603         num_comp_vectors = mlx5_comp_vectors_count(mdev);
2604
2605         for (ix = 0; ix < params->num_channels; ix++) {
2606                 cpumask_clear(priv->scratchpad.cpumask);
2607
2608                 for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) {
2609                         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(mdev, irq));
2610
2611                         cpumask_set_cpu(cpu, priv->scratchpad.cpumask);
2612                 }
2613
2614                 netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix);
2615         }
2616 }
2617
2618 int mlx5e_num_channels_changed(struct mlx5e_priv *priv)
2619 {
2620         u16 count = priv->channels.params.num_channels;
2621         int err;
2622
2623         err = mlx5e_update_netdev_queues(priv);
2624         if (err)
2625                 return err;
2626
2627         mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params);
2628
2629         /* This function may be called on attach, before priv->rx_res is created. */
2630         if (!netif_is_rxfh_configured(priv->netdev) && priv->rx_res)
2631                 mlx5e_rx_res_rss_set_indir_uniform(priv->rx_res, count);
2632
2633         return 0;
2634 }
2635
2636 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed);
2637
2638 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv)
2639 {
2640         int i, ch, tc, num_tc;
2641
2642         ch = priv->channels.num;
2643         num_tc = mlx5e_get_dcb_num_tc(&priv->channels.params);
2644
2645         for (i = 0; i < ch; i++) {
2646                 for (tc = 0; tc < num_tc; tc++) {
2647                         struct mlx5e_channel *c = priv->channels.c[i];
2648                         struct mlx5e_txqsq *sq = &c->sq[tc];
2649
2650                         priv->txq2sq[sq->txq_ix] = sq;
2651                         priv->channel_tc2realtxq[i][tc] = i + tc * ch;
2652                 }
2653         }
2654
2655         if (!priv->channels.ptp)
2656                 return;
2657
2658         if (!test_bit(MLX5E_PTP_STATE_TX, priv->channels.ptp->state))
2659                 return;
2660
2661         for (tc = 0; tc < num_tc; tc++) {
2662                 struct mlx5e_ptp *c = priv->channels.ptp;
2663                 struct mlx5e_txqsq *sq = &c->ptpsq[tc].txqsq;
2664
2665                 priv->txq2sq[sq->txq_ix] = sq;
2666                 priv->port_ptp_tc2realtxq[tc] = priv->num_tc_x_num_ch + tc;
2667         }
2668 }
2669
2670 static void mlx5e_update_num_tc_x_num_ch(struct mlx5e_priv *priv)
2671 {
2672         /* Sync with mlx5e_select_queue. */
2673         WRITE_ONCE(priv->num_tc_x_num_ch,
2674                    mlx5e_get_dcb_num_tc(&priv->channels.params) * priv->channels.num);
2675 }
2676
2677 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2678 {
2679         mlx5e_update_num_tc_x_num_ch(priv);
2680         mlx5e_build_txq_maps(priv);
2681         mlx5e_activate_channels(&priv->channels);
2682         mlx5e_qos_activate_queues(priv);
2683         mlx5e_xdp_tx_enable(priv);
2684         netif_tx_start_all_queues(priv->netdev);
2685
2686         if (mlx5e_is_vport_rep(priv))
2687                 mlx5e_add_sqs_fwd_rules(priv);
2688
2689         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2690
2691         if (priv->rx_res)
2692                 mlx5e_rx_res_channels_activate(priv->rx_res, &priv->channels);
2693 }
2694
2695 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2696 {
2697         if (priv->rx_res)
2698                 mlx5e_rx_res_channels_deactivate(priv->rx_res);
2699
2700         if (mlx5e_is_vport_rep(priv))
2701                 mlx5e_remove_sqs_fwd_rules(priv);
2702
2703         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2704          * polling for inactive tx queues.
2705          */
2706         netif_tx_stop_all_queues(priv->netdev);
2707         netif_tx_disable(priv->netdev);
2708         mlx5e_xdp_tx_disable(priv);
2709         mlx5e_deactivate_channels(&priv->channels);
2710 }
2711
2712 static int mlx5e_switch_priv_params(struct mlx5e_priv *priv,
2713                                     struct mlx5e_params *new_params,
2714                                     mlx5e_fp_preactivate preactivate,
2715                                     void *context)
2716 {
2717         struct mlx5e_params old_params;
2718
2719         old_params = priv->channels.params;
2720         priv->channels.params = *new_params;
2721
2722         if (preactivate) {
2723                 int err;
2724
2725                 err = preactivate(priv, context);
2726                 if (err) {
2727                         priv->channels.params = old_params;
2728                         return err;
2729                 }
2730         }
2731
2732         return 0;
2733 }
2734
2735 static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2736                                       struct mlx5e_channels *new_chs,
2737                                       mlx5e_fp_preactivate preactivate,
2738                                       void *context)
2739 {
2740         struct net_device *netdev = priv->netdev;
2741         struct mlx5e_channels old_chs;
2742         int carrier_ok;
2743         int err = 0;
2744
2745         carrier_ok = netif_carrier_ok(netdev);
2746         netif_carrier_off(netdev);
2747
2748         mlx5e_deactivate_priv_channels(priv);
2749
2750         old_chs = priv->channels;
2751         priv->channels = *new_chs;
2752
2753         /* New channels are ready to roll, call the preactivate hook if needed
2754          * to modify HW settings or update kernel parameters.
2755          */
2756         if (preactivate) {
2757                 err = preactivate(priv, context);
2758                 if (err) {
2759                         priv->channels = old_chs;
2760                         goto out;
2761                 }
2762         }
2763
2764         mlx5e_close_channels(&old_chs);
2765         priv->profile->update_rx(priv);
2766
2767 out:
2768         mlx5e_activate_priv_channels(priv);
2769
2770         /* return carrier back if needed */
2771         if (carrier_ok)
2772                 netif_carrier_on(netdev);
2773
2774         return err;
2775 }
2776
2777 int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
2778                              struct mlx5e_params *params,
2779                              mlx5e_fp_preactivate preactivate,
2780                              void *context, bool reset)
2781 {
2782         struct mlx5e_channels new_chs = {};
2783         int err;
2784
2785         reset &= test_bit(MLX5E_STATE_OPENED, &priv->state);
2786         if (!reset)
2787                 return mlx5e_switch_priv_params(priv, params, preactivate, context);
2788
2789         new_chs.params = *params;
2790         err = mlx5e_open_channels(priv, &new_chs);
2791         if (err)
2792                 return err;
2793         err = mlx5e_switch_priv_channels(priv, &new_chs, preactivate, context);
2794         if (err)
2795                 mlx5e_close_channels(&new_chs);
2796
2797         return err;
2798 }
2799
2800 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
2801 {
2802         return mlx5e_safe_switch_params(priv, &priv->channels.params, NULL, NULL, true);
2803 }
2804
2805 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2806 {
2807         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2808         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2809 }
2810
2811 static void mlx5e_modify_admin_state(struct mlx5_core_dev *mdev,
2812                                      enum mlx5_port_status state)
2813 {
2814         struct mlx5_eswitch *esw = mdev->priv.eswitch;
2815         int vport_admin_state;
2816
2817         mlx5_set_port_admin_status(mdev, state);
2818
2819         if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS ||
2820             !MLX5_CAP_GEN(mdev, uplink_follow))
2821                 return;
2822
2823         if (state == MLX5_PORT_UP)
2824                 vport_admin_state = MLX5_VPORT_ADMIN_STATE_AUTO;
2825         else
2826                 vport_admin_state = MLX5_VPORT_ADMIN_STATE_DOWN;
2827
2828         mlx5_eswitch_set_vport_state(esw, MLX5_VPORT_UPLINK, vport_admin_state);
2829 }
2830
2831 int mlx5e_open_locked(struct net_device *netdev)
2832 {
2833         struct mlx5e_priv *priv = netdev_priv(netdev);
2834         int err;
2835
2836         set_bit(MLX5E_STATE_OPENED, &priv->state);
2837
2838         err = mlx5e_open_channels(priv, &priv->channels);
2839         if (err)
2840                 goto err_clear_state_opened_flag;
2841
2842         priv->profile->update_rx(priv);
2843         mlx5e_activate_priv_channels(priv);
2844         mlx5e_apply_traps(priv, true);
2845         if (priv->profile->update_carrier)
2846                 priv->profile->update_carrier(priv);
2847
2848         mlx5e_queue_update_stats(priv);
2849         return 0;
2850
2851 err_clear_state_opened_flag:
2852         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2853         return err;
2854 }
2855
2856 int mlx5e_open(struct net_device *netdev)
2857 {
2858         struct mlx5e_priv *priv = netdev_priv(netdev);
2859         int err;
2860
2861         mutex_lock(&priv->state_lock);
2862         err = mlx5e_open_locked(netdev);
2863         if (!err)
2864                 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_UP);
2865         mutex_unlock(&priv->state_lock);
2866
2867         return err;
2868 }
2869
2870 int mlx5e_close_locked(struct net_device *netdev)
2871 {
2872         struct mlx5e_priv *priv = netdev_priv(netdev);
2873
2874         /* May already be CLOSED in case a previous configuration operation
2875          * (e.g RX/TX queue size change) that involves close&open failed.
2876          */
2877         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2878                 return 0;
2879
2880         mlx5e_apply_traps(priv, false);
2881         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2882
2883         netif_carrier_off(priv->netdev);
2884         mlx5e_deactivate_priv_channels(priv);
2885         mlx5e_close_channels(&priv->channels);
2886
2887         return 0;
2888 }
2889
2890 int mlx5e_close(struct net_device *netdev)
2891 {
2892         struct mlx5e_priv *priv = netdev_priv(netdev);
2893         int err;
2894
2895         if (!netif_device_present(netdev))
2896                 return -ENODEV;
2897
2898         mutex_lock(&priv->state_lock);
2899         mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_DOWN);
2900         err = mlx5e_close_locked(netdev);
2901         mutex_unlock(&priv->state_lock);
2902
2903         return err;
2904 }
2905
2906 static void mlx5e_free_drop_rq(struct mlx5e_rq *rq)
2907 {
2908         mlx5_wq_destroy(&rq->wq_ctrl);
2909 }
2910
2911 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2912                                struct mlx5e_rq *rq,
2913                                struct mlx5e_rq_param *param)
2914 {
2915         void *rqc = param->rqc;
2916         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2917         int err;
2918
2919         param->wq.db_numa_node = param->wq.buf_numa_node;
2920
2921         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
2922                                  &rq->wq_ctrl);
2923         if (err)
2924                 return err;
2925
2926         /* Mark as unused given "Drop-RQ" packets never reach XDP */
2927         xdp_rxq_info_unused(&rq->xdp_rxq);
2928
2929         rq->mdev = mdev;
2930
2931         return 0;
2932 }
2933
2934 static int mlx5e_alloc_drop_cq(struct mlx5e_priv *priv,
2935                                struct mlx5e_cq *cq,
2936                                struct mlx5e_cq_param *param)
2937 {
2938         struct mlx5_core_dev *mdev = priv->mdev;
2939
2940         param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
2941         param->wq.db_numa_node  = dev_to_node(mlx5_core_dma_dev(mdev));
2942
2943         return mlx5e_alloc_cq_common(priv, param, cq);
2944 }
2945
2946 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
2947                        struct mlx5e_rq *drop_rq)
2948 {
2949         struct mlx5_core_dev *mdev = priv->mdev;
2950         struct mlx5e_cq_param cq_param = {};
2951         struct mlx5e_rq_param rq_param = {};
2952         struct mlx5e_cq *cq = &drop_rq->cq;
2953         int err;
2954
2955         mlx5e_build_drop_rq_param(mdev, priv->drop_rq_q_counter, &rq_param);
2956
2957         err = mlx5e_alloc_drop_cq(priv, cq, &cq_param);
2958         if (err)
2959                 return err;
2960
2961         err = mlx5e_create_cq(cq, &cq_param);
2962         if (err)
2963                 goto err_free_cq;
2964
2965         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
2966         if (err)
2967                 goto err_destroy_cq;
2968
2969         err = mlx5e_create_rq(drop_rq, &rq_param);
2970         if (err)
2971                 goto err_free_rq;
2972
2973         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
2974         if (err)
2975                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
2976
2977         return 0;
2978
2979 err_free_rq:
2980         mlx5e_free_drop_rq(drop_rq);
2981
2982 err_destroy_cq:
2983         mlx5e_destroy_cq(cq);
2984
2985 err_free_cq:
2986         mlx5e_free_cq(cq);
2987
2988         return err;
2989 }
2990
2991 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
2992 {
2993         mlx5e_destroy_rq(drop_rq);
2994         mlx5e_free_drop_rq(drop_rq);
2995         mlx5e_destroy_cq(&drop_rq->cq);
2996         mlx5e_free_cq(&drop_rq->cq);
2997 }
2998
2999 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
3000 {
3001         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3002
3003         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.hw_objs.td.tdn);
3004
3005         if (MLX5_GET(tisc, tisc, tls_en))
3006                 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.hw_objs.pdn);
3007
3008         if (mlx5_lag_is_lacp_owner(mdev))
3009                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3010
3011         return mlx5_core_create_tis(mdev, in, tisn);
3012 }
3013
3014 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3015 {
3016         mlx5_core_destroy_tis(mdev, tisn);
3017 }
3018
3019 void mlx5e_destroy_tises(struct mlx5e_priv *priv)
3020 {
3021         int tc, i;
3022
3023         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++)
3024                 for (tc = 0; tc < priv->profile->max_tc; tc++)
3025                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3026 }
3027
3028 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
3029 {
3030         return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
3031 }
3032
3033 int mlx5e_create_tises(struct mlx5e_priv *priv)
3034 {
3035         int tc, i;
3036         int err;
3037
3038         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) {
3039                 for (tc = 0; tc < priv->profile->max_tc; tc++) {
3040                         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
3041                         void *tisc;
3042
3043                         tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3044
3045                         MLX5_SET(tisc, tisc, prio, tc << 1);
3046
3047                         if (mlx5e_lag_should_assign_affinity(priv->mdev))
3048                                 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
3049
3050                         err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]);
3051                         if (err)
3052                                 goto err_close_tises;
3053                 }
3054         }
3055
3056         return 0;
3057
3058 err_close_tises:
3059         for (; i >= 0; i--) {
3060                 for (tc--; tc >= 0; tc--)
3061                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3062                 tc = priv->profile->max_tc;
3063         }
3064
3065         return err;
3066 }
3067
3068 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3069 {
3070         mlx5e_destroy_tises(priv);
3071 }
3072
3073 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3074 {
3075         int err = 0;
3076         int i;
3077
3078         for (i = 0; i < chs->num; i++) {
3079                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3080                 if (err)
3081                         return err;
3082         }
3083
3084         return 0;
3085 }
3086
3087 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3088 {
3089         int err;
3090         int i;
3091
3092         for (i = 0; i < chs->num; i++) {
3093                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3094                 if (err)
3095                         return err;
3096         }
3097         if (chs->ptp && test_bit(MLX5E_PTP_STATE_RX, chs->ptp->state))
3098                 return mlx5e_modify_rq_vsd(&chs->ptp->rq, vsd);
3099
3100         return 0;
3101 }
3102
3103 static void mlx5e_mqprio_build_default_tc_to_txq(struct netdev_tc_txq *tc_to_txq,
3104                                                  int ntc, int nch)
3105 {
3106         int tc;
3107
3108         memset(tc_to_txq, 0, sizeof(*tc_to_txq) * TC_MAX_QUEUE);
3109
3110         /* Map netdev TCs to offset 0.
3111          * We have our own UP to TXQ mapping for DCB mode of QoS
3112          */
3113         for (tc = 0; tc < ntc; tc++) {
3114                 tc_to_txq[tc] = (struct netdev_tc_txq) {
3115                         .count = nch,
3116                         .offset = 0,
3117                 };
3118         }
3119 }
3120
3121 static void mlx5e_mqprio_build_tc_to_txq(struct netdev_tc_txq *tc_to_txq,
3122                                          struct tc_mqprio_qopt *qopt)
3123 {
3124         int tc;
3125
3126         for (tc = 0; tc < TC_MAX_QUEUE; tc++) {
3127                 tc_to_txq[tc] = (struct netdev_tc_txq) {
3128                         .count = qopt->count[tc],
3129                         .offset = qopt->offset[tc],
3130                 };
3131         }
3132 }
3133
3134 static void mlx5e_params_mqprio_dcb_set(struct mlx5e_params *params, u8 num_tc)
3135 {
3136         params->mqprio.mode = TC_MQPRIO_MODE_DCB;
3137         params->mqprio.num_tc = num_tc;
3138         params->mqprio.channel.rl = NULL;
3139         mlx5e_mqprio_build_default_tc_to_txq(params->mqprio.tc_to_txq, num_tc,
3140                                              params->num_channels);
3141 }
3142
3143 static void mlx5e_params_mqprio_channel_set(struct mlx5e_params *params,
3144                                             struct tc_mqprio_qopt *qopt,
3145                                             struct mlx5e_mqprio_rl *rl)
3146 {
3147         params->mqprio.mode = TC_MQPRIO_MODE_CHANNEL;
3148         params->mqprio.num_tc = qopt->num_tc;
3149         params->mqprio.channel.rl = rl;
3150         mlx5e_mqprio_build_tc_to_txq(params->mqprio.tc_to_txq, qopt);
3151 }
3152
3153 static void mlx5e_params_mqprio_reset(struct mlx5e_params *params)
3154 {
3155         mlx5e_params_mqprio_dcb_set(params, 1);
3156 }
3157
3158 static int mlx5e_setup_tc_mqprio_dcb(struct mlx5e_priv *priv,
3159                                      struct tc_mqprio_qopt *mqprio)
3160 {
3161         struct mlx5e_params new_params;
3162         u8 tc = mqprio->num_tc;
3163         int err;
3164
3165         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3166
3167         if (tc && tc != MLX5E_MAX_NUM_TC)
3168                 return -EINVAL;
3169
3170         new_params = priv->channels.params;
3171         mlx5e_params_mqprio_dcb_set(&new_params, tc ? tc : 1);
3172
3173         err = mlx5e_safe_switch_params(priv, &new_params,
3174                                        mlx5e_num_channels_changed_ctx, NULL, true);
3175
3176         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3177                                     mlx5e_get_dcb_num_tc(&priv->channels.params));
3178         return err;
3179 }
3180
3181 static int mlx5e_mqprio_channel_validate(struct mlx5e_priv *priv,
3182                                          struct tc_mqprio_qopt_offload *mqprio)
3183 {
3184         struct net_device *netdev = priv->netdev;
3185         struct mlx5e_ptp *ptp_channel;
3186         int agg_count = 0;
3187         int i;
3188
3189         ptp_channel = priv->channels.ptp;
3190         if (ptp_channel && test_bit(MLX5E_PTP_STATE_TX, ptp_channel->state)) {
3191                 netdev_err(netdev,
3192                            "Cannot activate MQPRIO mode channel since it conflicts with TX port TS\n");
3193                 return -EINVAL;
3194         }
3195
3196         if (mqprio->qopt.offset[0] != 0 || mqprio->qopt.num_tc < 1 ||
3197             mqprio->qopt.num_tc > MLX5E_MAX_NUM_MQPRIO_CH_TC)
3198                 return -EINVAL;
3199
3200         for (i = 0; i < mqprio->qopt.num_tc; i++) {
3201                 if (!mqprio->qopt.count[i]) {
3202                         netdev_err(netdev, "Zero size for queue-group (%d) is not supported\n", i);
3203                         return -EINVAL;
3204                 }
3205                 if (mqprio->min_rate[i]) {
3206                         netdev_err(netdev, "Min tx rate is not supported\n");
3207                         return -EINVAL;
3208                 }
3209
3210                 if (mqprio->max_rate[i]) {
3211                         int err;
3212
3213                         err = mlx5e_qos_bytes_rate_check(priv->mdev, mqprio->max_rate[i]);
3214                         if (err)
3215                                 return err;
3216                 }
3217
3218                 if (mqprio->qopt.offset[i] != agg_count) {
3219                         netdev_err(netdev, "Discontinuous queues config is not supported\n");
3220                         return -EINVAL;
3221                 }
3222                 agg_count += mqprio->qopt.count[i];
3223         }
3224
3225         if (priv->channels.params.num_channels != agg_count) {
3226                 netdev_err(netdev, "Num of queues (%d) does not match available (%d)\n",
3227                            agg_count, priv->channels.params.num_channels);
3228                 return -EINVAL;
3229         }
3230
3231         return 0;
3232 }
3233
3234 static bool mlx5e_mqprio_rate_limit(struct tc_mqprio_qopt_offload *mqprio)
3235 {
3236         int tc;
3237
3238         for (tc = 0; tc < mqprio->qopt.num_tc; tc++)
3239                 if (mqprio->max_rate[tc])
3240                         return true;
3241         return false;
3242 }
3243
3244 static int mlx5e_setup_tc_mqprio_channel(struct mlx5e_priv *priv,
3245                                          struct tc_mqprio_qopt_offload *mqprio)
3246 {
3247         mlx5e_fp_preactivate preactivate;
3248         struct mlx5e_params new_params;
3249         struct mlx5e_mqprio_rl *rl;
3250         bool nch_changed;
3251         int err;
3252
3253         err = mlx5e_mqprio_channel_validate(priv, mqprio);
3254         if (err)
3255                 return err;
3256
3257         rl = NULL;
3258         if (mlx5e_mqprio_rate_limit(mqprio)) {
3259                 rl = mlx5e_mqprio_rl_alloc();
3260                 if (!rl)
3261                         return -ENOMEM;
3262                 err = mlx5e_mqprio_rl_init(rl, priv->mdev, mqprio->qopt.num_tc,
3263                                            mqprio->max_rate);
3264                 if (err) {
3265                         mlx5e_mqprio_rl_free(rl);
3266                         return err;
3267                 }
3268         }
3269
3270         new_params = priv->channels.params;
3271         mlx5e_params_mqprio_channel_set(&new_params, &mqprio->qopt, rl);
3272
3273         nch_changed = mlx5e_get_dcb_num_tc(&priv->channels.params) > 1;
3274         preactivate = nch_changed ? mlx5e_num_channels_changed_ctx :
3275                 mlx5e_update_netdev_queues_ctx;
3276         err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, true);
3277         if (err && rl) {
3278                 mlx5e_mqprio_rl_cleanup(rl);
3279                 mlx5e_mqprio_rl_free(rl);
3280         }
3281
3282         return err;
3283 }
3284
3285 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3286                                  struct tc_mqprio_qopt_offload *mqprio)
3287 {
3288         /* MQPRIO is another toplevel qdisc that can't be attached
3289          * simultaneously with the offloaded HTB.
3290          */
3291         if (WARN_ON(priv->htb.maj_id))
3292                 return -EINVAL;
3293
3294         switch (mqprio->mode) {
3295         case TC_MQPRIO_MODE_DCB:
3296                 return mlx5e_setup_tc_mqprio_dcb(priv, &mqprio->qopt);
3297         case TC_MQPRIO_MODE_CHANNEL:
3298                 return mlx5e_setup_tc_mqprio_channel(priv, mqprio);
3299         default:
3300                 return -EOPNOTSUPP;
3301         }
3302 }
3303
3304 static int mlx5e_setup_tc_htb(struct mlx5e_priv *priv, struct tc_htb_qopt_offload *htb)
3305 {
3306         int res;
3307
3308         switch (htb->command) {
3309         case TC_HTB_CREATE:
3310                 return mlx5e_htb_root_add(priv, htb->parent_classid, htb->classid,
3311                                           htb->extack);
3312         case TC_HTB_DESTROY:
3313                 return mlx5e_htb_root_del(priv);
3314         case TC_HTB_LEAF_ALLOC_QUEUE:
3315                 res = mlx5e_htb_leaf_alloc_queue(priv, htb->classid, htb->parent_classid,
3316                                                  htb->rate, htb->ceil, htb->extack);
3317                 if (res < 0)
3318                         return res;
3319                 htb->qid = res;
3320                 return 0;
3321         case TC_HTB_LEAF_TO_INNER:
3322                 return mlx5e_htb_leaf_to_inner(priv, htb->parent_classid, htb->classid,
3323                                                htb->rate, htb->ceil, htb->extack);
3324         case TC_HTB_LEAF_DEL:
3325                 return mlx5e_htb_leaf_del(priv, &htb->classid, htb->extack);
3326         case TC_HTB_LEAF_DEL_LAST:
3327         case TC_HTB_LEAF_DEL_LAST_FORCE:
3328                 return mlx5e_htb_leaf_del_last(priv, htb->classid,
3329                                                htb->command == TC_HTB_LEAF_DEL_LAST_FORCE,
3330                                                htb->extack);
3331         case TC_HTB_NODE_MODIFY:
3332                 return mlx5e_htb_node_modify(priv, htb->classid, htb->rate, htb->ceil,
3333                                              htb->extack);
3334         case TC_HTB_LEAF_QUERY_QUEUE:
3335                 res = mlx5e_get_txq_by_classid(priv, htb->classid);
3336                 if (res < 0)
3337                         return res;
3338                 htb->qid = res;
3339                 return 0;
3340         default:
3341                 return -EOPNOTSUPP;
3342         }
3343 }
3344
3345 static LIST_HEAD(mlx5e_block_cb_list);
3346
3347 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3348                           void *type_data)
3349 {
3350         struct mlx5e_priv *priv = netdev_priv(dev);
3351         bool tc_unbind = false;
3352         int err;
3353
3354         if (type == TC_SETUP_BLOCK &&
3355             ((struct flow_block_offload *)type_data)->command == FLOW_BLOCK_UNBIND)
3356                 tc_unbind = true;
3357
3358         if (!netif_device_present(dev) && !tc_unbind)
3359                 return -ENODEV;
3360
3361         switch (type) {
3362         case TC_SETUP_BLOCK: {
3363                 struct flow_block_offload *f = type_data;
3364
3365                 f->unlocked_driver_cb = true;
3366                 return flow_block_cb_setup_simple(type_data,
3367                                                   &mlx5e_block_cb_list,
3368                                                   mlx5e_setup_tc_block_cb,
3369                                                   priv, priv, true);
3370         }
3371         case TC_SETUP_QDISC_MQPRIO:
3372                 mutex_lock(&priv->state_lock);
3373                 err = mlx5e_setup_tc_mqprio(priv, type_data);
3374                 mutex_unlock(&priv->state_lock);
3375                 return err;
3376         case TC_SETUP_QDISC_HTB:
3377                 mutex_lock(&priv->state_lock);
3378                 err = mlx5e_setup_tc_htb(priv, type_data);
3379                 mutex_unlock(&priv->state_lock);
3380                 return err;
3381         default:
3382                 return -EOPNOTSUPP;
3383         }
3384 }
3385
3386 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3387 {
3388         int i;
3389
3390         for (i = 0; i < priv->stats_nch; i++) {
3391                 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3392                 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3393                 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3394                 int j;
3395
3396                 s->rx_packets   += rq_stats->packets + xskrq_stats->packets;
3397                 s->rx_bytes     += rq_stats->bytes + xskrq_stats->bytes;
3398                 s->multicast    += rq_stats->mcast_packets + xskrq_stats->mcast_packets;
3399
3400                 for (j = 0; j < priv->max_opened_tc; j++) {
3401                         struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3402
3403                         s->tx_packets    += sq_stats->packets;
3404                         s->tx_bytes      += sq_stats->bytes;
3405                         s->tx_dropped    += sq_stats->dropped;
3406                 }
3407         }
3408         if (priv->tx_ptp_opened) {
3409                 for (i = 0; i < priv->max_opened_tc; i++) {
3410                         struct mlx5e_sq_stats *sq_stats = &priv->ptp_stats.sq[i];
3411
3412                         s->tx_packets    += sq_stats->packets;
3413                         s->tx_bytes      += sq_stats->bytes;
3414                         s->tx_dropped    += sq_stats->dropped;
3415                 }
3416         }
3417         if (priv->rx_ptp_opened) {
3418                 struct mlx5e_rq_stats *rq_stats = &priv->ptp_stats.rq;
3419
3420                 s->rx_packets   += rq_stats->packets;
3421                 s->rx_bytes     += rq_stats->bytes;
3422                 s->multicast    += rq_stats->mcast_packets;
3423         }
3424 }
3425
3426 void
3427 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3428 {
3429         struct mlx5e_priv *priv = netdev_priv(dev);
3430         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3431
3432         if (!netif_device_present(dev))
3433                 return;
3434
3435         /* In switchdev mode, monitor counters doesn't monitor
3436          * rx/tx stats of 802_3. The update stats mechanism
3437          * should keep the 802_3 layout counters updated
3438          */
3439         if (!mlx5e_monitor_counter_supported(priv) ||
3440             mlx5e_is_uplink_rep(priv)) {
3441                 /* update HW stats in background for next time */
3442                 mlx5e_queue_update_stats(priv);
3443         }
3444
3445         if (mlx5e_is_uplink_rep(priv)) {
3446                 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3447
3448                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3449                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3450                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3451                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3452
3453                 /* vport multicast also counts packets that are dropped due to steering
3454                  * or rx out of buffer
3455                  */
3456                 stats->multicast = VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3457         } else {
3458                 mlx5e_fold_sw_stats64(priv, stats);
3459         }
3460
3461         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3462
3463         stats->rx_length_errors =
3464                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3465                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3466                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3467         stats->rx_crc_errors =
3468                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3469         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3470         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3471         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3472                            stats->rx_frame_errors;
3473         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3474 }
3475
3476 static void mlx5e_nic_set_rx_mode(struct mlx5e_priv *priv)
3477 {
3478         if (mlx5e_is_uplink_rep(priv))
3479                 return; /* no rx mode for uplink rep */
3480
3481         queue_work(priv->wq, &priv->set_rx_mode_work);
3482 }
3483
3484 static void mlx5e_set_rx_mode(struct net_device *dev)
3485 {
3486         struct mlx5e_priv *priv = netdev_priv(dev);
3487
3488         mlx5e_nic_set_rx_mode(priv);
3489 }
3490
3491 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3492 {
3493         struct mlx5e_priv *priv = netdev_priv(netdev);
3494         struct sockaddr *saddr = addr;
3495
3496         if (!is_valid_ether_addr(saddr->sa_data))
3497                 return -EADDRNOTAVAIL;
3498
3499         netif_addr_lock_bh(netdev);
3500         eth_hw_addr_set(netdev, saddr->sa_data);
3501         netif_addr_unlock_bh(netdev);
3502
3503         mlx5e_nic_set_rx_mode(priv);
3504
3505         return 0;
3506 }
3507
3508 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3509         do {                                            \
3510                 if (enable)                             \
3511                         *features |= feature;           \
3512                 else                                    \
3513                         *features &= ~feature;          \
3514         } while (0)
3515
3516 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3517
3518 static int set_feature_lro(struct net_device *netdev, bool enable)
3519 {
3520         struct mlx5e_priv *priv = netdev_priv(netdev);
3521         struct mlx5_core_dev *mdev = priv->mdev;
3522         struct mlx5e_params *cur_params;
3523         struct mlx5e_params new_params;
3524         bool reset = true;
3525         int err = 0;
3526
3527         mutex_lock(&priv->state_lock);
3528
3529         if (enable && priv->xsk.refcnt) {
3530                 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%u XSKs are active)\n",
3531                             priv->xsk.refcnt);
3532                 err = -EINVAL;
3533                 goto out;
3534         }
3535
3536         cur_params = &priv->channels.params;
3537         if (enable && !MLX5E_GET_PFLAG(cur_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3538                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3539                 err = -EINVAL;
3540                 goto out;
3541         }
3542
3543         new_params = *cur_params;
3544
3545         if (enable)
3546                 new_params.packet_merge.type = MLX5E_PACKET_MERGE_LRO;
3547         else if (new_params.packet_merge.type == MLX5E_PACKET_MERGE_LRO)
3548                 new_params.packet_merge.type = MLX5E_PACKET_MERGE_NONE;
3549         else
3550                 goto out;
3551
3552         if (!(cur_params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO &&
3553               new_params.packet_merge.type == MLX5E_PACKET_MERGE_LRO)) {
3554                 if (cur_params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3555                         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, cur_params, NULL) ==
3556                             mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_params, NULL))
3557                                 reset = false;
3558                 }
3559         }
3560
3561         err = mlx5e_safe_switch_params(priv, &new_params,
3562                                        mlx5e_modify_tirs_packet_merge_ctx, NULL, reset);
3563 out:
3564         mutex_unlock(&priv->state_lock);
3565         return err;
3566 }
3567
3568 static int set_feature_hw_gro(struct net_device *netdev, bool enable)
3569 {
3570         struct mlx5e_priv *priv = netdev_priv(netdev);
3571         struct mlx5e_params new_params;
3572         bool reset = true;
3573         int err = 0;
3574
3575         mutex_lock(&priv->state_lock);
3576         new_params = priv->channels.params;
3577
3578         if (enable) {
3579                 if (MLX5E_GET_PFLAG(&new_params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3580                         netdev_warn(netdev, "Can't set HW-GRO when CQE compress is active\n");
3581                         err = -EINVAL;
3582                         goto out;
3583                 }
3584                 new_params.packet_merge.type = MLX5E_PACKET_MERGE_SHAMPO;
3585                 new_params.packet_merge.shampo.match_criteria_type =
3586                         MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED;
3587                 new_params.packet_merge.shampo.alignment_granularity =
3588                         MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE;
3589         } else if (new_params.packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) {
3590                 new_params.packet_merge.type = MLX5E_PACKET_MERGE_NONE;
3591         } else {
3592                 goto out;
3593         }
3594
3595         err = mlx5e_safe_switch_params(priv, &new_params,
3596                                        mlx5e_modify_tirs_packet_merge_ctx, NULL, reset);
3597 out:
3598         mutex_unlock(&priv->state_lock);
3599         return err;
3600 }
3601
3602 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3603 {
3604         struct mlx5e_priv *priv = netdev_priv(netdev);
3605
3606         if (enable)
3607                 mlx5e_enable_cvlan_filter(priv);
3608         else
3609                 mlx5e_disable_cvlan_filter(priv);
3610
3611         return 0;
3612 }
3613
3614 static int set_feature_hw_tc(struct net_device *netdev, bool enable)
3615 {
3616         struct mlx5e_priv *priv = netdev_priv(netdev);
3617
3618 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3619         if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) {
3620                 netdev_err(netdev,
3621                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3622                 return -EINVAL;
3623         }
3624 #endif
3625
3626         if (!enable && priv->htb.maj_id) {
3627                 netdev_err(netdev, "Active HTB offload, can't turn hw_tc_offload off\n");
3628                 return -EINVAL;
3629         }
3630
3631         return 0;
3632 }
3633
3634 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3635 {
3636         struct mlx5e_priv *priv = netdev_priv(netdev);
3637         struct mlx5_core_dev *mdev = priv->mdev;
3638
3639         return mlx5_set_port_fcs(mdev, !enable);
3640 }
3641
3642 static int mlx5e_set_rx_port_ts(struct mlx5_core_dev *mdev, bool enable)
3643 {
3644         u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {};
3645         bool supported, curr_state;
3646         int err;
3647
3648         if (!MLX5_CAP_GEN(mdev, ports_check))
3649                 return 0;
3650
3651         err = mlx5_query_ports_check(mdev, in, sizeof(in));
3652         if (err)
3653                 return err;
3654
3655         supported = MLX5_GET(pcmr_reg, in, rx_ts_over_crc_cap);
3656         curr_state = MLX5_GET(pcmr_reg, in, rx_ts_over_crc);
3657
3658         if (!supported || enable == curr_state)
3659                 return 0;
3660
3661         MLX5_SET(pcmr_reg, in, local_port, 1);
3662         MLX5_SET(pcmr_reg, in, rx_ts_over_crc, enable);
3663
3664         return mlx5_set_ports_check(mdev, in, sizeof(in));
3665 }
3666
3667 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3668 {
3669         struct mlx5e_priv *priv = netdev_priv(netdev);
3670         struct mlx5e_channels *chs = &priv->channels;
3671         struct mlx5_core_dev *mdev = priv->mdev;
3672         int err;
3673
3674         mutex_lock(&priv->state_lock);
3675
3676         if (enable) {
3677                 err = mlx5e_set_rx_port_ts(mdev, false);
3678                 if (err)
3679                         goto out;
3680
3681                 chs->params.scatter_fcs_en = true;
3682                 err = mlx5e_modify_channels_scatter_fcs(chs, true);
3683                 if (err) {
3684                         chs->params.scatter_fcs_en = false;
3685                         mlx5e_set_rx_port_ts(mdev, true);
3686                 }
3687         } else {
3688                 chs->params.scatter_fcs_en = false;
3689                 err = mlx5e_modify_channels_scatter_fcs(chs, false);
3690                 if (err) {
3691                         chs->params.scatter_fcs_en = true;
3692                         goto out;
3693                 }
3694                 err = mlx5e_set_rx_port_ts(mdev, true);
3695                 if (err) {
3696                         mlx5_core_warn(mdev, "Failed to set RX port timestamp %d\n", err);
3697                         err = 0;
3698                 }
3699         }
3700
3701 out:
3702         mutex_unlock(&priv->state_lock);
3703         return err;
3704 }
3705
3706 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3707 {
3708         struct mlx5e_priv *priv = netdev_priv(netdev);
3709         int err = 0;
3710
3711         mutex_lock(&priv->state_lock);
3712
3713         priv->channels.params.vlan_strip_disable = !enable;
3714         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3715                 goto unlock;
3716
3717         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3718         if (err)
3719                 priv->channels.params.vlan_strip_disable = enable;
3720
3721 unlock:
3722         mutex_unlock(&priv->state_lock);
3723
3724         return err;
3725 }
3726
3727 #ifdef CONFIG_MLX5_EN_ARFS
3728 static int set_feature_arfs(struct net_device *netdev, bool enable)
3729 {
3730         struct mlx5e_priv *priv = netdev_priv(netdev);
3731         int err;
3732
3733         if (enable)
3734                 err = mlx5e_arfs_enable(priv);
3735         else
3736                 err = mlx5e_arfs_disable(priv);
3737
3738         return err;
3739 }
3740 #endif
3741
3742 static int mlx5e_handle_feature(struct net_device *netdev,
3743                                 netdev_features_t *features,
3744                                 netdev_features_t feature,
3745                                 mlx5e_feature_handler feature_handler)
3746 {
3747         netdev_features_t changes = *features ^ netdev->features;
3748         bool enable = !!(*features & feature);
3749         int err;
3750
3751         if (!(changes & feature))
3752                 return 0;
3753
3754         err = feature_handler(netdev, enable);
3755         if (err) {
3756                 MLX5E_SET_FEATURE(features, feature, !enable);
3757                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3758                            enable ? "Enable" : "Disable", &feature, err);
3759                 return err;
3760         }
3761
3762         return 0;
3763 }
3764
3765 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3766 {
3767         netdev_features_t oper_features = features;
3768         int err = 0;
3769
3770 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3771         mlx5e_handle_feature(netdev, &oper_features, feature, handler)
3772
3773         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3774         err |= MLX5E_HANDLE_FEATURE(NETIF_F_GRO_HW, set_feature_hw_gro);
3775         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3776                                     set_feature_cvlan_filter);
3777         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_hw_tc);
3778         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3779         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3780         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3781 #ifdef CONFIG_MLX5_EN_ARFS
3782         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3783 #endif
3784         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TLS_RX, mlx5e_ktls_set_feature_rx);
3785
3786         if (err) {
3787                 netdev->features = oper_features;
3788                 return -EINVAL;
3789         }
3790
3791         return 0;
3792 }
3793
3794 static netdev_features_t mlx5e_fix_uplink_rep_features(struct net_device *netdev,
3795                                                        netdev_features_t features)
3796 {
3797         features &= ~NETIF_F_HW_TLS_RX;
3798         if (netdev->features & NETIF_F_HW_TLS_RX)
3799                 netdev_warn(netdev, "Disabling hw_tls_rx, not supported in switchdev mode\n");
3800
3801         features &= ~NETIF_F_HW_TLS_TX;
3802         if (netdev->features & NETIF_F_HW_TLS_TX)
3803                 netdev_warn(netdev, "Disabling hw_tls_tx, not supported in switchdev mode\n");
3804
3805         features &= ~NETIF_F_NTUPLE;
3806         if (netdev->features & NETIF_F_NTUPLE)
3807                 netdev_warn(netdev, "Disabling ntuple, not supported in switchdev mode\n");
3808
3809         return features;
3810 }
3811
3812 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3813                                             netdev_features_t features)
3814 {
3815         struct mlx5e_priv *priv = netdev_priv(netdev);
3816         struct mlx5e_params *params;
3817
3818         mutex_lock(&priv->state_lock);
3819         params = &priv->channels.params;
3820         if (!priv->fs.vlan ||
3821             !bitmap_empty(mlx5e_vlan_get_active_svlans(priv->fs.vlan), VLAN_N_VID)) {
3822                 /* HW strips the outer C-tag header, this is a problem
3823                  * for S-tag traffic.
3824                  */
3825                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3826                 if (!params->vlan_strip_disable)
3827                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3828         }
3829
3830         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3831                 if (features & NETIF_F_LRO) {
3832                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3833                         features &= ~NETIF_F_LRO;
3834                 }
3835                 if (features & NETIF_F_GRO_HW) {
3836                         netdev_warn(netdev, "Disabling HW-GRO, not supported in legacy RQ\n");
3837                         features &= ~NETIF_F_GRO_HW;
3838                 }
3839         }
3840
3841         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3842                 features &= ~NETIF_F_RXHASH;
3843                 if (netdev->features & NETIF_F_RXHASH)
3844                         netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3845         }
3846
3847         if (mlx5e_is_uplink_rep(priv))
3848                 features = mlx5e_fix_uplink_rep_features(netdev, features);
3849
3850         mutex_unlock(&priv->state_lock);
3851
3852         return features;
3853 }
3854
3855 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
3856                                    struct mlx5e_channels *chs,
3857                                    struct mlx5e_params *new_params,
3858                                    struct mlx5_core_dev *mdev)
3859 {
3860         u16 ix;
3861
3862         for (ix = 0; ix < chs->params.num_channels; ix++) {
3863                 struct xsk_buff_pool *xsk_pool =
3864                         mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, ix);
3865                 struct mlx5e_xsk_param xsk;
3866
3867                 if (!xsk_pool)
3868                         continue;
3869
3870                 mlx5e_build_xsk_param(xsk_pool, &xsk);
3871
3872                 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
3873                         u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
3874                         int max_mtu_frame, max_mtu_page, max_mtu;
3875
3876                         /* Two criteria must be met:
3877                          * 1. HW MTU + all headrooms <= XSK frame size.
3878                          * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
3879                          */
3880                         max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
3881                         max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
3882                         max_mtu = min(max_mtu_frame, max_mtu_page);
3883
3884                         netdev_err(netdev, "MTU %d is too big for an XSK running on channel %u. Try MTU <= %d\n",
3885                                    new_params->sw_mtu, ix, max_mtu);
3886                         return false;
3887                 }
3888         }
3889
3890         return true;
3891 }
3892
3893 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3894                      mlx5e_fp_preactivate preactivate)
3895 {
3896         struct mlx5e_priv *priv = netdev_priv(netdev);
3897         struct mlx5e_params new_params;
3898         struct mlx5e_params *params;
3899         bool reset = true;
3900         int err = 0;
3901
3902         mutex_lock(&priv->state_lock);
3903
3904         params = &priv->channels.params;
3905
3906         new_params = *params;
3907         new_params.sw_mtu = new_mtu;
3908         err = mlx5e_validate_params(priv->mdev, &new_params);
3909         if (err)
3910                 goto out;
3911
3912         if (params->xdp_prog &&
3913             !mlx5e_rx_is_linear_skb(&new_params, NULL)) {
3914                 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3915                            new_mtu, mlx5e_xdp_max_mtu(params, NULL));
3916                 err = -EINVAL;
3917                 goto out;
3918         }
3919
3920         if (priv->xsk.refcnt &&
3921             !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
3922                                     &new_params, priv->mdev)) {
3923                 err = -EINVAL;
3924                 goto out;
3925         }
3926
3927         if (params->packet_merge.type == MLX5E_PACKET_MERGE_LRO)
3928                 reset = false;
3929
3930         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3931                 bool is_linear_old = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, params, NULL);
3932                 bool is_linear_new = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
3933                                                                   &new_params, NULL);
3934                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
3935                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_params, NULL);
3936
3937                 /* Always reset in linear mode - hw_mtu is used in data path.
3938                  * Check that the mode was non-linear and didn't change.
3939                  * If XSK is active, XSK RQs are linear.
3940                  */
3941                 if (!is_linear_old && !is_linear_new && !priv->xsk.refcnt &&
3942                     ppw_old == ppw_new)
3943                         reset = false;
3944         }
3945
3946         err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, reset);
3947
3948 out:
3949         netdev->mtu = params->sw_mtu;
3950         mutex_unlock(&priv->state_lock);
3951         return err;
3952 }
3953
3954 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3955 {
3956         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx);
3957 }
3958
3959 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx)
3960 {
3961         bool set  = *(bool *)ctx;
3962
3963         return mlx5e_ptp_rx_manage_fs(priv, set);
3964 }
3965
3966 static int mlx5e_hwstamp_config_no_ptp_rx(struct mlx5e_priv *priv, bool rx_filter)
3967 {
3968         bool rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
3969         int err;
3970
3971         if (!rx_filter)
3972                 /* Reset CQE compression to Admin default */
3973                 return mlx5e_modify_rx_cqe_compression_locked(priv, rx_cqe_compress_def, false);
3974
3975         if (!MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
3976                 return 0;
3977
3978         /* Disable CQE compression */
3979         netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
3980         err = mlx5e_modify_rx_cqe_compression_locked(priv, false, true);
3981         if (err)
3982                 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3983
3984         return err;
3985 }
3986
3987 static int mlx5e_hwstamp_config_ptp_rx(struct mlx5e_priv *priv, bool ptp_rx)
3988 {
3989         struct mlx5e_params new_params;
3990
3991         if (ptp_rx == priv->channels.params.ptp_rx)
3992                 return 0;
3993
3994         new_params = priv->channels.params;
3995         new_params.ptp_rx = ptp_rx;
3996         return mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx,
3997                                         &new_params.ptp_rx, true);
3998 }
3999
4000 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
4001 {
4002         struct hwtstamp_config config;
4003         bool rx_cqe_compress_def;
4004         bool ptp_rx;
4005         int err;
4006
4007         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
4008             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
4009                 return -EOPNOTSUPP;
4010
4011         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4012                 return -EFAULT;
4013
4014         /* TX HW timestamp */
4015         switch (config.tx_type) {
4016         case HWTSTAMP_TX_OFF:
4017         case HWTSTAMP_TX_ON:
4018                 break;
4019         default:
4020                 return -ERANGE;
4021         }
4022
4023         mutex_lock(&priv->state_lock);
4024         rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
4025
4026         /* RX HW timestamp */
4027         switch (config.rx_filter) {
4028         case HWTSTAMP_FILTER_NONE:
4029                 ptp_rx = false;
4030                 break;
4031         case HWTSTAMP_FILTER_ALL:
4032         case HWTSTAMP_FILTER_SOME:
4033         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4034         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4035         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4036         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4037         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4038         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4039         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4040         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4041         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4042         case HWTSTAMP_FILTER_PTP_V2_EVENT:
4043         case HWTSTAMP_FILTER_PTP_V2_SYNC:
4044         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4045         case HWTSTAMP_FILTER_NTP_ALL:
4046                 config.rx_filter = HWTSTAMP_FILTER_ALL;
4047                 /* ptp_rx is set if both HW TS is set and CQE
4048                  * compression is set
4049                  */
4050                 ptp_rx = rx_cqe_compress_def;
4051                 break;
4052         default:
4053                 err = -ERANGE;
4054                 goto err_unlock;
4055         }
4056
4057         if (!priv->profile->rx_ptp_support)
4058                 err = mlx5e_hwstamp_config_no_ptp_rx(priv,
4059                                                      config.rx_filter != HWTSTAMP_FILTER_NONE);
4060         else
4061                 err = mlx5e_hwstamp_config_ptp_rx(priv, ptp_rx);
4062         if (err)
4063                 goto err_unlock;
4064
4065         memcpy(&priv->tstamp, &config, sizeof(config));
4066         mutex_unlock(&priv->state_lock);
4067
4068         /* might need to fix some features */
4069         netdev_update_features(priv->netdev);
4070
4071         return copy_to_user(ifr->ifr_data, &config,
4072                             sizeof(config)) ? -EFAULT : 0;
4073 err_unlock:
4074         mutex_unlock(&priv->state_lock);
4075         return err;
4076 }
4077
4078 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
4079 {
4080         struct hwtstamp_config *cfg = &priv->tstamp;
4081
4082         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
4083                 return -EOPNOTSUPP;
4084
4085         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
4086 }
4087
4088 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4089 {
4090         struct mlx5e_priv *priv = netdev_priv(dev);
4091
4092         switch (cmd) {
4093         case SIOCSHWTSTAMP:
4094                 return mlx5e_hwstamp_set(priv, ifr);
4095         case SIOCGHWTSTAMP:
4096                 return mlx5e_hwstamp_get(priv, ifr);
4097         default:
4098                 return -EOPNOTSUPP;
4099         }
4100 }
4101
4102 #ifdef CONFIG_MLX5_ESWITCH
4103 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4104 {
4105         struct mlx5e_priv *priv = netdev_priv(dev);
4106         struct mlx5_core_dev *mdev = priv->mdev;
4107
4108         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4109 }
4110
4111 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4112                              __be16 vlan_proto)
4113 {
4114         struct mlx5e_priv *priv = netdev_priv(dev);
4115         struct mlx5_core_dev *mdev = priv->mdev;
4116
4117         if (vlan_proto != htons(ETH_P_8021Q))
4118                 return -EPROTONOSUPPORT;
4119
4120         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4121                                            vlan, qos);
4122 }
4123
4124 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4125 {
4126         struct mlx5e_priv *priv = netdev_priv(dev);
4127         struct mlx5_core_dev *mdev = priv->mdev;
4128
4129         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4130 }
4131
4132 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4133 {
4134         struct mlx5e_priv *priv = netdev_priv(dev);
4135         struct mlx5_core_dev *mdev = priv->mdev;
4136
4137         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4138 }
4139
4140 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4141                       int max_tx_rate)
4142 {
4143         struct mlx5e_priv *priv = netdev_priv(dev);
4144         struct mlx5_core_dev *mdev = priv->mdev;
4145
4146         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4147                                            max_tx_rate, min_tx_rate);
4148 }
4149
4150 static int mlx5_vport_link2ifla(u8 esw_link)
4151 {
4152         switch (esw_link) {
4153         case MLX5_VPORT_ADMIN_STATE_DOWN:
4154                 return IFLA_VF_LINK_STATE_DISABLE;
4155         case MLX5_VPORT_ADMIN_STATE_UP:
4156                 return IFLA_VF_LINK_STATE_ENABLE;
4157         }
4158         return IFLA_VF_LINK_STATE_AUTO;
4159 }
4160
4161 static int mlx5_ifla_link2vport(u8 ifla_link)
4162 {
4163         switch (ifla_link) {
4164         case IFLA_VF_LINK_STATE_DISABLE:
4165                 return MLX5_VPORT_ADMIN_STATE_DOWN;
4166         case IFLA_VF_LINK_STATE_ENABLE:
4167                 return MLX5_VPORT_ADMIN_STATE_UP;
4168         }
4169         return MLX5_VPORT_ADMIN_STATE_AUTO;
4170 }
4171
4172 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4173                                    int link_state)
4174 {
4175         struct mlx5e_priv *priv = netdev_priv(dev);
4176         struct mlx5_core_dev *mdev = priv->mdev;
4177
4178         if (mlx5e_is_uplink_rep(priv))
4179                 return -EOPNOTSUPP;
4180
4181         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4182                                             mlx5_ifla_link2vport(link_state));
4183 }
4184
4185 int mlx5e_get_vf_config(struct net_device *dev,
4186                         int vf, struct ifla_vf_info *ivi)
4187 {
4188         struct mlx5e_priv *priv = netdev_priv(dev);
4189         struct mlx5_core_dev *mdev = priv->mdev;
4190         int err;
4191
4192         if (!netif_device_present(dev))
4193                 return -EOPNOTSUPP;
4194
4195         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4196         if (err)
4197                 return err;
4198         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4199         return 0;
4200 }
4201
4202 int mlx5e_get_vf_stats(struct net_device *dev,
4203                        int vf, struct ifla_vf_stats *vf_stats)
4204 {
4205         struct mlx5e_priv *priv = netdev_priv(dev);
4206         struct mlx5_core_dev *mdev = priv->mdev;
4207
4208         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4209                                             vf_stats);
4210 }
4211
4212 static bool
4213 mlx5e_has_offload_stats(const struct net_device *dev, int attr_id)
4214 {
4215         struct mlx5e_priv *priv = netdev_priv(dev);
4216
4217         if (!netif_device_present(dev))
4218                 return false;
4219
4220         if (!mlx5e_is_uplink_rep(priv))
4221                 return false;
4222
4223         return mlx5e_rep_has_offload_stats(dev, attr_id);
4224 }
4225
4226 static int
4227 mlx5e_get_offload_stats(int attr_id, const struct net_device *dev,
4228                         void *sp)
4229 {
4230         struct mlx5e_priv *priv = netdev_priv(dev);
4231
4232         if (!mlx5e_is_uplink_rep(priv))
4233                 return -EOPNOTSUPP;
4234
4235         return mlx5e_rep_get_offload_stats(attr_id, dev, sp);
4236 }
4237 #endif
4238
4239 static bool mlx5e_tunnel_proto_supported_tx(struct mlx5_core_dev *mdev, u8 proto_type)
4240 {
4241         switch (proto_type) {
4242         case IPPROTO_GRE:
4243                 return MLX5_CAP_ETH(mdev, tunnel_stateless_gre);
4244         case IPPROTO_IPIP:
4245         case IPPROTO_IPV6:
4246                 return (MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip) ||
4247                         MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip_tx));
4248         default:
4249                 return false;
4250         }
4251 }
4252
4253 static bool mlx5e_gre_tunnel_inner_proto_offload_supported(struct mlx5_core_dev *mdev,
4254                                                            struct sk_buff *skb)
4255 {
4256         switch (skb->inner_protocol) {
4257         case htons(ETH_P_IP):
4258         case htons(ETH_P_IPV6):
4259         case htons(ETH_P_TEB):
4260                 return true;
4261         case htons(ETH_P_MPLS_UC):
4262         case htons(ETH_P_MPLS_MC):
4263                 return MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre);
4264         }
4265         return false;
4266 }
4267
4268 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4269                                                      struct sk_buff *skb,
4270                                                      netdev_features_t features)
4271 {
4272         unsigned int offset = 0;
4273         struct udphdr *udph;
4274         u8 proto;
4275         u16 port;
4276
4277         switch (vlan_get_protocol(skb)) {
4278         case htons(ETH_P_IP):
4279                 proto = ip_hdr(skb)->protocol;
4280                 break;
4281         case htons(ETH_P_IPV6):
4282                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4283                 break;
4284         default:
4285                 goto out;
4286         }
4287
4288         switch (proto) {
4289         case IPPROTO_GRE:
4290                 if (mlx5e_gre_tunnel_inner_proto_offload_supported(priv->mdev, skb))
4291                         return features;
4292                 break;
4293         case IPPROTO_IPIP:
4294         case IPPROTO_IPV6:
4295                 if (mlx5e_tunnel_proto_supported_tx(priv->mdev, IPPROTO_IPIP))
4296                         return features;
4297                 break;
4298         case IPPROTO_UDP:
4299                 udph = udp_hdr(skb);
4300                 port = be16_to_cpu(udph->dest);
4301
4302                 /* Verify if UDP port is being offloaded by HW */
4303                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4304                         return features;
4305
4306 #if IS_ENABLED(CONFIG_GENEVE)
4307                 /* Support Geneve offload for default UDP port */
4308                 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4309                         return features;
4310 #endif
4311                 break;
4312 #ifdef CONFIG_MLX5_EN_IPSEC
4313         case IPPROTO_ESP:
4314                 return mlx5e_ipsec_feature_check(skb, features);
4315 #endif
4316         }
4317
4318 out:
4319         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4320         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4321 }
4322
4323 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4324                                        struct net_device *netdev,
4325                                        netdev_features_t features)
4326 {
4327         struct mlx5e_priv *priv = netdev_priv(netdev);
4328
4329         features = vlan_features_check(skb, features);
4330         features = vxlan_features_check(skb, features);
4331
4332         /* Validate if the tunneled packet is being offloaded by HW */
4333         if (skb->encapsulation &&
4334             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4335                 return mlx5e_tunnel_features_check(priv, skb, features);
4336
4337         return features;
4338 }
4339
4340 static void mlx5e_tx_timeout_work(struct work_struct *work)
4341 {
4342         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4343                                                tx_timeout_work);
4344         struct net_device *netdev = priv->netdev;
4345         int i;
4346
4347         rtnl_lock();
4348         mutex_lock(&priv->state_lock);
4349
4350         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4351                 goto unlock;
4352
4353         for (i = 0; i < netdev->real_num_tx_queues; i++) {
4354                 struct netdev_queue *dev_queue =
4355                         netdev_get_tx_queue(netdev, i);
4356                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4357
4358                 if (!netif_xmit_stopped(dev_queue))
4359                         continue;
4360
4361                 if (mlx5e_reporter_tx_timeout(sq))
4362                 /* break if tried to reopened channels */
4363                         break;
4364         }
4365
4366 unlock:
4367         mutex_unlock(&priv->state_lock);
4368         rtnl_unlock();
4369 }
4370
4371 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue)
4372 {
4373         struct mlx5e_priv *priv = netdev_priv(dev);
4374
4375         netdev_err(dev, "TX timeout detected\n");
4376         queue_work(priv->wq, &priv->tx_timeout_work);
4377 }
4378
4379 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4380 {
4381         struct net_device *netdev = priv->netdev;
4382         struct mlx5e_params new_params;
4383
4384         if (priv->channels.params.packet_merge.type != MLX5E_PACKET_MERGE_NONE) {
4385                 netdev_warn(netdev, "can't set XDP while HW-GRO/LRO is on, disable them first\n");
4386                 return -EINVAL;
4387         }
4388
4389         if (mlx5_fpga_is_ipsec_device(priv->mdev)) {
4390                 netdev_warn(netdev,
4391                             "XDP is not available on Innova cards with IPsec support\n");
4392                 return -EINVAL;
4393         }
4394
4395         new_params = priv->channels.params;
4396         new_params.xdp_prog = prog;
4397
4398         /* No XSK params: AF_XDP can't be enabled yet at the point of setting
4399          * the XDP program.
4400          */
4401         if (!mlx5e_rx_is_linear_skb(&new_params, NULL)) {
4402                 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4403                             new_params.sw_mtu,
4404                             mlx5e_xdp_max_mtu(&new_params, NULL));
4405                 return -EINVAL;
4406         }
4407
4408         return 0;
4409 }
4410
4411 static void mlx5e_rq_replace_xdp_prog(struct mlx5e_rq *rq, struct bpf_prog *prog)
4412 {
4413         struct bpf_prog *old_prog;
4414
4415         old_prog = rcu_replace_pointer(rq->xdp_prog, prog,
4416                                        lockdep_is_held(&rq->priv->state_lock));
4417         if (old_prog)
4418                 bpf_prog_put(old_prog);
4419 }
4420
4421 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4422 {
4423         struct mlx5e_priv *priv = netdev_priv(netdev);
4424         struct mlx5e_params new_params;
4425         struct bpf_prog *old_prog;
4426         int err = 0;
4427         bool reset;
4428         int i;
4429
4430         mutex_lock(&priv->state_lock);
4431
4432         if (prog) {
4433                 err = mlx5e_xdp_allowed(priv, prog);
4434                 if (err)
4435                         goto unlock;
4436         }
4437
4438         /* no need for full reset when exchanging programs */
4439         reset = (!priv->channels.params.xdp_prog || !prog);
4440
4441         new_params = priv->channels.params;
4442         new_params.xdp_prog = prog;
4443         if (reset)
4444                 mlx5e_set_rq_type(priv->mdev, &new_params);
4445         old_prog = priv->channels.params.xdp_prog;
4446
4447         err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
4448         if (err)
4449                 goto unlock;
4450
4451         if (old_prog)
4452                 bpf_prog_put(old_prog);
4453
4454         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4455                 goto unlock;
4456
4457         /* exchanging programs w/o reset, we update ref counts on behalf
4458          * of the channels RQs here.
4459          */
4460         bpf_prog_add(prog, priv->channels.num);
4461         for (i = 0; i < priv->channels.num; i++) {
4462                 struct mlx5e_channel *c = priv->channels.c[i];
4463
4464                 mlx5e_rq_replace_xdp_prog(&c->rq, prog);
4465                 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) {
4466                         bpf_prog_inc(prog);
4467                         mlx5e_rq_replace_xdp_prog(&c->xskrq, prog);
4468                 }
4469         }
4470
4471 unlock:
4472         mutex_unlock(&priv->state_lock);
4473         return err;
4474 }
4475
4476 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4477 {
4478         switch (xdp->command) {
4479         case XDP_SETUP_PROG:
4480                 return mlx5e_xdp_set(dev, xdp->prog);
4481         case XDP_SETUP_XSK_POOL:
4482                 return mlx5e_xsk_setup_pool(dev, xdp->xsk.pool,
4483                                             xdp->xsk.queue_id);
4484         default:
4485                 return -EINVAL;
4486         }
4487 }
4488
4489 #ifdef CONFIG_MLX5_ESWITCH
4490 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4491                                 struct net_device *dev, u32 filter_mask,
4492                                 int nlflags)
4493 {
4494         struct mlx5e_priv *priv = netdev_priv(dev);
4495         struct mlx5_core_dev *mdev = priv->mdev;
4496         u8 mode, setting;
4497         int err;
4498
4499         err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4500         if (err)
4501                 return err;
4502         mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4503         return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4504                                        mode,
4505                                        0, 0, nlflags, filter_mask, NULL);
4506 }
4507
4508 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4509                                 u16 flags, struct netlink_ext_ack *extack)
4510 {
4511         struct mlx5e_priv *priv = netdev_priv(dev);
4512         struct mlx5_core_dev *mdev = priv->mdev;
4513         struct nlattr *attr, *br_spec;
4514         u16 mode = BRIDGE_MODE_UNDEF;
4515         u8 setting;
4516         int rem;
4517
4518         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4519         if (!br_spec)
4520                 return -EINVAL;
4521
4522         nla_for_each_nested(attr, br_spec, rem) {
4523                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4524                         continue;
4525
4526                 if (nla_len(attr) < sizeof(mode))
4527                         return -EINVAL;
4528
4529                 mode = nla_get_u16(attr);
4530                 if (mode > BRIDGE_MODE_VEPA)
4531                         return -EINVAL;
4532
4533                 break;
4534         }
4535
4536         if (mode == BRIDGE_MODE_UNDEF)
4537                 return -EINVAL;
4538
4539         setting = (mode == BRIDGE_MODE_VEPA) ?  1 : 0;
4540         return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4541 }
4542 #endif
4543
4544 const struct net_device_ops mlx5e_netdev_ops = {
4545         .ndo_open                = mlx5e_open,
4546         .ndo_stop                = mlx5e_close,
4547         .ndo_start_xmit          = mlx5e_xmit,
4548         .ndo_setup_tc            = mlx5e_setup_tc,
4549         .ndo_select_queue        = mlx5e_select_queue,
4550         .ndo_get_stats64         = mlx5e_get_stats,
4551         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4552         .ndo_set_mac_address     = mlx5e_set_mac,
4553         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4554         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4555         .ndo_set_features        = mlx5e_set_features,
4556         .ndo_fix_features        = mlx5e_fix_features,
4557         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4558         .ndo_eth_ioctl            = mlx5e_ioctl,
4559         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4560         .ndo_features_check      = mlx5e_features_check,
4561         .ndo_tx_timeout          = mlx5e_tx_timeout,
4562         .ndo_bpf                 = mlx5e_xdp,
4563         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4564         .ndo_xsk_wakeup          = mlx5e_xsk_wakeup,
4565 #ifdef CONFIG_MLX5_EN_ARFS
4566         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4567 #endif
4568 #ifdef CONFIG_MLX5_ESWITCH
4569         .ndo_bridge_setlink      = mlx5e_bridge_setlink,
4570         .ndo_bridge_getlink      = mlx5e_bridge_getlink,
4571
4572         /* SRIOV E-Switch NDOs */
4573         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4574         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4575         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4576         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4577         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4578         .ndo_get_vf_config       = mlx5e_get_vf_config,
4579         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4580         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4581         .ndo_has_offload_stats   = mlx5e_has_offload_stats,
4582         .ndo_get_offload_stats   = mlx5e_get_offload_stats,
4583 #endif
4584         .ndo_get_devlink_port    = mlx5e_get_devlink_port,
4585 };
4586
4587 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4588 {
4589         int i;
4590
4591         /* The supported periods are organized in ascending order */
4592         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4593                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4594                         break;
4595
4596         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4597 }
4598
4599 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu)
4600 {
4601         struct mlx5e_params *params = &priv->channels.params;
4602         struct mlx5_core_dev *mdev = priv->mdev;
4603         u8 rx_cq_period_mode;
4604
4605         params->sw_mtu = mtu;
4606         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4607         params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2,
4608                                      priv->max_nch);
4609         mlx5e_params_mqprio_reset(params);
4610
4611         /* Set an initial non-zero value, so that mlx5e_select_queue won't
4612          * divide by zero if called before first activating channels.
4613          */
4614         priv->num_tc_x_num_ch = params->num_channels * params->mqprio.num_tc;
4615
4616         /* SQ */
4617         params->log_sq_size = is_kdump_kernel() ?
4618                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4619                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4620         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
4621
4622         /* XDP SQ */
4623         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
4624
4625         /* set CQE compression */
4626         params->rx_cqe_compress_def = false;
4627         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4628             MLX5_CAP_GEN(mdev, vport_group_manager))
4629                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4630
4631         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4632         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4633
4634         /* RQ */
4635         mlx5e_build_rq_params(mdev, params);
4636
4637         /* HW LRO */
4638         if (MLX5_CAP_ETH(mdev, lro_cap) &&
4639             params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4640                 /* No XSK params: checking the availability of striding RQ in general. */
4641                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4642                         params->packet_merge.type = slow_pci_heuristic(mdev) ?
4643                                 MLX5E_PACKET_MERGE_NONE : MLX5E_PACKET_MERGE_LRO;
4644         }
4645         params->packet_merge.timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4646
4647         /* CQ moderation params */
4648         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4649                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4650                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4651         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4652         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4653         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4654         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4655
4656         /* TX inline */
4657         mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
4658
4659         params->tunneled_offload_en = mlx5_tunnel_inner_ft_supported(mdev);
4660
4661         /* AF_XDP */
4662         params->xsk = xsk;
4663
4664         /* Do not update netdev->features directly in here
4665          * on mlx5e_attach_netdev() we will call mlx5e_update_features()
4666          * To update netdev->features please modify mlx5e_fix_features()
4667          */
4668 }
4669
4670 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4671 {
4672         struct mlx5e_priv *priv = netdev_priv(netdev);
4673         u8 addr[ETH_ALEN];
4674
4675         mlx5_query_mac_address(priv->mdev, addr);
4676         if (is_zero_ether_addr(addr) &&
4677             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4678                 eth_hw_addr_random(netdev);
4679                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4680                 return;
4681         }
4682
4683         eth_hw_addr_set(netdev, addr);
4684 }
4685
4686 static int mlx5e_vxlan_set_port(struct net_device *netdev, unsigned int table,
4687                                 unsigned int entry, struct udp_tunnel_info *ti)
4688 {
4689         struct mlx5e_priv *priv = netdev_priv(netdev);
4690
4691         return mlx5_vxlan_add_port(priv->mdev->vxlan, ntohs(ti->port));
4692 }
4693
4694 static int mlx5e_vxlan_unset_port(struct net_device *netdev, unsigned int table,
4695                                   unsigned int entry, struct udp_tunnel_info *ti)
4696 {
4697         struct mlx5e_priv *priv = netdev_priv(netdev);
4698
4699         return mlx5_vxlan_del_port(priv->mdev->vxlan, ntohs(ti->port));
4700 }
4701
4702 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv)
4703 {
4704         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4705                 return;
4706
4707         priv->nic_info.set_port = mlx5e_vxlan_set_port;
4708         priv->nic_info.unset_port = mlx5e_vxlan_unset_port;
4709         priv->nic_info.flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
4710                                 UDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN;
4711         priv->nic_info.tables[0].tunnel_types = UDP_TUNNEL_TYPE_VXLAN;
4712         /* Don't count the space hard-coded to the IANA port */
4713         priv->nic_info.tables[0].n_entries =
4714                 mlx5_vxlan_max_udp_ports(priv->mdev) - 1;
4715
4716         priv->netdev->udp_tunnel_nic_info = &priv->nic_info;
4717 }
4718
4719 static bool mlx5e_tunnel_any_tx_proto_supported(struct mlx5_core_dev *mdev)
4720 {
4721         int tt;
4722
4723         for (tt = 0; tt < MLX5_NUM_TUNNEL_TT; tt++) {
4724                 if (mlx5e_tunnel_proto_supported_tx(mdev, mlx5_get_proto_by_tunnel_type(tt)))
4725                         return true;
4726         }
4727         return (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev));
4728 }
4729
4730 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4731 {
4732         struct mlx5e_priv *priv = netdev_priv(netdev);
4733         struct mlx5_core_dev *mdev = priv->mdev;
4734         bool fcs_supported;
4735         bool fcs_enabled;
4736
4737         SET_NETDEV_DEV(netdev, mdev->device);
4738
4739         netdev->netdev_ops = &mlx5e_netdev_ops;
4740
4741         mlx5e_dcbnl_build_netdev(netdev);
4742
4743         netdev->watchdog_timeo    = 15 * HZ;
4744
4745         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4746
4747         netdev->vlan_features    |= NETIF_F_SG;
4748         netdev->vlan_features    |= NETIF_F_HW_CSUM;
4749         netdev->vlan_features    |= NETIF_F_GRO;
4750         netdev->vlan_features    |= NETIF_F_TSO;
4751         netdev->vlan_features    |= NETIF_F_TSO6;
4752         netdev->vlan_features    |= NETIF_F_RXCSUM;
4753         netdev->vlan_features    |= NETIF_F_RXHASH;
4754
4755         netdev->mpls_features    |= NETIF_F_SG;
4756         netdev->mpls_features    |= NETIF_F_HW_CSUM;
4757         netdev->mpls_features    |= NETIF_F_TSO;
4758         netdev->mpls_features    |= NETIF_F_TSO6;
4759
4760         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4761         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4762
4763         /* Tunneled LRO is not supported in the driver, and the same RQs are
4764          * shared between inner and outer TIRs, so the driver can't disable LRO
4765          * for inner TIRs while having it enabled for outer TIRs. Due to this,
4766          * block LRO altogether if the firmware declares tunneled LRO support.
4767          */
4768         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4769             !MLX5_CAP_ETH(mdev, tunnel_lro_vxlan) &&
4770             !MLX5_CAP_ETH(mdev, tunnel_lro_gre) &&
4771             mlx5e_check_fragmented_striding_rq_cap(mdev))
4772                 netdev->vlan_features    |= NETIF_F_LRO;
4773
4774         netdev->hw_features       = netdev->vlan_features;
4775         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4776         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4777         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4778         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4779
4780         if (!!MLX5_CAP_GEN(mdev, shampo) &&
4781             mlx5e_check_fragmented_striding_rq_cap(mdev))
4782                 netdev->hw_features    |= NETIF_F_GRO_HW;
4783
4784         if (mlx5e_tunnel_any_tx_proto_supported(mdev)) {
4785                 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4786                 netdev->hw_enc_features |= NETIF_F_TSO;
4787                 netdev->hw_enc_features |= NETIF_F_TSO6;
4788                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4789         }
4790
4791         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4792                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL;
4793                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
4794                 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL;
4795         }
4796
4797         if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_GRE)) {
4798                 netdev->hw_features     |= NETIF_F_GSO_GRE;
4799                 netdev->hw_enc_features |= NETIF_F_GSO_GRE;
4800                 netdev->gso_partial_features |= NETIF_F_GSO_GRE;
4801         }
4802
4803         if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_IPIP)) {
4804                 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
4805                                        NETIF_F_GSO_IPXIP6;
4806                 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
4807                                            NETIF_F_GSO_IPXIP6;
4808                 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
4809                                                 NETIF_F_GSO_IPXIP6;
4810         }
4811
4812         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4813         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4814         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4815         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4816
4817         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4818
4819         if (fcs_supported)
4820                 netdev->hw_features |= NETIF_F_RXALL;
4821
4822         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4823                 netdev->hw_features |= NETIF_F_RXFCS;
4824
4825         if (mlx5_qos_is_supported(mdev))
4826                 netdev->hw_features |= NETIF_F_HW_TC;
4827
4828         netdev->features          = netdev->hw_features;
4829
4830         /* Defaults */
4831         if (fcs_enabled)
4832                 netdev->features  &= ~NETIF_F_RXALL;
4833         netdev->features  &= ~NETIF_F_LRO;
4834         netdev->features  &= ~NETIF_F_GRO_HW;
4835         netdev->features  &= ~NETIF_F_RXFCS;
4836
4837 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4838         if (FT_CAP(flow_modify_en) &&
4839             FT_CAP(modify_root) &&
4840             FT_CAP(identified_miss_table_mode) &&
4841             FT_CAP(flow_table_modify)) {
4842 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
4843                 netdev->hw_features      |= NETIF_F_HW_TC;
4844 #endif
4845 #ifdef CONFIG_MLX5_EN_ARFS
4846                 netdev->hw_features      |= NETIF_F_NTUPLE;
4847 #endif
4848         }
4849
4850         netdev->features         |= NETIF_F_HIGHDMA;
4851         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4852
4853         netdev->priv_flags       |= IFF_UNICAST_FLT;
4854
4855         mlx5e_set_netdev_dev_addr(netdev);
4856         mlx5e_ipsec_build_netdev(priv);
4857         mlx5e_tls_build_netdev(priv);
4858 }
4859
4860 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4861 {
4862         u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {};
4863         u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {};
4864         struct mlx5_core_dev *mdev = priv->mdev;
4865         int err;
4866
4867         MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
4868         err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4869         if (!err)
4870                 priv->q_counter =
4871                         MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4872
4873         err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4874         if (!err)
4875                 priv->drop_rq_q_counter =
4876                         MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4877 }
4878
4879 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4880 {
4881         u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {};
4882
4883         MLX5_SET(dealloc_q_counter_in, in, opcode,
4884                  MLX5_CMD_OP_DEALLOC_Q_COUNTER);
4885         if (priv->q_counter) {
4886                 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
4887                          priv->q_counter);
4888                 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
4889         }
4890
4891         if (priv->drop_rq_q_counter) {
4892                 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
4893                          priv->drop_rq_q_counter);
4894                 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
4895         }
4896 }
4897
4898 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
4899                           struct net_device *netdev)
4900 {
4901         struct mlx5e_priv *priv = netdev_priv(netdev);
4902         int err;
4903
4904         mlx5e_build_nic_params(priv, &priv->xsk, netdev->mtu);
4905         mlx5e_vxlan_set_netdev_info(priv);
4906
4907         mlx5e_timestamp_init(priv);
4908
4909         err = mlx5e_fs_init(priv);
4910         if (err) {
4911                 mlx5_core_err(mdev, "FS initialization failed, %d\n", err);
4912                 return err;
4913         }
4914
4915         err = mlx5e_ipsec_init(priv);
4916         if (err)
4917                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4918
4919         err = mlx5e_tls_init(priv);
4920         if (err)
4921                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4922
4923         mlx5e_health_create_reporters(priv);
4924         return 0;
4925 }
4926
4927 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4928 {
4929         mlx5e_health_destroy_reporters(priv);
4930         mlx5e_tls_cleanup(priv);
4931         mlx5e_ipsec_cleanup(priv);
4932         mlx5e_fs_cleanup(priv);
4933 }
4934
4935 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4936 {
4937         struct mlx5_core_dev *mdev = priv->mdev;
4938         enum mlx5e_rx_res_features features;
4939         int err;
4940
4941         priv->rx_res = mlx5e_rx_res_alloc();
4942         if (!priv->rx_res)
4943                 return -ENOMEM;
4944
4945         mlx5e_create_q_counters(priv);
4946
4947         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4948         if (err) {
4949                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4950                 goto err_destroy_q_counters;
4951         }
4952
4953         features = MLX5E_RX_RES_FEATURE_XSK | MLX5E_RX_RES_FEATURE_PTP;
4954         if (priv->channels.params.tunneled_offload_en)
4955                 features |= MLX5E_RX_RES_FEATURE_INNER_FT;
4956         err = mlx5e_rx_res_init(priv->rx_res, priv->mdev, features,
4957                                 priv->max_nch, priv->drop_rq.rqn,
4958                                 &priv->channels.params.packet_merge,
4959                                 priv->channels.params.num_channels);
4960         if (err)
4961                 goto err_close_drop_rq;
4962
4963         err = mlx5e_create_flow_steering(priv);
4964         if (err) {
4965                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4966                 goto err_destroy_rx_res;
4967         }
4968
4969         err = mlx5e_tc_nic_init(priv);
4970         if (err)
4971                 goto err_destroy_flow_steering;
4972
4973         err = mlx5e_accel_init_rx(priv);
4974         if (err)
4975                 goto err_tc_nic_cleanup;
4976
4977 #ifdef CONFIG_MLX5_EN_ARFS
4978         priv->netdev->rx_cpu_rmap =  mlx5_eq_table_get_rmap(priv->mdev);
4979 #endif
4980
4981         return 0;
4982
4983 err_tc_nic_cleanup:
4984         mlx5e_tc_nic_cleanup(priv);
4985 err_destroy_flow_steering:
4986         mlx5e_destroy_flow_steering(priv);
4987 err_destroy_rx_res:
4988         mlx5e_rx_res_destroy(priv->rx_res);
4989 err_close_drop_rq:
4990         mlx5e_close_drop_rq(&priv->drop_rq);
4991 err_destroy_q_counters:
4992         mlx5e_destroy_q_counters(priv);
4993         mlx5e_rx_res_free(priv->rx_res);
4994         priv->rx_res = NULL;
4995         return err;
4996 }
4997
4998 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4999 {
5000         mlx5e_accel_cleanup_rx(priv);
5001         mlx5e_tc_nic_cleanup(priv);
5002         mlx5e_destroy_flow_steering(priv);
5003         mlx5e_rx_res_destroy(priv->rx_res);
5004         mlx5e_close_drop_rq(&priv->drop_rq);
5005         mlx5e_destroy_q_counters(priv);
5006         mlx5e_rx_res_free(priv->rx_res);
5007         priv->rx_res = NULL;
5008 }
5009
5010 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5011 {
5012         int err;
5013
5014         err = mlx5e_create_tises(priv);
5015         if (err) {
5016                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
5017                 return err;
5018         }
5019
5020         mlx5e_dcbnl_initialize(priv);
5021         return 0;
5022 }
5023
5024 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5025 {
5026         struct net_device *netdev = priv->netdev;
5027         struct mlx5_core_dev *mdev = priv->mdev;
5028
5029         mlx5e_init_l2_addr(priv);
5030
5031         /* Marking the link as currently not needed by the Driver */
5032         if (!netif_running(netdev))
5033                 mlx5e_modify_admin_state(mdev, MLX5_PORT_DOWN);
5034
5035         mlx5e_set_netdev_mtu_boundaries(priv);
5036         mlx5e_set_dev_port_mtu(priv);
5037
5038         mlx5_lag_add_netdev(mdev, netdev);
5039
5040         mlx5e_enable_async_events(priv);
5041         mlx5e_enable_blocking_events(priv);
5042         if (mlx5e_monitor_counter_supported(priv))
5043                 mlx5e_monitor_counter_init(priv);
5044
5045         mlx5e_hv_vhca_stats_create(priv);
5046         if (netdev->reg_state != NETREG_REGISTERED)
5047                 return;
5048         mlx5e_dcbnl_init_app(priv);
5049
5050         mlx5e_nic_set_rx_mode(priv);
5051
5052         rtnl_lock();
5053         if (netif_running(netdev))
5054                 mlx5e_open(netdev);
5055         udp_tunnel_nic_reset_ntf(priv->netdev);
5056         netif_device_attach(netdev);
5057         rtnl_unlock();
5058 }
5059
5060 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5061 {
5062         struct mlx5_core_dev *mdev = priv->mdev;
5063
5064         if (priv->netdev->reg_state == NETREG_REGISTERED)
5065                 mlx5e_dcbnl_delete_app(priv);
5066
5067         rtnl_lock();
5068         if (netif_running(priv->netdev))
5069                 mlx5e_close(priv->netdev);
5070         netif_device_detach(priv->netdev);
5071         rtnl_unlock();
5072
5073         mlx5e_nic_set_rx_mode(priv);
5074
5075         mlx5e_hv_vhca_stats_destroy(priv);
5076         if (mlx5e_monitor_counter_supported(priv))
5077                 mlx5e_monitor_counter_cleanup(priv);
5078
5079         mlx5e_disable_blocking_events(priv);
5080         if (priv->en_trap) {
5081                 mlx5e_deactivate_trap(priv);
5082                 mlx5e_close_trap(priv->en_trap);
5083                 priv->en_trap = NULL;
5084         }
5085         mlx5e_disable_async_events(priv);
5086         mlx5_lag_remove_netdev(mdev, priv->netdev);
5087         mlx5_vxlan_reset_to_default(mdev->vxlan);
5088 }
5089
5090 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5091 {
5092         return mlx5e_refresh_tirs(priv, false, false);
5093 }
5094
5095 static const struct mlx5e_profile mlx5e_nic_profile = {
5096         .init              = mlx5e_nic_init,
5097         .cleanup           = mlx5e_nic_cleanup,
5098         .init_rx           = mlx5e_init_nic_rx,
5099         .cleanup_rx        = mlx5e_cleanup_nic_rx,
5100         .init_tx           = mlx5e_init_nic_tx,
5101         .cleanup_tx        = mlx5e_cleanup_nic_tx,
5102         .enable            = mlx5e_nic_enable,
5103         .disable           = mlx5e_nic_disable,
5104         .update_rx         = mlx5e_update_nic_rx,
5105         .update_stats      = mlx5e_stats_update_ndo_stats,
5106         .update_carrier    = mlx5e_update_carrier,
5107         .rx_handlers       = &mlx5e_rx_handlers_nic,
5108         .max_tc            = MLX5E_MAX_NUM_TC,
5109         .rq_groups         = MLX5E_NUM_RQ_GROUPS(XSK),
5110         .stats_grps        = mlx5e_nic_stats_grps,
5111         .stats_grps_num    = mlx5e_nic_stats_grps_num,
5112         .rx_ptp_support    = true,
5113 };
5114
5115 static unsigned int
5116 mlx5e_calc_max_nch(struct mlx5_core_dev *mdev, struct net_device *netdev,
5117                    const struct mlx5e_profile *profile)
5118
5119 {
5120         unsigned int max_nch, tmp;
5121
5122         /* core resources */
5123         max_nch = mlx5e_get_max_num_channels(mdev);
5124
5125         /* netdev rx queues */
5126         tmp = netdev->num_rx_queues / max_t(u8, profile->rq_groups, 1);
5127         max_nch = min_t(unsigned int, max_nch, tmp);
5128
5129         /* netdev tx queues */
5130         tmp = netdev->num_tx_queues;
5131         if (mlx5_qos_is_supported(mdev))
5132                 tmp -= mlx5e_qos_max_leaf_nodes(mdev);
5133         if (MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn))
5134                 tmp -= profile->max_tc;
5135         tmp = tmp / profile->max_tc;
5136         max_nch = min_t(unsigned int, max_nch, tmp);
5137
5138         return max_nch;
5139 }
5140
5141 /* mlx5e generic netdev management API (move to en_common.c) */
5142 int mlx5e_priv_init(struct mlx5e_priv *priv,
5143                     const struct mlx5e_profile *profile,
5144                     struct net_device *netdev,
5145                     struct mlx5_core_dev *mdev)
5146 {
5147         /* priv init */
5148         priv->mdev        = mdev;
5149         priv->netdev      = netdev;
5150         priv->msglevel    = MLX5E_MSG_LEVEL;
5151         priv->max_nch     = mlx5e_calc_max_nch(mdev, netdev, profile);
5152         priv->stats_nch   = priv->max_nch;
5153         priv->max_opened_tc = 1;
5154
5155         if (!alloc_cpumask_var(&priv->scratchpad.cpumask, GFP_KERNEL))
5156                 return -ENOMEM;
5157
5158         mutex_init(&priv->state_lock);
5159         hash_init(priv->htb.qos_tc2node);
5160         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5161         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5162         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5163         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5164
5165         priv->wq = create_singlethread_workqueue("mlx5e");
5166         if (!priv->wq)
5167                 goto err_free_cpumask;
5168
5169         return 0;
5170
5171 err_free_cpumask:
5172         free_cpumask_var(priv->scratchpad.cpumask);
5173
5174         return -ENOMEM;
5175 }
5176
5177 void mlx5e_priv_cleanup(struct mlx5e_priv *priv)
5178 {
5179         int i;
5180
5181         /* bail if change profile failed and also rollback failed */
5182         if (!priv->mdev)
5183                 return;
5184
5185         destroy_workqueue(priv->wq);
5186         free_cpumask_var(priv->scratchpad.cpumask);
5187
5188         for (i = 0; i < priv->htb.max_qos_sqs; i++)
5189                 kfree(priv->htb.qos_sq_stats[i]);
5190         kvfree(priv->htb.qos_sq_stats);
5191
5192         if (priv->mqprio_rl) {
5193                 mlx5e_mqprio_rl_cleanup(priv->mqprio_rl);
5194                 mlx5e_mqprio_rl_free(priv->mqprio_rl);
5195         }
5196
5197         memset(priv, 0, sizeof(*priv));
5198 }
5199
5200 struct net_device *
5201 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile,
5202                     unsigned int txqs, unsigned int rxqs)
5203 {
5204         struct net_device *netdev;
5205         int err;
5206
5207         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), txqs, rxqs);
5208         if (!netdev) {
5209                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5210                 return NULL;
5211         }
5212
5213         err = mlx5e_priv_init(netdev_priv(netdev), profile, netdev, mdev);
5214         if (err) {
5215                 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5216                 goto err_free_netdev;
5217         }
5218
5219         netif_carrier_off(netdev);
5220         dev_net_set(netdev, mlx5_core_net(mdev));
5221
5222         return netdev;
5223
5224 err_free_netdev:
5225         free_netdev(netdev);
5226
5227         return NULL;
5228 }
5229
5230 static void mlx5e_update_features(struct net_device *netdev)
5231 {
5232         if (netdev->reg_state != NETREG_REGISTERED)
5233                 return; /* features will be updated on netdev registration */
5234
5235         rtnl_lock();
5236         netdev_update_features(netdev);
5237         rtnl_unlock();
5238 }
5239
5240 static void mlx5e_reset_channels(struct net_device *netdev)
5241 {
5242         netdev_reset_tc(netdev);
5243 }
5244
5245 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5246 {
5247         const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED;
5248         const struct mlx5e_profile *profile = priv->profile;
5249         int max_nch;
5250         int err;
5251
5252         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5253
5254         /* max number of channels may have changed */
5255         max_nch = mlx5e_calc_max_nch(priv->mdev, priv->netdev, profile);
5256         if (priv->channels.params.num_channels > max_nch) {
5257                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5258                 /* Reducing the number of channels - RXFH has to be reset, and
5259                  * mlx5e_num_channels_changed below will build the RQT.
5260                  */
5261                 priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED;
5262                 priv->channels.params.num_channels = max_nch;
5263                 if (priv->channels.params.mqprio.mode == TC_MQPRIO_MODE_CHANNEL) {
5264                         mlx5_core_warn(priv->mdev, "MLX5E: Disabling MQPRIO channel mode\n");
5265                         mlx5e_params_mqprio_reset(&priv->channels.params);
5266                 }
5267         }
5268         if (max_nch != priv->max_nch) {
5269                 mlx5_core_warn(priv->mdev,
5270                                "MLX5E: Updating max number of channels from %u to %u\n",
5271                                priv->max_nch, max_nch);
5272                 priv->max_nch = max_nch;
5273         }
5274
5275         /* 1. Set the real number of queues in the kernel the first time.
5276          * 2. Set our default XPS cpumask.
5277          * 3. Build the RQT.
5278          *
5279          * rtnl_lock is required by netif_set_real_num_*_queues in case the
5280          * netdev has been registered by this point (if this function was called
5281          * in the reload or resume flow).
5282          */
5283         if (take_rtnl)
5284                 rtnl_lock();
5285         err = mlx5e_num_channels_changed(priv);
5286         if (take_rtnl)
5287                 rtnl_unlock();
5288         if (err)
5289                 goto out;
5290
5291         err = profile->init_tx(priv);
5292         if (err)
5293                 goto out;
5294
5295         err = profile->init_rx(priv);
5296         if (err)
5297                 goto err_cleanup_tx;
5298
5299         if (profile->enable)
5300                 profile->enable(priv);
5301
5302         mlx5e_update_features(priv->netdev);
5303
5304         return 0;
5305
5306 err_cleanup_tx:
5307         profile->cleanup_tx(priv);
5308
5309 out:
5310         mlx5e_reset_channels(priv->netdev);
5311         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5312         cancel_work_sync(&priv->update_stats_work);
5313         return err;
5314 }
5315
5316 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5317 {
5318         const struct mlx5e_profile *profile = priv->profile;
5319
5320         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5321
5322         if (profile->disable)
5323                 profile->disable(priv);
5324         flush_workqueue(priv->wq);
5325
5326         profile->cleanup_rx(priv);
5327         profile->cleanup_tx(priv);
5328         mlx5e_reset_channels(priv->netdev);
5329         cancel_work_sync(&priv->update_stats_work);
5330 }
5331
5332 static int
5333 mlx5e_netdev_attach_profile(struct net_device *netdev, struct mlx5_core_dev *mdev,
5334                             const struct mlx5e_profile *new_profile, void *new_ppriv)
5335 {
5336         struct mlx5e_priv *priv = netdev_priv(netdev);
5337         int err;
5338
5339         err = mlx5e_priv_init(priv, new_profile, netdev, mdev);
5340         if (err) {
5341                 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5342                 return err;
5343         }
5344         netif_carrier_off(netdev);
5345         priv->profile = new_profile;
5346         priv->ppriv = new_ppriv;
5347         err = new_profile->init(priv->mdev, priv->netdev);
5348         if (err)
5349                 goto priv_cleanup;
5350         err = mlx5e_attach_netdev(priv);
5351         if (err)
5352                 goto profile_cleanup;
5353         return err;
5354
5355 profile_cleanup:
5356         new_profile->cleanup(priv);
5357 priv_cleanup:
5358         mlx5e_priv_cleanup(priv);
5359         return err;
5360 }
5361
5362 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
5363                                 const struct mlx5e_profile *new_profile, void *new_ppriv)
5364 {
5365         const struct mlx5e_profile *orig_profile = priv->profile;
5366         struct net_device *netdev = priv->netdev;
5367         struct mlx5_core_dev *mdev = priv->mdev;
5368         void *orig_ppriv = priv->ppriv;
5369         int err, rollback_err;
5370
5371         /* cleanup old profile */
5372         mlx5e_detach_netdev(priv);
5373         priv->profile->cleanup(priv);
5374         mlx5e_priv_cleanup(priv);
5375
5376         err = mlx5e_netdev_attach_profile(netdev, mdev, new_profile, new_ppriv);
5377         if (err) { /* roll back to original profile */
5378                 netdev_warn(netdev, "%s: new profile init failed, %d\n", __func__, err);
5379                 goto rollback;
5380         }
5381
5382         return 0;
5383
5384 rollback:
5385         rollback_err = mlx5e_netdev_attach_profile(netdev, mdev, orig_profile, orig_ppriv);
5386         if (rollback_err)
5387                 netdev_err(netdev, "%s: failed to rollback to orig profile, %d\n",
5388                            __func__, rollback_err);
5389         return err;
5390 }
5391
5392 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv)
5393 {
5394         mlx5e_netdev_change_profile(priv, &mlx5e_nic_profile, NULL);
5395 }
5396
5397 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5398 {
5399         struct net_device *netdev = priv->netdev;
5400
5401         mlx5e_priv_cleanup(priv);
5402         free_netdev(netdev);
5403 }
5404
5405 static int mlx5e_resume(struct auxiliary_device *adev)
5406 {
5407         struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5408         struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5409         struct net_device *netdev = priv->netdev;
5410         struct mlx5_core_dev *mdev = edev->mdev;
5411         int err;
5412
5413         if (netif_device_present(netdev))
5414                 return 0;
5415
5416         err = mlx5e_create_mdev_resources(mdev);
5417         if (err)
5418                 return err;
5419
5420         err = mlx5e_attach_netdev(priv);
5421         if (err) {
5422                 mlx5e_destroy_mdev_resources(mdev);
5423                 return err;
5424         }
5425
5426         return 0;
5427 }
5428
5429 static int mlx5e_suspend(struct auxiliary_device *adev, pm_message_t state)
5430 {
5431         struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5432         struct net_device *netdev = priv->netdev;
5433         struct mlx5_core_dev *mdev = priv->mdev;
5434
5435         if (!netif_device_present(netdev))
5436                 return -ENODEV;
5437
5438         mlx5e_detach_netdev(priv);
5439         mlx5e_destroy_mdev_resources(mdev);
5440         return 0;
5441 }
5442
5443 static int mlx5e_probe(struct auxiliary_device *adev,
5444                        const struct auxiliary_device_id *id)
5445 {
5446         struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5447         const struct mlx5e_profile *profile = &mlx5e_nic_profile;
5448         struct mlx5_core_dev *mdev = edev->mdev;
5449         struct net_device *netdev;
5450         pm_message_t state = {};
5451         unsigned int txqs, rxqs, ptp_txqs = 0;
5452         struct mlx5e_priv *priv;
5453         int qos_sqs = 0;
5454         int err;
5455         int nch;
5456
5457         if (MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn))
5458                 ptp_txqs = profile->max_tc;
5459
5460         if (mlx5_qos_is_supported(mdev))
5461                 qos_sqs = mlx5e_qos_max_leaf_nodes(mdev);
5462
5463         nch = mlx5e_get_max_num_channels(mdev);
5464         txqs = nch * profile->max_tc + ptp_txqs + qos_sqs;
5465         rxqs = nch * profile->rq_groups;
5466         netdev = mlx5e_create_netdev(mdev, profile, txqs, rxqs);
5467         if (!netdev) {
5468                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5469                 return -ENOMEM;
5470         }
5471
5472         mlx5e_build_nic_netdev(netdev);
5473
5474         priv = netdev_priv(netdev);
5475         dev_set_drvdata(&adev->dev, priv);
5476
5477         priv->profile = profile;
5478         priv->ppriv = NULL;
5479
5480         err = mlx5e_devlink_port_register(priv);
5481         if (err) {
5482                 mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err);
5483                 goto err_destroy_netdev;
5484         }
5485
5486         err = profile->init(mdev, netdev);
5487         if (err) {
5488                 mlx5_core_err(mdev, "mlx5e_nic_profile init failed, %d\n", err);
5489                 goto err_devlink_cleanup;
5490         }
5491
5492         err = mlx5e_resume(adev);
5493         if (err) {
5494                 mlx5_core_err(mdev, "mlx5e_resume failed, %d\n", err);
5495                 goto err_profile_cleanup;
5496         }
5497
5498         err = register_netdev(netdev);
5499         if (err) {
5500                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5501                 goto err_resume;
5502         }
5503
5504         mlx5e_devlink_port_type_eth_set(priv);
5505
5506         mlx5e_dcbnl_init_app(priv);
5507         mlx5_uplink_netdev_set(mdev, netdev);
5508         return 0;
5509
5510 err_resume:
5511         mlx5e_suspend(adev, state);
5512 err_profile_cleanup:
5513         profile->cleanup(priv);
5514 err_devlink_cleanup:
5515         mlx5e_devlink_port_unregister(priv);
5516 err_destroy_netdev:
5517         mlx5e_destroy_netdev(priv);
5518         return err;
5519 }
5520
5521 static void mlx5e_remove(struct auxiliary_device *adev)
5522 {
5523         struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5524         pm_message_t state = {};
5525
5526         mlx5e_dcbnl_delete_app(priv);
5527         unregister_netdev(priv->netdev);
5528         mlx5e_suspend(adev, state);
5529         priv->profile->cleanup(priv);
5530         mlx5e_devlink_port_unregister(priv);
5531         mlx5e_destroy_netdev(priv);
5532 }
5533
5534 static const struct auxiliary_device_id mlx5e_id_table[] = {
5535         { .name = MLX5_ADEV_NAME ".eth", },
5536         {},
5537 };
5538
5539 MODULE_DEVICE_TABLE(auxiliary, mlx5e_id_table);
5540
5541 static struct auxiliary_driver mlx5e_driver = {
5542         .name = "eth",
5543         .probe = mlx5e_probe,
5544         .remove = mlx5e_remove,
5545         .suspend = mlx5e_suspend,
5546         .resume = mlx5e_resume,
5547         .id_table = mlx5e_id_table,
5548 };
5549
5550 int mlx5e_init(void)
5551 {
5552         int ret;
5553
5554         mlx5e_ipsec_build_inverse_table();
5555         mlx5e_build_ptys2ethtool_map();
5556         ret = auxiliary_driver_register(&mlx5e_driver);
5557         if (ret)
5558                 return ret;
5559
5560         ret = mlx5e_rep_init();
5561         if (ret)
5562                 auxiliary_driver_unregister(&mlx5e_driver);
5563         return ret;
5564 }
5565
5566 void mlx5e_cleanup(void)
5567 {
5568         mlx5e_rep_cleanup();
5569         auxiliary_driver_unregister(&mlx5e_driver);
5570 }