2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
43 MLX5_EN_QP_FLUSH_TIMEOUT_MS = 5000,
44 MLX5_EN_QP_FLUSH_MSLEEP_QUANT = 20,
45 MLX5_EN_QP_FLUSH_MAX_ITER = MLX5_EN_QP_FLUSH_TIMEOUT_MS /
46 MLX5_EN_QP_FLUSH_MSLEEP_QUANT,
49 struct mlx5e_rq_param {
50 u32 rqc[MLX5_ST_SZ_DW(rqc)];
51 struct mlx5_wq_param wq;
55 struct mlx5e_sq_param {
56 u32 sqc[MLX5_ST_SZ_DW(sqc)];
57 struct mlx5_wq_param wq;
63 struct mlx5e_cq_param {
64 u32 cqc[MLX5_ST_SZ_DW(cqc)];
65 struct mlx5_wq_param wq;
70 struct mlx5e_channel_param {
71 struct mlx5e_rq_param rq;
72 struct mlx5e_sq_param sq;
73 struct mlx5e_sq_param icosq;
74 struct mlx5e_cq_param rx_cq;
75 struct mlx5e_cq_param tx_cq;
76 struct mlx5e_cq_param icosq_cq;
79 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
81 struct mlx5_core_dev *mdev = priv->mdev;
84 port_state = mlx5_query_vport_state(mdev,
85 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
87 if (port_state == VPORT_STATE_UP) {
88 netdev_info(priv->netdev, "Link up\n");
89 netif_carrier_on(priv->netdev);
91 netdev_info(priv->netdev, "Link down\n");
92 netif_carrier_off(priv->netdev);
96 static void mlx5e_update_carrier_work(struct work_struct *work)
98 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
101 mutex_lock(&priv->state_lock);
102 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
103 mlx5e_update_carrier(priv);
104 mutex_unlock(&priv->state_lock);
107 static void mlx5e_tx_timeout_work(struct work_struct *work)
109 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
114 mutex_lock(&priv->state_lock);
115 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
117 mlx5e_close_locked(priv->netdev);
118 err = mlx5e_open_locked(priv->netdev);
120 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
123 mutex_unlock(&priv->state_lock);
127 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
129 struct mlx5e_sw_stats *s = &priv->stats.sw;
130 struct mlx5e_rq_stats *rq_stats;
131 struct mlx5e_sq_stats *sq_stats;
132 u64 tx_offload_none = 0;
135 memset(s, 0, sizeof(*s));
136 for (i = 0; i < priv->params.num_channels; i++) {
137 rq_stats = &priv->channel[i]->rq.stats;
139 s->rx_packets += rq_stats->packets;
140 s->rx_bytes += rq_stats->bytes;
141 s->rx_lro_packets += rq_stats->lro_packets;
142 s->rx_lro_bytes += rq_stats->lro_bytes;
143 s->rx_csum_none += rq_stats->csum_none;
144 s->rx_csum_complete += rq_stats->csum_complete;
145 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
146 s->rx_wqe_err += rq_stats->wqe_err;
147 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
148 s->rx_mpwqe_frag += rq_stats->mpwqe_frag;
149 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
150 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
151 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
153 for (j = 0; j < priv->params.num_tc; j++) {
154 sq_stats = &priv->channel[i]->sq[j].stats;
156 s->tx_packets += sq_stats->packets;
157 s->tx_bytes += sq_stats->bytes;
158 s->tx_tso_packets += sq_stats->tso_packets;
159 s->tx_tso_bytes += sq_stats->tso_bytes;
160 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
161 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
162 s->tx_queue_stopped += sq_stats->stopped;
163 s->tx_queue_wake += sq_stats->wake;
164 s->tx_queue_dropped += sq_stats->dropped;
165 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
166 tx_offload_none += sq_stats->csum_none;
170 /* Update calculated offload counters */
171 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
172 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
174 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
175 priv->stats.pport.phy_counters,
176 counter_set.phys_layer_cntrs.link_down_events);
179 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
181 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
182 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
183 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
184 struct mlx5_core_dev *mdev = priv->mdev;
186 MLX5_SET(query_vport_counter_in, in, opcode,
187 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
188 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
189 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
191 memset(out, 0, outlen);
192 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
195 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
197 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
198 struct mlx5_core_dev *mdev = priv->mdev;
199 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
204 in = mlx5_vzalloc(sz);
208 MLX5_SET(ppcnt_reg, in, local_port, 1);
210 out = pstats->IEEE_802_3_counters;
211 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
212 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
214 out = pstats->RFC_2863_counters;
215 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
216 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
218 out = pstats->RFC_2819_counters;
219 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
220 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
222 out = pstats->phy_counters;
223 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
224 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
226 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
227 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
228 out = pstats->per_prio_counters[prio];
229 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
230 mlx5_core_access_reg(mdev, in, sz, out, sz,
231 MLX5_REG_PPCNT, 0, 0);
238 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
240 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
242 if (!priv->q_counter)
245 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
246 &qcnt->rx_out_of_buffer);
249 void mlx5e_update_stats(struct mlx5e_priv *priv)
251 mlx5e_update_q_counter(priv);
252 mlx5e_update_vport_counters(priv);
253 mlx5e_update_pport_counters(priv);
254 mlx5e_update_sw_counters(priv);
257 void mlx5e_update_stats_work(struct work_struct *work)
259 struct delayed_work *dwork = to_delayed_work(work);
260 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
262 mutex_lock(&priv->state_lock);
263 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
264 priv->profile->update_stats(priv);
265 queue_delayed_work(priv->wq, dwork,
266 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
268 mutex_unlock(&priv->state_lock);
271 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
272 enum mlx5_dev_event event, unsigned long param)
274 struct mlx5e_priv *priv = vpriv;
276 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
280 case MLX5_DEV_EVENT_PORT_UP:
281 case MLX5_DEV_EVENT_PORT_DOWN:
282 queue_work(priv->wq, &priv->update_carrier_work);
290 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
292 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
295 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
297 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
298 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
301 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
302 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
304 static int mlx5e_create_rq(struct mlx5e_channel *c,
305 struct mlx5e_rq_param *param,
308 struct mlx5e_priv *priv = c->priv;
309 struct mlx5_core_dev *mdev = priv->mdev;
310 void *rqc = param->rqc;
311 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
317 param->wq.db_numa_node = cpu_to_node(c->cpu);
319 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
324 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
326 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
328 switch (priv->params.rq_wq_type) {
329 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
330 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
331 GFP_KERNEL, cpu_to_node(c->cpu));
334 goto err_rq_wq_destroy;
336 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
337 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
338 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
340 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
341 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
342 rq->wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
343 byte_count = rq->wqe_sz;
345 default: /* MLX5_WQ_TYPE_LINKED_LIST */
346 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
347 cpu_to_node(c->cpu));
350 goto err_rq_wq_destroy;
352 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
353 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
354 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
356 rq->wqe_sz = (priv->params.lro_en) ?
357 priv->params.lro_wqe_sz :
358 MLX5E_SW2HW_MTU(priv->netdev->mtu);
359 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
360 byte_count = rq->wqe_sz;
361 byte_count |= MLX5_HW_START_PADDING;
364 for (i = 0; i < wq_sz; i++) {
365 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
367 wqe->data.byte_count = cpu_to_be32(byte_count);
370 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
371 rq->am.mode = priv->params.rx_cq_period_mode;
373 rq->wq_type = priv->params.rq_wq_type;
375 rq->netdev = c->netdev;
376 rq->tstamp = &priv->tstamp;
380 rq->mkey_be = c->mkey_be;
381 rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
386 mlx5_wq_destroy(&rq->wq_ctrl);
391 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
393 switch (rq->wq_type) {
394 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
397 default: /* MLX5_WQ_TYPE_LINKED_LIST */
401 mlx5_wq_destroy(&rq->wq_ctrl);
404 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
406 struct mlx5e_priv *priv = rq->priv;
407 struct mlx5_core_dev *mdev = priv->mdev;
415 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
416 sizeof(u64) * rq->wq_ctrl.buf.npages;
417 in = mlx5_vzalloc(inlen);
421 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
422 wq = MLX5_ADDR_OF(rqc, rqc, wq);
424 memcpy(rqc, param->rqc, sizeof(param->rqc));
426 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
427 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
428 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
429 MLX5_SET(rqc, rqc, vsd, priv->params.vlan_strip_disable);
430 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
431 MLX5_ADAPTER_PAGE_SHIFT);
432 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
434 mlx5_fill_page_array(&rq->wq_ctrl.buf,
435 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
437 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
444 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
447 struct mlx5e_channel *c = rq->channel;
448 struct mlx5e_priv *priv = c->priv;
449 struct mlx5_core_dev *mdev = priv->mdev;
456 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
457 in = mlx5_vzalloc(inlen);
461 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
463 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
464 MLX5_SET(rqc, rqc, state, next_state);
466 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
473 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
475 struct mlx5e_channel *c = rq->channel;
476 struct mlx5e_priv *priv = c->priv;
477 struct mlx5_core_dev *mdev = priv->mdev;
484 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
485 in = mlx5_vzalloc(inlen);
489 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
491 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
492 MLX5_SET64(modify_rq_in, in, modify_bitmask, MLX5_RQ_BITMASK_VSD);
493 MLX5_SET(rqc, rqc, vsd, vsd);
494 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
496 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
503 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
505 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
508 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
510 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
511 struct mlx5e_channel *c = rq->channel;
512 struct mlx5e_priv *priv = c->priv;
513 struct mlx5_wq_ll *wq = &rq->wq;
515 while (time_before(jiffies, exp_time)) {
516 if (wq->cur_sz >= priv->params.min_rx_wqes)
525 static int mlx5e_open_rq(struct mlx5e_channel *c,
526 struct mlx5e_rq_param *param,
529 struct mlx5e_sq *sq = &c->icosq;
530 u16 pi = sq->pc & sq->wq.sz_m1;
533 err = mlx5e_create_rq(c, param, rq);
537 err = mlx5e_enable_rq(rq, param);
541 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
545 if (param->am_enabled)
546 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
548 set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
550 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_NOP;
551 sq->ico_wqe_info[pi].num_wqebbs = 1;
552 mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
557 mlx5e_disable_rq(rq);
559 mlx5e_destroy_rq(rq);
564 static void mlx5e_close_rq(struct mlx5e_rq *rq)
569 clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
570 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
572 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
573 while (!mlx5_wq_ll_is_empty(&rq->wq) && !err &&
574 tout++ < MLX5_EN_QP_FLUSH_MAX_ITER)
575 msleep(MLX5_EN_QP_FLUSH_MSLEEP_QUANT);
577 if (err || tout == MLX5_EN_QP_FLUSH_MAX_ITER)
578 set_bit(MLX5E_RQ_STATE_FLUSH_TIMEOUT, &rq->state);
580 /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
581 napi_synchronize(&rq->channel->napi);
583 cancel_work_sync(&rq->am.work);
585 mlx5e_disable_rq(rq);
586 mlx5e_free_rx_descs(rq);
587 mlx5e_destroy_rq(rq);
590 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
597 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
599 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
600 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
602 sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
603 sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
605 sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
608 if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
609 mlx5e_free_sq_db(sq);
613 sq->dma_fifo_mask = df_sz - 1;
618 static int mlx5e_create_sq(struct mlx5e_channel *c,
620 struct mlx5e_sq_param *param,
623 struct mlx5e_priv *priv = c->priv;
624 struct mlx5_core_dev *mdev = priv->mdev;
626 void *sqc = param->sqc;
627 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
630 err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
634 param->wq.db_numa_node = cpu_to_node(c->cpu);
636 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq,
639 goto err_unmap_free_uar;
641 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
642 if (sq->uar.bf_map) {
643 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
644 sq->uar_map = sq->uar.bf_map;
646 sq->uar_map = sq->uar.map;
648 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
649 sq->max_inline = param->max_inline;
650 sq->min_inline_mode =
651 MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5E_INLINE_MODE_VPORT_CONTEXT ?
652 param->min_inline_mode : 0;
654 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
656 goto err_sq_wq_destroy;
659 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
661 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
664 cpu_to_node(c->cpu));
665 if (!sq->ico_wqe_info) {
672 txq_ix = c->ix + tc * priv->params.num_channels;
673 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
674 priv->txq_to_sq_map[txq_ix] = sq;
678 sq->tstamp = &priv->tstamp;
679 sq->mkey_be = c->mkey_be;
682 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
683 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
688 mlx5e_free_sq_db(sq);
691 mlx5_wq_destroy(&sq->wq_ctrl);
694 mlx5_unmap_free_uar(mdev, &sq->uar);
699 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
701 struct mlx5e_channel *c = sq->channel;
702 struct mlx5e_priv *priv = c->priv;
704 kfree(sq->ico_wqe_info);
705 mlx5e_free_sq_db(sq);
706 mlx5_wq_destroy(&sq->wq_ctrl);
707 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
710 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
712 struct mlx5e_channel *c = sq->channel;
713 struct mlx5e_priv *priv = c->priv;
714 struct mlx5_core_dev *mdev = priv->mdev;
722 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
723 sizeof(u64) * sq->wq_ctrl.buf.npages;
724 in = mlx5_vzalloc(inlen);
728 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
729 wq = MLX5_ADDR_OF(sqc, sqc, wq);
731 memcpy(sqc, param->sqc, sizeof(param->sqc));
733 MLX5_SET(sqc, sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
734 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
735 MLX5_SET(sqc, sqc, min_wqe_inline_mode, sq->min_inline_mode);
736 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
737 MLX5_SET(sqc, sqc, tis_lst_sz, param->icosq ? 0 : 1);
738 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
740 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
741 MLX5_SET(wq, wq, uar_page, sq->uar.index);
742 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
743 MLX5_ADAPTER_PAGE_SHIFT);
744 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
746 mlx5_fill_page_array(&sq->wq_ctrl.buf,
747 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
749 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
756 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
757 int next_state, bool update_rl, int rl_index)
759 struct mlx5e_channel *c = sq->channel;
760 struct mlx5e_priv *priv = c->priv;
761 struct mlx5_core_dev *mdev = priv->mdev;
768 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
769 in = mlx5_vzalloc(inlen);
773 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
775 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
776 MLX5_SET(sqc, sqc, state, next_state);
777 if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
778 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
779 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
782 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
789 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
791 struct mlx5e_channel *c = sq->channel;
792 struct mlx5e_priv *priv = c->priv;
793 struct mlx5_core_dev *mdev = priv->mdev;
795 mlx5_core_destroy_sq(mdev, sq->sqn);
797 mlx5_rl_remove_rate(mdev, sq->rate_limit);
800 static int mlx5e_open_sq(struct mlx5e_channel *c,
802 struct mlx5e_sq_param *param,
807 err = mlx5e_create_sq(c, tc, param, sq);
811 err = mlx5e_enable_sq(sq, param);
815 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
821 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
822 netdev_tx_reset_queue(sq->txq);
823 netif_tx_start_queue(sq->txq);
829 mlx5e_disable_sq(sq);
831 mlx5e_destroy_sq(sq);
836 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
838 __netif_tx_lock_bh(txq);
839 netif_tx_stop_queue(txq);
840 __netif_tx_unlock_bh(txq);
843 static void mlx5e_close_sq(struct mlx5e_sq *sq)
849 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
850 /* prevent netif_tx_wake_queue */
851 napi_synchronize(&sq->channel->napi);
852 netif_tx_disable_queue(sq->txq);
854 /* ensure hw is notified of all pending wqes */
855 if (mlx5e_sq_has_room_for(sq, 1))
856 mlx5e_send_nop(sq, true);
858 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
859 MLX5_SQC_STATE_ERR, false, 0);
861 set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
864 /* wait till sq is empty, unless a TX timeout occurred on this SQ */
865 while (sq->cc != sq->pc &&
866 !test_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state)) {
867 msleep(MLX5_EN_QP_FLUSH_MSLEEP_QUANT);
868 if (tout++ > MLX5_EN_QP_FLUSH_MAX_ITER)
869 set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
872 /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
873 napi_synchronize(&sq->channel->napi);
875 mlx5e_free_tx_descs(sq);
876 mlx5e_disable_sq(sq);
877 mlx5e_destroy_sq(sq);
880 static int mlx5e_create_cq(struct mlx5e_channel *c,
881 struct mlx5e_cq_param *param,
884 struct mlx5e_priv *priv = c->priv;
885 struct mlx5_core_dev *mdev = priv->mdev;
886 struct mlx5_core_cq *mcq = &cq->mcq;
892 param->wq.buf_numa_node = cpu_to_node(c->cpu);
893 param->wq.db_numa_node = cpu_to_node(c->cpu);
894 param->eq_ix = c->ix;
896 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
901 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
906 mcq->set_ci_db = cq->wq_ctrl.db.db;
907 mcq->arm_db = cq->wq_ctrl.db.db + 1;
910 mcq->vector = param->eq_ix;
911 mcq->comp = mlx5e_completion_event;
912 mcq->event = mlx5e_cq_error_event;
914 mcq->uar = &mdev->mlx5e_res.cq_uar;
916 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
917 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
928 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
930 mlx5_wq_destroy(&cq->wq_ctrl);
933 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
935 struct mlx5e_priv *priv = cq->priv;
936 struct mlx5_core_dev *mdev = priv->mdev;
937 struct mlx5_core_cq *mcq = &cq->mcq;
942 unsigned int irqn_not_used;
946 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
947 sizeof(u64) * cq->wq_ctrl.buf.npages;
948 in = mlx5_vzalloc(inlen);
952 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
954 memcpy(cqc, param->cqc, sizeof(param->cqc));
956 mlx5_fill_page_array(&cq->wq_ctrl.buf,
957 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
959 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
961 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
962 MLX5_SET(cqc, cqc, c_eqn, eqn);
963 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
964 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
965 MLX5_ADAPTER_PAGE_SHIFT);
966 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
968 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
980 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
982 struct mlx5e_priv *priv = cq->priv;
983 struct mlx5_core_dev *mdev = priv->mdev;
985 mlx5_core_destroy_cq(mdev, &cq->mcq);
988 static int mlx5e_open_cq(struct mlx5e_channel *c,
989 struct mlx5e_cq_param *param,
991 struct mlx5e_cq_moder moderation)
994 struct mlx5e_priv *priv = c->priv;
995 struct mlx5_core_dev *mdev = priv->mdev;
997 err = mlx5e_create_cq(c, param, cq);
1001 err = mlx5e_enable_cq(cq, param);
1003 goto err_destroy_cq;
1005 if (MLX5_CAP_GEN(mdev, cq_moderation))
1006 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
1012 mlx5e_destroy_cq(cq);
1017 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1019 mlx5e_disable_cq(cq);
1020 mlx5e_destroy_cq(cq);
1023 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1025 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1028 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1029 struct mlx5e_channel_param *cparam)
1031 struct mlx5e_priv *priv = c->priv;
1035 for (tc = 0; tc < c->num_tc; tc++) {
1036 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
1037 priv->params.tx_cq_moderation);
1039 goto err_close_tx_cqs;
1045 for (tc--; tc >= 0; tc--)
1046 mlx5e_close_cq(&c->sq[tc].cq);
1051 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1055 for (tc = 0; tc < c->num_tc; tc++)
1056 mlx5e_close_cq(&c->sq[tc].cq);
1059 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1060 struct mlx5e_channel_param *cparam)
1065 for (tc = 0; tc < c->num_tc; tc++) {
1066 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1074 for (tc--; tc >= 0; tc--)
1075 mlx5e_close_sq(&c->sq[tc]);
1080 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1084 for (tc = 0; tc < c->num_tc; tc++)
1085 mlx5e_close_sq(&c->sq[tc]);
1088 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1092 for (i = 0; i < priv->profile->max_tc; i++)
1093 priv->channeltc_to_txq_map[ix][i] =
1094 ix + i * priv->params.num_channels;
1097 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1098 struct mlx5e_sq *sq, u32 rate)
1100 struct mlx5e_priv *priv = netdev_priv(dev);
1101 struct mlx5_core_dev *mdev = priv->mdev;
1105 if (rate == sq->rate_limit)
1110 /* remove current rl index to free space to next ones */
1111 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1116 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1118 netdev_err(dev, "Failed configuring rate %u: %d\n",
1124 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1125 MLX5_SQC_STATE_RDY, true, rl_index);
1127 netdev_err(dev, "Failed configuring rate %u: %d\n",
1129 /* remove the rate from the table */
1131 mlx5_rl_remove_rate(mdev, rate);
1135 sq->rate_limit = rate;
1139 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1141 struct mlx5e_priv *priv = netdev_priv(dev);
1142 struct mlx5_core_dev *mdev = priv->mdev;
1143 struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1146 if (!mlx5_rl_is_supported(mdev)) {
1147 netdev_err(dev, "Rate limiting is not supported on this device\n");
1151 /* rate is given in Mb/sec, HW config is in Kb/sec */
1154 /* Check whether rate in valid range, 0 is always valid */
1155 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1156 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1160 mutex_lock(&priv->state_lock);
1161 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1162 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1164 priv->tx_rates[index] = rate;
1165 mutex_unlock(&priv->state_lock);
1170 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1171 struct mlx5e_channel_param *cparam,
1172 struct mlx5e_channel **cp)
1174 struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
1175 struct net_device *netdev = priv->netdev;
1176 struct mlx5e_cq_moder rx_cq_profile;
1177 int cpu = mlx5e_get_cpu(priv, ix);
1178 struct mlx5e_channel *c;
1179 struct mlx5e_sq *sq;
1183 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1190 c->pdev = &priv->mdev->pdev->dev;
1191 c->netdev = priv->netdev;
1192 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1193 c->num_tc = priv->params.num_tc;
1195 if (priv->params.rx_am_enabled)
1196 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1198 rx_cq_profile = priv->params.rx_cq_moderation;
1200 mlx5e_build_channeltc_to_txq_map(priv, ix);
1202 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1204 err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
1208 err = mlx5e_open_tx_cqs(c, cparam);
1210 goto err_close_icosq_cq;
1212 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1215 goto err_close_tx_cqs;
1217 napi_enable(&c->napi);
1219 err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1221 goto err_disable_napi;
1223 err = mlx5e_open_sqs(c, cparam);
1225 goto err_close_icosq;
1227 for (i = 0; i < priv->params.num_tc; i++) {
1228 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1230 if (priv->tx_rates[txq_ix]) {
1231 sq = priv->txq_to_sq_map[txq_ix];
1232 mlx5e_set_sq_maxrate(priv->netdev, sq,
1233 priv->tx_rates[txq_ix]);
1237 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1241 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1250 mlx5e_close_sq(&c->icosq);
1253 napi_disable(&c->napi);
1254 mlx5e_close_cq(&c->rq.cq);
1257 mlx5e_close_tx_cqs(c);
1260 mlx5e_close_cq(&c->icosq.cq);
1263 netif_napi_del(&c->napi);
1264 napi_hash_del(&c->napi);
1270 static void mlx5e_close_channel(struct mlx5e_channel *c)
1272 mlx5e_close_rq(&c->rq);
1274 mlx5e_close_sq(&c->icosq);
1275 napi_disable(&c->napi);
1276 mlx5e_close_cq(&c->rq.cq);
1277 mlx5e_close_tx_cqs(c);
1278 mlx5e_close_cq(&c->icosq.cq);
1279 netif_napi_del(&c->napi);
1281 napi_hash_del(&c->napi);
1287 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1288 struct mlx5e_rq_param *param)
1290 void *rqc = param->rqc;
1291 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1293 switch (priv->params.rq_wq_type) {
1294 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1295 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1296 priv->params.mpwqe_log_num_strides - 9);
1297 MLX5_SET(wq, wq, log_wqe_stride_size,
1298 priv->params.mpwqe_log_stride_sz - 6);
1299 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1301 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1302 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1305 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1306 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1307 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1308 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
1309 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1311 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1312 param->wq.linear = 1;
1314 param->am_enabled = priv->params.rx_am_enabled;
1317 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1319 void *rqc = param->rqc;
1320 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1322 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1323 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1326 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1327 struct mlx5e_sq_param *param)
1329 void *sqc = param->sqc;
1330 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1332 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1333 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
1335 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1338 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1339 struct mlx5e_sq_param *param)
1341 void *sqc = param->sqc;
1342 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1344 mlx5e_build_sq_param_common(priv, param);
1345 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1347 param->max_inline = priv->params.tx_max_inline;
1348 param->min_inline_mode = priv->params.tx_min_inline_mode;
1351 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1352 struct mlx5e_cq_param *param)
1354 void *cqc = param->cqc;
1356 MLX5_SET(cqc, cqc, uar_page, priv->mdev->mlx5e_res.cq_uar.index);
1359 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1360 struct mlx5e_cq_param *param)
1362 void *cqc = param->cqc;
1365 switch (priv->params.rq_wq_type) {
1366 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1367 log_cq_size = priv->params.log_rq_size +
1368 priv->params.mpwqe_log_num_strides;
1370 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1371 log_cq_size = priv->params.log_rq_size;
1374 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1375 if (priv->params.rx_cqe_compress) {
1376 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1377 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1380 mlx5e_build_common_cq_param(priv, param);
1382 param->cq_period_mode = priv->params.rx_cq_period_mode;
1385 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1386 struct mlx5e_cq_param *param)
1388 void *cqc = param->cqc;
1390 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1392 mlx5e_build_common_cq_param(priv, param);
1394 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1397 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1398 struct mlx5e_cq_param *param,
1401 void *cqc = param->cqc;
1403 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1405 mlx5e_build_common_cq_param(priv, param);
1407 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1410 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1411 struct mlx5e_sq_param *param,
1414 void *sqc = param->sqc;
1415 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1417 mlx5e_build_sq_param_common(priv, param);
1419 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1420 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1422 param->icosq = true;
1425 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1427 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1429 mlx5e_build_rq_param(priv, &cparam->rq);
1430 mlx5e_build_sq_param(priv, &cparam->sq);
1431 mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1432 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1433 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1434 mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1437 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1439 struct mlx5e_channel_param *cparam;
1440 int nch = priv->params.num_channels;
1445 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1448 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1449 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1451 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1453 if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1454 goto err_free_txq_to_sq_map;
1456 mlx5e_build_channel_param(priv, cparam);
1458 for (i = 0; i < nch; i++) {
1459 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1461 goto err_close_channels;
1464 for (j = 0; j < nch; j++) {
1465 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1467 goto err_close_channels;
1470 /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1471 * polling for inactive tx queues.
1473 netif_tx_start_all_queues(priv->netdev);
1479 for (i--; i >= 0; i--)
1480 mlx5e_close_channel(priv->channel[i]);
1482 err_free_txq_to_sq_map:
1483 kfree(priv->txq_to_sq_map);
1484 kfree(priv->channel);
1490 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1494 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1495 * polling for inactive tx queues.
1497 netif_tx_stop_all_queues(priv->netdev);
1498 netif_tx_disable(priv->netdev);
1500 for (i = 0; i < priv->params.num_channels; i++)
1501 mlx5e_close_channel(priv->channel[i]);
1503 kfree(priv->txq_to_sq_map);
1504 kfree(priv->channel);
1507 static int mlx5e_rx_hash_fn(int hfunc)
1509 return (hfunc == ETH_RSS_HASH_TOP) ?
1510 MLX5_RX_HASH_FN_TOEPLITZ :
1511 MLX5_RX_HASH_FN_INVERTED_XOR8;
1514 static int mlx5e_bits_invert(unsigned long a, int size)
1519 for (i = 0; i < size; i++)
1520 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1525 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1529 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1533 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1534 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1536 ix = priv->params.indirection_rqt[ix];
1537 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1538 priv->channel[ix]->rq.rqn :
1540 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1544 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1547 u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1548 priv->channel[ix]->rq.rqn :
1551 MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1554 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1555 int ix, struct mlx5e_rqt *rqt)
1557 struct mlx5_core_dev *mdev = priv->mdev;
1563 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1564 in = mlx5_vzalloc(inlen);
1568 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1570 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1571 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1573 if (sz > 1) /* RSS */
1574 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1576 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1578 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1580 rqt->enabled = true;
1586 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1588 rqt->enabled = false;
1589 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1592 static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1594 struct mlx5e_rqt *rqt = &priv->indir_rqt;
1596 return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1599 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1601 struct mlx5e_rqt *rqt;
1605 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1606 rqt = &priv->direct_tir[ix].rqt;
1607 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1609 goto err_destroy_rqts;
1615 for (ix--; ix >= 0; ix--)
1616 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1621 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
1623 struct mlx5_core_dev *mdev = priv->mdev;
1629 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1630 in = mlx5_vzalloc(inlen);
1634 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1636 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1637 if (sz > 1) /* RSS */
1638 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1640 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1642 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1644 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
1651 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1656 if (priv->indir_rqt.enabled) {
1657 rqtn = priv->indir_rqt.rqtn;
1658 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1661 for (ix = 0; ix < priv->params.num_channels; ix++) {
1662 if (!priv->direct_tir[ix].rqt.enabled)
1664 rqtn = priv->direct_tir[ix].rqt.rqtn;
1665 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1669 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1671 if (!priv->params.lro_en)
1674 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1676 MLX5_SET(tirc, tirc, lro_enable_mask,
1677 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1678 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1679 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1680 (priv->params.lro_wqe_sz -
1681 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1682 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1683 MLX5_CAP_ETH(priv->mdev,
1684 lro_timer_supported_periods[2]));
1687 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1689 MLX5_SET(tirc, tirc, rx_hash_fn,
1690 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1691 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1692 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1693 rx_hash_toeplitz_key);
1694 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1695 rx_hash_toeplitz_key);
1697 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1698 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1702 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1704 struct mlx5_core_dev *mdev = priv->mdev;
1713 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1714 in = mlx5_vzalloc(inlen);
1718 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1719 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1721 mlx5e_build_tir_ctx_lro(tirc, priv);
1723 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1724 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1730 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1731 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
1743 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
1745 struct mlx5_core_dev *mdev = priv->mdev;
1746 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
1749 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
1753 /* Update vport context MTU */
1754 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
1758 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
1760 struct mlx5_core_dev *mdev = priv->mdev;
1764 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
1765 if (err || !hw_mtu) /* fallback to port oper mtu */
1766 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1768 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
1771 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1773 struct mlx5e_priv *priv = netdev_priv(netdev);
1777 err = mlx5e_set_mtu(priv, netdev->mtu);
1781 mlx5e_query_mtu(priv, &mtu);
1782 if (mtu != netdev->mtu)
1783 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
1784 __func__, mtu, netdev->mtu);
1790 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1792 struct mlx5e_priv *priv = netdev_priv(netdev);
1793 int nch = priv->params.num_channels;
1794 int ntc = priv->params.num_tc;
1797 netdev_reset_tc(netdev);
1802 netdev_set_num_tc(netdev, ntc);
1804 /* Map netdev TCs to offset 0
1805 * We have our own UP to TXQ mapping for QoS
1807 for (tc = 0; tc < ntc; tc++)
1808 netdev_set_tc_queue(netdev, tc, nch, 0);
1811 int mlx5e_open_locked(struct net_device *netdev)
1813 struct mlx5e_priv *priv = netdev_priv(netdev);
1814 struct mlx5_core_dev *mdev = priv->mdev;
1818 set_bit(MLX5E_STATE_OPENED, &priv->state);
1820 mlx5e_netdev_set_tcs(netdev);
1822 num_txqs = priv->params.num_channels * priv->params.num_tc;
1823 netif_set_real_num_tx_queues(netdev, num_txqs);
1824 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1826 err = mlx5e_set_dev_port_mtu(netdev);
1828 goto err_clear_state_opened_flag;
1830 err = mlx5e_open_channels(priv);
1832 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1834 goto err_clear_state_opened_flag;
1837 err = mlx5e_refresh_tirs_self_loopback_enable(priv->mdev);
1839 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1841 goto err_close_channels;
1844 mlx5e_redirect_rqts(priv);
1845 mlx5e_update_carrier(priv);
1846 mlx5e_timestamp_init(priv);
1847 #ifdef CONFIG_RFS_ACCEL
1848 priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
1850 if (priv->profile->update_stats)
1851 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
1853 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
1854 err = mlx5e_add_sqs_fwd_rules(priv);
1856 goto err_close_channels;
1861 mlx5e_close_channels(priv);
1862 err_clear_state_opened_flag:
1863 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1867 int mlx5e_open(struct net_device *netdev)
1869 struct mlx5e_priv *priv = netdev_priv(netdev);
1872 mutex_lock(&priv->state_lock);
1873 err = mlx5e_open_locked(netdev);
1874 mutex_unlock(&priv->state_lock);
1879 int mlx5e_close_locked(struct net_device *netdev)
1881 struct mlx5e_priv *priv = netdev_priv(netdev);
1882 struct mlx5_core_dev *mdev = priv->mdev;
1884 /* May already be CLOSED in case a previous configuration operation
1885 * (e.g RX/TX queue size change) that involves close&open failed.
1887 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1890 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1892 if (MLX5_CAP_GEN(mdev, vport_group_manager))
1893 mlx5e_remove_sqs_fwd_rules(priv);
1895 mlx5e_timestamp_cleanup(priv);
1896 netif_carrier_off(priv->netdev);
1897 mlx5e_redirect_rqts(priv);
1898 mlx5e_close_channels(priv);
1903 int mlx5e_close(struct net_device *netdev)
1905 struct mlx5e_priv *priv = netdev_priv(netdev);
1908 mutex_lock(&priv->state_lock);
1909 err = mlx5e_close_locked(netdev);
1910 mutex_unlock(&priv->state_lock);
1915 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1916 struct mlx5e_rq *rq,
1917 struct mlx5e_rq_param *param)
1919 struct mlx5_core_dev *mdev = priv->mdev;
1920 void *rqc = param->rqc;
1921 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1924 param->wq.db_numa_node = param->wq.buf_numa_node;
1926 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
1936 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1937 struct mlx5e_cq *cq,
1938 struct mlx5e_cq_param *param)
1940 struct mlx5_core_dev *mdev = priv->mdev;
1941 struct mlx5_core_cq *mcq = &cq->mcq;
1946 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1951 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1954 mcq->set_ci_db = cq->wq_ctrl.db.db;
1955 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1956 *mcq->set_ci_db = 0;
1958 mcq->vector = param->eq_ix;
1959 mcq->comp = mlx5e_completion_event;
1960 mcq->event = mlx5e_cq_error_event;
1962 mcq->uar = &mdev->mlx5e_res.cq_uar;
1969 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1971 struct mlx5e_cq_param cq_param;
1972 struct mlx5e_rq_param rq_param;
1973 struct mlx5e_rq *rq = &priv->drop_rq;
1974 struct mlx5e_cq *cq = &priv->drop_rq.cq;
1977 memset(&cq_param, 0, sizeof(cq_param));
1978 memset(&rq_param, 0, sizeof(rq_param));
1979 mlx5e_build_drop_rq_param(&rq_param);
1981 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1985 err = mlx5e_enable_cq(cq, &cq_param);
1987 goto err_destroy_cq;
1989 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1991 goto err_disable_cq;
1993 err = mlx5e_enable_rq(rq, &rq_param);
1995 goto err_destroy_rq;
2000 mlx5e_destroy_rq(&priv->drop_rq);
2003 mlx5e_disable_cq(&priv->drop_rq.cq);
2006 mlx5e_destroy_cq(&priv->drop_rq.cq);
2011 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
2013 mlx5e_disable_rq(&priv->drop_rq);
2014 mlx5e_destroy_rq(&priv->drop_rq);
2015 mlx5e_disable_cq(&priv->drop_rq.cq);
2016 mlx5e_destroy_cq(&priv->drop_rq.cq);
2019 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2021 struct mlx5_core_dev *mdev = priv->mdev;
2022 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2023 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2025 MLX5_SET(tisc, tisc, prio, tc << 1);
2026 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2027 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2030 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2032 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2035 int mlx5e_create_tises(struct mlx5e_priv *priv)
2040 for (tc = 0; tc < priv->profile->max_tc; tc++) {
2041 err = mlx5e_create_tis(priv, tc);
2043 goto err_close_tises;
2049 for (tc--; tc >= 0; tc--)
2050 mlx5e_destroy_tis(priv, tc);
2055 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2059 for (tc = 0; tc < priv->profile->max_tc; tc++)
2060 mlx5e_destroy_tis(priv, tc);
2063 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2064 enum mlx5e_traffic_types tt)
2066 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2068 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2070 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2071 MLX5_HASH_FIELD_SEL_DST_IP)
2073 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2074 MLX5_HASH_FIELD_SEL_DST_IP |\
2075 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2076 MLX5_HASH_FIELD_SEL_L4_DPORT)
2078 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2079 MLX5_HASH_FIELD_SEL_DST_IP |\
2080 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2082 mlx5e_build_tir_ctx_lro(tirc, priv);
2084 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2085 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2086 mlx5e_build_tir_ctx_hash(tirc, priv);
2089 case MLX5E_TT_IPV4_TCP:
2090 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2091 MLX5_L3_PROT_TYPE_IPV4);
2092 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2093 MLX5_L4_PROT_TYPE_TCP);
2094 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2095 MLX5_HASH_IP_L4PORTS);
2098 case MLX5E_TT_IPV6_TCP:
2099 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2100 MLX5_L3_PROT_TYPE_IPV6);
2101 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2102 MLX5_L4_PROT_TYPE_TCP);
2103 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2104 MLX5_HASH_IP_L4PORTS);
2107 case MLX5E_TT_IPV4_UDP:
2108 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2109 MLX5_L3_PROT_TYPE_IPV4);
2110 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2111 MLX5_L4_PROT_TYPE_UDP);
2112 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2113 MLX5_HASH_IP_L4PORTS);
2116 case MLX5E_TT_IPV6_UDP:
2117 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2118 MLX5_L3_PROT_TYPE_IPV6);
2119 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2120 MLX5_L4_PROT_TYPE_UDP);
2121 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2122 MLX5_HASH_IP_L4PORTS);
2125 case MLX5E_TT_IPV4_IPSEC_AH:
2126 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2127 MLX5_L3_PROT_TYPE_IPV4);
2128 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2129 MLX5_HASH_IP_IPSEC_SPI);
2132 case MLX5E_TT_IPV6_IPSEC_AH:
2133 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2134 MLX5_L3_PROT_TYPE_IPV6);
2135 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2136 MLX5_HASH_IP_IPSEC_SPI);
2139 case MLX5E_TT_IPV4_IPSEC_ESP:
2140 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2141 MLX5_L3_PROT_TYPE_IPV4);
2142 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2143 MLX5_HASH_IP_IPSEC_SPI);
2146 case MLX5E_TT_IPV6_IPSEC_ESP:
2147 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2148 MLX5_L3_PROT_TYPE_IPV6);
2149 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2150 MLX5_HASH_IP_IPSEC_SPI);
2154 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2155 MLX5_L3_PROT_TYPE_IPV4);
2156 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2161 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2162 MLX5_L3_PROT_TYPE_IPV6);
2163 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2168 "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2172 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2175 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2177 mlx5e_build_tir_ctx_lro(tirc, priv);
2179 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2180 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2181 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2184 static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2186 struct mlx5e_tir *tir;
2193 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2194 in = mlx5_vzalloc(inlen);
2198 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2199 memset(in, 0, inlen);
2200 tir = &priv->indir_tir[tt];
2201 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2202 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2203 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2205 goto err_destroy_tirs;
2213 for (tt--; tt >= 0; tt--)
2214 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2221 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2223 int nch = priv->profile->max_nch(priv->mdev);
2224 struct mlx5e_tir *tir;
2231 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2232 in = mlx5_vzalloc(inlen);
2236 for (ix = 0; ix < nch; ix++) {
2237 memset(in, 0, inlen);
2238 tir = &priv->direct_tir[ix];
2239 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2240 mlx5e_build_direct_tir_ctx(priv, tirc,
2241 priv->direct_tir[ix].rqt.rqtn);
2242 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2244 goto err_destroy_ch_tirs;
2251 err_destroy_ch_tirs:
2252 for (ix--; ix >= 0; ix--)
2253 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2260 static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
2264 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2265 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
2268 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
2270 int nch = priv->profile->max_nch(priv->mdev);
2273 for (i = 0; i < nch; i++)
2274 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2277 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2282 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2285 for (i = 0; i < priv->params.num_channels; i++) {
2286 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2294 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2296 struct mlx5e_priv *priv = netdev_priv(netdev);
2300 if (tc && tc != MLX5E_MAX_NUM_TC)
2303 mutex_lock(&priv->state_lock);
2305 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2307 mlx5e_close_locked(priv->netdev);
2309 priv->params.num_tc = tc ? tc : 1;
2312 err = mlx5e_open_locked(priv->netdev);
2314 mutex_unlock(&priv->state_lock);
2319 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2320 __be16 proto, struct tc_to_netdev *tc)
2322 struct mlx5e_priv *priv = netdev_priv(dev);
2324 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2328 case TC_SETUP_CLSFLOWER:
2329 switch (tc->cls_flower->command) {
2330 case TC_CLSFLOWER_REPLACE:
2331 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2332 case TC_CLSFLOWER_DESTROY:
2333 return mlx5e_delete_flower(priv, tc->cls_flower);
2334 case TC_CLSFLOWER_STATS:
2335 return mlx5e_stats_flower(priv, tc->cls_flower);
2342 if (tc->type != TC_SETUP_MQPRIO)
2345 return mlx5e_setup_tc(dev, tc->tc);
2348 struct rtnl_link_stats64 *
2349 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2351 struct mlx5e_priv *priv = netdev_priv(dev);
2352 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2353 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2354 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2356 stats->rx_packets = sstats->rx_packets;
2357 stats->rx_bytes = sstats->rx_bytes;
2358 stats->tx_packets = sstats->tx_packets;
2359 stats->tx_bytes = sstats->tx_bytes;
2361 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2362 stats->tx_dropped = sstats->tx_queue_dropped;
2364 stats->rx_length_errors =
2365 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2366 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2367 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2368 stats->rx_crc_errors =
2369 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2370 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2371 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2372 stats->tx_carrier_errors =
2373 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2374 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2375 stats->rx_frame_errors;
2376 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2378 /* vport multicast also counts packets that are dropped due to steering
2379 * or rx out of buffer
2382 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2387 static void mlx5e_set_rx_mode(struct net_device *dev)
2389 struct mlx5e_priv *priv = netdev_priv(dev);
2391 queue_work(priv->wq, &priv->set_rx_mode_work);
2394 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2396 struct mlx5e_priv *priv = netdev_priv(netdev);
2397 struct sockaddr *saddr = addr;
2399 if (!is_valid_ether_addr(saddr->sa_data))
2400 return -EADDRNOTAVAIL;
2402 netif_addr_lock_bh(netdev);
2403 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2404 netif_addr_unlock_bh(netdev);
2406 queue_work(priv->wq, &priv->set_rx_mode_work);
2411 #define MLX5E_SET_FEATURE(netdev, feature, enable) \
2414 netdev->features |= feature; \
2416 netdev->features &= ~feature; \
2419 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2421 static int set_feature_lro(struct net_device *netdev, bool enable)
2423 struct mlx5e_priv *priv = netdev_priv(netdev);
2424 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2427 mutex_lock(&priv->state_lock);
2429 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2430 mlx5e_close_locked(priv->netdev);
2432 priv->params.lro_en = enable;
2433 err = mlx5e_modify_tirs_lro(priv);
2435 netdev_err(netdev, "lro modify failed, %d\n", err);
2436 priv->params.lro_en = !enable;
2439 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2440 mlx5e_open_locked(priv->netdev);
2442 mutex_unlock(&priv->state_lock);
2447 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2449 struct mlx5e_priv *priv = netdev_priv(netdev);
2452 mlx5e_enable_vlan_filter(priv);
2454 mlx5e_disable_vlan_filter(priv);
2459 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2461 struct mlx5e_priv *priv = netdev_priv(netdev);
2463 if (!enable && mlx5e_tc_num_filters(priv)) {
2465 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2472 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2474 struct mlx5e_priv *priv = netdev_priv(netdev);
2475 struct mlx5_core_dev *mdev = priv->mdev;
2477 return mlx5_set_port_fcs(mdev, !enable);
2480 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2482 struct mlx5e_priv *priv = netdev_priv(netdev);
2485 mutex_lock(&priv->state_lock);
2487 priv->params.vlan_strip_disable = !enable;
2488 err = mlx5e_modify_rqs_vsd(priv, !enable);
2490 priv->params.vlan_strip_disable = enable;
2492 mutex_unlock(&priv->state_lock);
2497 #ifdef CONFIG_RFS_ACCEL
2498 static int set_feature_arfs(struct net_device *netdev, bool enable)
2500 struct mlx5e_priv *priv = netdev_priv(netdev);
2504 err = mlx5e_arfs_enable(priv);
2506 err = mlx5e_arfs_disable(priv);
2512 static int mlx5e_handle_feature(struct net_device *netdev,
2513 netdev_features_t wanted_features,
2514 netdev_features_t feature,
2515 mlx5e_feature_handler feature_handler)
2517 netdev_features_t changes = wanted_features ^ netdev->features;
2518 bool enable = !!(wanted_features & feature);
2521 if (!(changes & feature))
2524 err = feature_handler(netdev, enable);
2526 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2527 enable ? "Enable" : "Disable", feature, err);
2531 MLX5E_SET_FEATURE(netdev, feature, enable);
2535 static int mlx5e_set_features(struct net_device *netdev,
2536 netdev_features_t features)
2540 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2542 err |= mlx5e_handle_feature(netdev, features,
2543 NETIF_F_HW_VLAN_CTAG_FILTER,
2544 set_feature_vlan_filter);
2545 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2546 set_feature_tc_num_filters);
2547 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2548 set_feature_rx_all);
2549 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2550 set_feature_rx_vlan);
2551 #ifdef CONFIG_RFS_ACCEL
2552 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2556 return err ? -EINVAL : 0;
2559 #define MXL5_HW_MIN_MTU 64
2560 #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2562 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2564 struct mlx5e_priv *priv = netdev_priv(netdev);
2565 struct mlx5_core_dev *mdev = priv->mdev;
2571 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2573 max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2574 min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
2576 if (new_mtu > max_mtu || new_mtu < min_mtu) {
2578 "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2579 __func__, new_mtu, min_mtu, max_mtu);
2583 mutex_lock(&priv->state_lock);
2585 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2587 mlx5e_close_locked(netdev);
2589 netdev->mtu = new_mtu;
2592 err = mlx5e_open_locked(netdev);
2594 mutex_unlock(&priv->state_lock);
2599 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2603 return mlx5e_hwstamp_set(dev, ifr);
2605 return mlx5e_hwstamp_get(dev, ifr);
2611 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2613 struct mlx5e_priv *priv = netdev_priv(dev);
2614 struct mlx5_core_dev *mdev = priv->mdev;
2616 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2619 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2621 struct mlx5e_priv *priv = netdev_priv(dev);
2622 struct mlx5_core_dev *mdev = priv->mdev;
2624 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2628 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2630 struct mlx5e_priv *priv = netdev_priv(dev);
2631 struct mlx5_core_dev *mdev = priv->mdev;
2633 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2636 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2638 struct mlx5e_priv *priv = netdev_priv(dev);
2639 struct mlx5_core_dev *mdev = priv->mdev;
2641 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2643 static int mlx5_vport_link2ifla(u8 esw_link)
2646 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2647 return IFLA_VF_LINK_STATE_DISABLE;
2648 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2649 return IFLA_VF_LINK_STATE_ENABLE;
2651 return IFLA_VF_LINK_STATE_AUTO;
2654 static int mlx5_ifla_link2vport(u8 ifla_link)
2656 switch (ifla_link) {
2657 case IFLA_VF_LINK_STATE_DISABLE:
2658 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2659 case IFLA_VF_LINK_STATE_ENABLE:
2660 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2662 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2665 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2668 struct mlx5e_priv *priv = netdev_priv(dev);
2669 struct mlx5_core_dev *mdev = priv->mdev;
2671 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2672 mlx5_ifla_link2vport(link_state));
2675 static int mlx5e_get_vf_config(struct net_device *dev,
2676 int vf, struct ifla_vf_info *ivi)
2678 struct mlx5e_priv *priv = netdev_priv(dev);
2679 struct mlx5_core_dev *mdev = priv->mdev;
2682 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2685 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2689 static int mlx5e_get_vf_stats(struct net_device *dev,
2690 int vf, struct ifla_vf_stats *vf_stats)
2692 struct mlx5e_priv *priv = netdev_priv(dev);
2693 struct mlx5_core_dev *mdev = priv->mdev;
2695 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2699 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2700 struct udp_tunnel_info *ti)
2702 struct mlx5e_priv *priv = netdev_priv(netdev);
2704 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2707 if (!mlx5e_vxlan_allowed(priv->mdev))
2710 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
2713 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2714 struct udp_tunnel_info *ti)
2716 struct mlx5e_priv *priv = netdev_priv(netdev);
2718 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2721 if (!mlx5e_vxlan_allowed(priv->mdev))
2724 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
2727 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2728 struct sk_buff *skb,
2729 netdev_features_t features)
2731 struct udphdr *udph;
2735 switch (vlan_get_protocol(skb)) {
2736 case htons(ETH_P_IP):
2737 proto = ip_hdr(skb)->protocol;
2739 case htons(ETH_P_IPV6):
2740 proto = ipv6_hdr(skb)->nexthdr;
2746 if (proto == IPPROTO_UDP) {
2747 udph = udp_hdr(skb);
2748 port = be16_to_cpu(udph->dest);
2751 /* Verify if UDP port is being offloaded by HW */
2752 if (port && mlx5e_vxlan_lookup_port(priv, port))
2756 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2757 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2760 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2761 struct net_device *netdev,
2762 netdev_features_t features)
2764 struct mlx5e_priv *priv = netdev_priv(netdev);
2766 features = vlan_features_check(skb, features);
2767 features = vxlan_features_check(skb, features);
2769 /* Validate if the tunneled packet is being offloaded by HW */
2770 if (skb->encapsulation &&
2771 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2772 return mlx5e_vxlan_features_check(priv, skb, features);
2777 static void mlx5e_tx_timeout(struct net_device *dev)
2779 struct mlx5e_priv *priv = netdev_priv(dev);
2780 bool sched_work = false;
2783 netdev_err(dev, "TX timeout detected\n");
2785 for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
2786 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
2788 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
2791 set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
2792 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
2793 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
2796 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
2797 schedule_work(&priv->tx_timeout_work);
2800 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2801 .ndo_open = mlx5e_open,
2802 .ndo_stop = mlx5e_close,
2803 .ndo_start_xmit = mlx5e_xmit,
2804 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2805 .ndo_select_queue = mlx5e_select_queue,
2806 .ndo_get_stats64 = mlx5e_get_stats,
2807 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2808 .ndo_set_mac_address = mlx5e_set_mac,
2809 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2810 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2811 .ndo_set_features = mlx5e_set_features,
2812 .ndo_change_mtu = mlx5e_change_mtu,
2813 .ndo_do_ioctl = mlx5e_ioctl,
2814 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
2815 #ifdef CONFIG_RFS_ACCEL
2816 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
2818 .ndo_tx_timeout = mlx5e_tx_timeout,
2821 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2822 .ndo_open = mlx5e_open,
2823 .ndo_stop = mlx5e_close,
2824 .ndo_start_xmit = mlx5e_xmit,
2825 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2826 .ndo_select_queue = mlx5e_select_queue,
2827 .ndo_get_stats64 = mlx5e_get_stats,
2828 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2829 .ndo_set_mac_address = mlx5e_set_mac,
2830 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2831 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2832 .ndo_set_features = mlx5e_set_features,
2833 .ndo_change_mtu = mlx5e_change_mtu,
2834 .ndo_do_ioctl = mlx5e_ioctl,
2835 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
2836 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
2837 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
2838 .ndo_features_check = mlx5e_features_check,
2839 #ifdef CONFIG_RFS_ACCEL
2840 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
2842 .ndo_set_vf_mac = mlx5e_set_vf_mac,
2843 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
2844 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
2845 .ndo_set_vf_trust = mlx5e_set_vf_trust,
2846 .ndo_get_vf_config = mlx5e_get_vf_config,
2847 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
2848 .ndo_get_vf_stats = mlx5e_get_vf_stats,
2849 .ndo_tx_timeout = mlx5e_tx_timeout,
2852 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2854 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2856 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2857 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2858 !MLX5_CAP_ETH(mdev, csum_cap) ||
2859 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2860 !MLX5_CAP_ETH(mdev, vlan_cap) ||
2861 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2862 MLX5_CAP_FLOWTABLE(mdev,
2863 flow_table_properties_nic_receive.max_ft_level)
2865 mlx5_core_warn(mdev,
2866 "Not creating net device, some required device capabilities are missing\n");
2869 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2870 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2871 if (!MLX5_CAP_GEN(mdev, cq_moderation))
2872 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2877 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2879 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2881 return bf_buf_size -
2882 sizeof(struct mlx5e_tx_wqe) +
2883 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2886 #ifdef CONFIG_MLX5_CORE_EN_DCB
2887 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2891 priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2892 for (i = 0; i < priv->params.ets.ets_cap; i++) {
2893 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2894 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2895 priv->params.ets.prio_tc[i] = i;
2898 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2899 priv->params.ets.prio_tc[0] = 1;
2900 priv->params.ets.prio_tc[1] = 0;
2904 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2905 u32 *indirection_rqt, int len,
2908 int node = mdev->priv.numa_node;
2909 int node_num_of_cores;
2913 node = first_online_node;
2915 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2917 if (node_num_of_cores)
2918 num_channels = min_t(int, num_channels, node_num_of_cores);
2920 for (i = 0; i < len; i++)
2921 indirection_rqt[i] = i % num_channels;
2924 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2926 return MLX5_CAP_GEN(mdev, striding_rq) &&
2927 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2928 MLX5_CAP_ETH(mdev, reg_umr_sq);
2931 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
2933 enum pcie_link_width width;
2934 enum pci_bus_speed speed;
2937 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
2941 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
2945 case PCIE_SPEED_2_5GT:
2946 *pci_bw = 2500 * width;
2948 case PCIE_SPEED_5_0GT:
2949 *pci_bw = 5000 * width;
2951 case PCIE_SPEED_8_0GT:
2952 *pci_bw = 8000 * width;
2961 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
2963 return (link_speed && pci_bw &&
2964 (pci_bw < 40000) && (pci_bw < link_speed));
2967 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
2969 params->rx_cq_period_mode = cq_period_mode;
2971 params->rx_cq_moderation.pkts =
2972 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2973 params->rx_cq_moderation.usec =
2974 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2976 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
2977 params->rx_cq_moderation.usec =
2978 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
2981 static void mlx5e_query_min_inline(struct mlx5_core_dev *mdev,
2982 u8 *min_inline_mode)
2984 switch (MLX5_CAP_ETH(mdev, wqe_inline_mode)) {
2985 case MLX5E_INLINE_MODE_L2:
2986 *min_inline_mode = MLX5_INLINE_MODE_L2;
2988 case MLX5E_INLINE_MODE_VPORT_CONTEXT:
2989 mlx5_query_nic_vport_min_inline(mdev,
2992 case MLX5_INLINE_MODE_NOT_REQUIRED:
2993 *min_inline_mode = MLX5_INLINE_MODE_NONE;
2998 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
2999 struct net_device *netdev,
3000 const struct mlx5e_profile *profile,
3003 struct mlx5e_priv *priv = netdev_priv(netdev);
3006 u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3007 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3008 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3010 priv->params.log_sq_size =
3011 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3012 priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
3013 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
3014 MLX5_WQ_TYPE_LINKED_LIST;
3016 /* set CQE compression */
3017 priv->params.rx_cqe_compress_admin = false;
3018 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3019 MLX5_CAP_GEN(mdev, vport_group_manager)) {
3020 mlx5e_get_max_linkspeed(mdev, &link_speed);
3021 mlx5e_get_pci_bw(mdev, &pci_bw);
3022 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3023 link_speed, pci_bw);
3024 priv->params.rx_cqe_compress_admin =
3025 cqe_compress_heuristic(link_speed, pci_bw);
3028 priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
3030 switch (priv->params.rq_wq_type) {
3031 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
3032 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
3033 priv->params.mpwqe_log_stride_sz =
3034 priv->params.rx_cqe_compress ?
3035 MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
3036 MLX5_MPWRQ_LOG_STRIDE_SIZE;
3037 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
3038 priv->params.mpwqe_log_stride_sz;
3039 priv->params.lro_en = true;
3041 default: /* MLX5_WQ_TYPE_LINKED_LIST */
3042 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3045 mlx5_core_info(mdev,
3046 "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
3047 priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
3048 BIT(priv->params.log_rq_size),
3049 BIT(priv->params.mpwqe_log_stride_sz),
3050 priv->params.rx_cqe_compress_admin);
3052 priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
3053 BIT(priv->params.log_rq_size));
3055 priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3056 mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
3058 priv->params.tx_cq_moderation.usec =
3059 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3060 priv->params.tx_cq_moderation.pkts =
3061 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3062 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3063 mlx5e_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3064 priv->params.num_tc = 1;
3065 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
3067 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
3068 sizeof(priv->params.toeplitz_hash_key));
3070 mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
3071 MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
3073 priv->params.lro_wqe_sz =
3074 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3076 /* Initialize pflags */
3077 MLX5E_SET_PRIV_FLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3078 priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3081 priv->netdev = netdev;
3082 priv->params.num_channels = profile->max_nch(mdev);
3083 priv->profile = profile;
3084 priv->ppriv = ppriv;
3086 #ifdef CONFIG_MLX5_CORE_EN_DCB
3087 mlx5e_ets_init(priv);
3090 mutex_init(&priv->state_lock);
3092 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3093 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3094 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
3095 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3098 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3100 struct mlx5e_priv *priv = netdev_priv(netdev);
3102 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
3103 if (is_zero_ether_addr(netdev->dev_addr) &&
3104 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3105 eth_hw_addr_random(netdev);
3106 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3110 static const struct switchdev_ops mlx5e_switchdev_ops = {
3111 .switchdev_port_attr_get = mlx5e_attr_get,
3114 static void mlx5e_build_nic_netdev(struct net_device *netdev)
3116 struct mlx5e_priv *priv = netdev_priv(netdev);
3117 struct mlx5_core_dev *mdev = priv->mdev;
3121 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3123 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3124 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
3125 #ifdef CONFIG_MLX5_CORE_EN_DCB
3126 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
3129 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
3132 netdev->watchdog_timeo = 15 * HZ;
3134 netdev->ethtool_ops = &mlx5e_ethtool_ops;
3136 netdev->vlan_features |= NETIF_F_SG;
3137 netdev->vlan_features |= NETIF_F_IP_CSUM;
3138 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
3139 netdev->vlan_features |= NETIF_F_GRO;
3140 netdev->vlan_features |= NETIF_F_TSO;
3141 netdev->vlan_features |= NETIF_F_TSO6;
3142 netdev->vlan_features |= NETIF_F_RXCSUM;
3143 netdev->vlan_features |= NETIF_F_RXHASH;
3145 if (!!MLX5_CAP_ETH(mdev, lro_cap))
3146 netdev->vlan_features |= NETIF_F_LRO;
3148 netdev->hw_features = netdev->vlan_features;
3149 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
3150 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
3151 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3153 if (mlx5e_vxlan_allowed(mdev)) {
3154 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3155 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3156 NETIF_F_GSO_PARTIAL;
3157 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
3158 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
3159 netdev->hw_enc_features |= NETIF_F_TSO;
3160 netdev->hw_enc_features |= NETIF_F_TSO6;
3161 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
3162 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3163 NETIF_F_GSO_PARTIAL;
3164 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
3167 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3170 netdev->hw_features |= NETIF_F_RXALL;
3172 netdev->features = netdev->hw_features;
3173 if (!priv->params.lro_en)
3174 netdev->features &= ~NETIF_F_LRO;
3177 netdev->features &= ~NETIF_F_RXALL;
3179 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3180 if (FT_CAP(flow_modify_en) &&
3181 FT_CAP(modify_root) &&
3182 FT_CAP(identified_miss_table_mode) &&
3183 FT_CAP(flow_table_modify)) {
3184 netdev->hw_features |= NETIF_F_HW_TC;
3185 #ifdef CONFIG_RFS_ACCEL
3186 netdev->hw_features |= NETIF_F_NTUPLE;
3190 netdev->features |= NETIF_F_HIGHDMA;
3192 netdev->priv_flags |= IFF_UNICAST_FLT;
3194 mlx5e_set_netdev_dev_addr(netdev);
3196 #ifdef CONFIG_NET_SWITCHDEV
3197 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3198 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3202 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3204 struct mlx5_core_dev *mdev = priv->mdev;
3207 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3209 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3210 priv->q_counter = 0;
3214 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3216 if (!priv->q_counter)
3219 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3222 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
3224 struct mlx5_core_dev *mdev = priv->mdev;
3225 u64 npages = priv->profile->max_nch(mdev) * MLX5_CHANNEL_MAX_NUM_MTTS;
3226 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3231 in = mlx5_vzalloc(inlen);
3235 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3237 MLX5_SET(mkc, mkc, free, 1);
3238 MLX5_SET(mkc, mkc, umr_en, 1);
3239 MLX5_SET(mkc, mkc, lw, 1);
3240 MLX5_SET(mkc, mkc, lr, 1);
3241 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
3243 MLX5_SET(mkc, mkc, qpn, 0xffffff);
3244 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
3245 MLX5_SET64(mkc, mkc, len, npages << PAGE_SHIFT);
3246 MLX5_SET(mkc, mkc, translations_octword_size,
3247 mlx5e_get_mtt_octw(npages));
3248 MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT);
3250 err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen);
3256 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3257 struct net_device *netdev,
3258 const struct mlx5e_profile *profile,
3261 struct mlx5e_priv *priv = netdev_priv(netdev);
3263 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
3264 mlx5e_build_nic_netdev(netdev);
3265 mlx5e_vxlan_init(priv);
3268 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3270 struct mlx5_core_dev *mdev = priv->mdev;
3271 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3273 mlx5e_vxlan_cleanup(priv);
3275 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3276 mlx5_eswitch_unregister_vport_rep(esw, 0);
3279 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3281 struct mlx5_core_dev *mdev = priv->mdev;
3285 err = mlx5e_create_indirect_rqts(priv);
3287 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3291 err = mlx5e_create_direct_rqts(priv);
3293 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3294 goto err_destroy_indirect_rqts;
3297 err = mlx5e_create_indirect_tirs(priv);
3299 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3300 goto err_destroy_direct_rqts;
3303 err = mlx5e_create_direct_tirs(priv);
3305 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3306 goto err_destroy_indirect_tirs;
3309 err = mlx5e_create_flow_steering(priv);
3311 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3312 goto err_destroy_direct_tirs;
3315 err = mlx5e_tc_init(priv);
3317 goto err_destroy_flow_steering;
3321 err_destroy_flow_steering:
3322 mlx5e_destroy_flow_steering(priv);
3323 err_destroy_direct_tirs:
3324 mlx5e_destroy_direct_tirs(priv);
3325 err_destroy_indirect_tirs:
3326 mlx5e_destroy_indirect_tirs(priv);
3327 err_destroy_direct_rqts:
3328 for (i = 0; i < priv->profile->max_nch(mdev); i++)
3329 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3330 err_destroy_indirect_rqts:
3331 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3335 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
3339 mlx5e_tc_cleanup(priv);
3340 mlx5e_destroy_flow_steering(priv);
3341 mlx5e_destroy_direct_tirs(priv);
3342 mlx5e_destroy_indirect_tirs(priv);
3343 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
3344 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3345 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3348 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
3352 err = mlx5e_create_tises(priv);
3354 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
3358 #ifdef CONFIG_MLX5_CORE_EN_DCB
3359 mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3364 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
3366 struct net_device *netdev = priv->netdev;
3367 struct mlx5_core_dev *mdev = priv->mdev;
3368 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3369 struct mlx5_eswitch_rep rep;
3371 if (mlx5e_vxlan_allowed(mdev)) {
3373 udp_tunnel_get_rx_info(netdev);
3377 mlx5e_enable_async_events(priv);
3378 queue_work(priv->wq, &priv->set_rx_mode_work);
3380 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3381 rep.load = mlx5e_nic_rep_load;
3382 rep.unload = mlx5e_nic_rep_unload;
3384 rep.priv_data = priv;
3385 mlx5_eswitch_register_vport_rep(esw, &rep);
3389 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
3391 queue_work(priv->wq, &priv->set_rx_mode_work);
3392 mlx5e_disable_async_events(priv);
3395 static const struct mlx5e_profile mlx5e_nic_profile = {
3396 .init = mlx5e_nic_init,
3397 .cleanup = mlx5e_nic_cleanup,
3398 .init_rx = mlx5e_init_nic_rx,
3399 .cleanup_rx = mlx5e_cleanup_nic_rx,
3400 .init_tx = mlx5e_init_nic_tx,
3401 .cleanup_tx = mlx5e_cleanup_nic_tx,
3402 .enable = mlx5e_nic_enable,
3403 .disable = mlx5e_nic_disable,
3404 .update_stats = mlx5e_update_stats,
3405 .max_nch = mlx5e_get_max_num_channels,
3406 .max_tc = MLX5E_MAX_NUM_TC,
3409 void *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
3410 const struct mlx5e_profile *profile, void *ppriv)
3412 struct net_device *netdev;
3413 struct mlx5e_priv *priv;
3414 int nch = profile->max_nch(mdev);
3417 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
3418 nch * profile->max_tc,
3421 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3425 profile->init(mdev, netdev, profile, ppriv);
3427 netif_carrier_off(netdev);
3429 priv = netdev_priv(netdev);
3431 priv->wq = create_singlethread_workqueue("mlx5e");
3433 goto err_free_netdev;
3435 err = mlx5e_create_umr_mkey(priv);
3437 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
3438 goto err_destroy_wq;
3441 err = profile->init_tx(priv);
3443 goto err_destroy_umr_mkey;
3445 err = mlx5e_open_drop_rq(priv);
3447 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
3448 goto err_cleanup_tx;
3451 err = profile->init_rx(priv);
3453 goto err_close_drop_rq;
3455 mlx5e_create_q_counter(priv);
3457 mlx5e_init_l2_addr(priv);
3459 err = register_netdev(netdev);
3461 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
3462 goto err_dealloc_q_counters;
3465 if (profile->enable)
3466 profile->enable(priv);
3470 err_dealloc_q_counters:
3471 mlx5e_destroy_q_counter(priv);
3472 profile->cleanup_rx(priv);
3475 mlx5e_close_drop_rq(priv);
3478 profile->cleanup_tx(priv);
3480 err_destroy_umr_mkey:
3481 mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3484 destroy_workqueue(priv->wq);
3487 free_netdev(netdev);
3492 static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
3494 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3495 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3498 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3501 for (vport = 1; vport < total_vfs; vport++) {
3502 struct mlx5_eswitch_rep rep;
3504 rep.load = mlx5e_vport_rep_load;
3505 rep.unload = mlx5e_vport_rep_unload;
3507 mlx5_eswitch_register_vport_rep(esw, &rep);
3511 static void *mlx5e_add(struct mlx5_core_dev *mdev)
3513 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3517 if (mlx5e_check_required_hca_cap(mdev))
3520 if (mlx5e_create_mdev_resources(mdev))
3523 mlx5e_register_vport_rep(mdev);
3525 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3526 ppriv = &esw->offloads.vport_reps[0];
3528 ret = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
3530 mlx5e_destroy_mdev_resources(mdev);
3536 void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
3538 const struct mlx5e_profile *profile = priv->profile;
3539 struct net_device *netdev = priv->netdev;
3541 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3542 if (profile->disable)
3543 profile->disable(priv);
3545 flush_workqueue(priv->wq);
3546 if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) {
3547 netif_device_detach(netdev);
3548 mlx5e_close(netdev);
3550 unregister_netdev(netdev);
3553 mlx5e_destroy_q_counter(priv);
3554 profile->cleanup_rx(priv);
3555 mlx5e_close_drop_rq(priv);
3556 profile->cleanup_tx(priv);
3557 mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3558 cancel_delayed_work_sync(&priv->update_stats_work);
3559 destroy_workqueue(priv->wq);
3560 if (profile->cleanup)
3561 profile->cleanup(priv);
3563 if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state))
3564 free_netdev(netdev);
3567 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
3569 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3570 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3571 struct mlx5e_priv *priv = vpriv;
3574 mlx5e_destroy_netdev(mdev, priv);
3576 for (vport = 1; vport < total_vfs; vport++)
3577 mlx5_eswitch_unregister_vport_rep(esw, vport);
3579 mlx5e_destroy_mdev_resources(mdev);
3582 static void *mlx5e_get_netdev(void *vpriv)
3584 struct mlx5e_priv *priv = vpriv;
3586 return priv->netdev;
3589 static struct mlx5_interface mlx5e_interface = {
3591 .remove = mlx5e_remove,
3592 .event = mlx5e_async_event,
3593 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3594 .get_dev = mlx5e_get_netdev,
3597 void mlx5e_init(void)
3599 mlx5e_build_ptys2ethtool_map();
3600 mlx5_register_interface(&mlx5e_interface);
3603 void mlx5e_cleanup(void)
3605 mlx5_unregister_interface(&mlx5e_interface);