2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
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11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
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21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
42 struct mlx5e_rq_param {
43 u32 rqc[MLX5_ST_SZ_DW(rqc)];
44 struct mlx5_wq_param wq;
47 struct mlx5e_sq_param {
48 u32 sqc[MLX5_ST_SZ_DW(sqc)];
49 struct mlx5_wq_param wq;
54 struct mlx5e_cq_param {
55 u32 cqc[MLX5_ST_SZ_DW(cqc)];
56 struct mlx5_wq_param wq;
60 struct mlx5e_channel_param {
61 struct mlx5e_rq_param rq;
62 struct mlx5e_sq_param sq;
63 struct mlx5e_sq_param icosq;
64 struct mlx5e_cq_param rx_cq;
65 struct mlx5e_cq_param tx_cq;
66 struct mlx5e_cq_param icosq_cq;
69 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
71 struct mlx5_core_dev *mdev = priv->mdev;
74 port_state = mlx5_query_vport_state(mdev,
75 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
77 if (port_state == VPORT_STATE_UP)
78 netif_carrier_on(priv->netdev);
80 netif_carrier_off(priv->netdev);
83 static void mlx5e_update_carrier_work(struct work_struct *work)
85 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
88 mutex_lock(&priv->state_lock);
89 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
90 mlx5e_update_carrier(priv);
91 mutex_unlock(&priv->state_lock);
94 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
96 struct mlx5e_sw_stats *s = &priv->stats.sw;
97 struct mlx5e_rq_stats *rq_stats;
98 struct mlx5e_sq_stats *sq_stats;
99 u64 tx_offload_none = 0;
102 memset(s, 0, sizeof(*s));
103 for (i = 0; i < priv->params.num_channels; i++) {
104 rq_stats = &priv->channel[i]->rq.stats;
106 s->rx_packets += rq_stats->packets;
107 s->rx_bytes += rq_stats->bytes;
108 s->lro_packets += rq_stats->lro_packets;
109 s->lro_bytes += rq_stats->lro_bytes;
110 s->rx_csum_none += rq_stats->csum_none;
111 s->rx_csum_sw += rq_stats->csum_sw;
112 s->rx_csum_inner += rq_stats->csum_inner;
113 s->rx_wqe_err += rq_stats->wqe_err;
114 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
115 s->rx_mpwqe_frag += rq_stats->mpwqe_frag;
116 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
117 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
118 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
120 for (j = 0; j < priv->params.num_tc; j++) {
121 sq_stats = &priv->channel[i]->sq[j].stats;
123 s->tx_packets += sq_stats->packets;
124 s->tx_bytes += sq_stats->bytes;
125 s->tso_packets += sq_stats->tso_packets;
126 s->tso_bytes += sq_stats->tso_bytes;
127 s->tso_inner_packets += sq_stats->tso_inner_packets;
128 s->tso_inner_bytes += sq_stats->tso_inner_bytes;
129 s->tx_queue_stopped += sq_stats->stopped;
130 s->tx_queue_wake += sq_stats->wake;
131 s->tx_queue_dropped += sq_stats->dropped;
132 s->tx_csum_inner += sq_stats->csum_offload_inner;
133 tx_offload_none += sq_stats->csum_offload_none;
137 /* Update calculated offload counters */
138 s->tx_csum_offload = s->tx_packets - tx_offload_none - s->tx_csum_inner;
139 s->rx_csum_good = s->rx_packets - s->rx_csum_none -
142 s->link_down_events = MLX5_GET(ppcnt_reg,
143 priv->stats.pport.phy_counters,
144 counter_set.phys_layer_cntrs.link_down_events);
147 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
149 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
150 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
151 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
152 struct mlx5_core_dev *mdev = priv->mdev;
154 memset(in, 0, sizeof(in));
156 MLX5_SET(query_vport_counter_in, in, opcode,
157 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
158 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
159 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
161 memset(out, 0, outlen);
163 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
166 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
168 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
169 struct mlx5_core_dev *mdev = priv->mdev;
170 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
175 in = mlx5_vzalloc(sz);
179 MLX5_SET(ppcnt_reg, in, local_port, 1);
181 out = pstats->IEEE_802_3_counters;
182 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
183 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
185 out = pstats->RFC_2863_counters;
186 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
187 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
189 out = pstats->RFC_2819_counters;
190 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
191 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
193 out = pstats->phy_counters;
194 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
195 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
197 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
198 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
199 out = pstats->per_prio_counters[prio];
200 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
201 mlx5_core_access_reg(mdev, in, sz, out, sz,
202 MLX5_REG_PPCNT, 0, 0);
209 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
211 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
213 if (!priv->q_counter)
216 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
217 &qcnt->rx_out_of_buffer);
220 void mlx5e_update_stats(struct mlx5e_priv *priv)
222 mlx5e_update_q_counter(priv);
223 mlx5e_update_vport_counters(priv);
224 mlx5e_update_pport_counters(priv);
225 mlx5e_update_sw_counters(priv);
228 static void mlx5e_update_stats_work(struct work_struct *work)
230 struct delayed_work *dwork = to_delayed_work(work);
231 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
233 mutex_lock(&priv->state_lock);
234 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
235 mlx5e_update_stats(priv);
236 queue_delayed_work(priv->wq, dwork,
237 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
239 mutex_unlock(&priv->state_lock);
242 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
243 enum mlx5_dev_event event, unsigned long param)
245 struct mlx5e_priv *priv = vpriv;
247 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
251 case MLX5_DEV_EVENT_PORT_UP:
252 case MLX5_DEV_EVENT_PORT_DOWN:
253 queue_work(priv->wq, &priv->update_carrier_work);
261 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
263 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
266 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
268 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
269 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
272 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
273 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
275 static int mlx5e_create_rq(struct mlx5e_channel *c,
276 struct mlx5e_rq_param *param,
279 struct mlx5e_priv *priv = c->priv;
280 struct mlx5_core_dev *mdev = priv->mdev;
281 void *rqc = param->rqc;
282 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
288 param->wq.db_numa_node = cpu_to_node(c->cpu);
290 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
295 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
297 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
299 switch (priv->params.rq_wq_type) {
300 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
301 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
302 GFP_KERNEL, cpu_to_node(c->cpu));
305 goto err_rq_wq_destroy;
307 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
308 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
310 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
311 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
312 rq->wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
313 byte_count = rq->wqe_sz;
315 default: /* MLX5_WQ_TYPE_LINKED_LIST */
316 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
317 cpu_to_node(c->cpu));
320 goto err_rq_wq_destroy;
322 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
323 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
325 rq->wqe_sz = (priv->params.lro_en) ?
326 priv->params.lro_wqe_sz :
327 MLX5E_SW2HW_MTU(priv->netdev->mtu);
328 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
329 byte_count = rq->wqe_sz;
330 byte_count |= MLX5_HW_START_PADDING;
333 for (i = 0; i < wq_sz; i++) {
334 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
336 wqe->data.byte_count = cpu_to_be32(byte_count);
339 rq->wq_type = priv->params.rq_wq_type;
341 rq->netdev = c->netdev;
342 rq->tstamp = &priv->tstamp;
346 rq->mkey_be = c->mkey_be;
347 rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
352 mlx5_wq_destroy(&rq->wq_ctrl);
357 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
359 switch (rq->wq_type) {
360 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
363 default: /* MLX5_WQ_TYPE_LINKED_LIST */
367 mlx5_wq_destroy(&rq->wq_ctrl);
370 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
372 struct mlx5e_priv *priv = rq->priv;
373 struct mlx5_core_dev *mdev = priv->mdev;
381 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
382 sizeof(u64) * rq->wq_ctrl.buf.npages;
383 in = mlx5_vzalloc(inlen);
387 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
388 wq = MLX5_ADDR_OF(rqc, rqc, wq);
390 memcpy(rqc, param->rqc, sizeof(param->rqc));
392 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
393 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
394 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
395 MLX5_SET(rqc, rqc, vsd, priv->params.vlan_strip_disable);
396 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
397 MLX5_ADAPTER_PAGE_SHIFT);
398 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
400 mlx5_fill_page_array(&rq->wq_ctrl.buf,
401 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
403 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
410 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
413 struct mlx5e_channel *c = rq->channel;
414 struct mlx5e_priv *priv = c->priv;
415 struct mlx5_core_dev *mdev = priv->mdev;
422 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
423 in = mlx5_vzalloc(inlen);
427 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
429 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
430 MLX5_SET(rqc, rqc, state, next_state);
432 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
439 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
441 struct mlx5e_channel *c = rq->channel;
442 struct mlx5e_priv *priv = c->priv;
443 struct mlx5_core_dev *mdev = priv->mdev;
450 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
451 in = mlx5_vzalloc(inlen);
455 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
457 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
458 MLX5_SET64(modify_rq_in, in, modify_bitmask, MLX5_RQ_BITMASK_VSD);
459 MLX5_SET(rqc, rqc, vsd, vsd);
460 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
462 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
469 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
471 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
474 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
476 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
477 struct mlx5e_channel *c = rq->channel;
478 struct mlx5e_priv *priv = c->priv;
479 struct mlx5_wq_ll *wq = &rq->wq;
481 while (time_before(jiffies, exp_time)) {
482 if (wq->cur_sz >= priv->params.min_rx_wqes)
491 static int mlx5e_open_rq(struct mlx5e_channel *c,
492 struct mlx5e_rq_param *param,
495 struct mlx5e_sq *sq = &c->icosq;
496 u16 pi = sq->pc & sq->wq.sz_m1;
499 err = mlx5e_create_rq(c, param, rq);
503 err = mlx5e_enable_rq(rq, param);
507 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
511 set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
513 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_NOP;
514 sq->ico_wqe_info[pi].num_wqebbs = 1;
515 mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
520 mlx5e_disable_rq(rq);
522 mlx5e_destroy_rq(rq);
527 static void mlx5e_close_rq(struct mlx5e_rq *rq)
529 clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
530 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
532 mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
533 while (!mlx5_wq_ll_is_empty(&rq->wq))
536 /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
537 napi_synchronize(&rq->channel->napi);
539 mlx5e_disable_rq(rq);
540 mlx5e_destroy_rq(rq);
543 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
550 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
552 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
553 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
555 sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
556 sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
558 sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
561 if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
562 mlx5e_free_sq_db(sq);
566 sq->dma_fifo_mask = df_sz - 1;
571 static int mlx5e_create_sq(struct mlx5e_channel *c,
573 struct mlx5e_sq_param *param,
576 struct mlx5e_priv *priv = c->priv;
577 struct mlx5_core_dev *mdev = priv->mdev;
579 void *sqc = param->sqc;
580 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
583 err = mlx5_alloc_map_uar(mdev, &sq->uar, true);
587 param->wq.db_numa_node = cpu_to_node(c->cpu);
589 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq,
592 goto err_unmap_free_uar;
594 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
595 if (sq->uar.bf_map) {
596 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
597 sq->uar_map = sq->uar.bf_map;
599 sq->uar_map = sq->uar.map;
601 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
602 sq->max_inline = param->max_inline;
604 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
606 goto err_sq_wq_destroy;
609 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
611 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
614 cpu_to_node(c->cpu));
615 if (!sq->ico_wqe_info) {
622 txq_ix = c->ix + tc * priv->params.num_channels;
623 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
624 priv->txq_to_sq_map[txq_ix] = sq;
628 sq->tstamp = &priv->tstamp;
629 sq->mkey_be = c->mkey_be;
632 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
633 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
638 mlx5e_free_sq_db(sq);
641 mlx5_wq_destroy(&sq->wq_ctrl);
644 mlx5_unmap_free_uar(mdev, &sq->uar);
649 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
651 struct mlx5e_channel *c = sq->channel;
652 struct mlx5e_priv *priv = c->priv;
654 kfree(sq->ico_wqe_info);
655 mlx5e_free_sq_db(sq);
656 mlx5_wq_destroy(&sq->wq_ctrl);
657 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
660 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
662 struct mlx5e_channel *c = sq->channel;
663 struct mlx5e_priv *priv = c->priv;
664 struct mlx5_core_dev *mdev = priv->mdev;
672 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
673 sizeof(u64) * sq->wq_ctrl.buf.npages;
674 in = mlx5_vzalloc(inlen);
678 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
679 wq = MLX5_ADDR_OF(sqc, sqc, wq);
681 memcpy(sqc, param->sqc, sizeof(param->sqc));
683 MLX5_SET(sqc, sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
684 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
685 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
686 MLX5_SET(sqc, sqc, tis_lst_sz, param->icosq ? 0 : 1);
687 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
689 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
690 MLX5_SET(wq, wq, uar_page, sq->uar.index);
691 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
692 MLX5_ADAPTER_PAGE_SHIFT);
693 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
695 mlx5_fill_page_array(&sq->wq_ctrl.buf,
696 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
698 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
705 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
707 struct mlx5e_channel *c = sq->channel;
708 struct mlx5e_priv *priv = c->priv;
709 struct mlx5_core_dev *mdev = priv->mdev;
716 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
717 in = mlx5_vzalloc(inlen);
721 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
723 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
724 MLX5_SET(sqc, sqc, state, next_state);
726 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
733 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
735 struct mlx5e_channel *c = sq->channel;
736 struct mlx5e_priv *priv = c->priv;
737 struct mlx5_core_dev *mdev = priv->mdev;
739 mlx5_core_destroy_sq(mdev, sq->sqn);
742 static int mlx5e_open_sq(struct mlx5e_channel *c,
744 struct mlx5e_sq_param *param,
749 err = mlx5e_create_sq(c, tc, param, sq);
753 err = mlx5e_enable_sq(sq, param);
757 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
762 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
763 netdev_tx_reset_queue(sq->txq);
764 netif_tx_start_queue(sq->txq);
770 mlx5e_disable_sq(sq);
772 mlx5e_destroy_sq(sq);
777 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
779 __netif_tx_lock_bh(txq);
780 netif_tx_stop_queue(txq);
781 __netif_tx_unlock_bh(txq);
784 static void mlx5e_close_sq(struct mlx5e_sq *sq)
787 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
788 /* prevent netif_tx_wake_queue */
789 napi_synchronize(&sq->channel->napi);
790 netif_tx_disable_queue(sq->txq);
792 /* ensure hw is notified of all pending wqes */
793 if (mlx5e_sq_has_room_for(sq, 1))
794 mlx5e_send_nop(sq, true);
796 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
799 while (sq->cc != sq->pc) /* wait till sq is empty */
802 /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
803 napi_synchronize(&sq->channel->napi);
805 mlx5e_disable_sq(sq);
806 mlx5e_destroy_sq(sq);
809 static int mlx5e_create_cq(struct mlx5e_channel *c,
810 struct mlx5e_cq_param *param,
813 struct mlx5e_priv *priv = c->priv;
814 struct mlx5_core_dev *mdev = priv->mdev;
815 struct mlx5_core_cq *mcq = &cq->mcq;
821 param->wq.buf_numa_node = cpu_to_node(c->cpu);
822 param->wq.db_numa_node = cpu_to_node(c->cpu);
823 param->eq_ix = c->ix;
825 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
830 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
835 mcq->set_ci_db = cq->wq_ctrl.db.db;
836 mcq->arm_db = cq->wq_ctrl.db.db + 1;
839 mcq->vector = param->eq_ix;
840 mcq->comp = mlx5e_completion_event;
841 mcq->event = mlx5e_cq_error_event;
843 mcq->uar = &priv->cq_uar;
845 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
846 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
857 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
859 mlx5_wq_destroy(&cq->wq_ctrl);
862 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
864 struct mlx5e_priv *priv = cq->priv;
865 struct mlx5_core_dev *mdev = priv->mdev;
866 struct mlx5_core_cq *mcq = &cq->mcq;
871 unsigned int irqn_not_used;
875 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
876 sizeof(u64) * cq->wq_ctrl.buf.npages;
877 in = mlx5_vzalloc(inlen);
881 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
883 memcpy(cqc, param->cqc, sizeof(param->cqc));
885 mlx5_fill_page_array(&cq->wq_ctrl.buf,
886 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
888 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
890 MLX5_SET(cqc, cqc, c_eqn, eqn);
891 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
892 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
893 MLX5_ADAPTER_PAGE_SHIFT);
894 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
896 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
908 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
910 struct mlx5e_priv *priv = cq->priv;
911 struct mlx5_core_dev *mdev = priv->mdev;
913 mlx5_core_destroy_cq(mdev, &cq->mcq);
916 static int mlx5e_open_cq(struct mlx5e_channel *c,
917 struct mlx5e_cq_param *param,
919 u16 moderation_usecs,
920 u16 moderation_frames)
923 struct mlx5e_priv *priv = c->priv;
924 struct mlx5_core_dev *mdev = priv->mdev;
926 err = mlx5e_create_cq(c, param, cq);
930 err = mlx5e_enable_cq(cq, param);
934 if (MLX5_CAP_GEN(mdev, cq_moderation))
935 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
941 mlx5e_destroy_cq(cq);
946 static void mlx5e_close_cq(struct mlx5e_cq *cq)
948 mlx5e_disable_cq(cq);
949 mlx5e_destroy_cq(cq);
952 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
954 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
957 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
958 struct mlx5e_channel_param *cparam)
960 struct mlx5e_priv *priv = c->priv;
964 for (tc = 0; tc < c->num_tc; tc++) {
965 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
966 priv->params.tx_cq_moderation_usec,
967 priv->params.tx_cq_moderation_pkts);
969 goto err_close_tx_cqs;
975 for (tc--; tc >= 0; tc--)
976 mlx5e_close_cq(&c->sq[tc].cq);
981 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
985 for (tc = 0; tc < c->num_tc; tc++)
986 mlx5e_close_cq(&c->sq[tc].cq);
989 static int mlx5e_open_sqs(struct mlx5e_channel *c,
990 struct mlx5e_channel_param *cparam)
995 for (tc = 0; tc < c->num_tc; tc++) {
996 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1004 for (tc--; tc >= 0; tc--)
1005 mlx5e_close_sq(&c->sq[tc]);
1010 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1014 for (tc = 0; tc < c->num_tc; tc++)
1015 mlx5e_close_sq(&c->sq[tc]);
1018 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1022 for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
1023 priv->channeltc_to_txq_map[ix][i] =
1024 ix + i * priv->params.num_channels;
1027 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1028 struct mlx5e_channel_param *cparam,
1029 struct mlx5e_channel **cp)
1031 struct net_device *netdev = priv->netdev;
1032 int cpu = mlx5e_get_cpu(priv, ix);
1033 struct mlx5e_channel *c;
1036 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1043 c->pdev = &priv->mdev->pdev->dev;
1044 c->netdev = priv->netdev;
1045 c->mkey_be = cpu_to_be32(priv->mkey.key);
1046 c->num_tc = priv->params.num_tc;
1048 mlx5e_build_channeltc_to_txq_map(priv, ix);
1050 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1052 err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, 0, 0);
1056 err = mlx5e_open_tx_cqs(c, cparam);
1058 goto err_close_icosq_cq;
1060 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1061 priv->params.rx_cq_moderation_usec,
1062 priv->params.rx_cq_moderation_pkts);
1064 goto err_close_tx_cqs;
1066 napi_enable(&c->napi);
1068 err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1070 goto err_disable_napi;
1072 err = mlx5e_open_sqs(c, cparam);
1074 goto err_close_icosq;
1076 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1080 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1089 mlx5e_close_sq(&c->icosq);
1092 napi_disable(&c->napi);
1093 mlx5e_close_cq(&c->rq.cq);
1096 mlx5e_close_tx_cqs(c);
1099 mlx5e_close_cq(&c->icosq.cq);
1102 netif_napi_del(&c->napi);
1103 napi_hash_del(&c->napi);
1109 static void mlx5e_close_channel(struct mlx5e_channel *c)
1111 mlx5e_close_rq(&c->rq);
1113 mlx5e_close_sq(&c->icosq);
1114 napi_disable(&c->napi);
1115 mlx5e_close_cq(&c->rq.cq);
1116 mlx5e_close_tx_cqs(c);
1117 mlx5e_close_cq(&c->icosq.cq);
1118 netif_napi_del(&c->napi);
1120 napi_hash_del(&c->napi);
1126 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1127 struct mlx5e_rq_param *param)
1129 void *rqc = param->rqc;
1130 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1132 switch (priv->params.rq_wq_type) {
1133 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1134 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1135 priv->params.mpwqe_log_num_strides - 9);
1136 MLX5_SET(wq, wq, log_wqe_stride_size,
1137 priv->params.mpwqe_log_stride_sz - 6);
1138 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1140 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1141 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1144 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1145 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1146 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1147 MLX5_SET(wq, wq, pd, priv->pdn);
1148 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1150 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1151 param->wq.linear = 1;
1154 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1156 void *rqc = param->rqc;
1157 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1159 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1160 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1163 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1164 struct mlx5e_sq_param *param)
1166 void *sqc = param->sqc;
1167 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1169 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1170 MLX5_SET(wq, wq, pd, priv->pdn);
1172 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1175 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1176 struct mlx5e_sq_param *param)
1178 void *sqc = param->sqc;
1179 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1181 mlx5e_build_sq_param_common(priv, param);
1182 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1184 param->max_inline = priv->params.tx_max_inline;
1187 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1188 struct mlx5e_cq_param *param)
1190 void *cqc = param->cqc;
1192 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1195 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1196 struct mlx5e_cq_param *param)
1198 void *cqc = param->cqc;
1201 switch (priv->params.rq_wq_type) {
1202 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1203 log_cq_size = priv->params.log_rq_size +
1204 priv->params.mpwqe_log_num_strides;
1206 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1207 log_cq_size = priv->params.log_rq_size;
1210 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1211 if (priv->params.rx_cqe_compress) {
1212 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1213 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1216 mlx5e_build_common_cq_param(priv, param);
1219 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1220 struct mlx5e_cq_param *param)
1222 void *cqc = param->cqc;
1224 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1226 mlx5e_build_common_cq_param(priv, param);
1229 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1230 struct mlx5e_cq_param *param,
1233 void *cqc = param->cqc;
1235 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1237 mlx5e_build_common_cq_param(priv, param);
1240 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1241 struct mlx5e_sq_param *param,
1244 void *sqc = param->sqc;
1245 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1247 mlx5e_build_sq_param_common(priv, param);
1249 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1250 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1252 param->icosq = true;
1255 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1257 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1259 mlx5e_build_rq_param(priv, &cparam->rq);
1260 mlx5e_build_sq_param(priv, &cparam->sq);
1261 mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1262 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1263 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1264 mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1267 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1269 struct mlx5e_channel_param *cparam;
1270 int nch = priv->params.num_channels;
1275 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1278 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1279 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1281 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1283 if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1284 goto err_free_txq_to_sq_map;
1286 mlx5e_build_channel_param(priv, cparam);
1288 for (i = 0; i < nch; i++) {
1289 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1291 goto err_close_channels;
1294 for (j = 0; j < nch; j++) {
1295 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1297 goto err_close_channels;
1304 for (i--; i >= 0; i--)
1305 mlx5e_close_channel(priv->channel[i]);
1307 err_free_txq_to_sq_map:
1308 kfree(priv->txq_to_sq_map);
1309 kfree(priv->channel);
1315 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1319 for (i = 0; i < priv->params.num_channels; i++)
1320 mlx5e_close_channel(priv->channel[i]);
1322 kfree(priv->txq_to_sq_map);
1323 kfree(priv->channel);
1326 static int mlx5e_rx_hash_fn(int hfunc)
1328 return (hfunc == ETH_RSS_HASH_TOP) ?
1329 MLX5_RX_HASH_FN_TOEPLITZ :
1330 MLX5_RX_HASH_FN_INVERTED_XOR8;
1333 static int mlx5e_bits_invert(unsigned long a, int size)
1338 for (i = 0; i < size; i++)
1339 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1344 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1348 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1352 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1353 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1355 ix = priv->params.indirection_rqt[ix];
1356 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1357 priv->channel[ix]->rq.rqn :
1359 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1363 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1366 u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1367 priv->channel[ix]->rq.rqn :
1370 MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1373 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, int ix, u32 *rqtn)
1375 struct mlx5_core_dev *mdev = priv->mdev;
1381 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1382 in = mlx5_vzalloc(inlen);
1386 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1388 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1389 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1391 if (sz > 1) /* RSS */
1392 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1394 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1396 err = mlx5_core_create_rqt(mdev, in, inlen, rqtn);
1402 static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, u32 rqtn)
1404 mlx5_core_destroy_rqt(priv->mdev, rqtn);
1407 static int mlx5e_create_rqts(struct mlx5e_priv *priv)
1409 int nch = mlx5e_get_max_num_channels(priv->mdev);
1415 rqtn = &priv->indir_rqtn;
1416 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqtn);
1421 for (ix = 0; ix < nch; ix++) {
1422 rqtn = &priv->direct_tir[ix].rqtn;
1423 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqtn);
1425 goto err_destroy_rqts;
1431 for (ix--; ix >= 0; ix--)
1432 mlx5e_destroy_rqt(priv, priv->direct_tir[ix].rqtn);
1434 mlx5e_destroy_rqt(priv, priv->indir_rqtn);
1439 static void mlx5e_destroy_rqts(struct mlx5e_priv *priv)
1441 int nch = mlx5e_get_max_num_channels(priv->mdev);
1444 for (i = 0; i < nch; i++)
1445 mlx5e_destroy_rqt(priv, priv->direct_tir[i].rqtn);
1447 mlx5e_destroy_rqt(priv, priv->indir_rqtn);
1450 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
1452 struct mlx5_core_dev *mdev = priv->mdev;
1458 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1459 in = mlx5_vzalloc(inlen);
1463 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1465 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1466 if (sz > 1) /* RSS */
1467 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1469 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1471 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1473 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
1480 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1485 rqtn = priv->indir_rqtn;
1486 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1487 for (ix = 0; ix < priv->params.num_channels; ix++) {
1488 rqtn = priv->direct_tir[ix].rqtn;
1489 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1493 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1495 if (!priv->params.lro_en)
1498 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1500 MLX5_SET(tirc, tirc, lro_enable_mask,
1501 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1502 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1503 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1504 (priv->params.lro_wqe_sz -
1505 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1506 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1507 MLX5_CAP_ETH(priv->mdev,
1508 lro_timer_supported_periods[2]));
1511 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1513 MLX5_SET(tirc, tirc, rx_hash_fn,
1514 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1515 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1516 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1517 rx_hash_toeplitz_key);
1518 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1519 rx_hash_toeplitz_key);
1521 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1522 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1526 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1528 struct mlx5_core_dev *mdev = priv->mdev;
1537 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1538 in = mlx5_vzalloc(inlen);
1542 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1543 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1545 mlx5e_build_tir_ctx_lro(tirc, priv);
1547 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1548 err = mlx5_core_modify_tir(mdev, priv->indir_tirn[tt], in,
1554 for (ix = 0; ix < mlx5e_get_max_num_channels(mdev); ix++) {
1555 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
1567 static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1574 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1575 in = mlx5_vzalloc(inlen);
1579 MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1581 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
1582 err = mlx5_core_modify_tir(priv->mdev, priv->indir_tirn[i], in,
1588 for (i = 0; i < priv->params.num_channels; i++) {
1589 err = mlx5_core_modify_tir(priv->mdev,
1590 priv->direct_tir[i].tirn, in,
1601 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
1603 struct mlx5_core_dev *mdev = priv->mdev;
1604 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
1607 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
1611 /* Update vport context MTU */
1612 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
1616 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
1618 struct mlx5_core_dev *mdev = priv->mdev;
1622 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
1623 if (err || !hw_mtu) /* fallback to port oper mtu */
1624 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1626 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
1629 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1631 struct mlx5e_priv *priv = netdev_priv(netdev);
1635 err = mlx5e_set_mtu(priv, netdev->mtu);
1639 mlx5e_query_mtu(priv, &mtu);
1640 if (mtu != netdev->mtu)
1641 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
1642 __func__, mtu, netdev->mtu);
1648 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1650 struct mlx5e_priv *priv = netdev_priv(netdev);
1651 int nch = priv->params.num_channels;
1652 int ntc = priv->params.num_tc;
1655 netdev_reset_tc(netdev);
1660 netdev_set_num_tc(netdev, ntc);
1662 for (tc = 0; tc < ntc; tc++)
1663 netdev_set_tc_queue(netdev, tc, nch, tc * nch);
1666 int mlx5e_open_locked(struct net_device *netdev)
1668 struct mlx5e_priv *priv = netdev_priv(netdev);
1672 set_bit(MLX5E_STATE_OPENED, &priv->state);
1674 mlx5e_netdev_set_tcs(netdev);
1676 num_txqs = priv->params.num_channels * priv->params.num_tc;
1677 netif_set_real_num_tx_queues(netdev, num_txqs);
1678 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1680 err = mlx5e_set_dev_port_mtu(netdev);
1682 goto err_clear_state_opened_flag;
1684 err = mlx5e_open_channels(priv);
1686 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1688 goto err_clear_state_opened_flag;
1691 err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1693 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1695 goto err_close_channels;
1698 mlx5e_redirect_rqts(priv);
1699 mlx5e_update_carrier(priv);
1700 mlx5e_timestamp_init(priv);
1701 #ifdef CONFIG_RFS_ACCEL
1702 priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
1705 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
1710 mlx5e_close_channels(priv);
1711 err_clear_state_opened_flag:
1712 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1716 static int mlx5e_open(struct net_device *netdev)
1718 struct mlx5e_priv *priv = netdev_priv(netdev);
1721 mutex_lock(&priv->state_lock);
1722 err = mlx5e_open_locked(netdev);
1723 mutex_unlock(&priv->state_lock);
1728 int mlx5e_close_locked(struct net_device *netdev)
1730 struct mlx5e_priv *priv = netdev_priv(netdev);
1732 /* May already be CLOSED in case a previous configuration operation
1733 * (e.g RX/TX queue size change) that involves close&open failed.
1735 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1738 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1740 mlx5e_timestamp_cleanup(priv);
1741 netif_carrier_off(priv->netdev);
1742 mlx5e_redirect_rqts(priv);
1743 mlx5e_close_channels(priv);
1748 static int mlx5e_close(struct net_device *netdev)
1750 struct mlx5e_priv *priv = netdev_priv(netdev);
1753 mutex_lock(&priv->state_lock);
1754 err = mlx5e_close_locked(netdev);
1755 mutex_unlock(&priv->state_lock);
1760 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1761 struct mlx5e_rq *rq,
1762 struct mlx5e_rq_param *param)
1764 struct mlx5_core_dev *mdev = priv->mdev;
1765 void *rqc = param->rqc;
1766 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1769 param->wq.db_numa_node = param->wq.buf_numa_node;
1771 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
1781 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1782 struct mlx5e_cq *cq,
1783 struct mlx5e_cq_param *param)
1785 struct mlx5_core_dev *mdev = priv->mdev;
1786 struct mlx5_core_cq *mcq = &cq->mcq;
1791 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1796 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1799 mcq->set_ci_db = cq->wq_ctrl.db.db;
1800 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1801 *mcq->set_ci_db = 0;
1803 mcq->vector = param->eq_ix;
1804 mcq->comp = mlx5e_completion_event;
1805 mcq->event = mlx5e_cq_error_event;
1807 mcq->uar = &priv->cq_uar;
1814 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1816 struct mlx5e_cq_param cq_param;
1817 struct mlx5e_rq_param rq_param;
1818 struct mlx5e_rq *rq = &priv->drop_rq;
1819 struct mlx5e_cq *cq = &priv->drop_rq.cq;
1822 memset(&cq_param, 0, sizeof(cq_param));
1823 memset(&rq_param, 0, sizeof(rq_param));
1824 mlx5e_build_drop_rq_param(&rq_param);
1826 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1830 err = mlx5e_enable_cq(cq, &cq_param);
1832 goto err_destroy_cq;
1834 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1836 goto err_disable_cq;
1838 err = mlx5e_enable_rq(rq, &rq_param);
1840 goto err_destroy_rq;
1845 mlx5e_destroy_rq(&priv->drop_rq);
1848 mlx5e_disable_cq(&priv->drop_rq.cq);
1851 mlx5e_destroy_cq(&priv->drop_rq.cq);
1856 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1858 mlx5e_disable_rq(&priv->drop_rq);
1859 mlx5e_destroy_rq(&priv->drop_rq);
1860 mlx5e_disable_cq(&priv->drop_rq.cq);
1861 mlx5e_destroy_cq(&priv->drop_rq.cq);
1864 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1866 struct mlx5_core_dev *mdev = priv->mdev;
1867 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1868 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1870 memset(in, 0, sizeof(in));
1872 MLX5_SET(tisc, tisc, prio, tc << 1);
1873 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1875 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1878 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1880 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1883 static int mlx5e_create_tises(struct mlx5e_priv *priv)
1888 for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
1889 err = mlx5e_create_tis(priv, tc);
1891 goto err_close_tises;
1897 for (tc--; tc >= 0; tc--)
1898 mlx5e_destroy_tis(priv, tc);
1903 static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1907 for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
1908 mlx5e_destroy_tis(priv, tc);
1911 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
1912 enum mlx5e_traffic_types tt)
1914 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1916 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1918 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
1919 MLX5_HASH_FIELD_SEL_DST_IP)
1921 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
1922 MLX5_HASH_FIELD_SEL_DST_IP |\
1923 MLX5_HASH_FIELD_SEL_L4_SPORT |\
1924 MLX5_HASH_FIELD_SEL_L4_DPORT)
1926 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
1927 MLX5_HASH_FIELD_SEL_DST_IP |\
1928 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1930 mlx5e_build_tir_ctx_lro(tirc, priv);
1932 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1933 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqtn);
1934 mlx5e_build_tir_ctx_hash(tirc, priv);
1937 case MLX5E_TT_IPV4_TCP:
1938 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1939 MLX5_L3_PROT_TYPE_IPV4);
1940 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1941 MLX5_L4_PROT_TYPE_TCP);
1942 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1943 MLX5_HASH_IP_L4PORTS);
1946 case MLX5E_TT_IPV6_TCP:
1947 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1948 MLX5_L3_PROT_TYPE_IPV6);
1949 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1950 MLX5_L4_PROT_TYPE_TCP);
1951 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1952 MLX5_HASH_IP_L4PORTS);
1955 case MLX5E_TT_IPV4_UDP:
1956 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1957 MLX5_L3_PROT_TYPE_IPV4);
1958 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1959 MLX5_L4_PROT_TYPE_UDP);
1960 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1961 MLX5_HASH_IP_L4PORTS);
1964 case MLX5E_TT_IPV6_UDP:
1965 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1966 MLX5_L3_PROT_TYPE_IPV6);
1967 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1968 MLX5_L4_PROT_TYPE_UDP);
1969 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1970 MLX5_HASH_IP_L4PORTS);
1973 case MLX5E_TT_IPV4_IPSEC_AH:
1974 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1975 MLX5_L3_PROT_TYPE_IPV4);
1976 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1977 MLX5_HASH_IP_IPSEC_SPI);
1980 case MLX5E_TT_IPV6_IPSEC_AH:
1981 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1982 MLX5_L3_PROT_TYPE_IPV6);
1983 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1984 MLX5_HASH_IP_IPSEC_SPI);
1987 case MLX5E_TT_IPV4_IPSEC_ESP:
1988 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1989 MLX5_L3_PROT_TYPE_IPV4);
1990 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1991 MLX5_HASH_IP_IPSEC_SPI);
1994 case MLX5E_TT_IPV6_IPSEC_ESP:
1995 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1996 MLX5_L3_PROT_TYPE_IPV6);
1997 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1998 MLX5_HASH_IP_IPSEC_SPI);
2002 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2003 MLX5_L3_PROT_TYPE_IPV4);
2004 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2009 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2010 MLX5_L3_PROT_TYPE_IPV6);
2011 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2016 "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2020 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2023 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2025 mlx5e_build_tir_ctx_lro(tirc, priv);
2027 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2028 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2029 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2032 static int mlx5e_create_tirs(struct mlx5e_priv *priv)
2034 int nch = mlx5e_get_max_num_channels(priv->mdev);
2043 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2044 in = mlx5_vzalloc(inlen);
2049 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2050 memset(in, 0, inlen);
2051 tirn = &priv->indir_tirn[tt];
2052 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2053 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2054 err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn);
2056 goto err_destroy_tirs;
2060 for (ix = 0; ix < nch; ix++) {
2061 memset(in, 0, inlen);
2062 tirn = &priv->direct_tir[ix].tirn;
2063 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2064 mlx5e_build_direct_tir_ctx(priv, tirc,
2065 priv->direct_tir[ix].rqtn);
2066 err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn);
2068 goto err_destroy_ch_tirs;
2075 err_destroy_ch_tirs:
2076 for (ix--; ix >= 0; ix--)
2077 mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[ix].tirn);
2080 for (tt--; tt >= 0; tt--)
2081 mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[tt]);
2088 static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
2090 int nch = mlx5e_get_max_num_channels(priv->mdev);
2093 for (i = 0; i < nch; i++)
2094 mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[i].tirn);
2096 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2097 mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[i]);
2100 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2105 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2108 for (i = 0; i < priv->params.num_channels; i++) {
2109 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2117 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2119 struct mlx5e_priv *priv = netdev_priv(netdev);
2123 if (tc && tc != MLX5E_MAX_NUM_TC)
2126 mutex_lock(&priv->state_lock);
2128 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2130 mlx5e_close_locked(priv->netdev);
2132 priv->params.num_tc = tc ? tc : 1;
2135 err = mlx5e_open_locked(priv->netdev);
2137 mutex_unlock(&priv->state_lock);
2142 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2143 __be16 proto, struct tc_to_netdev *tc)
2145 struct mlx5e_priv *priv = netdev_priv(dev);
2147 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2151 case TC_SETUP_CLSFLOWER:
2152 switch (tc->cls_flower->command) {
2153 case TC_CLSFLOWER_REPLACE:
2154 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2155 case TC_CLSFLOWER_DESTROY:
2156 return mlx5e_delete_flower(priv, tc->cls_flower);
2163 if (tc->type != TC_SETUP_MQPRIO)
2166 return mlx5e_setup_tc(dev, tc->tc);
2169 static struct rtnl_link_stats64 *
2170 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2172 struct mlx5e_priv *priv = netdev_priv(dev);
2173 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2174 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2175 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2177 stats->rx_packets = sstats->rx_packets;
2178 stats->rx_bytes = sstats->rx_bytes;
2179 stats->tx_packets = sstats->tx_packets;
2180 stats->tx_bytes = sstats->tx_bytes;
2182 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2183 stats->tx_dropped = sstats->tx_queue_dropped;
2185 stats->rx_length_errors =
2186 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2187 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2188 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2189 stats->rx_crc_errors =
2190 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2191 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2192 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2193 stats->tx_carrier_errors =
2194 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2195 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2196 stats->rx_frame_errors;
2197 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2199 /* vport multicast also counts packets that are dropped due to steering
2200 * or rx out of buffer
2203 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2208 static void mlx5e_set_rx_mode(struct net_device *dev)
2210 struct mlx5e_priv *priv = netdev_priv(dev);
2212 queue_work(priv->wq, &priv->set_rx_mode_work);
2215 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2217 struct mlx5e_priv *priv = netdev_priv(netdev);
2218 struct sockaddr *saddr = addr;
2220 if (!is_valid_ether_addr(saddr->sa_data))
2221 return -EADDRNOTAVAIL;
2223 netif_addr_lock_bh(netdev);
2224 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2225 netif_addr_unlock_bh(netdev);
2227 queue_work(priv->wq, &priv->set_rx_mode_work);
2232 #define MLX5E_SET_FEATURE(netdev, feature, enable) \
2235 netdev->features |= feature; \
2237 netdev->features &= ~feature; \
2240 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2242 static int set_feature_lro(struct net_device *netdev, bool enable)
2244 struct mlx5e_priv *priv = netdev_priv(netdev);
2245 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2248 mutex_lock(&priv->state_lock);
2250 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2251 mlx5e_close_locked(priv->netdev);
2253 priv->params.lro_en = enable;
2254 err = mlx5e_modify_tirs_lro(priv);
2256 netdev_err(netdev, "lro modify failed, %d\n", err);
2257 priv->params.lro_en = !enable;
2260 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2261 mlx5e_open_locked(priv->netdev);
2263 mutex_unlock(&priv->state_lock);
2268 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2270 struct mlx5e_priv *priv = netdev_priv(netdev);
2273 mlx5e_enable_vlan_filter(priv);
2275 mlx5e_disable_vlan_filter(priv);
2280 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2282 struct mlx5e_priv *priv = netdev_priv(netdev);
2284 if (!enable && mlx5e_tc_num_filters(priv)) {
2286 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2293 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2295 struct mlx5e_priv *priv = netdev_priv(netdev);
2296 struct mlx5_core_dev *mdev = priv->mdev;
2298 return mlx5_set_port_fcs(mdev, !enable);
2301 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2303 struct mlx5e_priv *priv = netdev_priv(netdev);
2306 mutex_lock(&priv->state_lock);
2308 priv->params.vlan_strip_disable = !enable;
2309 err = mlx5e_modify_rqs_vsd(priv, !enable);
2311 priv->params.vlan_strip_disable = enable;
2313 mutex_unlock(&priv->state_lock);
2318 #ifdef CONFIG_RFS_ACCEL
2319 static int set_feature_arfs(struct net_device *netdev, bool enable)
2321 struct mlx5e_priv *priv = netdev_priv(netdev);
2325 err = mlx5e_arfs_enable(priv);
2327 err = mlx5e_arfs_disable(priv);
2333 static int mlx5e_handle_feature(struct net_device *netdev,
2334 netdev_features_t wanted_features,
2335 netdev_features_t feature,
2336 mlx5e_feature_handler feature_handler)
2338 netdev_features_t changes = wanted_features ^ netdev->features;
2339 bool enable = !!(wanted_features & feature);
2342 if (!(changes & feature))
2345 err = feature_handler(netdev, enable);
2347 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2348 enable ? "Enable" : "Disable", feature, err);
2352 MLX5E_SET_FEATURE(netdev, feature, enable);
2356 static int mlx5e_set_features(struct net_device *netdev,
2357 netdev_features_t features)
2361 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2363 err |= mlx5e_handle_feature(netdev, features,
2364 NETIF_F_HW_VLAN_CTAG_FILTER,
2365 set_feature_vlan_filter);
2366 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2367 set_feature_tc_num_filters);
2368 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2369 set_feature_rx_all);
2370 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2371 set_feature_rx_vlan);
2372 #ifdef CONFIG_RFS_ACCEL
2373 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2377 return err ? -EINVAL : 0;
2380 #define MXL5_HW_MIN_MTU 64
2381 #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2383 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2385 struct mlx5e_priv *priv = netdev_priv(netdev);
2386 struct mlx5_core_dev *mdev = priv->mdev;
2392 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2394 max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2395 min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
2397 if (new_mtu > max_mtu || new_mtu < min_mtu) {
2399 "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2400 __func__, new_mtu, min_mtu, max_mtu);
2404 mutex_lock(&priv->state_lock);
2406 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2408 mlx5e_close_locked(netdev);
2410 netdev->mtu = new_mtu;
2413 err = mlx5e_open_locked(netdev);
2415 mutex_unlock(&priv->state_lock);
2420 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2424 return mlx5e_hwstamp_set(dev, ifr);
2426 return mlx5e_hwstamp_get(dev, ifr);
2432 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2434 struct mlx5e_priv *priv = netdev_priv(dev);
2435 struct mlx5_core_dev *mdev = priv->mdev;
2437 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2440 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2442 struct mlx5e_priv *priv = netdev_priv(dev);
2443 struct mlx5_core_dev *mdev = priv->mdev;
2445 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2449 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2451 struct mlx5e_priv *priv = netdev_priv(dev);
2452 struct mlx5_core_dev *mdev = priv->mdev;
2454 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2457 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2459 struct mlx5e_priv *priv = netdev_priv(dev);
2460 struct mlx5_core_dev *mdev = priv->mdev;
2462 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2464 static int mlx5_vport_link2ifla(u8 esw_link)
2467 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2468 return IFLA_VF_LINK_STATE_DISABLE;
2469 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2470 return IFLA_VF_LINK_STATE_ENABLE;
2472 return IFLA_VF_LINK_STATE_AUTO;
2475 static int mlx5_ifla_link2vport(u8 ifla_link)
2477 switch (ifla_link) {
2478 case IFLA_VF_LINK_STATE_DISABLE:
2479 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2480 case IFLA_VF_LINK_STATE_ENABLE:
2481 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2483 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2486 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2489 struct mlx5e_priv *priv = netdev_priv(dev);
2490 struct mlx5_core_dev *mdev = priv->mdev;
2492 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2493 mlx5_ifla_link2vport(link_state));
2496 static int mlx5e_get_vf_config(struct net_device *dev,
2497 int vf, struct ifla_vf_info *ivi)
2499 struct mlx5e_priv *priv = netdev_priv(dev);
2500 struct mlx5_core_dev *mdev = priv->mdev;
2503 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2506 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2510 static int mlx5e_get_vf_stats(struct net_device *dev,
2511 int vf, struct ifla_vf_stats *vf_stats)
2513 struct mlx5e_priv *priv = netdev_priv(dev);
2514 struct mlx5_core_dev *mdev = priv->mdev;
2516 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2520 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2521 sa_family_t sa_family, __be16 port)
2523 struct mlx5e_priv *priv = netdev_priv(netdev);
2525 if (!mlx5e_vxlan_allowed(priv->mdev))
2528 mlx5e_vxlan_queue_work(priv, sa_family, be16_to_cpu(port), 1);
2531 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2532 sa_family_t sa_family, __be16 port)
2534 struct mlx5e_priv *priv = netdev_priv(netdev);
2536 if (!mlx5e_vxlan_allowed(priv->mdev))
2539 mlx5e_vxlan_queue_work(priv, sa_family, be16_to_cpu(port), 0);
2542 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2543 struct sk_buff *skb,
2544 netdev_features_t features)
2546 struct udphdr *udph;
2550 switch (vlan_get_protocol(skb)) {
2551 case htons(ETH_P_IP):
2552 proto = ip_hdr(skb)->protocol;
2554 case htons(ETH_P_IPV6):
2555 proto = ipv6_hdr(skb)->nexthdr;
2561 if (proto == IPPROTO_UDP) {
2562 udph = udp_hdr(skb);
2563 port = be16_to_cpu(udph->dest);
2566 /* Verify if UDP port is being offloaded by HW */
2567 if (port && mlx5e_vxlan_lookup_port(priv, port))
2571 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2572 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2575 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2576 struct net_device *netdev,
2577 netdev_features_t features)
2579 struct mlx5e_priv *priv = netdev_priv(netdev);
2581 features = vlan_features_check(skb, features);
2582 features = vxlan_features_check(skb, features);
2584 /* Validate if the tunneled packet is being offloaded by HW */
2585 if (skb->encapsulation &&
2586 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2587 return mlx5e_vxlan_features_check(priv, skb, features);
2592 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2593 .ndo_open = mlx5e_open,
2594 .ndo_stop = mlx5e_close,
2595 .ndo_start_xmit = mlx5e_xmit,
2596 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2597 .ndo_select_queue = mlx5e_select_queue,
2598 .ndo_get_stats64 = mlx5e_get_stats,
2599 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2600 .ndo_set_mac_address = mlx5e_set_mac,
2601 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2602 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2603 .ndo_set_features = mlx5e_set_features,
2604 .ndo_change_mtu = mlx5e_change_mtu,
2605 .ndo_do_ioctl = mlx5e_ioctl,
2606 #ifdef CONFIG_RFS_ACCEL
2607 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
2611 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2612 .ndo_open = mlx5e_open,
2613 .ndo_stop = mlx5e_close,
2614 .ndo_start_xmit = mlx5e_xmit,
2615 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2616 .ndo_select_queue = mlx5e_select_queue,
2617 .ndo_get_stats64 = mlx5e_get_stats,
2618 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2619 .ndo_set_mac_address = mlx5e_set_mac,
2620 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2621 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2622 .ndo_set_features = mlx5e_set_features,
2623 .ndo_change_mtu = mlx5e_change_mtu,
2624 .ndo_do_ioctl = mlx5e_ioctl,
2625 .ndo_add_vxlan_port = mlx5e_add_vxlan_port,
2626 .ndo_del_vxlan_port = mlx5e_del_vxlan_port,
2627 .ndo_features_check = mlx5e_features_check,
2628 #ifdef CONFIG_RFS_ACCEL
2629 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
2631 .ndo_set_vf_mac = mlx5e_set_vf_mac,
2632 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
2633 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
2634 .ndo_set_vf_trust = mlx5e_set_vf_trust,
2635 .ndo_get_vf_config = mlx5e_get_vf_config,
2636 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
2637 .ndo_get_vf_stats = mlx5e_get_vf_stats,
2640 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2642 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2644 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2645 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2646 !MLX5_CAP_ETH(mdev, csum_cap) ||
2647 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2648 !MLX5_CAP_ETH(mdev, vlan_cap) ||
2649 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2650 MLX5_CAP_FLOWTABLE(mdev,
2651 flow_table_properties_nic_receive.max_ft_level)
2653 mlx5_core_warn(mdev,
2654 "Not creating net device, some required device capabilities are missing\n");
2657 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2658 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2659 if (!MLX5_CAP_GEN(mdev, cq_moderation))
2660 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2665 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2667 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2669 return bf_buf_size -
2670 sizeof(struct mlx5e_tx_wqe) +
2671 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2674 #ifdef CONFIG_MLX5_CORE_EN_DCB
2675 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2679 priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2680 for (i = 0; i < priv->params.ets.ets_cap; i++) {
2681 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2682 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2683 priv->params.ets.prio_tc[i] = i;
2686 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2687 priv->params.ets.prio_tc[0] = 1;
2688 priv->params.ets.prio_tc[1] = 0;
2692 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2693 u32 *indirection_rqt, int len,
2696 int node = mdev->priv.numa_node;
2697 int node_num_of_cores;
2701 node = first_online_node;
2703 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2705 if (node_num_of_cores)
2706 num_channels = min_t(int, num_channels, node_num_of_cores);
2708 for (i = 0; i < len; i++)
2709 indirection_rqt[i] = i % num_channels;
2712 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2714 return MLX5_CAP_GEN(mdev, striding_rq) &&
2715 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2716 MLX5_CAP_ETH(mdev, reg_umr_sq);
2719 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
2721 enum pcie_link_width width;
2722 enum pci_bus_speed speed;
2725 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
2729 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
2733 case PCIE_SPEED_2_5GT:
2734 *pci_bw = 2500 * width;
2736 case PCIE_SPEED_5_0GT:
2737 *pci_bw = 5000 * width;
2739 case PCIE_SPEED_8_0GT:
2740 *pci_bw = 8000 * width;
2749 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
2751 return (link_speed && pci_bw &&
2752 (pci_bw < 40000) && (pci_bw < link_speed));
2755 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2756 struct net_device *netdev,
2759 struct mlx5e_priv *priv = netdev_priv(netdev);
2763 priv->params.log_sq_size =
2764 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2765 priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
2766 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
2767 MLX5_WQ_TYPE_LINKED_LIST;
2769 /* set CQE compression */
2770 priv->params.rx_cqe_compress_admin = false;
2771 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
2772 MLX5_CAP_GEN(mdev, vport_group_manager)) {
2773 mlx5e_get_max_linkspeed(mdev, &link_speed);
2774 mlx5e_get_pci_bw(mdev, &pci_bw);
2775 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
2776 link_speed, pci_bw);
2777 priv->params.rx_cqe_compress_admin =
2778 cqe_compress_heuristic(link_speed, pci_bw);
2781 priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
2783 switch (priv->params.rq_wq_type) {
2784 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2785 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
2786 priv->params.mpwqe_log_stride_sz =
2787 priv->params.rx_cqe_compress ?
2788 MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
2789 MLX5_MPWRQ_LOG_STRIDE_SIZE;
2790 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
2791 priv->params.mpwqe_log_stride_sz;
2792 priv->params.lro_en = true;
2794 default: /* MLX5_WQ_TYPE_LINKED_LIST */
2795 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2798 mlx5_core_info(mdev,
2799 "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
2800 priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
2801 BIT(priv->params.log_rq_size),
2802 BIT(priv->params.mpwqe_log_stride_sz),
2803 priv->params.rx_cqe_compress_admin);
2805 priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
2806 BIT(priv->params.log_rq_size));
2807 priv->params.rx_cq_moderation_usec =
2808 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2809 priv->params.rx_cq_moderation_pkts =
2810 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2811 priv->params.tx_cq_moderation_usec =
2812 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2813 priv->params.tx_cq_moderation_pkts =
2814 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2815 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
2816 priv->params.num_tc = 1;
2817 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
2819 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2820 sizeof(priv->params.toeplitz_hash_key));
2822 mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
2823 MLX5E_INDIR_RQT_SIZE, num_channels);
2825 priv->params.lro_wqe_sz =
2826 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2829 priv->netdev = netdev;
2830 priv->params.num_channels = num_channels;
2832 #ifdef CONFIG_MLX5_CORE_EN_DCB
2833 mlx5e_ets_init(priv);
2836 mutex_init(&priv->state_lock);
2838 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2839 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2840 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2843 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2845 struct mlx5e_priv *priv = netdev_priv(netdev);
2847 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
2848 if (is_zero_ether_addr(netdev->dev_addr) &&
2849 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2850 eth_hw_addr_random(netdev);
2851 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2855 static void mlx5e_build_netdev(struct net_device *netdev)
2857 struct mlx5e_priv *priv = netdev_priv(netdev);
2858 struct mlx5_core_dev *mdev = priv->mdev;
2862 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2864 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2865 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
2866 #ifdef CONFIG_MLX5_CORE_EN_DCB
2867 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2870 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
2873 netdev->watchdog_timeo = 15 * HZ;
2875 netdev->ethtool_ops = &mlx5e_ethtool_ops;
2877 netdev->vlan_features |= NETIF_F_SG;
2878 netdev->vlan_features |= NETIF_F_IP_CSUM;
2879 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
2880 netdev->vlan_features |= NETIF_F_GRO;
2881 netdev->vlan_features |= NETIF_F_TSO;
2882 netdev->vlan_features |= NETIF_F_TSO6;
2883 netdev->vlan_features |= NETIF_F_RXCSUM;
2884 netdev->vlan_features |= NETIF_F_RXHASH;
2886 if (!!MLX5_CAP_ETH(mdev, lro_cap))
2887 netdev->vlan_features |= NETIF_F_LRO;
2889 netdev->hw_features = netdev->vlan_features;
2890 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
2891 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
2892 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2894 if (mlx5e_vxlan_allowed(mdev)) {
2895 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
2896 NETIF_F_GSO_UDP_TUNNEL_CSUM |
2897 NETIF_F_GSO_PARTIAL;
2898 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
2899 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
2900 netdev->hw_enc_features |= NETIF_F_TSO;
2901 netdev->hw_enc_features |= NETIF_F_TSO6;
2902 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
2903 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
2904 NETIF_F_GSO_PARTIAL;
2905 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
2908 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
2911 netdev->hw_features |= NETIF_F_RXALL;
2913 netdev->features = netdev->hw_features;
2914 if (!priv->params.lro_en)
2915 netdev->features &= ~NETIF_F_LRO;
2918 netdev->features &= ~NETIF_F_RXALL;
2920 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
2921 if (FT_CAP(flow_modify_en) &&
2922 FT_CAP(modify_root) &&
2923 FT_CAP(identified_miss_table_mode) &&
2924 FT_CAP(flow_table_modify)) {
2925 netdev->hw_features |= NETIF_F_HW_TC;
2926 #ifdef CONFIG_RFS_ACCEL
2927 netdev->hw_features |= NETIF_F_NTUPLE;
2931 netdev->features |= NETIF_F_HIGHDMA;
2933 netdev->priv_flags |= IFF_UNICAST_FLT;
2935 mlx5e_set_netdev_dev_addr(netdev);
2938 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2939 struct mlx5_core_mkey *mkey)
2941 struct mlx5_core_dev *mdev = priv->mdev;
2942 struct mlx5_create_mkey_mbox_in *in;
2945 in = mlx5_vzalloc(sizeof(*in));
2949 in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2950 MLX5_PERM_LOCAL_READ |
2951 MLX5_ACCESS_MODE_PA;
2952 in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2953 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2955 err = mlx5_core_create_mkey(mdev, mkey, in, sizeof(*in), NULL, NULL,
2963 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
2965 struct mlx5_core_dev *mdev = priv->mdev;
2968 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
2970 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
2971 priv->q_counter = 0;
2975 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
2977 if (!priv->q_counter)
2980 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
2983 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
2985 struct mlx5_core_dev *mdev = priv->mdev;
2986 struct mlx5_create_mkey_mbox_in *in;
2987 struct mlx5_mkey_seg *mkc;
2988 int inlen = sizeof(*in);
2990 mlx5e_get_max_num_channels(mdev) * MLX5_CHANNEL_MAX_NUM_MTTS;
2993 in = mlx5_vzalloc(inlen);
2998 mkc->status = MLX5_MKEY_STATUS_FREE;
2999 mkc->flags = MLX5_PERM_UMR_EN |
3000 MLX5_PERM_LOCAL_READ |
3001 MLX5_PERM_LOCAL_WRITE |
3002 MLX5_ACCESS_MODE_MTT;
3004 mkc->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
3005 mkc->flags_pd = cpu_to_be32(priv->pdn);
3006 mkc->len = cpu_to_be64(npages << PAGE_SHIFT);
3007 mkc->xlt_oct_size = cpu_to_be32(mlx5e_get_mtt_octw(npages));
3008 mkc->log2_page_size = PAGE_SHIFT;
3010 err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen, NULL,
3018 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
3020 struct net_device *netdev;
3021 struct mlx5e_priv *priv;
3022 int nch = mlx5e_get_max_num_channels(mdev);
3025 if (mlx5e_check_required_hca_cap(mdev))
3028 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
3029 nch * MLX5E_MAX_NUM_TC,
3032 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3036 mlx5e_build_netdev_priv(mdev, netdev, nch);
3037 mlx5e_build_netdev(netdev);
3039 netif_carrier_off(netdev);
3041 priv = netdev_priv(netdev);
3043 priv->wq = create_singlethread_workqueue("mlx5e");
3045 goto err_free_netdev;
3047 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false);
3049 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
3050 goto err_destroy_wq;
3053 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3055 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
3056 goto err_unmap_free_uar;
3059 err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
3061 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
3062 goto err_dealloc_pd;
3065 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mkey);
3067 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
3068 goto err_dealloc_transport_domain;
3071 err = mlx5e_create_umr_mkey(priv);
3073 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
3074 goto err_destroy_mkey;
3077 err = mlx5e_create_tises(priv);
3079 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
3080 goto err_destroy_umr_mkey;
3083 err = mlx5e_open_drop_rq(priv);
3085 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
3086 goto err_destroy_tises;
3089 err = mlx5e_create_rqts(priv);
3091 mlx5_core_warn(mdev, "create rqts failed, %d\n", err);
3092 goto err_close_drop_rq;
3095 err = mlx5e_create_tirs(priv);
3097 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
3098 goto err_destroy_rqts;
3101 err = mlx5e_create_flow_steering(priv);
3103 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3104 goto err_destroy_tirs;
3107 mlx5e_create_q_counter(priv);
3109 mlx5e_init_l2_addr(priv);
3111 mlx5e_vxlan_init(priv);
3113 err = mlx5e_tc_init(priv);
3115 goto err_dealloc_q_counters;
3117 #ifdef CONFIG_MLX5_CORE_EN_DCB
3118 mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3121 err = register_netdev(netdev);
3123 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
3124 goto err_tc_cleanup;
3127 if (mlx5e_vxlan_allowed(mdev)) {
3129 vxlan_get_rx_port(netdev);
3133 mlx5e_enable_async_events(priv);
3134 queue_work(priv->wq, &priv->set_rx_mode_work);
3139 mlx5e_tc_cleanup(priv);
3141 err_dealloc_q_counters:
3142 mlx5e_destroy_q_counter(priv);
3143 mlx5e_destroy_flow_steering(priv);
3146 mlx5e_destroy_tirs(priv);
3149 mlx5e_destroy_rqts(priv);
3152 mlx5e_close_drop_rq(priv);
3155 mlx5e_destroy_tises(priv);
3157 err_destroy_umr_mkey:
3158 mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3161 mlx5_core_destroy_mkey(mdev, &priv->mkey);
3163 err_dealloc_transport_domain:
3164 mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
3167 mlx5_core_dealloc_pd(mdev, priv->pdn);
3170 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3173 destroy_workqueue(priv->wq);
3176 free_netdev(netdev);
3181 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
3183 struct mlx5e_priv *priv = vpriv;
3184 struct net_device *netdev = priv->netdev;
3186 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3188 queue_work(priv->wq, &priv->set_rx_mode_work);
3189 mlx5e_disable_async_events(priv);
3190 flush_workqueue(priv->wq);
3191 if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) {
3192 netif_device_detach(netdev);
3193 mutex_lock(&priv->state_lock);
3194 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
3195 mlx5e_close_locked(netdev);
3196 mutex_unlock(&priv->state_lock);
3198 unregister_netdev(netdev);
3201 mlx5e_tc_cleanup(priv);
3202 mlx5e_vxlan_cleanup(priv);
3203 mlx5e_destroy_q_counter(priv);
3204 mlx5e_destroy_flow_steering(priv);
3205 mlx5e_destroy_tirs(priv);
3206 mlx5e_destroy_rqts(priv);
3207 mlx5e_close_drop_rq(priv);
3208 mlx5e_destroy_tises(priv);
3209 mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3210 mlx5_core_destroy_mkey(priv->mdev, &priv->mkey);
3211 mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
3212 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3213 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3214 cancel_delayed_work_sync(&priv->update_stats_work);
3215 destroy_workqueue(priv->wq);
3217 if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state))
3218 free_netdev(netdev);
3221 static void *mlx5e_get_netdev(void *vpriv)
3223 struct mlx5e_priv *priv = vpriv;
3225 return priv->netdev;
3228 static struct mlx5_interface mlx5e_interface = {
3229 .add = mlx5e_create_netdev,
3230 .remove = mlx5e_destroy_netdev,
3231 .event = mlx5e_async_event,
3232 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3233 .get_dev = mlx5e_get_netdev,
3236 void mlx5e_init(void)
3238 mlx5_register_interface(&mlx5e_interface);
3241 void mlx5e_cleanup(void)
3243 mlx5_unregister_interface(&mlx5e_interface);