drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <net/geneve.h>
  38 #include <linux/bpf.h>
  39 #include <linux/if_bridge.h>
  40 #include <linux/filter.h>
  41 #include <net/page_pool.h>
  42 #include <net/xdp_sock_drv.h>
  43 #include "eswitch.h"
  44 #include "en.h"
  45 #include "en/txrx.h"
  46 #include "en_tc.h"
  47 #include "en_rep.h"
  48 #include "en_accel/ipsec.h"
  49 #include "en_accel/en_accel.h"
  50 #include "en_accel/ktls.h"
  51 #include "lib/vxlan.h"
  52 #include "lib/clock.h"
  53 #include "en/port.h"
  54 #include "en/xdp.h"
  55 #include "lib/eq.h"
  56 #include "en/monitor_stats.h"
  57 #include "en/health.h"
  58 #include "en/params.h"
  59 #include "en/xsk/pool.h"
  60 #include "en/xsk/setup.h"
  61 #include "en/xsk/rx.h"
  62 #include "en/xsk/tx.h"
  63 #include "en/hv_vhca_stats.h"
  64 #include "en/devlink.h"
  65 #include "lib/mlx5.h"
  66 #include "en/ptp.h"
  67 #include "qos.h"
  68 #include "en/trap.h"
  69
  70 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  71 {
  72         bool striding_rq_umr, inline_umr;
  73         u16 max_wqe_sz_cap;
  74
  75         striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) && MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  76                           MLX5_CAP_ETH(mdev, reg_umr_sq);
  77         max_wqe_sz_cap = mlx5e_get_max_sq_wqebbs(mdev) * MLX5_SEND_WQE_BB;
  78         inline_umr = max_wqe_sz_cap >= MLX5E_UMR_WQE_INLINE_SZ;
  79         if (!striding_rq_umr)
  80                 return false;
  81         if (!inline_umr) {
  82                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  83                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  84                 return false;
  85         }
  86         return true;
  87 }
  88
  89 void mlx5e_update_carrier(struct mlx5e_priv *priv)
  90 {
  91         struct mlx5_core_dev *mdev = priv->mdev;
  92         u8 port_state;
  93         bool up;
  94
  95         port_state = mlx5_query_vport_state(mdev,
  96                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
  97                                             0);
  98
  99         up = port_state == VPORT_STATE_UP;
 100         if (up == netif_carrier_ok(priv->netdev))
 101                 netif_carrier_event(priv->netdev);
 102         if (up) {
 103                 netdev_info(priv->netdev, "Link up\n");
 104                 netif_carrier_on(priv->netdev);
 105         } else {
 106                 netdev_info(priv->netdev, "Link down\n");
 107                 netif_carrier_off(priv->netdev);
 108         }
 109 }
 110
 111 static void mlx5e_update_carrier_work(struct work_struct *work)
 112 {
 113         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 114                                                update_carrier_work);
 115
 116         mutex_lock(&priv->state_lock);
 117         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 118                 if (priv->profile->update_carrier)
 119                         priv->profile->update_carrier(priv);
 120         mutex_unlock(&priv->state_lock);
 121 }
 122
 123 static void mlx5e_update_stats_work(struct work_struct *work)
 124 {
 125         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 126                                                update_stats_work);
 127
 128         mutex_lock(&priv->state_lock);
 129         priv->profile->update_stats(priv);
 130         mutex_unlock(&priv->state_lock);
 131 }
 132
 133 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
 134 {
 135         if (!priv->profile->update_stats)
 136                 return;
 137
 138         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
 139                 return;
 140
 141         queue_work(priv->wq, &priv->update_stats_work);
 142 }
 143
 144 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
 145 {
 146         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
 147         struct mlx5_eqe   *eqe = data;
 148
 149         if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
 150                 return NOTIFY_DONE;
 151
 152         switch (eqe->sub_type) {
 153         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 154         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 155                 queue_work(priv->wq, &priv->update_carrier_work);
 156                 break;
 157         default:
 158                 return NOTIFY_DONE;
 159         }
 160
 161         return NOTIFY_OK;
 162 }
 163
 164 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 165 {
 166         priv->events_nb.notifier_call = async_event;
 167         mlx5_notifier_register(priv->mdev, &priv->events_nb);
 168 }
 169
 170 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 171 {
 172         mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
 173 }
 174
 175 static int blocking_event(struct notifier_block *nb, unsigned long event, void *data)
 176 {
 177         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, blocking_events_nb);
 178         int err;
 179
 180         switch (event) {
 181         case MLX5_DRIVER_EVENT_TYPE_TRAP:
 182                 err = mlx5e_handle_trap_event(priv, data);
 183                 break;
 184         default:
 185                 netdev_warn(priv->netdev, "Sync event: Unknown event %ld\n", event);
 186                 err = -EINVAL;
 187         }
 188         return err;
 189 }
 190
 191 static void mlx5e_enable_blocking_events(struct mlx5e_priv *priv)
 192 {
 193         priv->blocking_events_nb.notifier_call = blocking_event;
 194         mlx5_blocking_notifier_register(priv->mdev, &priv->blocking_events_nb);
 195 }
 196
 197 static void mlx5e_disable_blocking_events(struct mlx5e_priv *priv)
 198 {
 199         mlx5_blocking_notifier_unregister(priv->mdev, &priv->blocking_events_nb);
 200 }
 201
 202 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 203                                        struct mlx5e_icosq *sq,
 204                                        struct mlx5e_umr_wqe *wqe)
 205 {
 206         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 207         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 208         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 209
 210         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 211                                       ds_cnt);
 212         cseg->umr_mkey  = rq->mkey_be;
 213
 214         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 215         ucseg->xlt_octowords =
 216                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 217         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 218 }
 219
 220 static int mlx5e_rq_shampo_hd_alloc(struct mlx5e_rq *rq, int node)
 221 {
 222         rq->mpwqe.shampo = kvzalloc_node(sizeof(*rq->mpwqe.shampo),
 223                                          GFP_KERNEL, node);
 224         if (!rq->mpwqe.shampo)
 225                 return -ENOMEM;
 226         return 0;
 227 }
 228
 229 static void mlx5e_rq_shampo_hd_free(struct mlx5e_rq *rq)
 230 {
 231         kvfree(rq->mpwqe.shampo);
 232 }
 233
 234 static int mlx5e_rq_shampo_hd_info_alloc(struct mlx5e_rq *rq, int node)
 235 {
 236         struct mlx5e_shampo_hd *shampo = rq->mpwqe.shampo;
 237
 238         shampo->bitmap = bitmap_zalloc_node(shampo->hd_per_wq, GFP_KERNEL,
 239                                             node);
 240         if (!shampo->bitmap)
 241                 return -ENOMEM;
 242
 243         shampo->info = kvzalloc_node(array_size(shampo->hd_per_wq,
 244                                                 sizeof(*shampo->info)),
 245                                      GFP_KERNEL, node);
 246         if (!shampo->info) {
 247                 kvfree(shampo->bitmap);
 248                 return -ENOMEM;
 249         }
 250         return 0;
 251 }
 252
 253 static void mlx5e_rq_shampo_hd_info_free(struct mlx5e_rq *rq)
 254 {
 255         kvfree(rq->mpwqe.shampo->bitmap);
 256         kvfree(rq->mpwqe.shampo->info);
 257 }
 258
 259 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, int node)
 260 {
 261         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 262
 263         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 264                                                   sizeof(*rq->mpwqe.info)),
 265                                        GFP_KERNEL, node);
 266         if (!rq->mpwqe.info)
 267                 return -ENOMEM;
 268
 269         mlx5e_build_umr_wqe(rq, rq->icosq, &rq->mpwqe.umr_wqe);
 270
 271         return 0;
 272 }
 273
 274 static int mlx5e_create_umr_mtt_mkey(struct mlx5_core_dev *mdev,
 275                                      u64 npages, u8 page_shift, u32 *umr_mkey,
 276                                      dma_addr_t filler_addr)
 277 {
 278         struct mlx5_mtt *mtt;
 279         int inlen;
 280         void *mkc;
 281         u32 *in;
 282         int err;
 283         int i;
 284
 285         inlen = MLX5_ST_SZ_BYTES(create_mkey_in) + sizeof(*mtt) * npages;
 286
 287         in = kvzalloc(inlen, GFP_KERNEL);
 288         if (!in)
 289                 return -ENOMEM;
 290
 291         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 292
 293         MLX5_SET(mkc, mkc, free, 1);
 294         MLX5_SET(mkc, mkc, umr_en, 1);
 295         MLX5_SET(mkc, mkc, lw, 1);
 296         MLX5_SET(mkc, mkc, lr, 1);
 297         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 298         mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
 299         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 300         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
 301         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 302         MLX5_SET(mkc, mkc, translations_octword_size,
 303                  MLX5_MTT_OCTW(npages));
 304         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 305         MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
 306                  MLX5_MTT_OCTW(npages));
 307
 308         /* Initialize the mkey with all MTTs pointing to a default
 309          * page (filler_addr). When the channels are activated, UMR
 310          * WQEs will redirect the RX WQEs to the actual memory from
 311          * the RQ's pool, while the gaps (wqe_overflow) remain mapped
 312          * to the default page.
 313          */
 314         mtt = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
 315         for (i = 0 ; i < npages ; i++)
 316                 mtt[i].ptag = cpu_to_be64(filler_addr);
 317
 318         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 319
 320         kvfree(in);
 321         return err;
 322 }
 323
 324 static int mlx5e_create_umr_klm_mkey(struct mlx5_core_dev *mdev,
 325                                      u64 nentries,
 326                                      u32 *umr_mkey)
 327 {
 328         int inlen;
 329         void *mkc;
 330         u32 *in;
 331         int err;
 332
 333         inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 334
 335         in = kvzalloc(inlen, GFP_KERNEL);
 336         if (!in)
 337                 return -ENOMEM;
 338
 339         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 340
 341         MLX5_SET(mkc, mkc, free, 1);
 342         MLX5_SET(mkc, mkc, umr_en, 1);
 343         MLX5_SET(mkc, mkc, lw, 1);
 344         MLX5_SET(mkc, mkc, lr, 1);
 345         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_KLMS);
 346         mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
 347         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 348         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
 349         MLX5_SET(mkc, mkc, translations_octword_size, nentries);
 350         MLX5_SET(mkc, mkc, length64, 1);
 351         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 352
 353         kvfree(in);
 354         return err;
 355 }
 356
 357 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 358 {
 359         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 360
 361         return mlx5e_create_umr_mtt_mkey(mdev, num_mtts, PAGE_SHIFT,
 362                                          &rq->umr_mkey, rq->wqe_overflow.addr);
 363 }
 364
 365 static int mlx5e_create_rq_hd_umr_mkey(struct mlx5_core_dev *mdev,
 366                                        struct mlx5e_rq *rq)
 367 {
 368         u32 max_klm_size = BIT(MLX5_CAP_GEN(mdev, log_max_klm_list_size));
 369
 370         if (max_klm_size < rq->mpwqe.shampo->hd_per_wq) {
 371                 mlx5_core_err(mdev, "max klm list size 0x%x is smaller than shampo header buffer list size 0x%x\n",
 372                               max_klm_size, rq->mpwqe.shampo->hd_per_wq);
 373                 return -EINVAL;
 374         }
 375         return mlx5e_create_umr_klm_mkey(mdev, rq->mpwqe.shampo->hd_per_wq,
 376                                          &rq->mpwqe.shampo->mkey);
 377 }
 378
 379 static u64 mlx5e_get_mpwqe_offset(u16 wqe_ix)
 380 {
 381         return MLX5E_REQUIRED_MTTS(wqe_ix) << PAGE_SHIFT;
 382 }
 383
 384 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 385 {
 386         struct mlx5e_wqe_frag_info next_frag = {};
 387         struct mlx5e_wqe_frag_info *prev = NULL;
 388         int i;
 389
 390         next_frag.di = &rq->wqe.di[0];
 391
 392         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 393                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 394                 struct mlx5e_wqe_frag_info *frag =
 395                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 396                 int f;
 397
 398                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 399                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 400                                 next_frag.di++;
 401                                 next_frag.offset = 0;
 402                                 if (prev)
 403                                         prev->last_in_page = true;
 404                         }
 405                         *frag = next_frag;
 406
 407                         /* prepare next */
 408                         next_frag.offset += frag_info[f].frag_stride;
 409                         prev = frag;
 410                 }
 411         }
 412
 413         if (prev)
 414                 prev->last_in_page = true;
 415 }
 416
 417 int mlx5e_init_di_list(struct mlx5e_rq *rq, int wq_sz, int node)
 418 {
 419         int len = wq_sz << rq->wqe.info.log_num_frags;
 420
 421         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)), GFP_KERNEL, node);
 422         if (!rq->wqe.di)
 423                 return -ENOMEM;
 424
 425         mlx5e_init_frags_partition(rq);
 426
 427         return 0;
 428 }
 429
 430 void mlx5e_free_di_list(struct mlx5e_rq *rq)
 431 {
 432         kvfree(rq->wqe.di);
 433 }
 434
 435 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
 436 {
 437         struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
 438
 439         mlx5e_reporter_rq_cqe_err(rq);
 440 }
 441
 442 static int mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
 443 {
 444         rq->wqe_overflow.page = alloc_page(GFP_KERNEL);
 445         if (!rq->wqe_overflow.page)
 446                 return -ENOMEM;
 447
 448         rq->wqe_overflow.addr = dma_map_page(rq->pdev, rq->wqe_overflow.page, 0,
 449                                              PAGE_SIZE, rq->buff.map_dir);
 450         if (dma_mapping_error(rq->pdev, rq->wqe_overflow.addr)) {
 451                 __free_page(rq->wqe_overflow.page);
 452                 return -ENOMEM;
 453         }
 454         return 0;
 455 }
 456
 457 static void mlx5e_free_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
 458 {
 459          dma_unmap_page(rq->pdev, rq->wqe_overflow.addr, PAGE_SIZE,
 460                         rq->buff.map_dir);
 461          __free_page(rq->wqe_overflow.page);
 462 }
 463
 464 static int mlx5e_init_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
 465                              struct mlx5e_rq *rq)
 466 {
 467         struct mlx5_core_dev *mdev = c->mdev;
 468         int err;
 469
 470         rq->wq_type      = params->rq_wq_type;
 471         rq->pdev         = c->pdev;
 472         rq->netdev       = c->netdev;
 473         rq->priv         = c->priv;
 474         rq->tstamp       = c->tstamp;
 475         rq->clock        = &mdev->clock;
 476         rq->icosq        = &c->icosq;
 477         rq->ix           = c->ix;
 478         rq->mdev         = mdev;
 479         rq->hw_mtu       = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 480         rq->xdpsq        = &c->rq_xdpsq;
 481         rq->stats        = &c->priv->channel_stats[c->ix]->rq;
 482         rq->ptp_cyc2time = mlx5_rq_ts_translator(mdev);
 483         err = mlx5e_rq_set_handlers(rq, params, NULL);
 484         if (err)
 485                 return err;
 486
 487         return xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix, 0);
 488 }
 489
 490 static int mlx5_rq_shampo_alloc(struct mlx5_core_dev *mdev,
 491                                 struct mlx5e_params *params,
 492                                 struct mlx5e_rq_param *rqp,
 493                                 struct mlx5e_rq *rq,
 494                                 u32 *pool_size,
 495                                 int node)
 496 {
 497         void *wqc = MLX5_ADDR_OF(rqc, rqp->rqc, wq);
 498         int wq_size;
 499         int err;
 500
 501         if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
 502                 return 0;
 503         err = mlx5e_rq_shampo_hd_alloc(rq, node);
 504         if (err)
 505                 goto out;
 506         rq->mpwqe.shampo->hd_per_wq =
 507                 mlx5e_shampo_hd_per_wq(mdev, params, rqp);
 508         err = mlx5e_create_rq_hd_umr_mkey(mdev, rq);
 509         if (err)
 510                 goto err_shampo_hd;
 511         err = mlx5e_rq_shampo_hd_info_alloc(rq, node);
 512         if (err)
 513                 goto err_shampo_info;
 514         rq->hw_gro_data = kvzalloc_node(sizeof(*rq->hw_gro_data), GFP_KERNEL, node);
 515         if (!rq->hw_gro_data) {
 516                 err = -ENOMEM;
 517                 goto err_hw_gro_data;
 518         }
 519         rq->mpwqe.shampo->key =
 520                 cpu_to_be32(rq->mpwqe.shampo->mkey);
 521         rq->mpwqe.shampo->hd_per_wqe =
 522                 mlx5e_shampo_hd_per_wqe(mdev, params, rqp);
 523         wq_size = BIT(MLX5_GET(wq, wqc, log_wq_sz));
 524         *pool_size += (rq->mpwqe.shampo->hd_per_wqe * wq_size) /
 525                      MLX5E_SHAMPO_WQ_HEADER_PER_PAGE;
 526         return 0;
 527
 528 err_hw_gro_data:
 529         mlx5e_rq_shampo_hd_info_free(rq);
 530 err_shampo_info:
 531         mlx5_core_destroy_mkey(mdev, rq->mpwqe.shampo->mkey);
 532 err_shampo_hd:
 533         mlx5e_rq_shampo_hd_free(rq);
 534 out:
 535         return err;
 536 }
 537
 538 static void mlx5e_rq_free_shampo(struct mlx5e_rq *rq)
 539 {
 540         if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
 541                 return;
 542
 543         kvfree(rq->hw_gro_data);
 544         mlx5e_rq_shampo_hd_info_free(rq);
 545         mlx5_core_destroy_mkey(rq->mdev, rq->mpwqe.shampo->mkey);
 546         mlx5e_rq_shampo_hd_free(rq);
 547 }
 548
 549 static int mlx5e_alloc_rq(struct mlx5e_params *params,
 550                           struct mlx5e_xsk_param *xsk,
 551                           struct mlx5e_rq_param *rqp,
 552                           int node, struct mlx5e_rq *rq)
 553 {
 554         struct page_pool_params pp_params = { 0 };
 555         struct mlx5_core_dev *mdev = rq->mdev;
 556         void *rqc = rqp->rqc;
 557         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 558         u32 pool_size;
 559         int wq_sz;
 560         int err;
 561         int i;
 562
 563         rqp->wq.db_numa_node = node;
 564         INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
 565
 566         if (params->xdp_prog)
 567                 bpf_prog_inc(params->xdp_prog);
 568         RCU_INIT_POINTER(rq->xdp_prog, params->xdp_prog);
 569
 570         rq->buff.map_dir = params->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 571         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
 572         pool_size = 1 << params->log_rq_mtu_frames;
 573
 574         switch (rq->wq_type) {
 575         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 576                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 577                                         &rq->wq_ctrl);
 578                 if (err)
 579                         goto err_rq_xdp_prog;
 580
 581                 err = mlx5e_alloc_mpwqe_rq_drop_page(rq);
 582                 if (err)
 583                         goto err_rq_wq_destroy;
 584
 585                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 586
 587                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 588
 589                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
 590                         mlx5e_mpwqe_get_log_rq_size(params, xsk);
 591
 592                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
 593                 rq->mpwqe.num_strides =
 594                         BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
 595                 rq->mpwqe.min_wqe_bulk = mlx5e_mpwqe_get_min_wqe_bulk(wq_sz);
 596
 597                 rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz);
 598
 599                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 600                 if (err)
 601                         goto err_rq_drop_page;
 602                 rq->mkey_be = cpu_to_be32(rq->umr_mkey);
 603
 604                 err = mlx5e_rq_alloc_mpwqe_info(rq, node);
 605                 if (err)
 606                         goto err_rq_mkey;
 607
 608                 err = mlx5_rq_shampo_alloc(mdev, params, rqp, rq, &pool_size, node);
 609                 if (err)
 610                         goto err_free_by_rq_type;
 611
 612                 break;
 613         default: /* MLX5_WQ_TYPE_CYCLIC */
 614                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 615                                          &rq->wq_ctrl);
 616                 if (err)
 617                         goto err_rq_xdp_prog;
 618
 619                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 620
 621                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 622
 623                 rq->wqe.info = rqp->frags_info;
 624                 rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride;
 625
 626                 rq->wqe.frags =
 627                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 628                                         (wq_sz << rq->wqe.info.log_num_frags)),
 629                                       GFP_KERNEL, node);
 630                 if (!rq->wqe.frags) {
 631                         err = -ENOMEM;
 632                         goto err_rq_wq_destroy;
 633                 }
 634
 635                 err = mlx5e_init_di_list(rq, wq_sz, node);
 636                 if (err)
 637                         goto err_rq_frags;
 638
 639                 rq->mkey_be = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey);
 640         }
 641
 642         if (xsk) {
 643                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 644                                                  MEM_TYPE_XSK_BUFF_POOL, NULL);
 645                 xsk_pool_set_rxq_info(rq->xsk_pool, &rq->xdp_rxq);
 646         } else {
 647                 /* Create a page_pool and register it with rxq */
 648                 pp_params.order     = 0;
 649                 pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 650                 pp_params.pool_size = pool_size;
 651                 pp_params.nid       = node;
 652                 pp_params.dev       = rq->pdev;
 653                 pp_params.dma_dir   = rq->buff.map_dir;
 654
 655                 /* page_pool can be used even when there is no rq->xdp_prog,
 656                  * given page_pool does not handle DMA mapping there is no
 657                  * required state to clear. And page_pool gracefully handle
 658                  * elevated refcnt.
 659                  */
 660                 rq->page_pool = page_pool_create(&pp_params);
 661                 if (IS_ERR(rq->page_pool)) {
 662                         err = PTR_ERR(rq->page_pool);
 663                         rq->page_pool = NULL;
 664                         goto err_free_shampo;
 665                 }
 666                 if (xdp_rxq_info_is_reg(&rq->xdp_rxq))
 667                         err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 668                                                          MEM_TYPE_PAGE_POOL, rq->page_pool);
 669         }
 670         if (err)
 671                 goto err_free_shampo;
 672
 673         for (i = 0; i < wq_sz; i++) {
 674                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 675                         struct mlx5e_rx_wqe_ll *wqe =
 676                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 677                         u32 byte_count =
 678                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 679                         u64 dma_offset = mlx5e_get_mpwqe_offset(i);
 680                         u16 headroom = test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state) ?
 681                                        0 : rq->buff.headroom;
 682
 683                         wqe->data[0].addr = cpu_to_be64(dma_offset + headroom);
 684                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 685                         wqe->data[0].lkey = rq->mkey_be;
 686                 } else {
 687                         struct mlx5e_rx_wqe_cyc *wqe =
 688                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 689                         int f;
 690
 691                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 692                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 693                                         MLX5_HW_START_PADDING;
 694
 695                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 696                                 wqe->data[f].lkey = rq->mkey_be;
 697                         }
 698                         /* check if num_frags is not a pow of two */
 699                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 700                                 wqe->data[f].byte_count = 0;
 701                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 702                                 wqe->data[f].addr = 0;
 703                         }
 704                 }
 705         }
 706
 707         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 708
 709         switch (params->rx_cq_moderation.cq_period_mode) {
 710         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 711                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 712                 break;
 713         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 714         default:
 715                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 716         }
 717
 718         rq->page_cache.head = 0;
 719         rq->page_cache.tail = 0;
 720
 721         return 0;
 722
 723 err_free_shampo:
 724         mlx5e_rq_free_shampo(rq);
 725 err_free_by_rq_type:
 726         switch (rq->wq_type) {
 727         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 728                 kvfree(rq->mpwqe.info);
 729 err_rq_mkey:
 730                 mlx5_core_destroy_mkey(mdev, rq->umr_mkey);
 731 err_rq_drop_page:
 732                 mlx5e_free_mpwqe_rq_drop_page(rq);
 733                 break;
 734         default: /* MLX5_WQ_TYPE_CYCLIC */
 735                 mlx5e_free_di_list(rq);
 736 err_rq_frags:
 737                 kvfree(rq->wqe.frags);
 738         }
 739 err_rq_wq_destroy:
 740         mlx5_wq_destroy(&rq->wq_ctrl);
 741 err_rq_xdp_prog:
 742         if (params->xdp_prog)
 743                 bpf_prog_put(params->xdp_prog);
 744
 745         return err;
 746 }
 747
 748 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 749 {
 750         struct bpf_prog *old_prog;
 751         int i;
 752
 753         if (xdp_rxq_info_is_reg(&rq->xdp_rxq)) {
 754                 old_prog = rcu_dereference_protected(rq->xdp_prog,
 755                                                      lockdep_is_held(&rq->priv->state_lock));
 756                 if (old_prog)
 757                         bpf_prog_put(old_prog);
 758         }
 759
 760         switch (rq->wq_type) {
 761         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 762                 kvfree(rq->mpwqe.info);
 763                 mlx5_core_destroy_mkey(rq->mdev, rq->umr_mkey);
 764                 mlx5e_free_mpwqe_rq_drop_page(rq);
 765                 mlx5e_rq_free_shampo(rq);
 766                 break;
 767         default: /* MLX5_WQ_TYPE_CYCLIC */
 768                 kvfree(rq->wqe.frags);
 769                 mlx5e_free_di_list(rq);
 770         }
 771
 772         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 773              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 774                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 775
 776                 /* With AF_XDP, page_cache is not used, so this loop is not
 777                  * entered, and it's safe to call mlx5e_page_release_dynamic
 778                  * directly.
 779                  */
 780                 mlx5e_page_release_dynamic(rq, dma_info->page, false);
 781         }
 782
 783         xdp_rxq_info_unreg(&rq->xdp_rxq);
 784         page_pool_destroy(rq->page_pool);
 785         mlx5_wq_destroy(&rq->wq_ctrl);
 786 }
 787
 788 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 789 {
 790         struct mlx5_core_dev *mdev = rq->mdev;
 791         u8 ts_format;
 792         void *in;
 793         void *rqc;
 794         void *wq;
 795         int inlen;
 796         int err;
 797
 798         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 799                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 800         in = kvzalloc(inlen, GFP_KERNEL);
 801         if (!in)
 802                 return -ENOMEM;
 803
 804         ts_format = mlx5_is_real_time_rq(mdev) ?
 805                             MLX5_TIMESTAMP_FORMAT_REAL_TIME :
 806                             MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
 807         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 808         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 809
 810         memcpy(rqc, param->rqc, sizeof(param->rqc));
 811
 812         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 813         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 814         MLX5_SET(rqc,  rqc, ts_format,          ts_format);
 815         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 816                                                 MLX5_ADAPTER_PAGE_SHIFT);
 817         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 818
 819         if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) {
 820                 MLX5_SET(wq, wq, log_headers_buffer_entry_num,
 821                          order_base_2(rq->mpwqe.shampo->hd_per_wq));
 822                 MLX5_SET(wq, wq, headers_mkey, rq->mpwqe.shampo->mkey);
 823         }
 824
 825         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 826                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 827
 828         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 829
 830         kvfree(in);
 831
 832         return err;
 833 }
 834
 835 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
 836 {
 837         struct mlx5_core_dev *mdev = rq->mdev;
 838
 839         void *in;
 840         void *rqc;
 841         int inlen;
 842         int err;
 843
 844         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 845         in = kvzalloc(inlen, GFP_KERNEL);
 846         if (!in)
 847                 return -ENOMEM;
 848
 849         if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY)
 850                 mlx5e_rqwq_reset(rq);
 851
 852         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 853
 854         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 855         MLX5_SET(rqc, rqc, state, next_state);
 856
 857         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 858
 859         kvfree(in);
 860
 861         return err;
 862 }
 863
 864 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 865 {
 866         struct mlx5_core_dev *mdev = rq->mdev;
 867
 868         void *in;
 869         void *rqc;
 870         int inlen;
 871         int err;
 872
 873         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 874         in = kvzalloc(inlen, GFP_KERNEL);
 875         if (!in)
 876                 return -ENOMEM;
 877
 878         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 879
 880         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 881         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 882                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 883         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 884         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 885
 886         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 887
 888         kvfree(in);
 889
 890         return err;
 891 }
 892
 893 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 894 {
 895         struct mlx5_core_dev *mdev = rq->mdev;
 896         void *in;
 897         void *rqc;
 898         int inlen;
 899         int err;
 900
 901         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 902         in = kvzalloc(inlen, GFP_KERNEL);
 903         if (!in)
 904                 return -ENOMEM;
 905
 906         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 907
 908         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 909         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 910                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 911         MLX5_SET(rqc, rqc, vsd, vsd);
 912         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 913
 914         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 915
 916         kvfree(in);
 917
 918         return err;
 919 }
 920
 921 void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 922 {
 923         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 924 }
 925
 926 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 927 {
 928         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 929
 930         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 931
 932         do {
 933                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 934                         return 0;
 935
 936                 msleep(20);
 937         } while (time_before(jiffies, exp_time));
 938
 939         netdev_warn(rq->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 940                     rq->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 941
 942         mlx5e_reporter_rx_timeout(rq);
 943         return -ETIMEDOUT;
 944 }
 945
 946 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq *rq)
 947 {
 948         struct mlx5_wq_ll *wq;
 949         u16 head;
 950         int i;
 951
 952         if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 953                 return;
 954
 955         wq = &rq->mpwqe.wq;
 956         head = wq->head;
 957
 958         /* Outstanding UMR WQEs (in progress) start at wq->head */
 959         for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
 960                 rq->dealloc_wqe(rq, head);
 961                 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
 962         }
 963
 964         if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) {
 965                 u16 len;
 966
 967                 len = (rq->mpwqe.shampo->pi - rq->mpwqe.shampo->ci) &
 968                       (rq->mpwqe.shampo->hd_per_wq - 1);
 969                 mlx5e_shampo_dealloc_hd(rq, len, rq->mpwqe.shampo->ci, false);
 970                 rq->mpwqe.shampo->pi = rq->mpwqe.shampo->ci;
 971         }
 972
 973         rq->mpwqe.actual_wq_head = wq->head;
 974         rq->mpwqe.umr_in_progress = 0;
 975         rq->mpwqe.umr_completed = 0;
 976 }
 977
 978 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 979 {
 980         __be16 wqe_ix_be;
 981         u16 wqe_ix;
 982
 983         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 984                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 985
 986                 mlx5e_free_rx_in_progress_descs(rq);
 987
 988                 while (!mlx5_wq_ll_is_empty(wq)) {
 989                         struct mlx5e_rx_wqe_ll *wqe;
 990
 991                         wqe_ix_be = *wq->tail_next;
 992                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 993                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 994                         rq->dealloc_wqe(rq, wqe_ix);
 995                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 996                                        &wqe->next.next_wqe_index);
 997                 }
 998
 999                 if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
1000                         mlx5e_shampo_dealloc_hd(rq, rq->mpwqe.shampo->hd_per_wq,
1001                                                 0, true);
1002         } else {
1003                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1004
1005                 while (!mlx5_wq_cyc_is_empty(wq)) {
1006                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
1007                         rq->dealloc_wqe(rq, wqe_ix);
1008                         mlx5_wq_cyc_pop(wq);
1009                 }
1010         }
1011
1012 }
1013
1014 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
1015                   struct mlx5e_xsk_param *xsk, int node,
1016                   struct mlx5e_rq *rq)
1017 {
1018         struct mlx5_core_dev *mdev = rq->mdev;
1019         int err;
1020
1021         if (params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO)
1022                 __set_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state);
1023
1024         err = mlx5e_alloc_rq(params, xsk, param, node, rq);
1025         if (err)
1026                 return err;
1027
1028         err = mlx5e_create_rq(rq, param);
1029         if (err)
1030                 goto err_free_rq;
1031
1032         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1033         if (err)
1034                 goto err_destroy_rq;
1035
1036         if (MLX5_CAP_ETH(mdev, cqe_checksum_full))
1037                 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state);
1038
1039         if (params->rx_dim_enabled)
1040                 __set_bit(MLX5E_RQ_STATE_AM, &rq->state);
1041
1042         /* We disable csum_complete when XDP is enabled since
1043          * XDP programs might manipulate packets which will render
1044          * skb->checksum incorrect.
1045          */
1046         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || params->xdp_prog)
1047                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state);
1048
1049         /* For CQE compression on striding RQ, use stride index provided by
1050          * HW if capability is supported.
1051          */
1052         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) &&
1053             MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index))
1054                 __set_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &rq->state);
1055
1056         return 0;
1057
1058 err_destroy_rq:
1059         mlx5e_destroy_rq(rq);
1060 err_free_rq:
1061         mlx5e_free_rq(rq);
1062
1063         return err;
1064 }
1065
1066 void mlx5e_activate_rq(struct mlx5e_rq *rq)
1067 {
1068         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
1069         if (rq->icosq) {
1070                 mlx5e_trigger_irq(rq->icosq);
1071         } else {
1072                 local_bh_disable();
1073                 napi_schedule(rq->cq.napi);
1074                 local_bh_enable();
1075         }
1076 }
1077
1078 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
1079 {
1080         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
1081         synchronize_net(); /* Sync with NAPI to prevent mlx5e_post_rx_wqes. */
1082 }
1083
1084 void mlx5e_close_rq(struct mlx5e_rq *rq)
1085 {
1086         cancel_work_sync(&rq->dim.work);
1087         cancel_work_sync(&rq->recover_work);
1088         mlx5e_destroy_rq(rq);
1089         mlx5e_free_rx_descs(rq);
1090         mlx5e_free_rq(rq);
1091 }
1092
1093 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
1094 {
1095         kvfree(sq->db.xdpi_fifo.xi);
1096         kvfree(sq->db.wqe_info);
1097 }
1098
1099 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
1100 {
1101         struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
1102         int wq_sz        = mlx5_wq_cyc_get_size(&sq->wq);
1103         int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1104         size_t size;
1105
1106         size = array_size(sizeof(*xdpi_fifo->xi), dsegs_per_wq);
1107         xdpi_fifo->xi = kvzalloc_node(size, GFP_KERNEL, numa);
1108         if (!xdpi_fifo->xi)
1109                 return -ENOMEM;
1110
1111         xdpi_fifo->pc   = &sq->xdpi_fifo_pc;
1112         xdpi_fifo->cc   = &sq->xdpi_fifo_cc;
1113         xdpi_fifo->mask = dsegs_per_wq - 1;
1114
1115         return 0;
1116 }
1117
1118 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
1119 {
1120         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1121         size_t size;
1122         int err;
1123
1124         size = array_size(sizeof(*sq->db.wqe_info), wq_sz);
1125         sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1126         if (!sq->db.wqe_info)
1127                 return -ENOMEM;
1128
1129         err = mlx5e_alloc_xdpsq_fifo(sq, numa);
1130         if (err) {
1131                 mlx5e_free_xdpsq_db(sq);
1132                 return err;
1133         }
1134
1135         return 0;
1136 }
1137
1138 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
1139                              struct mlx5e_params *params,
1140                              struct xsk_buff_pool *xsk_pool,
1141                              struct mlx5e_sq_param *param,
1142                              struct mlx5e_xdpsq *sq,
1143                              bool is_redirect)
1144 {
1145         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1146         struct mlx5_core_dev *mdev = c->mdev;
1147         struct mlx5_wq_cyc *wq = &sq->wq;
1148         int err;
1149
1150         sq->pdev      = c->pdev;
1151         sq->mkey_be   = c->mkey_be;
1152         sq->channel   = c;
1153         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1154         sq->min_inline_mode = params->tx_min_inline_mode;
1155         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1156         sq->xsk_pool  = xsk_pool;
1157
1158         sq->stats = sq->xsk_pool ?
1159                 &c->priv->channel_stats[c->ix]->xsksq :
1160                 is_redirect ?
1161                         &c->priv->channel_stats[c->ix]->xdpsq :
1162                         &c->priv->channel_stats[c->ix]->rq_xdpsq;
1163         sq->max_sq_wqebbs = mlx5e_get_max_sq_wqebbs(mdev);
1164         sq->stop_room = MLX5E_STOP_ROOM(sq->max_sq_wqebbs);
1165         sq->max_sq_mpw_wqebbs = mlx5e_get_sw_max_sq_mpw_wqebbs(sq->max_sq_wqebbs);
1166
1167         param->wq.db_numa_node = cpu_to_node(c->cpu);
1168         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1169         if (err)
1170                 return err;
1171         wq->db = &wq->db[MLX5_SND_DBR];
1172
1173         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1174         if (err)
1175                 goto err_sq_wq_destroy;
1176
1177         return 0;
1178
1179 err_sq_wq_destroy:
1180         mlx5_wq_destroy(&sq->wq_ctrl);
1181
1182         return err;
1183 }
1184
1185 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1186 {
1187         mlx5e_free_xdpsq_db(sq);
1188         mlx5_wq_destroy(&sq->wq_ctrl);
1189 }
1190
1191 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1192 {
1193         kvfree(sq->db.wqe_info);
1194 }
1195
1196 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1197 {
1198         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1199         size_t size;
1200
1201         size = array_size(wq_sz, sizeof(*sq->db.wqe_info));
1202         sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1203         if (!sq->db.wqe_info)
1204                 return -ENOMEM;
1205
1206         return 0;
1207 }
1208
1209 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1210 {
1211         struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1212                                               recover_work);
1213
1214         mlx5e_reporter_icosq_cqe_err(sq);
1215 }
1216
1217 static void mlx5e_async_icosq_err_cqe_work(struct work_struct *recover_work)
1218 {
1219         struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1220                                               recover_work);
1221
1222         /* Not implemented yet. */
1223
1224         netdev_warn(sq->channel->netdev, "async_icosq recovery is not implemented\n");
1225 }
1226
1227 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1228                              struct mlx5e_sq_param *param,
1229                              struct mlx5e_icosq *sq,
1230                              work_func_t recover_work_func)
1231 {
1232         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1233         struct mlx5_core_dev *mdev = c->mdev;
1234         struct mlx5_wq_cyc *wq = &sq->wq;
1235         int err;
1236
1237         sq->channel   = c;
1238         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1239         sq->reserved_room = param->stop_room;
1240         sq->max_sq_wqebbs = mlx5e_get_max_sq_wqebbs(mdev);
1241
1242         param->wq.db_numa_node = cpu_to_node(c->cpu);
1243         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1244         if (err)
1245                 return err;
1246         wq->db = &wq->db[MLX5_SND_DBR];
1247
1248         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1249         if (err)
1250                 goto err_sq_wq_destroy;
1251
1252         INIT_WORK(&sq->recover_work, recover_work_func);
1253
1254         return 0;
1255
1256 err_sq_wq_destroy:
1257         mlx5_wq_destroy(&sq->wq_ctrl);
1258
1259         return err;
1260 }
1261
1262 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1263 {
1264         mlx5e_free_icosq_db(sq);
1265         mlx5_wq_destroy(&sq->wq_ctrl);
1266 }
1267
1268 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1269 {
1270         kvfree(sq->db.wqe_info);
1271         kvfree(sq->db.skb_fifo.fifo);
1272         kvfree(sq->db.dma_fifo);
1273 }
1274
1275 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1276 {
1277         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1278         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1279
1280         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1281                                                    sizeof(*sq->db.dma_fifo)),
1282                                         GFP_KERNEL, numa);
1283         sq->db.skb_fifo.fifo = kvzalloc_node(array_size(df_sz,
1284                                                         sizeof(*sq->db.skb_fifo.fifo)),
1285                                         GFP_KERNEL, numa);
1286         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1287                                                    sizeof(*sq->db.wqe_info)),
1288                                         GFP_KERNEL, numa);
1289         if (!sq->db.dma_fifo || !sq->db.skb_fifo.fifo || !sq->db.wqe_info) {
1290                 mlx5e_free_txqsq_db(sq);
1291                 return -ENOMEM;
1292         }
1293
1294         sq->dma_fifo_mask = df_sz - 1;
1295
1296         sq->db.skb_fifo.pc   = &sq->skb_fifo_pc;
1297         sq->db.skb_fifo.cc   = &sq->skb_fifo_cc;
1298         sq->db.skb_fifo.mask = df_sz - 1;
1299
1300         return 0;
1301 }
1302
1303 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1304                              int txq_ix,
1305                              struct mlx5e_params *params,
1306                              struct mlx5e_sq_param *param,
1307                              struct mlx5e_txqsq *sq,
1308                              int tc)
1309 {
1310         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1311         struct mlx5_core_dev *mdev = c->mdev;
1312         struct mlx5_wq_cyc *wq = &sq->wq;
1313         int err;
1314
1315         sq->pdev      = c->pdev;
1316         sq->clock     = &mdev->clock;
1317         sq->mkey_be   = c->mkey_be;
1318         sq->netdev    = c->netdev;
1319         sq->mdev      = c->mdev;
1320         sq->priv      = c->priv;
1321         sq->ch_ix     = c->ix;
1322         sq->txq_ix    = txq_ix;
1323         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1324         sq->min_inline_mode = params->tx_min_inline_mode;
1325         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1326         sq->max_sq_wqebbs = mlx5e_get_max_sq_wqebbs(mdev);
1327         sq->max_sq_mpw_wqebbs = mlx5e_get_sw_max_sq_mpw_wqebbs(sq->max_sq_wqebbs);
1328         INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1329         if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1330                 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1331         if (mlx5_ipsec_device_caps(c->priv->mdev))
1332                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1333         if (param->is_mpw)
1334                 set_bit(MLX5E_SQ_STATE_MPWQE, &sq->state);
1335         sq->stop_room = param->stop_room;
1336         sq->ptp_cyc2time = mlx5_sq_ts_translator(mdev);
1337
1338         param->wq.db_numa_node = cpu_to_node(c->cpu);
1339         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1340         if (err)
1341                 return err;
1342         wq->db    = &wq->db[MLX5_SND_DBR];
1343
1344         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1345         if (err)
1346                 goto err_sq_wq_destroy;
1347
1348         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1349         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1350
1351         return 0;
1352
1353 err_sq_wq_destroy:
1354         mlx5_wq_destroy(&sq->wq_ctrl);
1355
1356         return err;
1357 }
1358
1359 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1360 {
1361         mlx5e_free_txqsq_db(sq);
1362         mlx5_wq_destroy(&sq->wq_ctrl);
1363 }
1364
1365 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1366                            struct mlx5e_sq_param *param,
1367                            struct mlx5e_create_sq_param *csp,
1368                            u32 *sqn)
1369 {
1370         u8 ts_format;
1371         void *in;
1372         void *sqc;
1373         void *wq;
1374         int inlen;
1375         int err;
1376
1377         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1378                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1379         in = kvzalloc(inlen, GFP_KERNEL);
1380         if (!in)
1381                 return -ENOMEM;
1382
1383         ts_format = mlx5_is_real_time_sq(mdev) ?
1384                             MLX5_TIMESTAMP_FORMAT_REAL_TIME :
1385                             MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
1386         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1387         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1388
1389         memcpy(sqc, param->sqc, sizeof(param->sqc));
1390         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1391         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1392         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1393         MLX5_SET(sqc,  sqc, ts_cqe_to_dest_cqn, csp->ts_cqe_to_dest_cqn);
1394         MLX5_SET(sqc,  sqc, ts_format, ts_format);
1395
1396
1397         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1398                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1399
1400         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1401         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1402
1403         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1404         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.hw_objs.bfreg.index);
1405         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1406                                           MLX5_ADAPTER_PAGE_SHIFT);
1407         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1408
1409         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1410                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1411
1412         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1413
1414         kvfree(in);
1415
1416         return err;
1417 }
1418
1419 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1420                     struct mlx5e_modify_sq_param *p)
1421 {
1422         u64 bitmask = 0;
1423         void *in;
1424         void *sqc;
1425         int inlen;
1426         int err;
1427
1428         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1429         in = kvzalloc(inlen, GFP_KERNEL);
1430         if (!in)
1431                 return -ENOMEM;
1432
1433         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1434
1435         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1436         MLX5_SET(sqc, sqc, state, p->next_state);
1437         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1438                 bitmask |= 1;
1439                 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1440         }
1441         if (p->qos_update && p->next_state == MLX5_SQC_STATE_RDY) {
1442                 bitmask |= 1 << 2;
1443                 MLX5_SET(sqc, sqc, qos_queue_group_id, p->qos_queue_group_id);
1444         }
1445         MLX5_SET64(modify_sq_in, in, modify_bitmask, bitmask);
1446
1447         err = mlx5_core_modify_sq(mdev, sqn, in);
1448
1449         kvfree(in);
1450
1451         return err;
1452 }
1453
1454 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1455 {
1456         mlx5_core_destroy_sq(mdev, sqn);
1457 }
1458
1459 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1460                         struct mlx5e_sq_param *param,
1461                         struct mlx5e_create_sq_param *csp,
1462                         u16 qos_queue_group_id,
1463                         u32 *sqn)
1464 {
1465         struct mlx5e_modify_sq_param msp = {0};
1466         int err;
1467
1468         err = mlx5e_create_sq(mdev, param, csp, sqn);
1469         if (err)
1470                 return err;
1471
1472         msp.curr_state = MLX5_SQC_STATE_RST;
1473         msp.next_state = MLX5_SQC_STATE_RDY;
1474         if (qos_queue_group_id) {
1475                 msp.qos_update = true;
1476                 msp.qos_queue_group_id = qos_queue_group_id;
1477         }
1478         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1479         if (err)
1480                 mlx5e_destroy_sq(mdev, *sqn);
1481
1482         return err;
1483 }
1484
1485 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1486                                 struct mlx5e_txqsq *sq, u32 rate);
1487
1488 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1489                      struct mlx5e_params *params, struct mlx5e_sq_param *param,
1490                      struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id,
1491                      struct mlx5e_sq_stats *sq_stats)
1492 {
1493         struct mlx5e_create_sq_param csp = {};
1494         u32 tx_rate;
1495         int err;
1496
1497         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1498         if (err)
1499                 return err;
1500
1501         sq->stats = sq_stats;
1502
1503         csp.tisn            = tisn;
1504         csp.tis_lst_sz      = 1;
1505         csp.cqn             = sq->cq.mcq.cqn;
1506         csp.wq_ctrl         = &sq->wq_ctrl;
1507         csp.min_inline_mode = sq->min_inline_mode;
1508         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, qos_queue_group_id, &sq->sqn);
1509         if (err)
1510                 goto err_free_txqsq;
1511
1512         tx_rate = c->priv->tx_rates[sq->txq_ix];
1513         if (tx_rate)
1514                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1515
1516         if (params->tx_dim_enabled)
1517                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1518
1519         return 0;
1520
1521 err_free_txqsq:
1522         mlx5e_free_txqsq(sq);
1523
1524         return err;
1525 }
1526
1527 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1528 {
1529         sq->txq = netdev_get_tx_queue(sq->netdev, sq->txq_ix);
1530         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1531         netdev_tx_reset_queue(sq->txq);
1532         netif_tx_start_queue(sq->txq);
1533 }
1534
1535 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1536 {
1537         __netif_tx_lock_bh(txq);
1538         netif_tx_stop_queue(txq);
1539         __netif_tx_unlock_bh(txq);
1540 }
1541
1542 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1543 {
1544         struct mlx5_wq_cyc *wq = &sq->wq;
1545
1546         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1547         synchronize_net(); /* Sync with NAPI to prevent netif_tx_wake_queue. */
1548
1549         mlx5e_tx_disable_queue(sq->txq);
1550
1551         /* last doorbell out, godspeed .. */
1552         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1553                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1554                 struct mlx5e_tx_wqe *nop;
1555
1556                 sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) {
1557                         .num_wqebbs = 1,
1558                 };
1559
1560                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1561                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1562         }
1563 }
1564
1565 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1566 {
1567         struct mlx5_core_dev *mdev = sq->mdev;
1568         struct mlx5_rate_limit rl = {0};
1569
1570         cancel_work_sync(&sq->dim.work);
1571         cancel_work_sync(&sq->recover_work);
1572         mlx5e_destroy_sq(mdev, sq->sqn);
1573         if (sq->rate_limit) {
1574                 rl.rate = sq->rate_limit;
1575                 mlx5_rl_remove_rate(mdev, &rl);
1576         }
1577         mlx5e_free_txqsq_descs(sq);
1578         mlx5e_free_txqsq(sq);
1579 }
1580
1581 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1582 {
1583         struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1584                                               recover_work);
1585
1586         mlx5e_reporter_tx_err_cqe(sq);
1587 }
1588
1589 static int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1590                             struct mlx5e_sq_param *param, struct mlx5e_icosq *sq,
1591                             work_func_t recover_work_func)
1592 {
1593         struct mlx5e_create_sq_param csp = {};
1594         int err;
1595
1596         err = mlx5e_alloc_icosq(c, param, sq, recover_work_func);
1597         if (err)
1598                 return err;
1599
1600         csp.cqn             = sq->cq.mcq.cqn;
1601         csp.wq_ctrl         = &sq->wq_ctrl;
1602         csp.min_inline_mode = params->tx_min_inline_mode;
1603         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1604         if (err)
1605                 goto err_free_icosq;
1606
1607         if (param->is_tls) {
1608                 sq->ktls_resync = mlx5e_ktls_rx_resync_create_resp_list();
1609                 if (IS_ERR(sq->ktls_resync)) {
1610                         err = PTR_ERR(sq->ktls_resync);
1611                         goto err_destroy_icosq;
1612                 }
1613         }
1614         return 0;
1615
1616 err_destroy_icosq:
1617         mlx5e_destroy_sq(c->mdev, sq->sqn);
1618 err_free_icosq:
1619         mlx5e_free_icosq(sq);
1620
1621         return err;
1622 }
1623
1624 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1625 {
1626         set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1627 }
1628
1629 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1630 {
1631         clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1632         synchronize_net(); /* Sync with NAPI. */
1633 }
1634
1635 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1636 {
1637         struct mlx5e_channel *c = sq->channel;
1638
1639         if (sq->ktls_resync)
1640                 mlx5e_ktls_rx_resync_destroy_resp_list(sq->ktls_resync);
1641         mlx5e_destroy_sq(c->mdev, sq->sqn);
1642         mlx5e_free_icosq_descs(sq);
1643         mlx5e_free_icosq(sq);
1644 }
1645
1646 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1647                      struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
1648                      struct mlx5e_xdpsq *sq, bool is_redirect)
1649 {
1650         struct mlx5e_create_sq_param csp = {};
1651         int err;
1652
1653         err = mlx5e_alloc_xdpsq(c, params, xsk_pool, param, sq, is_redirect);
1654         if (err)
1655                 return err;
1656
1657         csp.tis_lst_sz      = 1;
1658         csp.tisn            = c->priv->tisn[c->lag_port][0]; /* tc = 0 */
1659         csp.cqn             = sq->cq.mcq.cqn;
1660         csp.wq_ctrl         = &sq->wq_ctrl;
1661         csp.min_inline_mode = sq->min_inline_mode;
1662         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1663
1664         /* Don't enable multi buffer on XDP_REDIRECT SQ, as it's not yet
1665          * supported by upstream, and there is no defined trigger to allow
1666          * transmitting redirected multi-buffer frames.
1667          */
1668         if (param->is_xdp_mb && !is_redirect)
1669                 set_bit(MLX5E_SQ_STATE_XDP_MULTIBUF, &sq->state);
1670
1671         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1672         if (err)
1673                 goto err_free_xdpsq;
1674
1675         mlx5e_set_xmit_fp(sq, param->is_mpw);
1676
1677         if (!param->is_mpw && !test_bit(MLX5E_SQ_STATE_XDP_MULTIBUF, &sq->state)) {
1678                 unsigned int ds_cnt = MLX5E_TX_WQE_EMPTY_DS_COUNT + 1;
1679                 unsigned int inline_hdr_sz = 0;
1680                 int i;
1681
1682                 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1683                         inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1684                         ds_cnt++;
1685                 }
1686
1687                 /* Pre initialize fixed WQE fields */
1688                 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1689                         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1690                         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1691                         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1692                         struct mlx5_wqe_data_seg *dseg;
1693
1694                         sq->db.wqe_info[i] = (struct mlx5e_xdp_wqe_info) {
1695                                 .num_wqebbs = 1,
1696                                 .num_pkts   = 1,
1697                         };
1698
1699                         cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1700                         eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1701
1702                         dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1703                         dseg->lkey = sq->mkey_be;
1704                 }
1705         }
1706
1707         return 0;
1708
1709 err_free_xdpsq:
1710         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1711         mlx5e_free_xdpsq(sq);
1712
1713         return err;
1714 }
1715
1716 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1717 {
1718         struct mlx5e_channel *c = sq->channel;
1719
1720         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1721         synchronize_net(); /* Sync with NAPI. */
1722
1723         mlx5e_destroy_sq(c->mdev, sq->sqn);
1724         mlx5e_free_xdpsq_descs(sq);
1725         mlx5e_free_xdpsq(sq);
1726 }
1727
1728 static int mlx5e_alloc_cq_common(struct mlx5e_priv *priv,
1729                                  struct mlx5e_cq_param *param,
1730                                  struct mlx5e_cq *cq)
1731 {
1732         struct mlx5_core_dev *mdev = priv->mdev;
1733         struct mlx5_core_cq *mcq = &cq->mcq;
1734         int err;
1735         u32 i;
1736
1737         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1738                                &cq->wq_ctrl);
1739         if (err)
1740                 return err;
1741
1742         mcq->cqe_sz     = 64;
1743         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1744         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1745         *mcq->set_ci_db = 0;
1746         *mcq->arm_db    = 0;
1747         mcq->vector     = param->eq_ix;
1748         mcq->comp       = mlx5e_completion_event;
1749         mcq->event      = mlx5e_cq_error_event;
1750
1751         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1752                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1753
1754                 cqe->op_own = 0xf1;
1755         }
1756
1757         cq->mdev = mdev;
1758         cq->netdev = priv->netdev;
1759         cq->priv = priv;
1760
1761         return 0;
1762 }
1763
1764 static int mlx5e_alloc_cq(struct mlx5e_priv *priv,
1765                           struct mlx5e_cq_param *param,
1766                           struct mlx5e_create_cq_param *ccp,
1767                           struct mlx5e_cq *cq)
1768 {
1769         int err;
1770
1771         param->wq.buf_numa_node = ccp->node;
1772         param->wq.db_numa_node  = ccp->node;
1773         param->eq_ix            = ccp->ix;
1774
1775         err = mlx5e_alloc_cq_common(priv, param, cq);
1776
1777         cq->napi     = ccp->napi;
1778         cq->ch_stats = ccp->ch_stats;
1779
1780         return err;
1781 }
1782
1783 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1784 {
1785         mlx5_wq_destroy(&cq->wq_ctrl);
1786 }
1787
1788 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1789 {
1790         u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1791         struct mlx5_core_dev *mdev = cq->mdev;
1792         struct mlx5_core_cq *mcq = &cq->mcq;
1793
1794         void *in;
1795         void *cqc;
1796         int inlen;
1797         int eqn;
1798         int err;
1799
1800         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn);
1801         if (err)
1802                 return err;
1803
1804         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1805                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1806         in = kvzalloc(inlen, GFP_KERNEL);
1807         if (!in)
1808                 return -ENOMEM;
1809
1810         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1811
1812         memcpy(cqc, param->cqc, sizeof(param->cqc));
1813
1814         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1815                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1816
1817         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1818         MLX5_SET(cqc,   cqc, c_eqn_or_apu_element, eqn);
1819         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1820         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1821                                             MLX5_ADAPTER_PAGE_SHIFT);
1822         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1823
1824         err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1825
1826         kvfree(in);
1827
1828         if (err)
1829                 return err;
1830
1831         mlx5e_cq_arm(cq);
1832
1833         return 0;
1834 }
1835
1836 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1837 {
1838         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1839 }
1840
1841 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder,
1842                   struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
1843                   struct mlx5e_cq *cq)
1844 {
1845         struct mlx5_core_dev *mdev = priv->mdev;
1846         int err;
1847
1848         err = mlx5e_alloc_cq(priv, param, ccp, cq);
1849         if (err)
1850                 return err;
1851
1852         err = mlx5e_create_cq(cq, param);
1853         if (err)
1854                 goto err_free_cq;
1855
1856         if (MLX5_CAP_GEN(mdev, cq_moderation))
1857                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1858         return 0;
1859
1860 err_free_cq:
1861         mlx5e_free_cq(cq);
1862
1863         return err;
1864 }
1865
1866 void mlx5e_close_cq(struct mlx5e_cq *cq)
1867 {
1868         mlx5e_destroy_cq(cq);
1869         mlx5e_free_cq(cq);
1870 }
1871
1872 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1873                              struct mlx5e_params *params,
1874                              struct mlx5e_create_cq_param *ccp,
1875                              struct mlx5e_channel_param *cparam)
1876 {
1877         int err;
1878         int tc;
1879
1880         for (tc = 0; tc < c->num_tc; tc++) {
1881                 err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->txq_sq.cqp,
1882                                     ccp, &c->sq[tc].cq);
1883                 if (err)
1884                         goto err_close_tx_cqs;
1885         }
1886
1887         return 0;
1888
1889 err_close_tx_cqs:
1890         for (tc--; tc >= 0; tc--)
1891                 mlx5e_close_cq(&c->sq[tc].cq);
1892
1893         return err;
1894 }
1895
1896 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1897 {
1898         int tc;
1899
1900         for (tc = 0; tc < c->num_tc; tc++)
1901                 mlx5e_close_cq(&c->sq[tc].cq);
1902 }
1903
1904 static int mlx5e_mqprio_txq_to_tc(struct netdev_tc_txq *tc_to_txq, unsigned int txq)
1905 {
1906         int tc;
1907
1908         for (tc = 0; tc < TC_MAX_QUEUE; tc++)
1909                 if (txq - tc_to_txq[tc].offset < tc_to_txq[tc].count)
1910                         return tc;
1911
1912         WARN(1, "Unexpected TCs configuration. No match found for txq %u", txq);
1913         return -ENOENT;
1914 }
1915
1916 static int mlx5e_txq_get_qos_node_hw_id(struct mlx5e_params *params, int txq_ix,
1917                                         u32 *hw_id)
1918 {
1919         int tc;
1920
1921         if (params->mqprio.mode != TC_MQPRIO_MODE_CHANNEL ||
1922             !params->mqprio.channel.rl) {
1923                 *hw_id = 0;
1924                 return 0;
1925         }
1926
1927         tc = mlx5e_mqprio_txq_to_tc(params->mqprio.tc_to_txq, txq_ix);
1928         if (tc < 0)
1929                 return tc;
1930
1931         return mlx5e_mqprio_rl_get_node_hw_id(params->mqprio.channel.rl, tc, hw_id);
1932 }
1933
1934 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1935                           struct mlx5e_params *params,
1936                           struct mlx5e_channel_param *cparam)
1937 {
1938         int err, tc;
1939
1940         for (tc = 0; tc < mlx5e_get_dcb_num_tc(params); tc++) {
1941                 int txq_ix = c->ix + tc * params->num_channels;
1942                 u32 qos_queue_group_id;
1943
1944                 err = mlx5e_txq_get_qos_node_hw_id(params, txq_ix, &qos_queue_group_id);
1945                 if (err)
1946                         goto err_close_sqs;
1947
1948                 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
1949                                        params, &cparam->txq_sq, &c->sq[tc], tc,
1950                                        qos_queue_group_id,
1951                                        &c->priv->channel_stats[c->ix]->sq[tc]);
1952                 if (err)
1953                         goto err_close_sqs;
1954         }
1955
1956         return 0;
1957
1958 err_close_sqs:
1959         for (tc--; tc >= 0; tc--)
1960                 mlx5e_close_txqsq(&c->sq[tc]);
1961
1962         return err;
1963 }
1964
1965 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1966 {
1967         int tc;
1968
1969         for (tc = 0; tc < c->num_tc; tc++)
1970                 mlx5e_close_txqsq(&c->sq[tc]);
1971 }
1972
1973 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1974                                 struct mlx5e_txqsq *sq, u32 rate)
1975 {
1976         struct mlx5e_priv *priv = netdev_priv(dev);
1977         struct mlx5_core_dev *mdev = priv->mdev;
1978         struct mlx5e_modify_sq_param msp = {0};
1979         struct mlx5_rate_limit rl = {0};
1980         u16 rl_index = 0;
1981         int err;
1982
1983         if (rate == sq->rate_limit)
1984                 /* nothing to do */
1985                 return 0;
1986
1987         if (sq->rate_limit) {
1988                 rl.rate = sq->rate_limit;
1989                 /* remove current rl index to free space to next ones */
1990                 mlx5_rl_remove_rate(mdev, &rl);
1991         }
1992
1993         sq->rate_limit = 0;
1994
1995         if (rate) {
1996                 rl.rate = rate;
1997                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1998                 if (err) {
1999                         netdev_err(dev, "Failed configuring rate %u: %d\n",
2000                                    rate, err);
2001                         return err;
2002                 }
2003         }
2004
2005         msp.curr_state = MLX5_SQC_STATE_RDY;
2006         msp.next_state = MLX5_SQC_STATE_RDY;
2007         msp.rl_index   = rl_index;
2008         msp.rl_update  = true;
2009         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
2010         if (err) {
2011                 netdev_err(dev, "Failed configuring rate %u: %d\n",
2012                            rate, err);
2013                 /* remove the rate from the table */
2014                 if (rate)
2015                         mlx5_rl_remove_rate(mdev, &rl);
2016                 return err;
2017         }
2018
2019         sq->rate_limit = rate;
2020         return 0;
2021 }
2022
2023 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
2024 {
2025         struct mlx5e_priv *priv = netdev_priv(dev);
2026         struct mlx5_core_dev *mdev = priv->mdev;
2027         struct mlx5e_txqsq *sq = priv->txq2sq[index];
2028         int err = 0;
2029
2030         if (!mlx5_rl_is_supported(mdev)) {
2031                 netdev_err(dev, "Rate limiting is not supported on this device\n");
2032                 return -EINVAL;
2033         }
2034
2035         /* rate is given in Mb/sec, HW config is in Kb/sec */
2036         rate = rate << 10;
2037
2038         /* Check whether rate in valid range, 0 is always valid */
2039         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
2040                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
2041                 return -ERANGE;
2042         }
2043
2044         mutex_lock(&priv->state_lock);
2045         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
2046                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
2047         if (!err)
2048                 priv->tx_rates[index] = rate;
2049         mutex_unlock(&priv->state_lock);
2050
2051         return err;
2052 }
2053
2054 static int mlx5e_open_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
2055                              struct mlx5e_rq_param *rq_params)
2056 {
2057         int err;
2058
2059         err = mlx5e_init_rxq_rq(c, params, &c->rq);
2060         if (err)
2061                 return err;
2062
2063         return mlx5e_open_rq(params, rq_params, NULL, cpu_to_node(c->cpu), &c->rq);
2064 }
2065
2066 static int mlx5e_open_queues(struct mlx5e_channel *c,
2067                              struct mlx5e_params *params,
2068                              struct mlx5e_channel_param *cparam)
2069 {
2070         struct dim_cq_moder icocq_moder = {0, 0};
2071         struct mlx5e_create_cq_param ccp;
2072         int err;
2073
2074         mlx5e_build_create_cq_param(&ccp, c);
2075
2076         err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->async_icosq.cqp, &ccp,
2077                             &c->async_icosq.cq);
2078         if (err)
2079                 return err;
2080
2081         err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->icosq.cqp, &ccp,
2082                             &c->icosq.cq);
2083         if (err)
2084                 goto err_close_async_icosq_cq;
2085
2086         err = mlx5e_open_tx_cqs(c, params, &ccp, cparam);
2087         if (err)
2088                 goto err_close_icosq_cq;
2089
2090         err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp, &ccp,
2091                             &c->xdpsq.cq);
2092         if (err)
2093                 goto err_close_tx_cqs;
2094
2095         err = mlx5e_open_cq(c->priv, params->rx_cq_moderation, &cparam->rq.cqp, &ccp,
2096                             &c->rq.cq);
2097         if (err)
2098                 goto err_close_xdp_tx_cqs;
2099
2100         err = c->xdp ? mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp,
2101                                      &ccp, &c->rq_xdpsq.cq) : 0;
2102         if (err)
2103                 goto err_close_rx_cq;
2104
2105         spin_lock_init(&c->async_icosq_lock);
2106
2107         err = mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq,
2108                                mlx5e_async_icosq_err_cqe_work);
2109         if (err)
2110                 goto err_close_xdpsq_cq;
2111
2112         mutex_init(&c->icosq_recovery_lock);
2113
2114         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq,
2115                                mlx5e_icosq_err_cqe_work);
2116         if (err)
2117                 goto err_close_async_icosq;
2118
2119         err = mlx5e_open_sqs(c, params, cparam);
2120         if (err)
2121                 goto err_close_icosq;
2122
2123         err = mlx5e_open_rxq_rq(c, params, &cparam->rq);
2124         if (err)
2125                 goto err_close_sqs;
2126
2127         if (c->xdp) {
2128                 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
2129                                        &c->rq_xdpsq, false);
2130                 if (err)
2131                         goto err_close_rq;
2132         }
2133
2134         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
2135         if (err)
2136                 goto err_close_xdp_sq;
2137
2138         return 0;
2139
2140 err_close_xdp_sq:
2141         if (c->xdp)
2142                 mlx5e_close_xdpsq(&c->rq_xdpsq);
2143
2144 err_close_rq:
2145         mlx5e_close_rq(&c->rq);
2146
2147 err_close_sqs:
2148         mlx5e_close_sqs(c);
2149
2150 err_close_icosq:
2151         mlx5e_close_icosq(&c->icosq);
2152
2153 err_close_async_icosq:
2154         mlx5e_close_icosq(&c->async_icosq);
2155
2156 err_close_xdpsq_cq:
2157         if (c->xdp)
2158                 mlx5e_close_cq(&c->rq_xdpsq.cq);
2159
2160 err_close_rx_cq:
2161         mlx5e_close_cq(&c->rq.cq);
2162
2163 err_close_xdp_tx_cqs:
2164         mlx5e_close_cq(&c->xdpsq.cq);
2165
2166 err_close_tx_cqs:
2167         mlx5e_close_tx_cqs(c);
2168
2169 err_close_icosq_cq:
2170         mlx5e_close_cq(&c->icosq.cq);
2171
2172 err_close_async_icosq_cq:
2173         mlx5e_close_cq(&c->async_icosq.cq);
2174
2175         return err;
2176 }
2177
2178 static void mlx5e_close_queues(struct mlx5e_channel *c)
2179 {
2180         mlx5e_close_xdpsq(&c->xdpsq);
2181         if (c->xdp)
2182                 mlx5e_close_xdpsq(&c->rq_xdpsq);
2183         /* The same ICOSQ is used for UMRs for both RQ and XSKRQ. */
2184         cancel_work_sync(&c->icosq.recover_work);
2185         mlx5e_close_rq(&c->rq);
2186         mlx5e_close_sqs(c);
2187         mlx5e_close_icosq(&c->icosq);
2188         mutex_destroy(&c->icosq_recovery_lock);
2189         mlx5e_close_icosq(&c->async_icosq);
2190         if (c->xdp)
2191                 mlx5e_close_cq(&c->rq_xdpsq.cq);
2192         mlx5e_close_cq(&c->rq.cq);
2193         mlx5e_close_cq(&c->xdpsq.cq);
2194         mlx5e_close_tx_cqs(c);
2195         mlx5e_close_cq(&c->icosq.cq);
2196         mlx5e_close_cq(&c->async_icosq.cq);
2197 }
2198
2199 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
2200 {
2201         u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
2202
2203         return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
2204 }
2205
2206 static int mlx5e_channel_stats_alloc(struct mlx5e_priv *priv, int ix, int cpu)
2207 {
2208         if (ix > priv->stats_nch)  {
2209                 netdev_warn(priv->netdev, "Unexpected channel stats index %d > %d\n", ix,
2210                             priv->stats_nch);
2211                 return -EINVAL;
2212         }
2213
2214         if (priv->channel_stats[ix])
2215                 return 0;
2216
2217         /* Asymmetric dynamic memory allocation.
2218          * Freed in mlx5e_priv_arrays_free, not on channel closure.
2219          */
2220         mlx5e_dbg(DRV, priv, "Creating channel stats %d\n", ix);
2221         priv->channel_stats[ix] = kvzalloc_node(sizeof(**priv->channel_stats),
2222                                                 GFP_KERNEL, cpu_to_node(cpu));
2223         if (!priv->channel_stats[ix])
2224                 return -ENOMEM;
2225         priv->stats_nch++;
2226
2227         return 0;
2228 }
2229
2230 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
2231                               struct mlx5e_params *params,
2232                               struct mlx5e_channel_param *cparam,
2233                               struct xsk_buff_pool *xsk_pool,
2234                               struct mlx5e_channel **cp)
2235 {
2236         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
2237         struct net_device *netdev = priv->netdev;
2238         struct mlx5e_xsk_param xsk;
2239         struct mlx5e_channel *c;
2240         unsigned int irq;
2241         int err;
2242
2243         err = mlx5_vector2irqn(priv->mdev, ix, &irq);
2244         if (err)
2245                 return err;
2246
2247         err = mlx5e_channel_stats_alloc(priv, ix, cpu);
2248         if (err)
2249                 return err;
2250
2251         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
2252         if (!c)
2253                 return -ENOMEM;
2254
2255         c->priv     = priv;
2256         c->mdev     = priv->mdev;
2257         c->tstamp   = &priv->tstamp;
2258         c->ix       = ix;
2259         c->cpu      = cpu;
2260         c->pdev     = mlx5_core_dma_dev(priv->mdev);
2261         c->netdev   = priv->netdev;
2262         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.hw_objs.mkey);
2263         c->num_tc   = mlx5e_get_dcb_num_tc(params);
2264         c->xdp      = !!params->xdp_prog;
2265         c->stats    = &priv->channel_stats[ix]->ch;
2266         c->aff_mask = irq_get_effective_affinity_mask(irq);
2267         c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix);
2268
2269         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
2270
2271         err = mlx5e_open_queues(c, params, cparam);
2272         if (unlikely(err))
2273                 goto err_napi_del;
2274
2275         if (xsk_pool) {
2276                 mlx5e_build_xsk_param(xsk_pool, &xsk);
2277                 err = mlx5e_open_xsk(priv, params, &xsk, xsk_pool, c);
2278                 if (unlikely(err))
2279                         goto err_close_queues;
2280         }
2281
2282         *cp = c;
2283
2284         return 0;
2285
2286 err_close_queues:
2287         mlx5e_close_queues(c);
2288
2289 err_napi_del:
2290         netif_napi_del(&c->napi);
2291
2292         kvfree(c);
2293
2294         return err;
2295 }
2296
2297 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2298 {
2299         int tc;
2300
2301         napi_enable(&c->napi);
2302
2303         for (tc = 0; tc < c->num_tc; tc++)
2304                 mlx5e_activate_txqsq(&c->sq[tc]);
2305         mlx5e_activate_icosq(&c->icosq);
2306         mlx5e_activate_icosq(&c->async_icosq);
2307         mlx5e_activate_rq(&c->rq);
2308
2309         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2310                 mlx5e_activate_xsk(c);
2311 }
2312
2313 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2314 {
2315         int tc;
2316
2317         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2318                 mlx5e_deactivate_xsk(c);
2319
2320         mlx5e_deactivate_rq(&c->rq);
2321         mlx5e_deactivate_icosq(&c->async_icosq);
2322         mlx5e_deactivate_icosq(&c->icosq);
2323         for (tc = 0; tc < c->num_tc; tc++)
2324                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2325         mlx5e_qos_deactivate_queues(c);
2326
2327         napi_disable(&c->napi);
2328 }
2329
2330 static void mlx5e_close_channel(struct mlx5e_channel *c)
2331 {
2332         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2333                 mlx5e_close_xsk(c);
2334         mlx5e_close_queues(c);
2335         mlx5e_qos_close_queues(c);
2336         netif_napi_del(&c->napi);
2337
2338         kvfree(c);
2339 }
2340
2341 int mlx5e_open_channels(struct mlx5e_priv *priv,
2342                         struct mlx5e_channels *chs)
2343 {
2344         struct mlx5e_channel_param *cparam;
2345         int err = -ENOMEM;
2346         int i;
2347
2348         chs->num = chs->params.num_channels;
2349
2350         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2351         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2352         if (!chs->c || !cparam)
2353                 goto err_free;
2354
2355         err = mlx5e_build_channel_param(priv->mdev, &chs->params, priv->q_counter, cparam);
2356         if (err)
2357                 goto err_free;
2358
2359         for (i = 0; i < chs->num; i++) {
2360                 struct xsk_buff_pool *xsk_pool = NULL;
2361
2362                 if (chs->params.xdp_prog)
2363                         xsk_pool = mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, i);
2364
2365                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, xsk_pool, &chs->c[i]);
2366                 if (err)
2367                         goto err_close_channels;
2368         }
2369
2370         if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS) || chs->params.ptp_rx) {
2371                 err = mlx5e_ptp_open(priv, &chs->params, chs->c[0]->lag_port, &chs->ptp);
2372                 if (err)
2373                         goto err_close_channels;
2374         }
2375
2376         err = mlx5e_qos_open_queues(priv, chs);
2377         if (err)
2378                 goto err_close_ptp;
2379
2380         mlx5e_health_channels_update(priv);
2381         kvfree(cparam);
2382         return 0;
2383
2384 err_close_ptp:
2385         if (chs->ptp)
2386                 mlx5e_ptp_close(chs->ptp);
2387
2388 err_close_channels:
2389         for (i--; i >= 0; i--)
2390                 mlx5e_close_channel(chs->c[i]);
2391
2392 err_free:
2393         kfree(chs->c);
2394         kvfree(cparam);
2395         chs->num = 0;
2396         return err;
2397 }
2398
2399 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2400 {
2401         int i;
2402
2403         for (i = 0; i < chs->num; i++)
2404                 mlx5e_activate_channel(chs->c[i]);
2405
2406         if (chs->ptp)
2407                 mlx5e_ptp_activate_channel(chs->ptp);
2408 }
2409
2410 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2411
2412 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2413 {
2414         int err = 0;
2415         int i;
2416
2417         for (i = 0; i < chs->num; i++) {
2418                 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2419
2420                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2421
2422                 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2423                  * doesn't provide any Fill Ring entries at the setup stage.
2424                  */
2425         }
2426
2427         return err ? -ETIMEDOUT : 0;
2428 }
2429
2430 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2431 {
2432         int i;
2433
2434         if (chs->ptp)
2435                 mlx5e_ptp_deactivate_channel(chs->ptp);
2436
2437         for (i = 0; i < chs->num; i++)
2438                 mlx5e_deactivate_channel(chs->c[i]);
2439 }
2440
2441 void mlx5e_close_channels(struct mlx5e_channels *chs)
2442 {
2443         int i;
2444
2445         if (chs->ptp) {
2446                 mlx5e_ptp_close(chs->ptp);
2447                 chs->ptp = NULL;
2448         }
2449         for (i = 0; i < chs->num; i++)
2450                 mlx5e_close_channel(chs->c[i]);
2451
2452         kfree(chs->c);
2453         chs->num = 0;
2454 }
2455
2456 static int mlx5e_modify_tirs_packet_merge(struct mlx5e_priv *priv)
2457 {
2458         struct mlx5e_rx_res *res = priv->rx_res;
2459
2460         return mlx5e_rx_res_packet_merge_set_param(res, &priv->channels.params.packet_merge);
2461 }
2462
2463 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_packet_merge);
2464
2465 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2466                          struct mlx5e_params *params, u16 mtu)
2467 {
2468         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2469         int err;
2470
2471         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2472         if (err)
2473                 return err;
2474
2475         /* Update vport context MTU */
2476         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2477         return 0;
2478 }
2479
2480 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2481                             struct mlx5e_params *params, u16 *mtu)
2482 {
2483         u16 hw_mtu = 0;
2484         int err;
2485
2486         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2487         if (err || !hw_mtu) /* fallback to port oper mtu */
2488                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2489
2490         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2491 }
2492
2493 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2494 {
2495         struct mlx5e_params *params = &priv->channels.params;
2496         struct net_device *netdev = priv->netdev;
2497         struct mlx5_core_dev *mdev = priv->mdev;
2498         u16 mtu;
2499         int err;
2500
2501         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2502         if (err)
2503                 return err;
2504
2505         mlx5e_query_mtu(mdev, params, &mtu);
2506         if (mtu != params->sw_mtu)
2507                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2508                             __func__, mtu, params->sw_mtu);
2509
2510         params->sw_mtu = mtu;
2511         return 0;
2512 }
2513
2514 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu);
2515
2516 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2517 {
2518         struct mlx5e_params *params = &priv->channels.params;
2519         struct net_device *netdev   = priv->netdev;
2520         struct mlx5_core_dev *mdev  = priv->mdev;
2521         u16 max_mtu;
2522
2523         /* MTU range: 68 - hw-specific max */
2524         netdev->min_mtu = ETH_MIN_MTU;
2525
2526         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2527         netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2528                                 ETH_MAX_MTU);
2529 }
2530
2531 static int mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc,
2532                                 struct netdev_tc_txq *tc_to_txq)
2533 {
2534         int tc, err;
2535
2536         netdev_reset_tc(netdev);
2537
2538         if (ntc == 1)
2539                 return 0;
2540
2541         err = netdev_set_num_tc(netdev, ntc);
2542         if (err) {
2543                 netdev_WARN(netdev, "netdev_set_num_tc failed (%d), ntc = %d\n", err, ntc);
2544                 return err;
2545         }
2546
2547         for (tc = 0; tc < ntc; tc++) {
2548                 u16 count, offset;
2549
2550                 count = tc_to_txq[tc].count;
2551                 offset = tc_to_txq[tc].offset;
2552                 netdev_set_tc_queue(netdev, tc, count, offset);
2553         }
2554
2555         return 0;
2556 }
2557
2558 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv)
2559 {
2560         int qos_queues, nch, ntc, num_txqs, err;
2561
2562         qos_queues = mlx5e_qos_cur_leaf_nodes(priv);
2563
2564         nch = priv->channels.params.num_channels;
2565         ntc = mlx5e_get_dcb_num_tc(&priv->channels.params);
2566         num_txqs = nch * ntc + qos_queues;
2567         if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_TX_PORT_TS))
2568                 num_txqs += ntc;
2569
2570         mlx5e_dbg(DRV, priv, "Setting num_txqs %d\n", num_txqs);
2571         err = netif_set_real_num_tx_queues(priv->netdev, num_txqs);
2572         if (err)
2573                 netdev_warn(priv->netdev, "netif_set_real_num_tx_queues failed, %d\n", err);
2574
2575         return err;
2576 }
2577
2578 static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv)
2579 {
2580         struct netdev_tc_txq old_tc_to_txq[TC_MAX_QUEUE], *tc_to_txq;
2581         struct net_device *netdev = priv->netdev;
2582         int old_num_txqs, old_ntc;
2583         int num_rxqs, nch, ntc;
2584         int err;
2585         int i;
2586
2587         old_num_txqs = netdev->real_num_tx_queues;
2588         old_ntc = netdev->num_tc ? : 1;
2589         for (i = 0; i < ARRAY_SIZE(old_tc_to_txq); i++)
2590                 old_tc_to_txq[i] = netdev->tc_to_txq[i];
2591
2592         nch = priv->channels.params.num_channels;
2593         ntc = priv->channels.params.mqprio.num_tc;
2594         num_rxqs = nch * priv->profile->rq_groups;
2595         tc_to_txq = priv->channels.params.mqprio.tc_to_txq;
2596
2597         err = mlx5e_netdev_set_tcs(netdev, nch, ntc, tc_to_txq);
2598         if (err)
2599                 goto err_out;
2600         err = mlx5e_update_tx_netdev_queues(priv);
2601         if (err)
2602                 goto err_tcs;
2603         err = netif_set_real_num_rx_queues(netdev, num_rxqs);
2604         if (err) {
2605                 netdev_warn(netdev, "netif_set_real_num_rx_queues failed, %d\n", err);
2606                 goto err_txqs;
2607         }
2608         if (priv->mqprio_rl != priv->channels.params.mqprio.channel.rl) {
2609                 if (priv->mqprio_rl) {
2610                         mlx5e_mqprio_rl_cleanup(priv->mqprio_rl);
2611                         mlx5e_mqprio_rl_free(priv->mqprio_rl);
2612                 }
2613                 priv->mqprio_rl = priv->channels.params.mqprio.channel.rl;
2614         }
2615
2616         return 0;
2617
2618 err_txqs:
2619         /* netif_set_real_num_rx_queues could fail only when nch increased. Only
2620          * one of nch and ntc is changed in this function. That means, the call
2621          * to netif_set_real_num_tx_queues below should not fail, because it
2622          * decreases the number of TX queues.
2623          */
2624         WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs));
2625
2626 err_tcs:
2627         WARN_ON_ONCE(mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc,
2628                                           old_tc_to_txq));
2629 err_out:
2630         return err;
2631 }
2632
2633 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_update_netdev_queues);
2634
2635 static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv,
2636                                            struct mlx5e_params *params)
2637 {
2638         struct mlx5_core_dev *mdev = priv->mdev;
2639         int num_comp_vectors, ix, irq;
2640
2641         num_comp_vectors = mlx5_comp_vectors_count(mdev);
2642
2643         for (ix = 0; ix < params->num_channels; ix++) {
2644                 cpumask_clear(priv->scratchpad.cpumask);
2645
2646                 for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) {
2647                         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(mdev, irq));
2648
2649                         cpumask_set_cpu(cpu, priv->scratchpad.cpumask);
2650                 }
2651
2652                 netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix);
2653         }
2654 }
2655
2656 static int mlx5e_num_channels_changed(struct mlx5e_priv *priv)
2657 {
2658         u16 count = priv->channels.params.num_channels;
2659         int err;
2660
2661         err = mlx5e_update_netdev_queues(priv);
2662         if (err)
2663                 return err;
2664
2665         mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params);
2666
2667         /* This function may be called on attach, before priv->rx_res is created. */
2668         if (!netif_is_rxfh_configured(priv->netdev) && priv->rx_res)
2669                 mlx5e_rx_res_rss_set_indir_uniform(priv->rx_res, count);
2670
2671         return 0;
2672 }
2673
2674 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed);
2675
2676 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv)
2677 {
2678         int i, ch, tc, num_tc;
2679
2680         ch = priv->channels.num;
2681         num_tc = mlx5e_get_dcb_num_tc(&priv->channels.params);
2682
2683         for (i = 0; i < ch; i++) {
2684                 for (tc = 0; tc < num_tc; tc++) {
2685                         struct mlx5e_channel *c = priv->channels.c[i];
2686                         struct mlx5e_txqsq *sq = &c->sq[tc];
2687
2688                         priv->txq2sq[sq->txq_ix] = sq;
2689                 }
2690         }
2691
2692         if (!priv->channels.ptp)
2693                 goto out;
2694
2695         if (!test_bit(MLX5E_PTP_STATE_TX, priv->channels.ptp->state))
2696                 goto out;
2697
2698         for (tc = 0; tc < num_tc; tc++) {
2699                 struct mlx5e_ptp *c = priv->channels.ptp;
2700                 struct mlx5e_txqsq *sq = &c->ptpsq[tc].txqsq;
2701
2702                 priv->txq2sq[sq->txq_ix] = sq;
2703         }
2704
2705 out:
2706         /* Make the change to txq2sq visible before the queue is started.
2707          * As mlx5e_xmit runs under a spinlock, there is an implicit ACQUIRE,
2708          * which pairs with this barrier.
2709          */
2710         smp_wmb();
2711 }
2712
2713 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2714 {
2715         mlx5e_build_txq_maps(priv);
2716         mlx5e_activate_channels(&priv->channels);
2717         mlx5e_qos_activate_queues(priv);
2718         mlx5e_xdp_tx_enable(priv);
2719
2720         /* dev_watchdog() wants all TX queues to be started when the carrier is
2721          * OK, including the ones in range real_num_tx_queues..num_tx_queues-1.
2722          * Make it happy to avoid TX timeout false alarms.
2723          */
2724         netif_tx_start_all_queues(priv->netdev);
2725
2726         if (mlx5e_is_vport_rep(priv))
2727                 mlx5e_add_sqs_fwd_rules(priv);
2728
2729         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2730
2731         if (priv->rx_res)
2732                 mlx5e_rx_res_channels_activate(priv->rx_res, &priv->channels);
2733 }
2734
2735 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2736 {
2737         if (priv->rx_res)
2738                 mlx5e_rx_res_channels_deactivate(priv->rx_res);
2739
2740         if (mlx5e_is_vport_rep(priv))
2741                 mlx5e_remove_sqs_fwd_rules(priv);
2742
2743         /* The results of ndo_select_queue are unreliable, while netdev config
2744          * is being changed (real_num_tx_queues, num_tc). Stop all queues to
2745          * prevent ndo_start_xmit from being called, so that it can assume that
2746          * the selected queue is always valid.
2747          */
2748         netif_tx_disable(priv->netdev);
2749
2750         mlx5e_xdp_tx_disable(priv);
2751         mlx5e_deactivate_channels(&priv->channels);
2752 }
2753
2754 static int mlx5e_switch_priv_params(struct mlx5e_priv *priv,
2755                                     struct mlx5e_params *new_params,
2756                                     mlx5e_fp_preactivate preactivate,
2757                                     void *context)
2758 {
2759         struct mlx5e_params old_params;
2760
2761         old_params = priv->channels.params;
2762         priv->channels.params = *new_params;
2763
2764         if (preactivate) {
2765                 int err;
2766
2767                 err = preactivate(priv, context);
2768                 if (err) {
2769                         priv->channels.params = old_params;
2770                         return err;
2771                 }
2772         }
2773
2774         return 0;
2775 }
2776
2777 static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2778                                       struct mlx5e_channels *new_chs,
2779                                       mlx5e_fp_preactivate preactivate,
2780                                       void *context)
2781 {
2782         struct net_device *netdev = priv->netdev;
2783         struct mlx5e_channels old_chs;
2784         int carrier_ok;
2785         int err = 0;
2786
2787         carrier_ok = netif_carrier_ok(netdev);
2788         netif_carrier_off(netdev);
2789
2790         mlx5e_deactivate_priv_channels(priv);
2791
2792         old_chs = priv->channels;
2793         priv->channels = *new_chs;
2794
2795         /* New channels are ready to roll, call the preactivate hook if needed
2796          * to modify HW settings or update kernel parameters.
2797          */
2798         if (preactivate) {
2799                 err = preactivate(priv, context);
2800                 if (err) {
2801                         priv->channels = old_chs;
2802                         goto out;
2803                 }
2804         }
2805
2806         mlx5e_close_channels(&old_chs);
2807         priv->profile->update_rx(priv);
2808
2809         mlx5e_selq_apply(&priv->selq);
2810 out:
2811         mlx5e_activate_priv_channels(priv);
2812
2813         /* return carrier back if needed */
2814         if (carrier_ok)
2815                 netif_carrier_on(netdev);
2816
2817         return err;
2818 }
2819
2820 int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
2821                              struct mlx5e_params *params,
2822                              mlx5e_fp_preactivate preactivate,
2823                              void *context, bool reset)
2824 {
2825         struct mlx5e_channels new_chs = {};
2826         int err;
2827
2828         reset &= test_bit(MLX5E_STATE_OPENED, &priv->state);
2829         if (!reset)
2830                 return mlx5e_switch_priv_params(priv, params, preactivate, context);
2831
2832         new_chs.params = *params;
2833
2834         mlx5e_selq_prepare(&priv->selq, &new_chs.params, !!priv->htb.maj_id);
2835
2836         err = mlx5e_open_channels(priv, &new_chs);
2837         if (err)
2838                 goto err_cancel_selq;
2839
2840         err = mlx5e_switch_priv_channels(priv, &new_chs, preactivate, context);
2841         if (err)
2842                 goto err_close;
2843
2844         return 0;
2845
2846 err_close:
2847         mlx5e_close_channels(&new_chs);
2848
2849 err_cancel_selq:
2850         mlx5e_selq_cancel(&priv->selq);
2851         return err;
2852 }
2853
2854 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
2855 {
2856         return mlx5e_safe_switch_params(priv, &priv->channels.params, NULL, NULL, true);
2857 }
2858
2859 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2860 {
2861         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2862         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2863 }
2864
2865 static void mlx5e_modify_admin_state(struct mlx5_core_dev *mdev,
2866                                      enum mlx5_port_status state)
2867 {
2868         struct mlx5_eswitch *esw = mdev->priv.eswitch;
2869         int vport_admin_state;
2870
2871         mlx5_set_port_admin_status(mdev, state);
2872
2873         if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS ||
2874             !MLX5_CAP_GEN(mdev, uplink_follow))
2875                 return;
2876
2877         if (state == MLX5_PORT_UP)
2878                 vport_admin_state = MLX5_VPORT_ADMIN_STATE_AUTO;
2879         else
2880                 vport_admin_state = MLX5_VPORT_ADMIN_STATE_DOWN;
2881
2882         mlx5_eswitch_set_vport_state(esw, MLX5_VPORT_UPLINK, vport_admin_state);
2883 }
2884
2885 int mlx5e_open_locked(struct net_device *netdev)
2886 {
2887         struct mlx5e_priv *priv = netdev_priv(netdev);
2888         int err;
2889
2890         mlx5e_selq_prepare(&priv->selq, &priv->channels.params, !!priv->htb.maj_id);
2891
2892         set_bit(MLX5E_STATE_OPENED, &priv->state);
2893
2894         err = mlx5e_open_channels(priv, &priv->channels);
2895         if (err)
2896                 goto err_clear_state_opened_flag;
2897
2898         priv->profile->update_rx(priv);
2899         mlx5e_selq_apply(&priv->selq);
2900         mlx5e_activate_priv_channels(priv);
2901         mlx5e_apply_traps(priv, true);
2902         if (priv->profile->update_carrier)
2903                 priv->profile->update_carrier(priv);
2904
2905         mlx5e_queue_update_stats(priv);
2906         return 0;
2907
2908 err_clear_state_opened_flag:
2909         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2910         mlx5e_selq_cancel(&priv->selq);
2911         return err;
2912 }
2913
2914 int mlx5e_open(struct net_device *netdev)
2915 {
2916         struct mlx5e_priv *priv = netdev_priv(netdev);
2917         int err;
2918
2919         mutex_lock(&priv->state_lock);
2920         err = mlx5e_open_locked(netdev);
2921         if (!err)
2922                 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_UP);
2923         mutex_unlock(&priv->state_lock);
2924
2925         return err;
2926 }
2927
2928 int mlx5e_close_locked(struct net_device *netdev)
2929 {
2930         struct mlx5e_priv *priv = netdev_priv(netdev);
2931
2932         /* May already be CLOSED in case a previous configuration operation
2933          * (e.g RX/TX queue size change) that involves close&open failed.
2934          */
2935         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2936                 return 0;
2937
2938         mlx5e_apply_traps(priv, false);
2939         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2940
2941         netif_carrier_off(priv->netdev);
2942         mlx5e_deactivate_priv_channels(priv);
2943         mlx5e_close_channels(&priv->channels);
2944
2945         return 0;
2946 }
2947
2948 int mlx5e_close(struct net_device *netdev)
2949 {
2950         struct mlx5e_priv *priv = netdev_priv(netdev);
2951         int err;
2952
2953         if (!netif_device_present(netdev))
2954                 return -ENODEV;
2955
2956         mutex_lock(&priv->state_lock);
2957         mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_DOWN);
2958         err = mlx5e_close_locked(netdev);
2959         mutex_unlock(&priv->state_lock);
2960
2961         return err;
2962 }
2963
2964 static void mlx5e_free_drop_rq(struct mlx5e_rq *rq)
2965 {
2966         mlx5_wq_destroy(&rq->wq_ctrl);
2967 }
2968
2969 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2970                                struct mlx5e_rq *rq,
2971                                struct mlx5e_rq_param *param)
2972 {
2973         void *rqc = param->rqc;
2974         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2975         int err;
2976
2977         param->wq.db_numa_node = param->wq.buf_numa_node;
2978
2979         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
2980                                  &rq->wq_ctrl);
2981         if (err)
2982                 return err;
2983
2984         /* Mark as unused given "Drop-RQ" packets never reach XDP */
2985         xdp_rxq_info_unused(&rq->xdp_rxq);
2986
2987         rq->mdev = mdev;
2988
2989         return 0;
2990 }
2991
2992 static int mlx5e_alloc_drop_cq(struct mlx5e_priv *priv,
2993                                struct mlx5e_cq *cq,
2994                                struct mlx5e_cq_param *param)
2995 {
2996         struct mlx5_core_dev *mdev = priv->mdev;
2997
2998         param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
2999         param->wq.db_numa_node  = dev_to_node(mlx5_core_dma_dev(mdev));
3000
3001         return mlx5e_alloc_cq_common(priv, param, cq);
3002 }
3003
3004 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3005                        struct mlx5e_rq *drop_rq)
3006 {
3007         struct mlx5_core_dev *mdev = priv->mdev;
3008         struct mlx5e_cq_param cq_param = {};
3009         struct mlx5e_rq_param rq_param = {};
3010         struct mlx5e_cq *cq = &drop_rq->cq;
3011         int err;
3012
3013         mlx5e_build_drop_rq_param(mdev, priv->drop_rq_q_counter, &rq_param);
3014
3015         err = mlx5e_alloc_drop_cq(priv, cq, &cq_param);
3016         if (err)
3017                 return err;
3018
3019         err = mlx5e_create_cq(cq, &cq_param);
3020         if (err)
3021                 goto err_free_cq;
3022
3023         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3024         if (err)
3025                 goto err_destroy_cq;
3026
3027         err = mlx5e_create_rq(drop_rq, &rq_param);
3028         if (err)
3029                 goto err_free_rq;
3030
3031         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3032         if (err)
3033                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3034
3035         return 0;
3036
3037 err_free_rq:
3038         mlx5e_free_drop_rq(drop_rq);
3039
3040 err_destroy_cq:
3041         mlx5e_destroy_cq(cq);
3042
3043 err_free_cq:
3044         mlx5e_free_cq(cq);
3045
3046         return err;
3047 }
3048
3049 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3050 {
3051         mlx5e_destroy_rq(drop_rq);
3052         mlx5e_free_drop_rq(drop_rq);
3053         mlx5e_destroy_cq(&drop_rq->cq);
3054         mlx5e_free_cq(&drop_rq->cq);
3055 }
3056
3057 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
3058 {
3059         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3060
3061         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.hw_objs.td.tdn);
3062
3063         if (MLX5_GET(tisc, tisc, tls_en))
3064                 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.hw_objs.pdn);
3065
3066         if (mlx5_lag_is_lacp_owner(mdev))
3067                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3068
3069         return mlx5_core_create_tis(mdev, in, tisn);
3070 }
3071
3072 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3073 {
3074         mlx5_core_destroy_tis(mdev, tisn);
3075 }
3076
3077 void mlx5e_destroy_tises(struct mlx5e_priv *priv)
3078 {
3079         int tc, i;
3080
3081         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++)
3082                 for (tc = 0; tc < priv->profile->max_tc; tc++)
3083                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3084 }
3085
3086 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
3087 {
3088         return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
3089 }
3090
3091 int mlx5e_create_tises(struct mlx5e_priv *priv)
3092 {
3093         int tc, i;
3094         int err;
3095
3096         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) {
3097                 for (tc = 0; tc < priv->profile->max_tc; tc++) {
3098                         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
3099                         void *tisc;
3100
3101                         tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3102
3103                         MLX5_SET(tisc, tisc, prio, tc << 1);
3104
3105                         if (mlx5e_lag_should_assign_affinity(priv->mdev))
3106                                 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
3107
3108                         err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]);
3109                         if (err)
3110                                 goto err_close_tises;
3111                 }
3112         }
3113
3114         return 0;
3115
3116 err_close_tises:
3117         for (; i >= 0; i--) {
3118                 for (tc--; tc >= 0; tc--)
3119                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3120                 tc = priv->profile->max_tc;
3121         }
3122
3123         return err;
3124 }
3125
3126 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3127 {
3128         mlx5e_destroy_tises(priv);
3129 }
3130
3131 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3132 {
3133         int err = 0;
3134         int i;
3135
3136         for (i = 0; i < chs->num; i++) {
3137                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3138                 if (err)
3139                         return err;
3140         }
3141
3142         return 0;
3143 }
3144
3145 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3146 {
3147         int err;
3148         int i;
3149
3150         for (i = 0; i < chs->num; i++) {
3151                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3152                 if (err)
3153                         return err;
3154         }
3155         if (chs->ptp && test_bit(MLX5E_PTP_STATE_RX, chs->ptp->state))
3156                 return mlx5e_modify_rq_vsd(&chs->ptp->rq, vsd);
3157
3158         return 0;
3159 }
3160
3161 static void mlx5e_mqprio_build_default_tc_to_txq(struct netdev_tc_txq *tc_to_txq,
3162                                                  int ntc, int nch)
3163 {
3164         int tc;
3165
3166         memset(tc_to_txq, 0, sizeof(*tc_to_txq) * TC_MAX_QUEUE);
3167
3168         /* Map netdev TCs to offset 0.
3169          * We have our own UP to TXQ mapping for DCB mode of QoS
3170          */
3171         for (tc = 0; tc < ntc; tc++) {
3172                 tc_to_txq[tc] = (struct netdev_tc_txq) {
3173                         .count = nch,
3174                         .offset = 0,
3175                 };
3176         }
3177 }
3178
3179 static void mlx5e_mqprio_build_tc_to_txq(struct netdev_tc_txq *tc_to_txq,
3180                                          struct tc_mqprio_qopt *qopt)
3181 {
3182         int tc;
3183
3184         for (tc = 0; tc < TC_MAX_QUEUE; tc++) {
3185                 tc_to_txq[tc] = (struct netdev_tc_txq) {
3186                         .count = qopt->count[tc],
3187                         .offset = qopt->offset[tc],
3188                 };
3189         }
3190 }
3191
3192 static void mlx5e_params_mqprio_dcb_set(struct mlx5e_params *params, u8 num_tc)
3193 {
3194         params->mqprio.mode = TC_MQPRIO_MODE_DCB;
3195         params->mqprio.num_tc = num_tc;
3196         params->mqprio.channel.rl = NULL;
3197         mlx5e_mqprio_build_default_tc_to_txq(params->mqprio.tc_to_txq, num_tc,
3198                                              params->num_channels);
3199 }
3200
3201 static void mlx5e_params_mqprio_channel_set(struct mlx5e_params *params,
3202                                             struct tc_mqprio_qopt *qopt,
3203                                             struct mlx5e_mqprio_rl *rl)
3204 {
3205         params->mqprio.mode = TC_MQPRIO_MODE_CHANNEL;
3206         params->mqprio.num_tc = qopt->num_tc;
3207         params->mqprio.channel.rl = rl;
3208         mlx5e_mqprio_build_tc_to_txq(params->mqprio.tc_to_txq, qopt);
3209 }
3210
3211 static void mlx5e_params_mqprio_reset(struct mlx5e_params *params)
3212 {
3213         mlx5e_params_mqprio_dcb_set(params, 1);
3214 }
3215
3216 static int mlx5e_setup_tc_mqprio_dcb(struct mlx5e_priv *priv,
3217                                      struct tc_mqprio_qopt *mqprio)
3218 {
3219         struct mlx5e_params new_params;
3220         u8 tc = mqprio->num_tc;
3221         int err;
3222
3223         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3224
3225         if (tc && tc != MLX5E_MAX_NUM_TC)
3226                 return -EINVAL;
3227
3228         new_params = priv->channels.params;
3229         mlx5e_params_mqprio_dcb_set(&new_params, tc ? tc : 1);
3230
3231         err = mlx5e_safe_switch_params(priv, &new_params,
3232                                        mlx5e_num_channels_changed_ctx, NULL, true);
3233
3234         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3235                                     mlx5e_get_dcb_num_tc(&priv->channels.params));
3236         return err;
3237 }
3238
3239 static int mlx5e_mqprio_channel_validate(struct mlx5e_priv *priv,
3240                                          struct tc_mqprio_qopt_offload *mqprio)
3241 {
3242         struct net_device *netdev = priv->netdev;
3243         struct mlx5e_ptp *ptp_channel;
3244         int agg_count = 0;
3245         int i;
3246
3247         ptp_channel = priv->channels.ptp;
3248         if (ptp_channel && test_bit(MLX5E_PTP_STATE_TX, ptp_channel->state)) {
3249                 netdev_err(netdev,
3250                            "Cannot activate MQPRIO mode channel since it conflicts with TX port TS\n");
3251                 return -EINVAL;
3252         }
3253
3254         if (mqprio->qopt.offset[0] != 0 || mqprio->qopt.num_tc < 1 ||
3255             mqprio->qopt.num_tc > MLX5E_MAX_NUM_MQPRIO_CH_TC)
3256                 return -EINVAL;
3257
3258         for (i = 0; i < mqprio->qopt.num_tc; i++) {
3259                 if (!mqprio->qopt.count[i]) {
3260                         netdev_err(netdev, "Zero size for queue-group (%d) is not supported\n", i);
3261                         return -EINVAL;
3262                 }
3263                 if (mqprio->min_rate[i]) {
3264                         netdev_err(netdev, "Min tx rate is not supported\n");
3265                         return -EINVAL;
3266                 }
3267
3268                 if (mqprio->max_rate[i]) {
3269                         int err;
3270
3271                         err = mlx5e_qos_bytes_rate_check(priv->mdev, mqprio->max_rate[i]);
3272                         if (err)
3273                                 return err;
3274                 }
3275
3276                 if (mqprio->qopt.offset[i] != agg_count) {
3277                         netdev_err(netdev, "Discontinuous queues config is not supported\n");
3278                         return -EINVAL;
3279                 }
3280                 agg_count += mqprio->qopt.count[i];
3281         }
3282
3283         if (priv->channels.params.num_channels != agg_count) {
3284                 netdev_err(netdev, "Num of queues (%d) does not match available (%d)\n",
3285                            agg_count, priv->channels.params.num_channels);
3286                 return -EINVAL;
3287         }
3288
3289         return 0;
3290 }
3291
3292 static bool mlx5e_mqprio_rate_limit(struct tc_mqprio_qopt_offload *mqprio)
3293 {
3294         int tc;
3295
3296         for (tc = 0; tc < mqprio->qopt.num_tc; tc++)
3297                 if (mqprio->max_rate[tc])
3298                         return true;
3299         return false;
3300 }
3301
3302 static int mlx5e_setup_tc_mqprio_channel(struct mlx5e_priv *priv,
3303                                          struct tc_mqprio_qopt_offload *mqprio)
3304 {
3305         mlx5e_fp_preactivate preactivate;
3306         struct mlx5e_params new_params;
3307         struct mlx5e_mqprio_rl *rl;
3308         bool nch_changed;
3309         int err;
3310
3311         err = mlx5e_mqprio_channel_validate(priv, mqprio);
3312         if (err)
3313                 return err;
3314
3315         rl = NULL;
3316         if (mlx5e_mqprio_rate_limit(mqprio)) {
3317                 rl = mlx5e_mqprio_rl_alloc();
3318                 if (!rl)
3319                         return -ENOMEM;
3320                 err = mlx5e_mqprio_rl_init(rl, priv->mdev, mqprio->qopt.num_tc,
3321                                            mqprio->max_rate);
3322                 if (err) {
3323                         mlx5e_mqprio_rl_free(rl);
3324                         return err;
3325                 }
3326         }
3327
3328         new_params = priv->channels.params;
3329         mlx5e_params_mqprio_channel_set(&new_params, &mqprio->qopt, rl);
3330
3331         nch_changed = mlx5e_get_dcb_num_tc(&priv->channels.params) > 1;
3332         preactivate = nch_changed ? mlx5e_num_channels_changed_ctx :
3333                 mlx5e_update_netdev_queues_ctx;
3334         err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, true);
3335         if (err && rl) {
3336                 mlx5e_mqprio_rl_cleanup(rl);
3337                 mlx5e_mqprio_rl_free(rl);
3338         }
3339
3340         return err;
3341 }
3342
3343 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3344                                  struct tc_mqprio_qopt_offload *mqprio)
3345 {
3346         /* MQPRIO is another toplevel qdisc that can't be attached
3347          * simultaneously with the offloaded HTB.
3348          */
3349         if (WARN_ON(priv->htb.maj_id))
3350                 return -EINVAL;
3351
3352         switch (mqprio->mode) {
3353         case TC_MQPRIO_MODE_DCB:
3354                 return mlx5e_setup_tc_mqprio_dcb(priv, &mqprio->qopt);
3355         case TC_MQPRIO_MODE_CHANNEL:
3356                 return mlx5e_setup_tc_mqprio_channel(priv, mqprio);
3357         default:
3358                 return -EOPNOTSUPP;
3359         }
3360 }
3361
3362 static int mlx5e_setup_tc_htb(struct mlx5e_priv *priv, struct tc_htb_qopt_offload *htb)
3363 {
3364         int res;
3365
3366         switch (htb->command) {
3367         case TC_HTB_CREATE:
3368                 return mlx5e_htb_root_add(priv, htb->parent_classid, htb->classid,
3369                                           htb->extack);
3370         case TC_HTB_DESTROY:
3371                 return mlx5e_htb_root_del(priv);
3372         case TC_HTB_LEAF_ALLOC_QUEUE:
3373                 res = mlx5e_htb_leaf_alloc_queue(priv, htb->classid, htb->parent_classid,
3374                                                  htb->rate, htb->ceil, htb->extack);
3375                 if (res < 0)
3376                         return res;
3377                 htb->qid = res;
3378                 return 0;
3379         case TC_HTB_LEAF_TO_INNER:
3380                 return mlx5e_htb_leaf_to_inner(priv, htb->parent_classid, htb->classid,
3381                                                htb->rate, htb->ceil, htb->extack);
3382         case TC_HTB_LEAF_DEL:
3383                 return mlx5e_htb_leaf_del(priv, &htb->classid, htb->extack);
3384         case TC_HTB_LEAF_DEL_LAST:
3385         case TC_HTB_LEAF_DEL_LAST_FORCE:
3386                 return mlx5e_htb_leaf_del_last(priv, htb->classid,
3387                                                htb->command == TC_HTB_LEAF_DEL_LAST_FORCE,
3388                                                htb->extack);
3389         case TC_HTB_NODE_MODIFY:
3390                 return mlx5e_htb_node_modify(priv, htb->classid, htb->rate, htb->ceil,
3391                                              htb->extack);
3392         case TC_HTB_LEAF_QUERY_QUEUE:
3393                 res = mlx5e_get_txq_by_classid(priv, htb->classid);
3394                 if (res < 0)
3395                         return res;
3396                 htb->qid = res;
3397                 return 0;
3398         default:
3399                 return -EOPNOTSUPP;
3400         }
3401 }
3402
3403 static LIST_HEAD(mlx5e_block_cb_list);
3404
3405 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3406                           void *type_data)
3407 {
3408         struct mlx5e_priv *priv = netdev_priv(dev);
3409         bool tc_unbind = false;
3410         int err;
3411
3412         if (type == TC_SETUP_BLOCK &&
3413             ((struct flow_block_offload *)type_data)->command == FLOW_BLOCK_UNBIND)
3414                 tc_unbind = true;
3415
3416         if (!netif_device_present(dev) && !tc_unbind)
3417                 return -ENODEV;
3418
3419         switch (type) {
3420         case TC_SETUP_BLOCK: {
3421                 struct flow_block_offload *f = type_data;
3422
3423                 f->unlocked_driver_cb = true;
3424                 return flow_block_cb_setup_simple(type_data,
3425                                                   &mlx5e_block_cb_list,
3426                                                   mlx5e_setup_tc_block_cb,
3427                                                   priv, priv, true);
3428         }
3429         case TC_SETUP_QDISC_MQPRIO:
3430                 mutex_lock(&priv->state_lock);
3431                 err = mlx5e_setup_tc_mqprio(priv, type_data);
3432                 mutex_unlock(&priv->state_lock);
3433                 return err;
3434         case TC_SETUP_QDISC_HTB:
3435                 mutex_lock(&priv->state_lock);
3436                 err = mlx5e_setup_tc_htb(priv, type_data);
3437                 mutex_unlock(&priv->state_lock);
3438                 return err;
3439         default:
3440                 return -EOPNOTSUPP;
3441         }
3442 }
3443
3444 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3445 {
3446         int i;
3447
3448         for (i = 0; i < priv->stats_nch; i++) {
3449                 struct mlx5e_channel_stats *channel_stats = priv->channel_stats[i];
3450                 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3451                 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3452                 int j;
3453
3454                 s->rx_packets   += rq_stats->packets + xskrq_stats->packets;
3455                 s->rx_bytes     += rq_stats->bytes + xskrq_stats->bytes;
3456                 s->multicast    += rq_stats->mcast_packets + xskrq_stats->mcast_packets;
3457
3458                 for (j = 0; j < priv->max_opened_tc; j++) {
3459                         struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3460
3461                         s->tx_packets    += sq_stats->packets;
3462                         s->tx_bytes      += sq_stats->bytes;
3463                         s->tx_dropped    += sq_stats->dropped;
3464                 }
3465         }
3466         if (priv->tx_ptp_opened) {
3467                 for (i = 0; i < priv->max_opened_tc; i++) {
3468                         struct mlx5e_sq_stats *sq_stats = &priv->ptp_stats.sq[i];
3469
3470                         s->tx_packets    += sq_stats->packets;
3471                         s->tx_bytes      += sq_stats->bytes;
3472                         s->tx_dropped    += sq_stats->dropped;
3473                 }
3474         }
3475         if (priv->rx_ptp_opened) {
3476                 struct mlx5e_rq_stats *rq_stats = &priv->ptp_stats.rq;
3477
3478                 s->rx_packets   += rq_stats->packets;
3479                 s->rx_bytes     += rq_stats->bytes;
3480                 s->multicast    += rq_stats->mcast_packets;
3481         }
3482 }
3483
3484 void
3485 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3486 {
3487         struct mlx5e_priv *priv = netdev_priv(dev);
3488         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3489
3490         if (!netif_device_present(dev))
3491                 return;
3492
3493         /* In switchdev mode, monitor counters doesn't monitor
3494          * rx/tx stats of 802_3. The update stats mechanism
3495          * should keep the 802_3 layout counters updated
3496          */
3497         if (!mlx5e_monitor_counter_supported(priv) ||
3498             mlx5e_is_uplink_rep(priv)) {
3499                 /* update HW stats in background for next time */
3500                 mlx5e_queue_update_stats(priv);
3501         }
3502
3503         if (mlx5e_is_uplink_rep(priv)) {
3504                 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3505
3506                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3507                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3508                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3509                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3510
3511                 /* vport multicast also counts packets that are dropped due to steering
3512                  * or rx out of buffer
3513                  */
3514                 stats->multicast = VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3515         } else {
3516                 mlx5e_fold_sw_stats64(priv, stats);
3517         }
3518
3519         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3520
3521         stats->rx_length_errors =
3522                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3523                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3524                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3525         stats->rx_crc_errors =
3526                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3527         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3528         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3529         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3530                            stats->rx_frame_errors;
3531         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3532 }
3533
3534 static void mlx5e_nic_set_rx_mode(struct mlx5e_priv *priv)
3535 {
3536         if (mlx5e_is_uplink_rep(priv))
3537                 return; /* no rx mode for uplink rep */
3538
3539         queue_work(priv->wq, &priv->set_rx_mode_work);
3540 }
3541
3542 static void mlx5e_set_rx_mode(struct net_device *dev)
3543 {
3544         struct mlx5e_priv *priv = netdev_priv(dev);
3545
3546         mlx5e_nic_set_rx_mode(priv);
3547 }
3548
3549 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3550 {
3551         struct mlx5e_priv *priv = netdev_priv(netdev);
3552         struct sockaddr *saddr = addr;
3553
3554         if (!is_valid_ether_addr(saddr->sa_data))
3555                 return -EADDRNOTAVAIL;
3556
3557         netif_addr_lock_bh(netdev);
3558         eth_hw_addr_set(netdev, saddr->sa_data);
3559         netif_addr_unlock_bh(netdev);
3560
3561         mlx5e_nic_set_rx_mode(priv);
3562
3563         return 0;
3564 }
3565
3566 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3567         do {                                            \
3568                 if (enable)                             \
3569                         *features |= feature;           \
3570                 else                                    \
3571                         *features &= ~feature;          \
3572         } while (0)
3573
3574 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3575
3576 static int set_feature_lro(struct net_device *netdev, bool enable)
3577 {
3578         struct mlx5e_priv *priv = netdev_priv(netdev);
3579         struct mlx5_core_dev *mdev = priv->mdev;
3580         struct mlx5e_params *cur_params;
3581         struct mlx5e_params new_params;
3582         bool reset = true;
3583         int err = 0;
3584
3585         mutex_lock(&priv->state_lock);
3586
3587         if (enable && priv->xsk.refcnt) {
3588                 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%u XSKs are active)\n",
3589                             priv->xsk.refcnt);
3590                 err = -EINVAL;
3591                 goto out;
3592         }
3593
3594         cur_params = &priv->channels.params;
3595         if (enable && !MLX5E_GET_PFLAG(cur_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3596                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3597                 err = -EINVAL;
3598                 goto out;
3599         }
3600
3601         new_params = *cur_params;
3602
3603         if (enable)
3604                 new_params.packet_merge.type = MLX5E_PACKET_MERGE_LRO;
3605         else if (new_params.packet_merge.type == MLX5E_PACKET_MERGE_LRO)
3606                 new_params.packet_merge.type = MLX5E_PACKET_MERGE_NONE;
3607         else
3608                 goto out;
3609
3610         if (!(cur_params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO &&
3611               new_params.packet_merge.type == MLX5E_PACKET_MERGE_LRO)) {
3612                 if (cur_params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3613                         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, cur_params, NULL) ==
3614                             mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_params, NULL))
3615                                 reset = false;
3616                 }
3617         }
3618
3619         err = mlx5e_safe_switch_params(priv, &new_params,
3620                                        mlx5e_modify_tirs_packet_merge_ctx, NULL, reset);
3621 out:
3622         mutex_unlock(&priv->state_lock);
3623         return err;
3624 }
3625
3626 static int set_feature_hw_gro(struct net_device *netdev, bool enable)
3627 {
3628         struct mlx5e_priv *priv = netdev_priv(netdev);
3629         struct mlx5e_params new_params;
3630         bool reset = true;
3631         int err = 0;
3632
3633         mutex_lock(&priv->state_lock);
3634         new_params = priv->channels.params;
3635
3636         if (enable) {
3637                 new_params.packet_merge.type = MLX5E_PACKET_MERGE_SHAMPO;
3638                 new_params.packet_merge.shampo.match_criteria_type =
3639                         MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED;
3640                 new_params.packet_merge.shampo.alignment_granularity =
3641                         MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE;
3642         } else if (new_params.packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) {
3643                 new_params.packet_merge.type = MLX5E_PACKET_MERGE_NONE;
3644         } else {
3645                 goto out;
3646         }
3647
3648         err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
3649 out:
3650         mutex_unlock(&priv->state_lock);
3651         return err;
3652 }
3653
3654 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3655 {
3656         struct mlx5e_priv *priv = netdev_priv(netdev);
3657
3658         if (enable)
3659                 mlx5e_enable_cvlan_filter(priv);
3660         else
3661                 mlx5e_disable_cvlan_filter(priv);
3662
3663         return 0;
3664 }
3665
3666 static int set_feature_hw_tc(struct net_device *netdev, bool enable)
3667 {
3668         struct mlx5e_priv *priv = netdev_priv(netdev);
3669
3670 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3671         if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) {
3672                 netdev_err(netdev,
3673                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3674                 return -EINVAL;
3675         }
3676 #endif
3677
3678         if (!enable && priv->htb.maj_id) {
3679                 netdev_err(netdev, "Active HTB offload, can't turn hw_tc_offload off\n");
3680                 return -EINVAL;
3681         }
3682
3683         return 0;
3684 }
3685
3686 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3687 {
3688         struct mlx5e_priv *priv = netdev_priv(netdev);
3689         struct mlx5_core_dev *mdev = priv->mdev;
3690
3691         return mlx5_set_port_fcs(mdev, !enable);
3692 }
3693
3694 static int mlx5e_set_rx_port_ts(struct mlx5_core_dev *mdev, bool enable)
3695 {
3696         u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {};
3697         bool supported, curr_state;
3698         int err;
3699
3700         if (!MLX5_CAP_GEN(mdev, ports_check))
3701                 return 0;
3702
3703         err = mlx5_query_ports_check(mdev, in, sizeof(in));
3704         if (err)
3705                 return err;
3706
3707         supported = MLX5_GET(pcmr_reg, in, rx_ts_over_crc_cap);
3708         curr_state = MLX5_GET(pcmr_reg, in, rx_ts_over_crc);
3709
3710         if (!supported || enable == curr_state)
3711                 return 0;
3712
3713         MLX5_SET(pcmr_reg, in, local_port, 1);
3714         MLX5_SET(pcmr_reg, in, rx_ts_over_crc, enable);
3715
3716         return mlx5_set_ports_check(mdev, in, sizeof(in));
3717 }
3718
3719 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3720 {
3721         struct mlx5e_priv *priv = netdev_priv(netdev);
3722         struct mlx5e_channels *chs = &priv->channels;
3723         struct mlx5_core_dev *mdev = priv->mdev;
3724         int err;
3725
3726         mutex_lock(&priv->state_lock);
3727
3728         if (enable) {
3729                 err = mlx5e_set_rx_port_ts(mdev, false);
3730                 if (err)
3731                         goto out;
3732
3733                 chs->params.scatter_fcs_en = true;
3734                 err = mlx5e_modify_channels_scatter_fcs(chs, true);
3735                 if (err) {
3736                         chs->params.scatter_fcs_en = false;
3737                         mlx5e_set_rx_port_ts(mdev, true);
3738                 }
3739         } else {
3740                 chs->params.scatter_fcs_en = false;
3741                 err = mlx5e_modify_channels_scatter_fcs(chs, false);
3742                 if (err) {
3743                         chs->params.scatter_fcs_en = true;
3744                         goto out;
3745                 }
3746                 err = mlx5e_set_rx_port_ts(mdev, true);
3747                 if (err) {
3748                         mlx5_core_warn(mdev, "Failed to set RX port timestamp %d\n", err);
3749                         err = 0;
3750                 }
3751         }
3752
3753 out:
3754         mutex_unlock(&priv->state_lock);
3755         return err;
3756 }
3757
3758 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3759 {
3760         struct mlx5e_priv *priv = netdev_priv(netdev);
3761         int err = 0;
3762
3763         mutex_lock(&priv->state_lock);
3764
3765         priv->channels.params.vlan_strip_disable = !enable;
3766         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3767                 goto unlock;
3768
3769         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3770         if (err)
3771                 priv->channels.params.vlan_strip_disable = enable;
3772
3773 unlock:
3774         mutex_unlock(&priv->state_lock);
3775
3776         return err;
3777 }
3778
3779 #ifdef CONFIG_MLX5_EN_ARFS
3780 static int set_feature_arfs(struct net_device *netdev, bool enable)
3781 {
3782         struct mlx5e_priv *priv = netdev_priv(netdev);
3783         int err;
3784
3785         if (enable)
3786                 err = mlx5e_arfs_enable(priv);
3787         else
3788                 err = mlx5e_arfs_disable(priv);
3789
3790         return err;
3791 }
3792 #endif
3793
3794 static int mlx5e_handle_feature(struct net_device *netdev,
3795                                 netdev_features_t *features,
3796                                 netdev_features_t feature,
3797                                 mlx5e_feature_handler feature_handler)
3798 {
3799         netdev_features_t changes = *features ^ netdev->features;
3800         bool enable = !!(*features & feature);
3801         int err;
3802
3803         if (!(changes & feature))
3804                 return 0;
3805
3806         err = feature_handler(netdev, enable);
3807         if (err) {
3808                 MLX5E_SET_FEATURE(features, feature, !enable);
3809                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3810                            enable ? "Enable" : "Disable", &feature, err);
3811                 return err;
3812         }
3813
3814         return 0;
3815 }
3816
3817 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3818 {
3819         netdev_features_t oper_features = features;
3820         int err = 0;
3821
3822 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3823         mlx5e_handle_feature(netdev, &oper_features, feature, handler)
3824
3825         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3826         err |= MLX5E_HANDLE_FEATURE(NETIF_F_GRO_HW, set_feature_hw_gro);
3827         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3828                                     set_feature_cvlan_filter);
3829         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_hw_tc);
3830         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3831         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3832         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3833 #ifdef CONFIG_MLX5_EN_ARFS
3834         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3835 #endif
3836         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TLS_RX, mlx5e_ktls_set_feature_rx);
3837
3838         if (err) {
3839                 netdev->features = oper_features;
3840                 return -EINVAL;
3841         }
3842
3843         return 0;
3844 }
3845
3846 static netdev_features_t mlx5e_fix_uplink_rep_features(struct net_device *netdev,
3847                                                        netdev_features_t features)
3848 {
3849         features &= ~NETIF_F_HW_TLS_RX;
3850         if (netdev->features & NETIF_F_HW_TLS_RX)
3851                 netdev_warn(netdev, "Disabling hw_tls_rx, not supported in switchdev mode\n");
3852
3853         features &= ~NETIF_F_HW_TLS_TX;
3854         if (netdev->features & NETIF_F_HW_TLS_TX)
3855                 netdev_warn(netdev, "Disabling hw_tls_tx, not supported in switchdev mode\n");
3856
3857         features &= ~NETIF_F_NTUPLE;
3858         if (netdev->features & NETIF_F_NTUPLE)
3859                 netdev_warn(netdev, "Disabling ntuple, not supported in switchdev mode\n");
3860
3861         features &= ~NETIF_F_GRO_HW;
3862         if (netdev->features & NETIF_F_GRO_HW)
3863                 netdev_warn(netdev, "Disabling HW_GRO, not supported in switchdev mode\n");
3864
3865         return features;
3866 }
3867
3868 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3869                                             netdev_features_t features)
3870 {
3871         struct mlx5e_priv *priv = netdev_priv(netdev);
3872         struct mlx5e_params *params;
3873
3874         mutex_lock(&priv->state_lock);
3875         params = &priv->channels.params;
3876         if (!priv->fs.vlan ||
3877             !bitmap_empty(mlx5e_vlan_get_active_svlans(priv->fs.vlan), VLAN_N_VID)) {
3878                 /* HW strips the outer C-tag header, this is a problem
3879                  * for S-tag traffic.
3880                  */
3881                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3882                 if (!params->vlan_strip_disable)
3883                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3884         }
3885
3886         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3887                 if (features & NETIF_F_LRO) {
3888                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3889                         features &= ~NETIF_F_LRO;
3890                 }
3891                 if (features & NETIF_F_GRO_HW) {
3892                         netdev_warn(netdev, "Disabling HW-GRO, not supported in legacy RQ\n");
3893                         features &= ~NETIF_F_GRO_HW;
3894                 }
3895         }
3896
3897         if (params->xdp_prog) {
3898                 if (features & NETIF_F_LRO) {
3899                         netdev_warn(netdev, "LRO is incompatible with XDP\n");
3900                         features &= ~NETIF_F_LRO;
3901                 }
3902                 if (features & NETIF_F_GRO_HW) {
3903                         netdev_warn(netdev, "HW GRO is incompatible with XDP\n");
3904                         features &= ~NETIF_F_GRO_HW;
3905                 }
3906         }
3907
3908         if (priv->xsk.refcnt) {
3909                 if (features & NETIF_F_GRO_HW) {
3910                         netdev_warn(netdev, "HW GRO is incompatible with AF_XDP (%u XSKs are active)\n",
3911                                     priv->xsk.refcnt);
3912                         features &= ~NETIF_F_GRO_HW;
3913                 }
3914         }
3915
3916         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3917                 features &= ~NETIF_F_RXHASH;
3918                 if (netdev->features & NETIF_F_RXHASH)
3919                         netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3920
3921                 if (features & NETIF_F_GRO_HW) {
3922                         netdev_warn(netdev, "Disabling HW-GRO, not supported when CQE compress is active\n");
3923                         features &= ~NETIF_F_GRO_HW;
3924                 }
3925         }
3926
3927         if (mlx5e_is_uplink_rep(priv))
3928                 features = mlx5e_fix_uplink_rep_features(netdev, features);
3929
3930         mutex_unlock(&priv->state_lock);
3931
3932         return features;
3933 }
3934
3935 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
3936                                    struct mlx5e_channels *chs,
3937                                    struct mlx5e_params *new_params,
3938                                    struct mlx5_core_dev *mdev)
3939 {
3940         u16 ix;
3941
3942         for (ix = 0; ix < chs->params.num_channels; ix++) {
3943                 struct xsk_buff_pool *xsk_pool =
3944                         mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, ix);
3945                 struct mlx5e_xsk_param xsk;
3946
3947                 if (!xsk_pool)
3948                         continue;
3949
3950                 mlx5e_build_xsk_param(xsk_pool, &xsk);
3951
3952                 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
3953                         u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
3954                         int max_mtu_frame, max_mtu_page, max_mtu;
3955
3956                         /* Two criteria must be met:
3957                          * 1. HW MTU + all headrooms <= XSK frame size.
3958                          * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
3959                          */
3960                         max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
3961                         max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
3962                         max_mtu = min(max_mtu_frame, max_mtu_page);
3963
3964                         netdev_err(netdev, "MTU %d is too big for an XSK running on channel %u. Try MTU <= %d\n",
3965                                    new_params->sw_mtu, ix, max_mtu);
3966                         return false;
3967                 }
3968         }
3969
3970         return true;
3971 }
3972
3973 static bool mlx5e_params_validate_xdp(struct net_device *netdev, struct mlx5e_params *params)
3974 {
3975         bool is_linear;
3976
3977         /* No XSK params: AF_XDP can't be enabled yet at the point of setting
3978          * the XDP program.
3979          */
3980         is_linear = mlx5e_rx_is_linear_skb(params, NULL);
3981
3982         if (!is_linear && params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3983                 netdev_warn(netdev, "XDP is not allowed with striding RQ and MTU(%d) > %d\n",
3984                             params->sw_mtu,
3985                             mlx5e_xdp_max_mtu(params, NULL));
3986                 return false;
3987         }
3988         if (!is_linear && !params->xdp_prog->aux->xdp_has_frags) {
3989                 netdev_warn(netdev, "MTU(%d) > %d, too big for an XDP program not aware of multi buffer\n",
3990                             params->sw_mtu,
3991                             mlx5e_xdp_max_mtu(params, NULL));
3992                 return false;
3993         }
3994
3995         return true;
3996 }
3997
3998 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3999                      mlx5e_fp_preactivate preactivate)
4000 {
4001         struct mlx5e_priv *priv = netdev_priv(netdev);
4002         struct mlx5e_params new_params;
4003         struct mlx5e_params *params;
4004         bool reset = true;
4005         int err = 0;
4006
4007         mutex_lock(&priv->state_lock);
4008
4009         params = &priv->channels.params;
4010
4011         new_params = *params;
4012         new_params.sw_mtu = new_mtu;
4013         err = mlx5e_validate_params(priv->mdev, &new_params);
4014         if (err)
4015                 goto out;
4016
4017         if (new_params.xdp_prog && !mlx5e_params_validate_xdp(netdev, &new_params)) {
4018                 err = -EINVAL;
4019                 goto out;
4020         }
4021
4022         if (priv->xsk.refcnt &&
4023             !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
4024                                     &new_params, priv->mdev)) {
4025                 err = -EINVAL;
4026                 goto out;
4027         }
4028
4029         if (params->packet_merge.type == MLX5E_PACKET_MERGE_LRO)
4030                 reset = false;
4031
4032         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4033                 bool is_linear_old = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, params, NULL);
4034                 bool is_linear_new = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
4035                                                                   &new_params, NULL);
4036                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
4037                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_params, NULL);
4038
4039                 /* Always reset in linear mode - hw_mtu is used in data path.
4040                  * Check that the mode was non-linear and didn't change.
4041                  * If XSK is active, XSK RQs are linear.
4042                  */
4043                 if (!is_linear_old && !is_linear_new && !priv->xsk.refcnt &&
4044                     ppw_old == ppw_new)
4045                         reset = false;
4046         }
4047
4048         err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, reset);
4049
4050 out:
4051         netdev->mtu = params->sw_mtu;
4052         mutex_unlock(&priv->state_lock);
4053         return err;
4054 }
4055
4056 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
4057 {
4058         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx);
4059 }
4060
4061 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx)
4062 {
4063         bool set  = *(bool *)ctx;
4064
4065         return mlx5e_ptp_rx_manage_fs(priv, set);
4066 }
4067
4068 static int mlx5e_hwstamp_config_no_ptp_rx(struct mlx5e_priv *priv, bool rx_filter)
4069 {
4070         bool rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
4071         int err;
4072
4073         if (!rx_filter)
4074                 /* Reset CQE compression to Admin default */
4075                 return mlx5e_modify_rx_cqe_compression_locked(priv, rx_cqe_compress_def, false);
4076
4077         if (!MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4078                 return 0;
4079
4080         /* Disable CQE compression */
4081         netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
4082         err = mlx5e_modify_rx_cqe_compression_locked(priv, false, true);
4083         if (err)
4084                 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
4085
4086         return err;
4087 }
4088
4089 static int mlx5e_hwstamp_config_ptp_rx(struct mlx5e_priv *priv, bool ptp_rx)
4090 {
4091         struct mlx5e_params new_params;
4092
4093         if (ptp_rx == priv->channels.params.ptp_rx)
4094                 return 0;
4095
4096         new_params = priv->channels.params;
4097         new_params.ptp_rx = ptp_rx;
4098         return mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx,
4099                                         &new_params.ptp_rx, true);
4100 }
4101
4102 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
4103 {
4104         struct hwtstamp_config config;
4105         bool rx_cqe_compress_def;
4106         bool ptp_rx;
4107         int err;
4108
4109         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
4110             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
4111                 return -EOPNOTSUPP;
4112
4113         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4114                 return -EFAULT;
4115
4116         /* TX HW timestamp */
4117         switch (config.tx_type) {
4118         case HWTSTAMP_TX_OFF:
4119         case HWTSTAMP_TX_ON:
4120                 break;
4121         default:
4122                 return -ERANGE;
4123         }
4124
4125         mutex_lock(&priv->state_lock);
4126         rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
4127
4128         /* RX HW timestamp */
4129         switch (config.rx_filter) {
4130         case HWTSTAMP_FILTER_NONE:
4131                 ptp_rx = false;
4132                 break;
4133         case HWTSTAMP_FILTER_ALL:
4134         case HWTSTAMP_FILTER_SOME:
4135         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4136         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4137         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4138         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4139         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4140         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4141         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4142         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4143         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4144         case HWTSTAMP_FILTER_PTP_V2_EVENT:
4145         case HWTSTAMP_FILTER_PTP_V2_SYNC:
4146         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4147         case HWTSTAMP_FILTER_NTP_ALL:
4148                 config.rx_filter = HWTSTAMP_FILTER_ALL;
4149                 /* ptp_rx is set if both HW TS is set and CQE
4150                  * compression is set
4151                  */
4152                 ptp_rx = rx_cqe_compress_def;
4153                 break;
4154         default:
4155                 err = -ERANGE;
4156                 goto err_unlock;
4157         }
4158
4159         if (!mlx5e_profile_feature_cap(priv->profile, PTP_RX))
4160                 err = mlx5e_hwstamp_config_no_ptp_rx(priv,
4161                                                      config.rx_filter != HWTSTAMP_FILTER_NONE);
4162         else
4163                 err = mlx5e_hwstamp_config_ptp_rx(priv, ptp_rx);
4164         if (err)
4165                 goto err_unlock;
4166
4167         memcpy(&priv->tstamp, &config, sizeof(config));
4168         mutex_unlock(&priv->state_lock);
4169
4170         /* might need to fix some features */
4171         netdev_update_features(priv->netdev);
4172
4173         return copy_to_user(ifr->ifr_data, &config,
4174                             sizeof(config)) ? -EFAULT : 0;
4175 err_unlock:
4176         mutex_unlock(&priv->state_lock);
4177         return err;
4178 }
4179
4180 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
4181 {
4182         struct hwtstamp_config *cfg = &priv->tstamp;
4183
4184         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
4185                 return -EOPNOTSUPP;
4186
4187         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
4188 }
4189
4190 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4191 {
4192         struct mlx5e_priv *priv = netdev_priv(dev);
4193
4194         switch (cmd) {
4195         case SIOCSHWTSTAMP:
4196                 return mlx5e_hwstamp_set(priv, ifr);
4197         case SIOCGHWTSTAMP:
4198                 return mlx5e_hwstamp_get(priv, ifr);
4199         default:
4200                 return -EOPNOTSUPP;
4201         }
4202 }
4203
4204 #ifdef CONFIG_MLX5_ESWITCH
4205 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4206 {
4207         struct mlx5e_priv *priv = netdev_priv(dev);
4208         struct mlx5_core_dev *mdev = priv->mdev;
4209
4210         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4211 }
4212
4213 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4214                              __be16 vlan_proto)
4215 {
4216         struct mlx5e_priv *priv = netdev_priv(dev);
4217         struct mlx5_core_dev *mdev = priv->mdev;
4218
4219         if (vlan_proto != htons(ETH_P_8021Q))
4220                 return -EPROTONOSUPPORT;
4221
4222         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4223                                            vlan, qos);
4224 }
4225
4226 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4227 {
4228         struct mlx5e_priv *priv = netdev_priv(dev);
4229         struct mlx5_core_dev *mdev = priv->mdev;
4230
4231         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4232 }
4233
4234 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4235 {
4236         struct mlx5e_priv *priv = netdev_priv(dev);
4237         struct mlx5_core_dev *mdev = priv->mdev;
4238
4239         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4240 }
4241
4242 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4243                       int max_tx_rate)
4244 {
4245         struct mlx5e_priv *priv = netdev_priv(dev);
4246         struct mlx5_core_dev *mdev = priv->mdev;
4247
4248         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4249                                            max_tx_rate, min_tx_rate);
4250 }
4251
4252 static int mlx5_vport_link2ifla(u8 esw_link)
4253 {
4254         switch (esw_link) {
4255         case MLX5_VPORT_ADMIN_STATE_DOWN:
4256                 return IFLA_VF_LINK_STATE_DISABLE;
4257         case MLX5_VPORT_ADMIN_STATE_UP:
4258                 return IFLA_VF_LINK_STATE_ENABLE;
4259         }
4260         return IFLA_VF_LINK_STATE_AUTO;
4261 }
4262
4263 static int mlx5_ifla_link2vport(u8 ifla_link)
4264 {
4265         switch (ifla_link) {
4266         case IFLA_VF_LINK_STATE_DISABLE:
4267                 return MLX5_VPORT_ADMIN_STATE_DOWN;
4268         case IFLA_VF_LINK_STATE_ENABLE:
4269                 return MLX5_VPORT_ADMIN_STATE_UP;
4270         }
4271         return MLX5_VPORT_ADMIN_STATE_AUTO;
4272 }
4273
4274 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4275                                    int link_state)
4276 {
4277         struct mlx5e_priv *priv = netdev_priv(dev);
4278         struct mlx5_core_dev *mdev = priv->mdev;
4279
4280         if (mlx5e_is_uplink_rep(priv))
4281                 return -EOPNOTSUPP;
4282
4283         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4284                                             mlx5_ifla_link2vport(link_state));
4285 }
4286
4287 int mlx5e_get_vf_config(struct net_device *dev,
4288                         int vf, struct ifla_vf_info *ivi)
4289 {
4290         struct mlx5e_priv *priv = netdev_priv(dev);
4291         struct mlx5_core_dev *mdev = priv->mdev;
4292         int err;
4293
4294         if (!netif_device_present(dev))
4295                 return -EOPNOTSUPP;
4296
4297         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4298         if (err)
4299                 return err;
4300         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4301         return 0;
4302 }
4303
4304 int mlx5e_get_vf_stats(struct net_device *dev,
4305                        int vf, struct ifla_vf_stats *vf_stats)
4306 {
4307         struct mlx5e_priv *priv = netdev_priv(dev);
4308         struct mlx5_core_dev *mdev = priv->mdev;
4309
4310         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4311                                             vf_stats);
4312 }
4313
4314 static bool
4315 mlx5e_has_offload_stats(const struct net_device *dev, int attr_id)
4316 {
4317         struct mlx5e_priv *priv = netdev_priv(dev);
4318
4319         if (!netif_device_present(dev))
4320                 return false;
4321
4322         if (!mlx5e_is_uplink_rep(priv))
4323                 return false;
4324
4325         return mlx5e_rep_has_offload_stats(dev, attr_id);
4326 }
4327
4328 static int
4329 mlx5e_get_offload_stats(int attr_id, const struct net_device *dev,
4330                         void *sp)
4331 {
4332         struct mlx5e_priv *priv = netdev_priv(dev);
4333
4334         if (!mlx5e_is_uplink_rep(priv))
4335                 return -EOPNOTSUPP;
4336
4337         return mlx5e_rep_get_offload_stats(attr_id, dev, sp);
4338 }
4339 #endif
4340
4341 static bool mlx5e_tunnel_proto_supported_tx(struct mlx5_core_dev *mdev, u8 proto_type)
4342 {
4343         switch (proto_type) {
4344         case IPPROTO_GRE:
4345                 return MLX5_CAP_ETH(mdev, tunnel_stateless_gre);
4346         case IPPROTO_IPIP:
4347         case IPPROTO_IPV6:
4348                 return (MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip) ||
4349                         MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip_tx));
4350         default:
4351                 return false;
4352         }
4353 }
4354
4355 static bool mlx5e_gre_tunnel_inner_proto_offload_supported(struct mlx5_core_dev *mdev,
4356                                                            struct sk_buff *skb)
4357 {
4358         switch (skb->inner_protocol) {
4359         case htons(ETH_P_IP):
4360         case htons(ETH_P_IPV6):
4361         case htons(ETH_P_TEB):
4362                 return true;
4363         case htons(ETH_P_MPLS_UC):
4364         case htons(ETH_P_MPLS_MC):
4365                 return MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre);
4366         }
4367         return false;
4368 }
4369
4370 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4371                                                      struct sk_buff *skb,
4372                                                      netdev_features_t features)
4373 {
4374         unsigned int offset = 0;
4375         struct udphdr *udph;
4376         u8 proto;
4377         u16 port;
4378
4379         switch (vlan_get_protocol(skb)) {
4380         case htons(ETH_P_IP):
4381                 proto = ip_hdr(skb)->protocol;
4382                 break;
4383         case htons(ETH_P_IPV6):
4384                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4385                 break;
4386         default:
4387                 goto out;
4388         }
4389
4390         switch (proto) {
4391         case IPPROTO_GRE:
4392                 if (mlx5e_gre_tunnel_inner_proto_offload_supported(priv->mdev, skb))
4393                         return features;
4394                 break;
4395         case IPPROTO_IPIP:
4396         case IPPROTO_IPV6:
4397                 if (mlx5e_tunnel_proto_supported_tx(priv->mdev, IPPROTO_IPIP))
4398                         return features;
4399                 break;
4400         case IPPROTO_UDP:
4401                 udph = udp_hdr(skb);
4402                 port = be16_to_cpu(udph->dest);
4403
4404                 /* Verify if UDP port is being offloaded by HW */
4405                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4406                         return features;
4407
4408 #if IS_ENABLED(CONFIG_GENEVE)
4409                 /* Support Geneve offload for default UDP port */
4410                 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4411                         return features;
4412 #endif
4413                 break;
4414 #ifdef CONFIG_MLX5_EN_IPSEC
4415         case IPPROTO_ESP:
4416                 return mlx5e_ipsec_feature_check(skb, features);
4417 #endif
4418         }
4419
4420 out:
4421         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4422         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4423 }
4424
4425 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4426                                        struct net_device *netdev,
4427                                        netdev_features_t features)
4428 {
4429         struct mlx5e_priv *priv = netdev_priv(netdev);
4430
4431         features = vlan_features_check(skb, features);
4432         features = vxlan_features_check(skb, features);
4433
4434         /* Validate if the tunneled packet is being offloaded by HW */
4435         if (skb->encapsulation &&
4436             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4437                 return mlx5e_tunnel_features_check(priv, skb, features);
4438
4439         return features;
4440 }
4441
4442 static void mlx5e_tx_timeout_work(struct work_struct *work)
4443 {
4444         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4445                                                tx_timeout_work);
4446         struct net_device *netdev = priv->netdev;
4447         int i;
4448
4449         rtnl_lock();
4450         mutex_lock(&priv->state_lock);
4451
4452         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4453                 goto unlock;
4454
4455         for (i = 0; i < netdev->real_num_tx_queues; i++) {
4456                 struct netdev_queue *dev_queue =
4457                         netdev_get_tx_queue(netdev, i);
4458                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4459
4460                 if (!netif_xmit_stopped(dev_queue))
4461                         continue;
4462
4463                 if (mlx5e_reporter_tx_timeout(sq))
4464                 /* break if tried to reopened channels */
4465                         break;
4466         }
4467
4468 unlock:
4469         mutex_unlock(&priv->state_lock);
4470         rtnl_unlock();
4471 }
4472
4473 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue)
4474 {
4475         struct mlx5e_priv *priv = netdev_priv(dev);
4476
4477         netdev_err(dev, "TX timeout detected\n");
4478         queue_work(priv->wq, &priv->tx_timeout_work);
4479 }
4480
4481 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4482 {
4483         struct net_device *netdev = priv->netdev;
4484         struct mlx5e_params new_params;
4485
4486         if (priv->channels.params.packet_merge.type != MLX5E_PACKET_MERGE_NONE) {
4487                 netdev_warn(netdev, "can't set XDP while HW-GRO/LRO is on, disable them first\n");
4488                 return -EINVAL;
4489         }
4490
4491         new_params = priv->channels.params;
4492         new_params.xdp_prog = prog;
4493
4494         if (!mlx5e_params_validate_xdp(netdev, &new_params))
4495                 return -EINVAL;
4496
4497         return 0;
4498 }
4499
4500 static void mlx5e_rq_replace_xdp_prog(struct mlx5e_rq *rq, struct bpf_prog *prog)
4501 {
4502         struct bpf_prog *old_prog;
4503
4504         old_prog = rcu_replace_pointer(rq->xdp_prog, prog,
4505                                        lockdep_is_held(&rq->priv->state_lock));
4506         if (old_prog)
4507                 bpf_prog_put(old_prog);
4508 }
4509
4510 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4511 {
4512         struct mlx5e_priv *priv = netdev_priv(netdev);
4513         struct mlx5e_params new_params;
4514         struct bpf_prog *old_prog;
4515         int err = 0;
4516         bool reset;
4517         int i;
4518
4519         mutex_lock(&priv->state_lock);
4520
4521         if (prog) {
4522                 err = mlx5e_xdp_allowed(priv, prog);
4523                 if (err)
4524                         goto unlock;
4525         }
4526
4527         /* no need for full reset when exchanging programs */
4528         reset = (!priv->channels.params.xdp_prog || !prog);
4529
4530         new_params = priv->channels.params;
4531         new_params.xdp_prog = prog;
4532         if (reset)
4533                 mlx5e_set_rq_type(priv->mdev, &new_params);
4534         old_prog = priv->channels.params.xdp_prog;
4535
4536         err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
4537         if (err)
4538                 goto unlock;
4539
4540         if (old_prog)
4541                 bpf_prog_put(old_prog);
4542
4543         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4544                 goto unlock;
4545
4546         /* exchanging programs w/o reset, we update ref counts on behalf
4547          * of the channels RQs here.
4548          */
4549         bpf_prog_add(prog, priv->channels.num);
4550         for (i = 0; i < priv->channels.num; i++) {
4551                 struct mlx5e_channel *c = priv->channels.c[i];
4552
4553                 mlx5e_rq_replace_xdp_prog(&c->rq, prog);
4554                 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) {
4555                         bpf_prog_inc(prog);
4556                         mlx5e_rq_replace_xdp_prog(&c->xskrq, prog);
4557                 }
4558         }
4559
4560 unlock:
4561         mutex_unlock(&priv->state_lock);
4562         return err;
4563 }
4564
4565 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4566 {
4567         switch (xdp->command) {
4568         case XDP_SETUP_PROG:
4569                 return mlx5e_xdp_set(dev, xdp->prog);
4570         case XDP_SETUP_XSK_POOL:
4571                 return mlx5e_xsk_setup_pool(dev, xdp->xsk.pool,
4572                                             xdp->xsk.queue_id);
4573         default:
4574                 return -EINVAL;
4575         }
4576 }
4577
4578 #ifdef CONFIG_MLX5_ESWITCH
4579 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4580                                 struct net_device *dev, u32 filter_mask,
4581                                 int nlflags)
4582 {
4583         struct mlx5e_priv *priv = netdev_priv(dev);
4584         struct mlx5_core_dev *mdev = priv->mdev;
4585         u8 mode, setting;
4586         int err;
4587
4588         err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4589         if (err)
4590                 return err;
4591         mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4592         return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4593                                        mode,
4594                                        0, 0, nlflags, filter_mask, NULL);
4595 }
4596
4597 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4598                                 u16 flags, struct netlink_ext_ack *extack)
4599 {
4600         struct mlx5e_priv *priv = netdev_priv(dev);
4601         struct mlx5_core_dev *mdev = priv->mdev;
4602         struct nlattr *attr, *br_spec;
4603         u16 mode = BRIDGE_MODE_UNDEF;
4604         u8 setting;
4605         int rem;
4606
4607         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4608         if (!br_spec)
4609                 return -EINVAL;
4610
4611         nla_for_each_nested(attr, br_spec, rem) {
4612                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4613                         continue;
4614
4615                 if (nla_len(attr) < sizeof(mode))
4616                         return -EINVAL;
4617
4618                 mode = nla_get_u16(attr);
4619                 if (mode > BRIDGE_MODE_VEPA)
4620                         return -EINVAL;
4621
4622                 break;
4623         }
4624
4625         if (mode == BRIDGE_MODE_UNDEF)
4626                 return -EINVAL;
4627
4628         setting = (mode == BRIDGE_MODE_VEPA) ?  1 : 0;
4629         return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4630 }
4631 #endif
4632
4633 const struct net_device_ops mlx5e_netdev_ops = {
4634         .ndo_open                = mlx5e_open,
4635         .ndo_stop                = mlx5e_close,
4636         .ndo_start_xmit          = mlx5e_xmit,
4637         .ndo_setup_tc            = mlx5e_setup_tc,
4638         .ndo_select_queue        = mlx5e_select_queue,
4639         .ndo_get_stats64         = mlx5e_get_stats,
4640         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4641         .ndo_set_mac_address     = mlx5e_set_mac,
4642         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4643         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4644         .ndo_set_features        = mlx5e_set_features,
4645         .ndo_fix_features        = mlx5e_fix_features,
4646         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4647         .ndo_eth_ioctl            = mlx5e_ioctl,
4648         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4649         .ndo_features_check      = mlx5e_features_check,
4650         .ndo_tx_timeout          = mlx5e_tx_timeout,
4651         .ndo_bpf                 = mlx5e_xdp,
4652         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4653         .ndo_xsk_wakeup          = mlx5e_xsk_wakeup,
4654 #ifdef CONFIG_MLX5_EN_ARFS
4655         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4656 #endif
4657 #ifdef CONFIG_MLX5_ESWITCH
4658         .ndo_bridge_setlink      = mlx5e_bridge_setlink,
4659         .ndo_bridge_getlink      = mlx5e_bridge_getlink,
4660
4661         /* SRIOV E-Switch NDOs */
4662         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4663         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4664         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4665         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4666         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4667         .ndo_get_vf_config       = mlx5e_get_vf_config,
4668         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4669         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4670         .ndo_has_offload_stats   = mlx5e_has_offload_stats,
4671         .ndo_get_offload_stats   = mlx5e_get_offload_stats,
4672 #endif
4673         .ndo_get_devlink_port    = mlx5e_get_devlink_port,
4674 };
4675
4676 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4677 {
4678         int i;
4679
4680         /* The supported periods are organized in ascending order */
4681         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4682                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4683                         break;
4684
4685         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4686 }
4687
4688 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu)
4689 {
4690         struct mlx5e_params *params = &priv->channels.params;
4691         struct mlx5_core_dev *mdev = priv->mdev;
4692         u8 rx_cq_period_mode;
4693
4694         params->sw_mtu = mtu;
4695         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4696         params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2,
4697                                      priv->max_nch);
4698         mlx5e_params_mqprio_reset(params);
4699
4700         /* SQ */
4701         params->log_sq_size = is_kdump_kernel() ?
4702                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4703                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4704         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
4705
4706         /* XDP SQ */
4707         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
4708
4709         /* set CQE compression */
4710         params->rx_cqe_compress_def = false;
4711         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4712             MLX5_CAP_GEN(mdev, vport_group_manager))
4713                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4714
4715         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4716         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4717
4718         /* RQ */
4719         mlx5e_build_rq_params(mdev, params);
4720
4721         /* HW LRO */
4722         if (MLX5_CAP_ETH(mdev, lro_cap) &&
4723             params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4724                 /* No XSK params: checking the availability of striding RQ in general. */
4725                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4726                         params->packet_merge.type = slow_pci_heuristic(mdev) ?
4727                                 MLX5E_PACKET_MERGE_NONE : MLX5E_PACKET_MERGE_LRO;
4728         }
4729         params->packet_merge.timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4730
4731         /* CQ moderation params */
4732         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4733                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4734                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4735         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4736         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4737         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4738         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4739
4740         /* TX inline */
4741         mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
4742
4743         params->tunneled_offload_en = mlx5_tunnel_inner_ft_supported(mdev);
4744
4745         /* AF_XDP */
4746         params->xsk = xsk;
4747
4748         /* Do not update netdev->features directly in here
4749          * on mlx5e_attach_netdev() we will call mlx5e_update_features()
4750          * To update netdev->features please modify mlx5e_fix_features()
4751          */
4752 }
4753
4754 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4755 {
4756         struct mlx5e_priv *priv = netdev_priv(netdev);
4757         u8 addr[ETH_ALEN];
4758
4759         mlx5_query_mac_address(priv->mdev, addr);
4760         if (is_zero_ether_addr(addr) &&
4761             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4762                 eth_hw_addr_random(netdev);
4763                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4764                 return;
4765         }
4766
4767         eth_hw_addr_set(netdev, addr);
4768 }
4769
4770 static int mlx5e_vxlan_set_port(struct net_device *netdev, unsigned int table,
4771                                 unsigned int entry, struct udp_tunnel_info *ti)
4772 {
4773         struct mlx5e_priv *priv = netdev_priv(netdev);
4774
4775         return mlx5_vxlan_add_port(priv->mdev->vxlan, ntohs(ti->port));
4776 }
4777
4778 static int mlx5e_vxlan_unset_port(struct net_device *netdev, unsigned int table,
4779                                   unsigned int entry, struct udp_tunnel_info *ti)
4780 {
4781         struct mlx5e_priv *priv = netdev_priv(netdev);
4782
4783         return mlx5_vxlan_del_port(priv->mdev->vxlan, ntohs(ti->port));
4784 }
4785
4786 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv)
4787 {
4788         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4789                 return;
4790
4791         priv->nic_info.set_port = mlx5e_vxlan_set_port;
4792         priv->nic_info.unset_port = mlx5e_vxlan_unset_port;
4793         priv->nic_info.flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
4794                                 UDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN;
4795         priv->nic_info.tables[0].tunnel_types = UDP_TUNNEL_TYPE_VXLAN;
4796         /* Don't count the space hard-coded to the IANA port */
4797         priv->nic_info.tables[0].n_entries =
4798                 mlx5_vxlan_max_udp_ports(priv->mdev) - 1;
4799
4800         priv->netdev->udp_tunnel_nic_info = &priv->nic_info;
4801 }
4802
4803 static bool mlx5e_tunnel_any_tx_proto_supported(struct mlx5_core_dev *mdev)
4804 {
4805         int tt;
4806
4807         for (tt = 0; tt < MLX5_NUM_TUNNEL_TT; tt++) {
4808                 if (mlx5e_tunnel_proto_supported_tx(mdev, mlx5_get_proto_by_tunnel_type(tt)))
4809                         return true;
4810         }
4811         return (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev));
4812 }
4813
4814 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4815 {
4816         struct mlx5e_priv *priv = netdev_priv(netdev);
4817         struct mlx5_core_dev *mdev = priv->mdev;
4818         bool fcs_supported;
4819         bool fcs_enabled;
4820
4821         SET_NETDEV_DEV(netdev, mdev->device);
4822
4823         netdev->netdev_ops = &mlx5e_netdev_ops;
4824
4825         mlx5e_dcbnl_build_netdev(netdev);
4826
4827         netdev->watchdog_timeo    = 15 * HZ;
4828
4829         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4830
4831         netdev->vlan_features    |= NETIF_F_SG;
4832         netdev->vlan_features    |= NETIF_F_HW_CSUM;
4833         netdev->vlan_features    |= NETIF_F_GRO;
4834         netdev->vlan_features    |= NETIF_F_TSO;
4835         netdev->vlan_features    |= NETIF_F_TSO6;
4836         netdev->vlan_features    |= NETIF_F_RXCSUM;
4837         netdev->vlan_features    |= NETIF_F_RXHASH;
4838         netdev->vlan_features    |= NETIF_F_GSO_PARTIAL;
4839
4840         netdev->mpls_features    |= NETIF_F_SG;
4841         netdev->mpls_features    |= NETIF_F_HW_CSUM;
4842         netdev->mpls_features    |= NETIF_F_TSO;
4843         netdev->mpls_features    |= NETIF_F_TSO6;
4844
4845         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4846         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4847
4848         /* Tunneled LRO is not supported in the driver, and the same RQs are
4849          * shared between inner and outer TIRs, so the driver can't disable LRO
4850          * for inner TIRs while having it enabled for outer TIRs. Due to this,
4851          * block LRO altogether if the firmware declares tunneled LRO support.
4852          */
4853         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4854             !MLX5_CAP_ETH(mdev, tunnel_lro_vxlan) &&
4855             !MLX5_CAP_ETH(mdev, tunnel_lro_gre) &&
4856             mlx5e_check_fragmented_striding_rq_cap(mdev))
4857                 netdev->vlan_features    |= NETIF_F_LRO;
4858
4859         netdev->hw_features       = netdev->vlan_features;
4860         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4861         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4862         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4863         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4864
4865         if (mlx5e_tunnel_any_tx_proto_supported(mdev)) {
4866                 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4867                 netdev->hw_enc_features |= NETIF_F_TSO;
4868                 netdev->hw_enc_features |= NETIF_F_TSO6;
4869                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4870         }
4871
4872         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4873                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4874                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4875                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4876                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4877                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4878                 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL |
4879                                          NETIF_F_GSO_UDP_TUNNEL_CSUM;
4880         }
4881
4882         if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_GRE)) {
4883                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4884                                            NETIF_F_GSO_GRE_CSUM;
4885                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4886                                            NETIF_F_GSO_GRE_CSUM;
4887                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4888                                                 NETIF_F_GSO_GRE_CSUM;
4889         }
4890
4891         if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_IPIP)) {
4892                 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
4893                                        NETIF_F_GSO_IPXIP6;
4894                 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
4895                                            NETIF_F_GSO_IPXIP6;
4896                 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
4897                                                 NETIF_F_GSO_IPXIP6;
4898         }
4899
4900         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4901         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4902         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4903
4904         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4905
4906         if (fcs_supported)
4907                 netdev->hw_features |= NETIF_F_RXALL;
4908
4909         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4910                 netdev->hw_features |= NETIF_F_RXFCS;
4911
4912         if (mlx5_qos_is_supported(mdev))
4913                 netdev->hw_features |= NETIF_F_HW_TC;
4914
4915         netdev->features          = netdev->hw_features;
4916
4917         /* Defaults */
4918         if (fcs_enabled)
4919                 netdev->features  &= ~NETIF_F_RXALL;
4920         netdev->features  &= ~NETIF_F_LRO;
4921         netdev->features  &= ~NETIF_F_GRO_HW;
4922         netdev->features  &= ~NETIF_F_RXFCS;
4923
4924 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4925         if (FT_CAP(flow_modify_en) &&
4926             FT_CAP(modify_root) &&
4927             FT_CAP(identified_miss_table_mode) &&
4928             FT_CAP(flow_table_modify)) {
4929 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
4930                 netdev->hw_features      |= NETIF_F_HW_TC;
4931 #endif
4932 #ifdef CONFIG_MLX5_EN_ARFS
4933                 netdev->hw_features      |= NETIF_F_NTUPLE;
4934 #endif
4935         }
4936
4937         netdev->features         |= NETIF_F_HIGHDMA;
4938         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4939
4940         netdev->priv_flags       |= IFF_UNICAST_FLT;
4941
4942         netif_set_tso_max_size(netdev, GSO_MAX_SIZE);
4943         mlx5e_set_netdev_dev_addr(netdev);
4944         mlx5e_ipsec_build_netdev(priv);
4945         mlx5e_ktls_build_netdev(priv);
4946 }
4947
4948 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4949 {
4950         u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {};
4951         u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {};
4952         struct mlx5_core_dev *mdev = priv->mdev;
4953         int err;
4954
4955         MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
4956         err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4957         if (!err)
4958                 priv->q_counter =
4959                         MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4960
4961         err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4962         if (!err)
4963                 priv->drop_rq_q_counter =
4964                         MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4965 }
4966
4967 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4968 {
4969         u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {};
4970
4971         MLX5_SET(dealloc_q_counter_in, in, opcode,
4972                  MLX5_CMD_OP_DEALLOC_Q_COUNTER);
4973         if (priv->q_counter) {
4974                 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
4975                          priv->q_counter);
4976                 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
4977         }
4978
4979         if (priv->drop_rq_q_counter) {
4980                 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
4981                          priv->drop_rq_q_counter);
4982                 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
4983         }
4984 }
4985
4986 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
4987                           struct net_device *netdev)
4988 {
4989         struct mlx5e_priv *priv = netdev_priv(netdev);
4990         int err;
4991
4992         mlx5e_build_nic_params(priv, &priv->xsk, netdev->mtu);
4993         mlx5e_vxlan_set_netdev_info(priv);
4994
4995         mlx5e_timestamp_init(priv);
4996
4997         err = mlx5e_fs_init(priv);
4998         if (err) {
4999                 mlx5_core_err(mdev, "FS initialization failed, %d\n", err);
5000                 return err;
5001         }
5002
5003         err = mlx5e_ipsec_init(priv);
5004         if (err)
5005                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
5006
5007         err = mlx5e_ktls_init(priv);
5008         if (err)
5009                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
5010
5011         mlx5e_health_create_reporters(priv);
5012         return 0;
5013 }
5014
5015 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
5016 {
5017         mlx5e_health_destroy_reporters(priv);
5018         mlx5e_ktls_cleanup(priv);
5019         mlx5e_ipsec_cleanup(priv);
5020         mlx5e_fs_cleanup(priv);
5021 }
5022
5023 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
5024 {
5025         struct mlx5_core_dev *mdev = priv->mdev;
5026         enum mlx5e_rx_res_features features;
5027         int err;
5028
5029         priv->rx_res = mlx5e_rx_res_alloc();
5030         if (!priv->rx_res)
5031                 return -ENOMEM;
5032
5033         mlx5e_create_q_counters(priv);
5034
5035         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
5036         if (err) {
5037                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
5038                 goto err_destroy_q_counters;
5039         }
5040
5041         features = MLX5E_RX_RES_FEATURE_XSK | MLX5E_RX_RES_FEATURE_PTP;
5042         if (priv->channels.params.tunneled_offload_en)
5043                 features |= MLX5E_RX_RES_FEATURE_INNER_FT;
5044         err = mlx5e_rx_res_init(priv->rx_res, priv->mdev, features,
5045                                 priv->max_nch, priv->drop_rq.rqn,
5046                                 &priv->channels.params.packet_merge,
5047                                 priv->channels.params.num_channels);
5048         if (err)
5049                 goto err_close_drop_rq;
5050
5051         err = mlx5e_create_flow_steering(priv);
5052         if (err) {
5053                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
5054                 goto err_destroy_rx_res;
5055         }
5056
5057         err = mlx5e_tc_nic_init(priv);
5058         if (err)
5059                 goto err_destroy_flow_steering;
5060
5061         err = mlx5e_accel_init_rx(priv);
5062         if (err)
5063                 goto err_tc_nic_cleanup;
5064
5065 #ifdef CONFIG_MLX5_EN_ARFS
5066         priv->netdev->rx_cpu_rmap =  mlx5_eq_table_get_rmap(priv->mdev);
5067 #endif
5068
5069         return 0;
5070
5071 err_tc_nic_cleanup:
5072         mlx5e_tc_nic_cleanup(priv);
5073 err_destroy_flow_steering:
5074         mlx5e_destroy_flow_steering(priv);
5075 err_destroy_rx_res:
5076         mlx5e_rx_res_destroy(priv->rx_res);
5077 err_close_drop_rq:
5078         mlx5e_close_drop_rq(&priv->drop_rq);
5079 err_destroy_q_counters:
5080         mlx5e_destroy_q_counters(priv);
5081         mlx5e_rx_res_free(priv->rx_res);
5082         priv->rx_res = NULL;
5083         return err;
5084 }
5085
5086 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5087 {
5088         mlx5e_accel_cleanup_rx(priv);
5089         mlx5e_tc_nic_cleanup(priv);
5090         mlx5e_destroy_flow_steering(priv);
5091         mlx5e_rx_res_destroy(priv->rx_res);
5092         mlx5e_close_drop_rq(&priv->drop_rq);
5093         mlx5e_destroy_q_counters(priv);
5094         mlx5e_rx_res_free(priv->rx_res);
5095         priv->rx_res = NULL;
5096 }
5097
5098 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5099 {
5100         int err;
5101
5102         err = mlx5e_create_tises(priv);
5103         if (err) {
5104                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
5105                 return err;
5106         }
5107
5108         mlx5e_dcbnl_initialize(priv);
5109         return 0;
5110 }
5111
5112 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5113 {
5114         struct net_device *netdev = priv->netdev;
5115         struct mlx5_core_dev *mdev = priv->mdev;
5116
5117         mlx5e_init_l2_addr(priv);
5118
5119         /* Marking the link as currently not needed by the Driver */
5120         if (!netif_running(netdev))
5121                 mlx5e_modify_admin_state(mdev, MLX5_PORT_DOWN);
5122
5123         mlx5e_set_netdev_mtu_boundaries(priv);
5124         mlx5e_set_dev_port_mtu(priv);
5125
5126         mlx5_lag_add_netdev(mdev, netdev);
5127
5128         mlx5e_enable_async_events(priv);
5129         mlx5e_enable_blocking_events(priv);
5130         if (mlx5e_monitor_counter_supported(priv))
5131                 mlx5e_monitor_counter_init(priv);
5132
5133         mlx5e_hv_vhca_stats_create(priv);
5134         if (netdev->reg_state != NETREG_REGISTERED)
5135                 return;
5136         mlx5e_dcbnl_init_app(priv);
5137
5138         mlx5e_nic_set_rx_mode(priv);
5139
5140         rtnl_lock();
5141         if (netif_running(netdev))
5142                 mlx5e_open(netdev);
5143         udp_tunnel_nic_reset_ntf(priv->netdev);
5144         netif_device_attach(netdev);
5145         rtnl_unlock();
5146 }
5147
5148 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5149 {
5150         struct mlx5_core_dev *mdev = priv->mdev;
5151
5152         if (priv->netdev->reg_state == NETREG_REGISTERED)
5153                 mlx5e_dcbnl_delete_app(priv);
5154
5155         rtnl_lock();
5156         if (netif_running(priv->netdev))
5157                 mlx5e_close(priv->netdev);
5158         netif_device_detach(priv->netdev);
5159         rtnl_unlock();
5160
5161         mlx5e_nic_set_rx_mode(priv);
5162
5163         mlx5e_hv_vhca_stats_destroy(priv);
5164         if (mlx5e_monitor_counter_supported(priv))
5165                 mlx5e_monitor_counter_cleanup(priv);
5166
5167         mlx5e_disable_blocking_events(priv);
5168         if (priv->en_trap) {
5169                 mlx5e_deactivate_trap(priv);
5170                 mlx5e_close_trap(priv->en_trap);
5171                 priv->en_trap = NULL;
5172         }
5173         mlx5e_disable_async_events(priv);
5174         mlx5_lag_remove_netdev(mdev, priv->netdev);
5175         mlx5_vxlan_reset_to_default(mdev->vxlan);
5176 }
5177
5178 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5179 {
5180         return mlx5e_refresh_tirs(priv, false, false);
5181 }
5182
5183 static const struct mlx5e_profile mlx5e_nic_profile = {
5184         .init              = mlx5e_nic_init,
5185         .cleanup           = mlx5e_nic_cleanup,
5186         .init_rx           = mlx5e_init_nic_rx,
5187         .cleanup_rx        = mlx5e_cleanup_nic_rx,
5188         .init_tx           = mlx5e_init_nic_tx,
5189         .cleanup_tx        = mlx5e_cleanup_nic_tx,
5190         .enable            = mlx5e_nic_enable,
5191         .disable           = mlx5e_nic_disable,
5192         .update_rx         = mlx5e_update_nic_rx,
5193         .update_stats      = mlx5e_stats_update_ndo_stats,
5194         .update_carrier    = mlx5e_update_carrier,
5195         .rx_handlers       = &mlx5e_rx_handlers_nic,
5196         .max_tc            = MLX5E_MAX_NUM_TC,
5197         .rq_groups         = MLX5E_NUM_RQ_GROUPS(XSK),
5198         .stats_grps        = mlx5e_nic_stats_grps,
5199         .stats_grps_num    = mlx5e_nic_stats_grps_num,
5200         .features          = BIT(MLX5E_PROFILE_FEATURE_PTP_RX) |
5201                 BIT(MLX5E_PROFILE_FEATURE_PTP_TX) |
5202                 BIT(MLX5E_PROFILE_FEATURE_QOS_HTB),
5203 };
5204
5205 static int mlx5e_profile_max_num_channels(struct mlx5_core_dev *mdev,
5206                                           const struct mlx5e_profile *profile)
5207 {
5208         int nch;
5209
5210         nch = mlx5e_get_max_num_channels(mdev);
5211
5212         if (profile->max_nch_limit)
5213                 nch = min_t(int, nch, profile->max_nch_limit(mdev));
5214         return nch;
5215 }
5216
5217 static unsigned int
5218 mlx5e_calc_max_nch(struct mlx5_core_dev *mdev, struct net_device *netdev,
5219                    const struct mlx5e_profile *profile)
5220
5221 {
5222         unsigned int max_nch, tmp;
5223
5224         /* core resources */
5225         max_nch = mlx5e_profile_max_num_channels(mdev, profile);
5226
5227         /* netdev rx queues */
5228         tmp = netdev->num_rx_queues / max_t(u8, profile->rq_groups, 1);
5229         max_nch = min_t(unsigned int, max_nch, tmp);
5230
5231         /* netdev tx queues */
5232         tmp = netdev->num_tx_queues;
5233         if (mlx5_qos_is_supported(mdev))
5234                 tmp -= mlx5e_qos_max_leaf_nodes(mdev);
5235         if (MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn))
5236                 tmp -= profile->max_tc;
5237         tmp = tmp / profile->max_tc;
5238         max_nch = min_t(unsigned int, max_nch, tmp);
5239
5240         return max_nch;
5241 }
5242
5243 int mlx5e_get_pf_num_tirs(struct mlx5_core_dev *mdev)
5244 {
5245         /* Indirect TIRS: 2 sets of TTCs (inner + outer steering)
5246          * and 1 set of direct TIRS
5247          */
5248         return 2 * MLX5E_NUM_INDIR_TIRS
5249                 + mlx5e_profile_max_num_channels(mdev, &mlx5e_nic_profile);
5250 }
5251
5252 /* mlx5e generic netdev management API (move to en_common.c) */
5253 int mlx5e_priv_init(struct mlx5e_priv *priv,
5254                     const struct mlx5e_profile *profile,
5255                     struct net_device *netdev,
5256                     struct mlx5_core_dev *mdev)
5257 {
5258         int nch, num_txqs, node;
5259         int err;
5260
5261         num_txqs = netdev->num_tx_queues;
5262         nch = mlx5e_calc_max_nch(mdev, netdev, profile);
5263         node = dev_to_node(mlx5_core_dma_dev(mdev));
5264
5265         /* priv init */
5266         priv->mdev        = mdev;
5267         priv->netdev      = netdev;
5268         priv->msglevel    = MLX5E_MSG_LEVEL;
5269         priv->max_nch     = nch;
5270         priv->max_opened_tc = 1;
5271
5272         if (!alloc_cpumask_var(&priv->scratchpad.cpumask, GFP_KERNEL))
5273                 return -ENOMEM;
5274
5275         mutex_init(&priv->state_lock);
5276
5277         err = mlx5e_selq_init(&priv->selq, &priv->state_lock);
5278         if (err)
5279                 goto err_free_cpumask;
5280
5281         hash_init(priv->htb.qos_tc2node);
5282         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5283         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5284         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5285         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5286
5287         priv->wq = create_singlethread_workqueue("mlx5e");
5288         if (!priv->wq)
5289                 goto err_free_selq;
5290
5291         priv->txq2sq = kcalloc_node(num_txqs, sizeof(*priv->txq2sq), GFP_KERNEL, node);
5292         if (!priv->txq2sq)
5293                 goto err_destroy_workqueue;
5294
5295         priv->tx_rates = kcalloc_node(num_txqs, sizeof(*priv->tx_rates), GFP_KERNEL, node);
5296         if (!priv->tx_rates)
5297                 goto err_free_txq2sq;
5298
5299         priv->channel_stats =
5300                 kcalloc_node(nch, sizeof(*priv->channel_stats), GFP_KERNEL, node);
5301         if (!priv->channel_stats)
5302                 goto err_free_tx_rates;
5303
5304         return 0;
5305
5306 err_free_tx_rates:
5307         kfree(priv->tx_rates);
5308 err_free_txq2sq:
5309         kfree(priv->txq2sq);
5310 err_destroy_workqueue:
5311         destroy_workqueue(priv->wq);
5312 err_free_selq:
5313         mlx5e_selq_cleanup(&priv->selq);
5314 err_free_cpumask:
5315         free_cpumask_var(priv->scratchpad.cpumask);
5316         return -ENOMEM;
5317 }
5318
5319 void mlx5e_priv_cleanup(struct mlx5e_priv *priv)
5320 {
5321         int i;
5322
5323         /* bail if change profile failed and also rollback failed */
5324         if (!priv->mdev)
5325                 return;
5326
5327         for (i = 0; i < priv->stats_nch; i++)
5328                 kvfree(priv->channel_stats[i]);
5329         kfree(priv->channel_stats);
5330         kfree(priv->tx_rates);
5331         kfree(priv->txq2sq);
5332         destroy_workqueue(priv->wq);
5333         mutex_lock(&priv->state_lock);
5334         mlx5e_selq_cleanup(&priv->selq);
5335         mutex_unlock(&priv->state_lock);
5336         free_cpumask_var(priv->scratchpad.cpumask);
5337
5338         for (i = 0; i < priv->htb.max_qos_sqs; i++)
5339                 kfree(priv->htb.qos_sq_stats[i]);
5340         kvfree(priv->htb.qos_sq_stats);
5341
5342         if (priv->mqprio_rl) {
5343                 mlx5e_mqprio_rl_cleanup(priv->mqprio_rl);
5344                 mlx5e_mqprio_rl_free(priv->mqprio_rl);
5345         }
5346
5347         memset(priv, 0, sizeof(*priv));
5348 }
5349
5350 static unsigned int mlx5e_get_max_num_txqs(struct mlx5_core_dev *mdev,
5351                                            const struct mlx5e_profile *profile)
5352 {
5353         unsigned int nch, ptp_txqs, qos_txqs;
5354
5355         nch = mlx5e_profile_max_num_channels(mdev, profile);
5356
5357         ptp_txqs = MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn) &&
5358                 mlx5e_profile_feature_cap(profile, PTP_TX) ?
5359                 profile->max_tc : 0;
5360
5361         qos_txqs = mlx5_qos_is_supported(mdev) &&
5362                 mlx5e_profile_feature_cap(profile, QOS_HTB) ?
5363                 mlx5e_qos_max_leaf_nodes(mdev) : 0;
5364
5365         return nch * profile->max_tc + ptp_txqs + qos_txqs;
5366 }
5367
5368 static unsigned int mlx5e_get_max_num_rxqs(struct mlx5_core_dev *mdev,
5369                                            const struct mlx5e_profile *profile)
5370 {
5371         unsigned int nch;
5372
5373         nch = mlx5e_profile_max_num_channels(mdev, profile);
5374
5375         return nch * profile->rq_groups;
5376 }
5377
5378 struct net_device *
5379 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile)
5380 {
5381         struct net_device *netdev;
5382         unsigned int txqs, rxqs;
5383         int err;
5384
5385         txqs = mlx5e_get_max_num_txqs(mdev, profile);
5386         rxqs = mlx5e_get_max_num_rxqs(mdev, profile);
5387
5388         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), txqs, rxqs);
5389         if (!netdev) {
5390                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5391                 return NULL;
5392         }
5393
5394         err = mlx5e_priv_init(netdev_priv(netdev), profile, netdev, mdev);
5395         if (err) {
5396                 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5397                 goto err_free_netdev;
5398         }
5399
5400         netif_carrier_off(netdev);
5401         netif_tx_disable(netdev);
5402         dev_net_set(netdev, mlx5_core_net(mdev));
5403
5404         return netdev;
5405
5406 err_free_netdev:
5407         free_netdev(netdev);
5408
5409         return NULL;
5410 }
5411
5412 static void mlx5e_update_features(struct net_device *netdev)
5413 {
5414         if (netdev->reg_state != NETREG_REGISTERED)
5415                 return; /* features will be updated on netdev registration */
5416
5417         rtnl_lock();
5418         netdev_update_features(netdev);
5419         rtnl_unlock();
5420 }
5421
5422 static void mlx5e_reset_channels(struct net_device *netdev)
5423 {
5424         netdev_reset_tc(netdev);
5425 }
5426
5427 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5428 {
5429         const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED;
5430         const struct mlx5e_profile *profile = priv->profile;
5431         int max_nch;
5432         int err;
5433
5434         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5435
5436         /* max number of channels may have changed */
5437         max_nch = mlx5e_calc_max_nch(priv->mdev, priv->netdev, profile);
5438         if (priv->channels.params.num_channels > max_nch) {
5439                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5440                 /* Reducing the number of channels - RXFH has to be reset, and
5441                  * mlx5e_num_channels_changed below will build the RQT.
5442                  */
5443                 priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED;
5444                 priv->channels.params.num_channels = max_nch;
5445                 if (priv->channels.params.mqprio.mode == TC_MQPRIO_MODE_CHANNEL) {
5446                         mlx5_core_warn(priv->mdev, "MLX5E: Disabling MQPRIO channel mode\n");
5447                         mlx5e_params_mqprio_reset(&priv->channels.params);
5448                 }
5449         }
5450         if (max_nch != priv->max_nch) {
5451                 mlx5_core_warn(priv->mdev,
5452                                "MLX5E: Updating max number of channels from %u to %u\n",
5453                                priv->max_nch, max_nch);
5454                 priv->max_nch = max_nch;
5455         }
5456
5457         /* 1. Set the real number of queues in the kernel the first time.
5458          * 2. Set our default XPS cpumask.
5459          * 3. Build the RQT.
5460          *
5461          * rtnl_lock is required by netif_set_real_num_*_queues in case the
5462          * netdev has been registered by this point (if this function was called
5463          * in the reload or resume flow).
5464          */
5465         if (take_rtnl)
5466                 rtnl_lock();
5467         err = mlx5e_num_channels_changed(priv);
5468         if (take_rtnl)
5469                 rtnl_unlock();
5470         if (err)
5471                 goto out;
5472
5473         err = profile->init_tx(priv);
5474         if (err)
5475                 goto out;
5476
5477         err = profile->init_rx(priv);
5478         if (err)
5479                 goto err_cleanup_tx;
5480
5481         if (profile->enable)
5482                 profile->enable(priv);
5483
5484         mlx5e_update_features(priv->netdev);
5485
5486         return 0;
5487
5488 err_cleanup_tx:
5489         profile->cleanup_tx(priv);
5490
5491 out:
5492         mlx5e_reset_channels(priv->netdev);
5493         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5494         cancel_work_sync(&priv->update_stats_work);
5495         return err;
5496 }
5497
5498 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5499 {
5500         const struct mlx5e_profile *profile = priv->profile;
5501
5502         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5503
5504         if (profile->disable)
5505                 profile->disable(priv);
5506         flush_workqueue(priv->wq);
5507
5508         profile->cleanup_rx(priv);
5509         profile->cleanup_tx(priv);
5510         mlx5e_reset_channels(priv->netdev);
5511         cancel_work_sync(&priv->update_stats_work);
5512 }
5513
5514 static int
5515 mlx5e_netdev_attach_profile(struct net_device *netdev, struct mlx5_core_dev *mdev,
5516                             const struct mlx5e_profile *new_profile, void *new_ppriv)
5517 {
5518         struct mlx5e_priv *priv = netdev_priv(netdev);
5519         int err;
5520
5521         err = mlx5e_priv_init(priv, new_profile, netdev, mdev);
5522         if (err) {
5523                 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5524                 return err;
5525         }
5526         netif_carrier_off(netdev);
5527         priv->profile = new_profile;
5528         priv->ppriv = new_ppriv;
5529         err = new_profile->init(priv->mdev, priv->netdev);
5530         if (err)
5531                 goto priv_cleanup;
5532         err = mlx5e_attach_netdev(priv);
5533         if (err)
5534                 goto profile_cleanup;
5535         return err;
5536
5537 profile_cleanup:
5538         new_profile->cleanup(priv);
5539 priv_cleanup:
5540         mlx5e_priv_cleanup(priv);
5541         return err;
5542 }
5543
5544 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
5545                                 const struct mlx5e_profile *new_profile, void *new_ppriv)
5546 {
5547         const struct mlx5e_profile *orig_profile = priv->profile;
5548         struct net_device *netdev = priv->netdev;
5549         struct mlx5_core_dev *mdev = priv->mdev;
5550         void *orig_ppriv = priv->ppriv;
5551         int err, rollback_err;
5552
5553         /* cleanup old profile */
5554         mlx5e_detach_netdev(priv);
5555         priv->profile->cleanup(priv);
5556         mlx5e_priv_cleanup(priv);
5557
5558         err = mlx5e_netdev_attach_profile(netdev, mdev, new_profile, new_ppriv);
5559         if (err) { /* roll back to original profile */
5560                 netdev_warn(netdev, "%s: new profile init failed, %d\n", __func__, err);
5561                 goto rollback;
5562         }
5563
5564         return 0;
5565
5566 rollback:
5567         rollback_err = mlx5e_netdev_attach_profile(netdev, mdev, orig_profile, orig_ppriv);
5568         if (rollback_err)
5569                 netdev_err(netdev, "%s: failed to rollback to orig profile, %d\n",
5570                            __func__, rollback_err);
5571         return err;
5572 }
5573
5574 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv)
5575 {
5576         mlx5e_netdev_change_profile(priv, &mlx5e_nic_profile, NULL);
5577 }
5578
5579 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5580 {
5581         struct net_device *netdev = priv->netdev;
5582
5583         mlx5e_priv_cleanup(priv);
5584         free_netdev(netdev);
5585 }
5586
5587 static int mlx5e_resume(struct auxiliary_device *adev)
5588 {
5589         struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5590         struct mlx5e_priv *priv = auxiliary_get_drvdata(adev);
5591         struct net_device *netdev = priv->netdev;
5592         struct mlx5_core_dev *mdev = edev->mdev;
5593         int err;
5594
5595         if (netif_device_present(netdev))
5596                 return 0;
5597
5598         err = mlx5e_create_mdev_resources(mdev);
5599         if (err)
5600                 return err;
5601
5602         err = mlx5e_attach_netdev(priv);
5603         if (err) {
5604                 mlx5e_destroy_mdev_resources(mdev);
5605                 return err;
5606         }
5607
5608         return 0;
5609 }
5610
5611 static int mlx5e_suspend(struct auxiliary_device *adev, pm_message_t state)
5612 {
5613         struct mlx5e_priv *priv = auxiliary_get_drvdata(adev);
5614         struct net_device *netdev = priv->netdev;
5615         struct mlx5_core_dev *mdev = priv->mdev;
5616
5617         if (!netif_device_present(netdev))
5618                 return -ENODEV;
5619
5620         mlx5e_detach_netdev(priv);
5621         mlx5e_destroy_mdev_resources(mdev);
5622         return 0;
5623 }
5624
5625 static int mlx5e_probe(struct auxiliary_device *adev,
5626                        const struct auxiliary_device_id *id)
5627 {
5628         struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5629         const struct mlx5e_profile *profile = &mlx5e_nic_profile;
5630         struct mlx5_core_dev *mdev = edev->mdev;
5631         struct net_device *netdev;
5632         pm_message_t state = {};
5633         struct mlx5e_priv *priv;
5634         int err;
5635
5636         netdev = mlx5e_create_netdev(mdev, profile);
5637         if (!netdev) {
5638                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5639                 return -ENOMEM;
5640         }
5641
5642         mlx5e_build_nic_netdev(netdev);
5643
5644         priv = netdev_priv(netdev);
5645         auxiliary_set_drvdata(adev, priv);
5646
5647         priv->profile = profile;
5648         priv->ppriv = NULL;
5649
5650         err = mlx5e_devlink_port_register(priv);
5651         if (err) {
5652                 mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err);
5653                 goto err_destroy_netdev;
5654         }
5655
5656         err = profile->init(mdev, netdev);
5657         if (err) {
5658                 mlx5_core_err(mdev, "mlx5e_nic_profile init failed, %d\n", err);
5659                 goto err_devlink_cleanup;
5660         }
5661
5662         err = mlx5e_resume(adev);
5663         if (err) {
5664                 mlx5_core_err(mdev, "mlx5e_resume failed, %d\n", err);
5665                 goto err_profile_cleanup;
5666         }
5667
5668         err = register_netdev(netdev);
5669         if (err) {
5670                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5671                 goto err_resume;
5672         }
5673
5674         mlx5e_devlink_port_type_eth_set(priv);
5675
5676         mlx5e_dcbnl_init_app(priv);
5677         mlx5_uplink_netdev_set(mdev, netdev);
5678         return 0;
5679
5680 err_resume:
5681         mlx5e_suspend(adev, state);
5682 err_profile_cleanup:
5683         profile->cleanup(priv);
5684 err_devlink_cleanup:
5685         mlx5e_devlink_port_unregister(priv);
5686 err_destroy_netdev:
5687         mlx5e_destroy_netdev(priv);
5688         return err;
5689 }
5690
5691 static void mlx5e_remove(struct auxiliary_device *adev)
5692 {
5693         struct mlx5e_priv *priv = auxiliary_get_drvdata(adev);
5694         pm_message_t state = {};
5695
5696         mlx5e_dcbnl_delete_app(priv);
5697         unregister_netdev(priv->netdev);
5698         mlx5e_suspend(adev, state);
5699         priv->profile->cleanup(priv);
5700         mlx5e_devlink_port_unregister(priv);
5701         mlx5e_destroy_netdev(priv);
5702 }
5703
5704 static const struct auxiliary_device_id mlx5e_id_table[] = {
5705         { .name = MLX5_ADEV_NAME ".eth", },
5706         {},
5707 };
5708
5709 MODULE_DEVICE_TABLE(auxiliary, mlx5e_id_table);
5710
5711 static struct auxiliary_driver mlx5e_driver = {
5712         .name = "eth",
5713         .probe = mlx5e_probe,
5714         .remove = mlx5e_remove,
5715         .suspend = mlx5e_suspend,
5716         .resume = mlx5e_resume,
5717         .id_table = mlx5e_id_table,
5718 };
5719
5720 int mlx5e_init(void)
5721 {
5722         int ret;
5723
5724         mlx5e_build_ptys2ethtool_map();
5725         ret = auxiliary_driver_register(&mlx5e_driver);
5726         if (ret)
5727                 return ret;
5728
5729         ret = mlx5e_rep_init();
5730         if (ret)
5731                 auxiliary_driver_unregister(&mlx5e_driver);
5732         return ret;
5733 }
5734
5735 void mlx5e_cleanup(void)
5736 {
5737         mlx5e_rep_cleanup();
5738         auxiliary_driver_unregister(&mlx5e_driver);
5739 }