2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 static void mlx5e_get_drvinfo(struct net_device *dev,
36 struct ethtool_drvinfo *drvinfo)
38 struct mlx5e_priv *priv = netdev_priv(dev);
39 struct mlx5_core_dev *mdev = priv->mdev;
41 strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
42 strlcpy(drvinfo->version, DRIVER_VERSION " (" DRIVER_RELDATE ")",
43 sizeof(drvinfo->version));
44 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
46 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev));
47 strlcpy(drvinfo->bus_info, pci_name(mdev->pdev),
48 sizeof(drvinfo->bus_info));
51 struct ptys2ethtool_config {
52 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
53 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
57 static struct ptys2ethtool_config ptys2ethtool_table[MLX5E_LINK_MODES_NUMBER];
59 #define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, speed_, ...) \
61 struct ptys2ethtool_config *cfg; \
62 const unsigned int modes[] = { __VA_ARGS__ }; \
64 cfg = &ptys2ethtool_table[reg_]; \
65 cfg->speed = speed_; \
66 bitmap_zero(cfg->supported, \
67 __ETHTOOL_LINK_MODE_MASK_NBITS); \
68 bitmap_zero(cfg->advertised, \
69 __ETHTOOL_LINK_MODE_MASK_NBITS); \
70 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
71 __set_bit(modes[i], cfg->supported); \
72 __set_bit(modes[i], cfg->advertised); \
76 void mlx5e_build_ptys2ethtool_map(void)
78 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, SPEED_1000,
79 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
80 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, SPEED_1000,
81 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
82 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, SPEED_10000,
83 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
84 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, SPEED_10000,
85 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
86 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, SPEED_10000,
87 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
88 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, SPEED_20000,
89 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
90 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, SPEED_40000,
91 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
92 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, SPEED_40000,
93 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
94 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, SPEED_56000,
95 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
96 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, SPEED_10000,
97 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
98 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, SPEED_10000,
99 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
100 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, SPEED_10000,
101 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
102 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, SPEED_40000,
103 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
104 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, SPEED_40000,
105 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
106 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, SPEED_50000,
107 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
108 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, SPEED_100000,
109 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
110 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, SPEED_100000,
111 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
112 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, SPEED_100000,
113 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
114 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, SPEED_100000,
115 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
116 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, SPEED_10000,
117 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
118 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, SPEED_25000,
119 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
120 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, SPEED_25000,
121 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
122 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, SPEED_25000,
123 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
124 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, SPEED_50000,
125 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
126 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, SPEED_50000,
127 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
130 static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv)
132 struct mlx5_core_dev *mdev = priv->mdev;
137 err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx);
139 return err ? 0 : pfc_en_tx | pfc_en_rx;
142 static bool mlx5e_query_global_pause_combined(struct mlx5e_priv *priv)
144 struct mlx5_core_dev *mdev = priv->mdev;
149 err = mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
151 return err ? false : rx_pause | tx_pause;
154 #define MLX5E_NUM_Q_CNTRS(priv) (NUM_Q_COUNTERS * (!!priv->q_counter))
155 #define MLX5E_NUM_RQ_STATS(priv) \
156 (NUM_RQ_STATS * priv->params.num_channels * \
157 test_bit(MLX5E_STATE_OPENED, &priv->state))
158 #define MLX5E_NUM_SQ_STATS(priv) \
159 (NUM_SQ_STATS * priv->params.num_channels * priv->params.num_tc * \
160 test_bit(MLX5E_STATE_OPENED, &priv->state))
161 #define MLX5E_NUM_PFC_COUNTERS(priv) \
162 ((mlx5e_query_global_pause_combined(priv) + hweight8(mlx5e_query_pfc_combined(priv))) * \
163 NUM_PPORT_PER_PRIO_PFC_COUNTERS)
165 static int mlx5e_get_sset_count(struct net_device *dev, int sset)
167 struct mlx5e_priv *priv = netdev_priv(dev);
171 return NUM_SW_COUNTERS +
172 MLX5E_NUM_Q_CNTRS(priv) +
173 NUM_VPORT_COUNTERS + NUM_PPORT_COUNTERS +
174 MLX5E_NUM_RQ_STATS(priv) +
175 MLX5E_NUM_SQ_STATS(priv) +
176 MLX5E_NUM_PFC_COUNTERS(priv);
177 case ETH_SS_PRIV_FLAGS:
178 return ARRAY_SIZE(mlx5e_priv_flags);
185 static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, uint8_t *data)
187 int i, j, tc, prio, idx = 0;
188 unsigned long pfc_combined;
191 for (i = 0; i < NUM_SW_COUNTERS; i++)
192 strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].format);
195 for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
196 strcpy(data + (idx++) * ETH_GSTRING_LEN, q_stats_desc[i].format);
199 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
200 strcpy(data + (idx++) * ETH_GSTRING_LEN,
201 vport_stats_desc[i].format);
204 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
205 strcpy(data + (idx++) * ETH_GSTRING_LEN,
206 pport_802_3_stats_desc[i].format);
208 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
209 strcpy(data + (idx++) * ETH_GSTRING_LEN,
210 pport_2863_stats_desc[i].format);
212 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
213 strcpy(data + (idx++) * ETH_GSTRING_LEN,
214 pport_2819_stats_desc[i].format);
216 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
217 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
218 sprintf(data + (idx++) * ETH_GSTRING_LEN,
219 pport_per_prio_traffic_stats_desc[i].format, prio);
222 pfc_combined = mlx5e_query_pfc_combined(priv);
223 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
224 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
225 char pfc_string[ETH_GSTRING_LEN];
227 snprintf(pfc_string, sizeof(pfc_string), "prio%d", prio);
228 sprintf(data + (idx++) * ETH_GSTRING_LEN,
229 pport_per_prio_pfc_stats_desc[i].format, pfc_string);
233 if (mlx5e_query_global_pause_combined(priv)) {
234 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
235 sprintf(data + (idx++) * ETH_GSTRING_LEN,
236 pport_per_prio_pfc_stats_desc[i].format, "global");
240 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
243 /* per channel counters */
244 for (i = 0; i < priv->params.num_channels; i++)
245 for (j = 0; j < NUM_RQ_STATS; j++)
246 sprintf(data + (idx++) * ETH_GSTRING_LEN,
247 rq_stats_desc[j].format, i);
249 for (tc = 0; tc < priv->params.num_tc; tc++)
250 for (i = 0; i < priv->params.num_channels; i++)
251 for (j = 0; j < NUM_SQ_STATS; j++)
252 sprintf(data + (idx++) * ETH_GSTRING_LEN,
253 sq_stats_desc[j].format,
254 priv->channeltc_to_txq_map[i][tc]);
257 static void mlx5e_get_strings(struct net_device *dev,
258 uint32_t stringset, uint8_t *data)
260 struct mlx5e_priv *priv = netdev_priv(dev);
264 case ETH_SS_PRIV_FLAGS:
265 for (i = 0; i < ARRAY_SIZE(mlx5e_priv_flags); i++)
266 strcpy(data + i * ETH_GSTRING_LEN, mlx5e_priv_flags[i]);
273 mlx5e_fill_stats_strings(priv, data);
278 static void mlx5e_get_ethtool_stats(struct net_device *dev,
279 struct ethtool_stats *stats, u64 *data)
281 struct mlx5e_priv *priv = netdev_priv(dev);
282 int i, j, tc, prio, idx = 0;
283 unsigned long pfc_combined;
288 mutex_lock(&priv->state_lock);
289 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
290 mlx5e_update_stats(priv);
291 mutex_unlock(&priv->state_lock);
293 for (i = 0; i < NUM_SW_COUNTERS; i++)
294 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw,
297 for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
298 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
301 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
302 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
303 vport_stats_desc, i);
305 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
306 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters,
307 pport_802_3_stats_desc, i);
309 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
310 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters,
311 pport_2863_stats_desc, i);
313 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
314 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters,
315 pport_2819_stats_desc, i);
317 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
318 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
319 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
320 pport_per_prio_traffic_stats_desc, i);
323 pfc_combined = mlx5e_query_pfc_combined(priv);
324 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
325 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
326 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
327 pport_per_prio_pfc_stats_desc, i);
331 if (mlx5e_query_global_pause_combined(priv)) {
332 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
333 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
334 pport_per_prio_pfc_stats_desc, 0);
338 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
341 /* per channel counters */
342 for (i = 0; i < priv->params.num_channels; i++)
343 for (j = 0; j < NUM_RQ_STATS; j++)
345 MLX5E_READ_CTR64_CPU(&priv->channel[i]->rq.stats,
348 for (tc = 0; tc < priv->params.num_tc; tc++)
349 for (i = 0; i < priv->params.num_channels; i++)
350 for (j = 0; j < NUM_SQ_STATS; j++)
351 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->channel[i]->sq[tc].stats,
355 static u32 mlx5e_rx_wqes_to_packets(struct mlx5e_priv *priv, int rq_wq_type,
363 if (rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
366 stride_size = 1 << priv->params.mpwqe_log_stride_sz;
367 num_strides = 1 << priv->params.mpwqe_log_num_strides;
368 wqe_size = stride_size * num_strides;
370 packets_per_wqe = wqe_size /
371 ALIGN(ETH_DATA_LEN, stride_size);
372 return (1 << (order_base_2(num_wqe * packets_per_wqe) - 1));
375 static u32 mlx5e_packets_to_rx_wqes(struct mlx5e_priv *priv, int rq_wq_type,
384 if (rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
387 stride_size = 1 << priv->params.mpwqe_log_stride_sz;
388 num_strides = 1 << priv->params.mpwqe_log_num_strides;
389 wqe_size = stride_size * num_strides;
391 num_packets = (1 << order_base_2(num_packets));
393 packets_per_wqe = wqe_size /
394 ALIGN(ETH_DATA_LEN, stride_size);
395 num_wqes = DIV_ROUND_UP(num_packets, packets_per_wqe);
396 return 1 << (order_base_2(num_wqes));
399 static void mlx5e_get_ringparam(struct net_device *dev,
400 struct ethtool_ringparam *param)
402 struct mlx5e_priv *priv = netdev_priv(dev);
403 int rq_wq_type = priv->params.rq_wq_type;
405 param->rx_max_pending = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
406 1 << mlx5_max_log_rq_size(rq_wq_type));
407 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
408 param->rx_pending = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
409 1 << priv->params.log_rq_size);
410 param->tx_pending = 1 << priv->params.log_sq_size;
413 static int mlx5e_set_ringparam(struct net_device *dev,
414 struct ethtool_ringparam *param)
416 struct mlx5e_priv *priv = netdev_priv(dev);
418 int rq_wq_type = priv->params.rq_wq_type;
428 if (param->rx_jumbo_pending) {
429 netdev_info(dev, "%s: rx_jumbo_pending not supported\n",
433 if (param->rx_mini_pending) {
434 netdev_info(dev, "%s: rx_mini_pending not supported\n",
439 min_rq_size = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
440 1 << mlx5_min_log_rq_size(rq_wq_type));
441 max_rq_size = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
442 1 << mlx5_max_log_rq_size(rq_wq_type));
443 rx_pending_wqes = mlx5e_packets_to_rx_wqes(priv, rq_wq_type,
446 if (param->rx_pending < min_rq_size) {
447 netdev_info(dev, "%s: rx_pending (%d) < min (%d)\n",
448 __func__, param->rx_pending,
452 if (param->rx_pending > max_rq_size) {
453 netdev_info(dev, "%s: rx_pending (%d) > max (%d)\n",
454 __func__, param->rx_pending,
459 num_mtts = MLX5E_REQUIRED_MTTS(priv->params.num_channels,
461 if (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
462 !MLX5E_VALID_NUM_MTTS(num_mtts)) {
463 netdev_info(dev, "%s: rx_pending (%d) request can't be satisfied, try to reduce.\n",
464 __func__, param->rx_pending);
468 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
469 netdev_info(dev, "%s: tx_pending (%d) < min (%d)\n",
470 __func__, param->tx_pending,
471 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
474 if (param->tx_pending > (1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE)) {
475 netdev_info(dev, "%s: tx_pending (%d) > max (%d)\n",
476 __func__, param->tx_pending,
477 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE);
481 log_rq_size = order_base_2(rx_pending_wqes);
482 log_sq_size = order_base_2(param->tx_pending);
483 min_rx_wqes = mlx5_min_rx_wqes(rq_wq_type, rx_pending_wqes);
485 if (log_rq_size == priv->params.log_rq_size &&
486 log_sq_size == priv->params.log_sq_size &&
487 min_rx_wqes == priv->params.min_rx_wqes)
490 mutex_lock(&priv->state_lock);
492 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
494 mlx5e_close_locked(dev);
496 priv->params.log_rq_size = log_rq_size;
497 priv->params.log_sq_size = log_sq_size;
498 priv->params.min_rx_wqes = min_rx_wqes;
501 err = mlx5e_open_locked(dev);
503 mutex_unlock(&priv->state_lock);
508 static void mlx5e_get_channels(struct net_device *dev,
509 struct ethtool_channels *ch)
511 struct mlx5e_priv *priv = netdev_priv(dev);
513 ch->max_combined = mlx5e_get_max_num_channels(priv->mdev);
514 ch->combined_count = priv->params.num_channels;
517 static int mlx5e_set_channels(struct net_device *dev,
518 struct ethtool_channels *ch)
520 struct mlx5e_priv *priv = netdev_priv(dev);
521 int ncv = mlx5e_get_max_num_channels(priv->mdev);
522 unsigned int count = ch->combined_count;
529 netdev_info(dev, "%s: combined_count=0 not supported\n",
533 if (ch->rx_count || ch->tx_count) {
534 netdev_info(dev, "%s: separate rx/tx count not supported\n",
539 netdev_info(dev, "%s: count (%d) > max (%d)\n",
540 __func__, count, ncv);
544 num_mtts = MLX5E_REQUIRED_MTTS(count, BIT(priv->params.log_rq_size));
545 if (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
546 !MLX5E_VALID_NUM_MTTS(num_mtts)) {
547 netdev_info(dev, "%s: rx count (%d) request can't be satisfied, try to reduce.\n",
552 if (priv->params.num_channels == count)
555 mutex_lock(&priv->state_lock);
557 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
559 mlx5e_close_locked(dev);
561 arfs_enabled = dev->features & NETIF_F_NTUPLE;
563 mlx5e_arfs_disable(priv);
565 priv->params.num_channels = count;
566 mlx5e_build_default_indir_rqt(priv->mdev, priv->params.indirection_rqt,
567 MLX5E_INDIR_RQT_SIZE, count);
570 err = mlx5e_open_locked(dev);
575 err = mlx5e_arfs_enable(priv);
577 netdev_err(dev, "%s: mlx5e_arfs_enable failed: %d\n",
582 mutex_unlock(&priv->state_lock);
587 static int mlx5e_get_coalesce(struct net_device *netdev,
588 struct ethtool_coalesce *coal)
590 struct mlx5e_priv *priv = netdev_priv(netdev);
592 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
595 coal->rx_coalesce_usecs = priv->params.rx_cq_moderation.usec;
596 coal->rx_max_coalesced_frames = priv->params.rx_cq_moderation.pkts;
597 coal->tx_coalesce_usecs = priv->params.tx_cq_moderation.usec;
598 coal->tx_max_coalesced_frames = priv->params.tx_cq_moderation.pkts;
599 coal->use_adaptive_rx_coalesce = priv->params.rx_am_enabled;
604 static int mlx5e_set_coalesce(struct net_device *netdev,
605 struct ethtool_coalesce *coal)
607 struct mlx5e_priv *priv = netdev_priv(netdev);
608 struct mlx5_core_dev *mdev = priv->mdev;
609 struct mlx5e_channel *c;
611 !!coal->use_adaptive_rx_coalesce != priv->params.rx_am_enabled;
617 if (!MLX5_CAP_GEN(mdev, cq_moderation))
620 mutex_lock(&priv->state_lock);
622 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
623 if (was_opened && restart) {
624 mlx5e_close_locked(netdev);
625 priv->params.rx_am_enabled = !!coal->use_adaptive_rx_coalesce;
628 priv->params.tx_cq_moderation.usec = coal->tx_coalesce_usecs;
629 priv->params.tx_cq_moderation.pkts = coal->tx_max_coalesced_frames;
630 priv->params.rx_cq_moderation.usec = coal->rx_coalesce_usecs;
631 priv->params.rx_cq_moderation.pkts = coal->rx_max_coalesced_frames;
633 if (!was_opened || restart)
636 for (i = 0; i < priv->params.num_channels; ++i) {
637 c = priv->channel[i];
639 for (tc = 0; tc < c->num_tc; tc++) {
640 mlx5_core_modify_cq_moderation(mdev,
642 coal->tx_coalesce_usecs,
643 coal->tx_max_coalesced_frames);
646 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
647 coal->rx_coalesce_usecs,
648 coal->rx_max_coalesced_frames);
652 if (was_opened && restart)
653 err = mlx5e_open_locked(netdev);
655 mutex_unlock(&priv->state_lock);
659 static void ptys2ethtool_supported_link(unsigned long *supported_modes,
664 for_each_set_bit(proto, (unsigned long *)ð_proto_cap, MLX5E_LINK_MODES_NUMBER)
665 bitmap_or(supported_modes, supported_modes,
666 ptys2ethtool_table[proto].supported,
667 __ETHTOOL_LINK_MODE_MASK_NBITS);
670 static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
675 for_each_set_bit(proto, (unsigned long *)ð_proto_cap, MLX5E_LINK_MODES_NUMBER)
676 bitmap_or(advertising_modes, advertising_modes,
677 ptys2ethtool_table[proto].advertised,
678 __ETHTOOL_LINK_MODE_MASK_NBITS);
681 static void ptys2ethtool_supported_port(struct ethtool_link_ksettings *link_ksettings,
684 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
685 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
686 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
687 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
688 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
689 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
690 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, FIBRE);
693 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
694 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
695 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
696 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
697 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
698 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Backplane);
702 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed)
709 err = mlx5_query_port_proto_cap(mdev, &proto_cap, MLX5_PTYS_EN);
713 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i)
714 if (proto_cap & MLX5E_PROT_MASK(i))
715 max_speed = max(max_speed, ptys2ethtool_table[i].speed);
721 static void get_speed_duplex(struct net_device *netdev,
723 struct ethtool_link_ksettings *link_ksettings)
726 u32 speed = SPEED_UNKNOWN;
727 u8 duplex = DUPLEX_UNKNOWN;
729 if (!netif_carrier_ok(netdev))
732 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
733 if (eth_proto_oper & MLX5E_PROT_MASK(i)) {
734 speed = ptys2ethtool_table[i].speed;
735 duplex = DUPLEX_FULL;
740 link_ksettings->base.speed = speed;
741 link_ksettings->base.duplex = duplex;
744 static void get_supported(u32 eth_proto_cap,
745 struct ethtool_link_ksettings *link_ksettings)
747 unsigned long *supported = link_ksettings->link_modes.supported;
749 ptys2ethtool_supported_port(link_ksettings, eth_proto_cap);
750 ptys2ethtool_supported_link(supported, eth_proto_cap);
751 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
752 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Asym_Pause);
755 static void get_advertising(u32 eth_proto_cap, u8 tx_pause,
757 struct ethtool_link_ksettings *link_ksettings)
759 unsigned long *advertising = link_ksettings->link_modes.advertising;
761 ptys2ethtool_adver_link(advertising, eth_proto_cap);
763 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
764 if (tx_pause ^ rx_pause)
765 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
768 static u8 get_connector_port(u32 eth_proto)
770 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
771 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
772 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
773 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
777 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
778 | MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
779 | MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
783 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
784 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
785 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
786 | MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
793 static void get_lp_advertising(u32 eth_proto_lp,
794 struct ethtool_link_ksettings *link_ksettings)
796 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
798 ptys2ethtool_adver_link(lp_advertising, eth_proto_lp);
801 static int mlx5e_get_link_ksettings(struct net_device *netdev,
802 struct ethtool_link_ksettings *link_ksettings)
804 struct mlx5e_priv *priv = netdev_priv(netdev);
805 struct mlx5_core_dev *mdev = priv->mdev;
806 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
815 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
818 netdev_err(netdev, "%s: query port ptys failed: %d\n",
823 eth_proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
824 eth_proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
825 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
826 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
827 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
828 an_status = MLX5_GET(ptys_reg, out, an_status);
830 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
831 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
833 get_supported(eth_proto_cap, link_ksettings);
834 get_advertising(eth_proto_admin, 0, 0, link_ksettings);
835 get_speed_duplex(netdev, eth_proto_oper, link_ksettings);
837 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
839 link_ksettings->base.port = get_connector_port(eth_proto_oper);
840 get_lp_advertising(eth_proto_lp, link_ksettings);
842 if (an_status == MLX5_AN_COMPLETE)
843 ethtool_link_ksettings_add_link_mode(link_ksettings,
844 lp_advertising, Autoneg);
846 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
848 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
850 if (!an_disable_admin)
851 ethtool_link_ksettings_add_link_mode(link_ksettings,
852 advertising, Autoneg);
858 static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
860 u32 i, ptys_modes = 0;
862 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
863 if (bitmap_intersects(ptys2ethtool_table[i].advertised,
865 __ETHTOOL_LINK_MODE_MASK_NBITS))
866 ptys_modes |= MLX5E_PROT_MASK(i);
872 static u32 mlx5e_ethtool2ptys_speed_link(u32 speed)
874 u32 i, speed_links = 0;
876 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
877 if (ptys2ethtool_table[i].speed == speed)
878 speed_links |= MLX5E_PROT_MASK(i);
884 static int mlx5e_set_link_ksettings(struct net_device *netdev,
885 const struct ethtool_link_ksettings *link_ksettings)
887 struct mlx5e_priv *priv = netdev_priv(netdev);
888 struct mlx5_core_dev *mdev = priv->mdev;
889 u32 eth_proto_cap, eth_proto_admin;
890 bool an_changes = false;
899 speed = link_ksettings->base.speed;
901 link_modes = link_ksettings->base.autoneg == AUTONEG_ENABLE ?
902 mlx5e_ethtool2ptys_adver_link(link_ksettings->link_modes.advertising) :
903 mlx5e_ethtool2ptys_speed_link(speed);
905 err = mlx5_query_port_proto_cap(mdev, ð_proto_cap, MLX5_PTYS_EN);
907 netdev_err(netdev, "%s: query port eth proto cap failed: %d\n",
912 link_modes = link_modes & eth_proto_cap;
914 netdev_err(netdev, "%s: Not supported link mode(s) requested",
920 err = mlx5_query_port_proto_admin(mdev, ð_proto_admin, MLX5_PTYS_EN);
922 netdev_err(netdev, "%s: query port eth proto admin failed: %d\n",
927 mlx5_query_port_autoneg(mdev, MLX5_PTYS_EN, &an_status,
928 &an_disable_cap, &an_disable_admin);
930 an_disable = link_ksettings->base.autoneg == AUTONEG_DISABLE;
931 an_changes = ((!an_disable && an_disable_admin) ||
932 (an_disable && !an_disable_admin));
934 if (!an_changes && link_modes == eth_proto_admin)
937 mlx5_set_port_ptys(mdev, an_disable, link_modes, MLX5_PTYS_EN);
938 mlx5_toggle_port_link(mdev);
944 static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
946 struct mlx5e_priv *priv = netdev_priv(netdev);
948 return sizeof(priv->params.toeplitz_hash_key);
951 static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
953 return MLX5E_INDIR_RQT_SIZE;
956 static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
959 struct mlx5e_priv *priv = netdev_priv(netdev);
962 memcpy(indir, priv->params.indirection_rqt,
963 sizeof(priv->params.indirection_rqt));
966 memcpy(key, priv->params.toeplitz_hash_key,
967 sizeof(priv->params.toeplitz_hash_key));
970 *hfunc = priv->params.rss_hfunc;
975 static void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
977 struct mlx5_core_dev *mdev = priv->mdev;
978 void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
981 MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
982 mlx5e_build_tir_ctx_hash(tirc, priv);
984 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
985 mlx5_core_modify_tir(mdev, priv->indir_tir[i].tirn, in, inlen);
988 static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
989 const u8 *key, const u8 hfunc)
991 struct mlx5e_priv *priv = netdev_priv(dev);
992 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
995 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
996 (hfunc != ETH_RSS_HASH_XOR) &&
997 (hfunc != ETH_RSS_HASH_TOP))
1000 in = mlx5_vzalloc(inlen);
1004 mutex_lock(&priv->state_lock);
1007 u32 rqtn = priv->indir_rqt.rqtn;
1009 memcpy(priv->params.indirection_rqt, indir,
1010 sizeof(priv->params.indirection_rqt));
1011 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1015 memcpy(priv->params.toeplitz_hash_key, key,
1016 sizeof(priv->params.toeplitz_hash_key));
1018 if (hfunc != ETH_RSS_HASH_NO_CHANGE)
1019 priv->params.rss_hfunc = hfunc;
1021 mlx5e_modify_tirs_hash(priv, in, inlen);
1023 mutex_unlock(&priv->state_lock);
1030 static int mlx5e_get_rxnfc(struct net_device *netdev,
1031 struct ethtool_rxnfc *info, u32 *rule_locs)
1033 struct mlx5e_priv *priv = netdev_priv(netdev);
1036 switch (info->cmd) {
1037 case ETHTOOL_GRXRINGS:
1038 info->data = priv->params.num_channels;
1040 case ETHTOOL_GRXCLSRLCNT:
1041 info->rule_cnt = priv->fs.ethtool.tot_num_rules;
1043 case ETHTOOL_GRXCLSRULE:
1044 err = mlx5e_ethtool_get_flow(priv, info, info->fs.location);
1046 case ETHTOOL_GRXCLSRLALL:
1047 err = mlx5e_ethtool_get_all_flows(priv, info, rule_locs);
1057 static int mlx5e_get_tunable(struct net_device *dev,
1058 const struct ethtool_tunable *tuna,
1061 const struct mlx5e_priv *priv = netdev_priv(dev);
1065 case ETHTOOL_TX_COPYBREAK:
1066 *(u32 *)data = priv->params.tx_max_inline;
1076 static int mlx5e_set_tunable(struct net_device *dev,
1077 const struct ethtool_tunable *tuna,
1080 struct mlx5e_priv *priv = netdev_priv(dev);
1081 struct mlx5_core_dev *mdev = priv->mdev;
1087 case ETHTOOL_TX_COPYBREAK:
1089 if (val > mlx5e_get_max_inline_cap(mdev)) {
1094 mutex_lock(&priv->state_lock);
1096 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1098 mlx5e_close_locked(dev);
1100 priv->params.tx_max_inline = val;
1103 err = mlx5e_open_locked(dev);
1105 mutex_unlock(&priv->state_lock);
1115 static void mlx5e_get_pauseparam(struct net_device *netdev,
1116 struct ethtool_pauseparam *pauseparam)
1118 struct mlx5e_priv *priv = netdev_priv(netdev);
1119 struct mlx5_core_dev *mdev = priv->mdev;
1122 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1123 &pauseparam->tx_pause);
1125 netdev_err(netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1130 static int mlx5e_set_pauseparam(struct net_device *netdev,
1131 struct ethtool_pauseparam *pauseparam)
1133 struct mlx5e_priv *priv = netdev_priv(netdev);
1134 struct mlx5_core_dev *mdev = priv->mdev;
1137 if (pauseparam->autoneg)
1140 err = mlx5_set_port_pause(mdev,
1141 pauseparam->rx_pause ? 1 : 0,
1142 pauseparam->tx_pause ? 1 : 0);
1144 netdev_err(netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1151 static int mlx5e_get_ts_info(struct net_device *dev,
1152 struct ethtool_ts_info *info)
1154 struct mlx5e_priv *priv = netdev_priv(dev);
1157 ret = ethtool_op_get_ts_info(dev, info);
1161 info->phc_index = priv->tstamp.ptp ?
1162 ptp_clock_index(priv->tstamp.ptp) : -1;
1164 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
1167 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
1168 SOF_TIMESTAMPING_RX_HARDWARE |
1169 SOF_TIMESTAMPING_RAW_HARDWARE;
1171 info->tx_types = (BIT(1) << HWTSTAMP_TX_OFF) |
1172 (BIT(1) << HWTSTAMP_TX_ON);
1174 info->rx_filters = (BIT(1) << HWTSTAMP_FILTER_NONE) |
1175 (BIT(1) << HWTSTAMP_FILTER_ALL);
1180 static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1184 if (MLX5_CAP_GEN(mdev, wol_g))
1187 if (MLX5_CAP_GEN(mdev, wol_s))
1188 ret |= WAKE_MAGICSECURE;
1190 if (MLX5_CAP_GEN(mdev, wol_a))
1193 if (MLX5_CAP_GEN(mdev, wol_b))
1196 if (MLX5_CAP_GEN(mdev, wol_m))
1199 if (MLX5_CAP_GEN(mdev, wol_u))
1202 if (MLX5_CAP_GEN(mdev, wol_p))
1208 static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode)
1212 if (mode & MLX5_WOL_MAGIC)
1215 if (mode & MLX5_WOL_SECURED_MAGIC)
1216 ret |= WAKE_MAGICSECURE;
1218 if (mode & MLX5_WOL_ARP)
1221 if (mode & MLX5_WOL_BROADCAST)
1224 if (mode & MLX5_WOL_MULTICAST)
1227 if (mode & MLX5_WOL_UNICAST)
1230 if (mode & MLX5_WOL_PHY_ACTIVITY)
1236 static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode)
1240 if (mode & WAKE_MAGIC)
1241 ret |= MLX5_WOL_MAGIC;
1243 if (mode & WAKE_MAGICSECURE)
1244 ret |= MLX5_WOL_SECURED_MAGIC;
1246 if (mode & WAKE_ARP)
1247 ret |= MLX5_WOL_ARP;
1249 if (mode & WAKE_BCAST)
1250 ret |= MLX5_WOL_BROADCAST;
1252 if (mode & WAKE_MCAST)
1253 ret |= MLX5_WOL_MULTICAST;
1255 if (mode & WAKE_UCAST)
1256 ret |= MLX5_WOL_UNICAST;
1258 if (mode & WAKE_PHY)
1259 ret |= MLX5_WOL_PHY_ACTIVITY;
1264 static void mlx5e_get_wol(struct net_device *netdev,
1265 struct ethtool_wolinfo *wol)
1267 struct mlx5e_priv *priv = netdev_priv(netdev);
1268 struct mlx5_core_dev *mdev = priv->mdev;
1272 memset(wol, 0, sizeof(*wol));
1274 wol->supported = mlx5e_get_wol_supported(mdev);
1275 if (!wol->supported)
1278 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1282 wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1285 static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1287 struct mlx5e_priv *priv = netdev_priv(netdev);
1288 struct mlx5_core_dev *mdev = priv->mdev;
1289 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1295 if (wol->wolopts & ~wol_supported)
1298 mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts);
1300 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1303 static int mlx5e_set_phys_id(struct net_device *dev,
1304 enum ethtool_phys_id_state state)
1306 struct mlx5e_priv *priv = netdev_priv(dev);
1307 struct mlx5_core_dev *mdev = priv->mdev;
1308 u16 beacon_duration;
1310 if (!MLX5_CAP_GEN(mdev, beacon_led))
1314 case ETHTOOL_ID_ACTIVE:
1315 beacon_duration = MLX5_BEACON_DURATION_INF;
1317 case ETHTOOL_ID_INACTIVE:
1318 beacon_duration = MLX5_BEACON_DURATION_OFF;
1324 return mlx5_set_port_beacon(mdev, beacon_duration);
1327 static int mlx5e_get_module_info(struct net_device *netdev,
1328 struct ethtool_modinfo *modinfo)
1330 struct mlx5e_priv *priv = netdev_priv(netdev);
1331 struct mlx5_core_dev *dev = priv->mdev;
1335 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1339 /* data[0] = identifier byte */
1341 case MLX5_MODULE_ID_QSFP:
1342 modinfo->type = ETH_MODULE_SFF_8436;
1343 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1345 case MLX5_MODULE_ID_QSFP_PLUS:
1346 case MLX5_MODULE_ID_QSFP28:
1347 /* data[1] = revision id */
1348 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1349 modinfo->type = ETH_MODULE_SFF_8636;
1350 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1352 modinfo->type = ETH_MODULE_SFF_8436;
1353 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1356 case MLX5_MODULE_ID_SFP:
1357 modinfo->type = ETH_MODULE_SFF_8472;
1358 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1361 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1369 static int mlx5e_get_module_eeprom(struct net_device *netdev,
1370 struct ethtool_eeprom *ee,
1373 struct mlx5e_priv *priv = netdev_priv(netdev);
1374 struct mlx5_core_dev *mdev = priv->mdev;
1375 int offset = ee->offset;
1382 memset(data, 0, ee->len);
1384 while (i < ee->len) {
1385 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1392 if (size_read < 0) {
1393 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1394 __func__, size_read);
1399 offset += size_read;
1405 typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
1407 static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
1409 struct mlx5e_priv *priv = netdev_priv(netdev);
1410 struct mlx5_core_dev *mdev = priv->mdev;
1411 bool rx_mode_changed;
1412 u8 rx_cq_period_mode;
1416 rx_cq_period_mode = enable ?
1417 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1418 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1419 rx_mode_changed = rx_cq_period_mode != priv->params.rx_cq_period_mode;
1421 if (rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
1422 !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
1425 if (!rx_mode_changed)
1428 reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
1430 mlx5e_close_locked(netdev);
1432 mlx5e_set_rx_cq_mode_params(&priv->params, rx_cq_period_mode);
1435 err = mlx5e_open_locked(netdev);
1440 static int mlx5e_handle_pflag(struct net_device *netdev,
1442 enum mlx5e_priv_flag flag,
1443 mlx5e_pflag_handler pflag_handler)
1445 struct mlx5e_priv *priv = netdev_priv(netdev);
1446 bool enable = !!(wanted_flags & flag);
1447 u32 changes = wanted_flags ^ priv->pflags;
1450 if (!(changes & flag))
1453 err = pflag_handler(netdev, enable);
1455 netdev_err(netdev, "%s private flag 0x%x failed err %d\n",
1456 enable ? "Enable" : "Disable", flag, err);
1460 MLX5E_SET_PRIV_FLAG(priv, flag, enable);
1464 static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
1466 struct mlx5e_priv *priv = netdev_priv(netdev);
1469 mutex_lock(&priv->state_lock);
1471 err = mlx5e_handle_pflag(netdev, pflags,
1472 MLX5E_PFLAG_RX_CQE_BASED_MODER,
1473 set_pflag_rx_cqe_based_moder);
1475 mutex_unlock(&priv->state_lock);
1476 return err ? -EINVAL : 0;
1479 static u32 mlx5e_get_priv_flags(struct net_device *netdev)
1481 struct mlx5e_priv *priv = netdev_priv(netdev);
1483 return priv->pflags;
1486 static int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1489 struct mlx5e_priv *priv = netdev_priv(dev);
1492 case ETHTOOL_SRXCLSRLINS:
1493 err = mlx5e_ethtool_flow_replace(priv, &cmd->fs);
1495 case ETHTOOL_SRXCLSRLDEL:
1496 err = mlx5e_ethtool_flow_remove(priv, cmd->fs.location);
1506 const struct ethtool_ops mlx5e_ethtool_ops = {
1507 .get_drvinfo = mlx5e_get_drvinfo,
1508 .get_link = ethtool_op_get_link,
1509 .get_strings = mlx5e_get_strings,
1510 .get_sset_count = mlx5e_get_sset_count,
1511 .get_ethtool_stats = mlx5e_get_ethtool_stats,
1512 .get_ringparam = mlx5e_get_ringparam,
1513 .set_ringparam = mlx5e_set_ringparam,
1514 .get_channels = mlx5e_get_channels,
1515 .set_channels = mlx5e_set_channels,
1516 .get_coalesce = mlx5e_get_coalesce,
1517 .set_coalesce = mlx5e_set_coalesce,
1518 .get_link_ksettings = mlx5e_get_link_ksettings,
1519 .set_link_ksettings = mlx5e_set_link_ksettings,
1520 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
1521 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
1522 .get_rxfh = mlx5e_get_rxfh,
1523 .set_rxfh = mlx5e_set_rxfh,
1524 .get_rxnfc = mlx5e_get_rxnfc,
1525 .set_rxnfc = mlx5e_set_rxnfc,
1526 .get_tunable = mlx5e_get_tunable,
1527 .set_tunable = mlx5e_set_tunable,
1528 .get_pauseparam = mlx5e_get_pauseparam,
1529 .set_pauseparam = mlx5e_set_pauseparam,
1530 .get_ts_info = mlx5e_get_ts_info,
1531 .set_phys_id = mlx5e_set_phys_id,
1532 .get_wol = mlx5e_get_wol,
1533 .set_wol = mlx5e_set_wol,
1534 .get_module_info = mlx5e_get_module_info,
1535 .get_module_eeprom = mlx5e_get_module_eeprom,
1536 .get_priv_flags = mlx5e_get_priv_flags,
1537 .set_priv_flags = mlx5e_set_priv_flags