2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 static void mlx5e_get_drvinfo(struct net_device *dev,
36 struct ethtool_drvinfo *drvinfo)
38 struct mlx5e_priv *priv = netdev_priv(dev);
39 struct mlx5_core_dev *mdev = priv->mdev;
41 strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
42 strlcpy(drvinfo->version, DRIVER_VERSION " (" DRIVER_RELDATE ")",
43 sizeof(drvinfo->version));
44 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
46 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev));
47 strlcpy(drvinfo->bus_info, pci_name(mdev->pdev),
48 sizeof(drvinfo->bus_info));
55 } ptys2ethtool_table[MLX5E_LINK_MODES_NUMBER] = {
56 [MLX5E_1000BASE_CX_SGMII] = {
57 .supported = SUPPORTED_1000baseKX_Full,
58 .advertised = ADVERTISED_1000baseKX_Full,
61 [MLX5E_1000BASE_KX] = {
62 .supported = SUPPORTED_1000baseKX_Full,
63 .advertised = ADVERTISED_1000baseKX_Full,
66 [MLX5E_10GBASE_CX4] = {
67 .supported = SUPPORTED_10000baseKX4_Full,
68 .advertised = ADVERTISED_10000baseKX4_Full,
71 [MLX5E_10GBASE_KX4] = {
72 .supported = SUPPORTED_10000baseKX4_Full,
73 .advertised = ADVERTISED_10000baseKX4_Full,
76 [MLX5E_10GBASE_KR] = {
77 .supported = SUPPORTED_10000baseKR_Full,
78 .advertised = ADVERTISED_10000baseKR_Full,
81 [MLX5E_20GBASE_KR2] = {
82 .supported = SUPPORTED_20000baseKR2_Full,
83 .advertised = ADVERTISED_20000baseKR2_Full,
86 [MLX5E_40GBASE_CR4] = {
87 .supported = SUPPORTED_40000baseCR4_Full,
88 .advertised = ADVERTISED_40000baseCR4_Full,
91 [MLX5E_40GBASE_KR4] = {
92 .supported = SUPPORTED_40000baseKR4_Full,
93 .advertised = ADVERTISED_40000baseKR4_Full,
96 [MLX5E_56GBASE_R4] = {
97 .supported = SUPPORTED_56000baseKR4_Full,
98 .advertised = ADVERTISED_56000baseKR4_Full,
101 [MLX5E_10GBASE_CR] = {
102 .supported = SUPPORTED_10000baseKR_Full,
103 .advertised = ADVERTISED_10000baseKR_Full,
106 [MLX5E_10GBASE_SR] = {
107 .supported = SUPPORTED_10000baseKR_Full,
108 .advertised = ADVERTISED_10000baseKR_Full,
111 [MLX5E_10GBASE_ER] = {
112 .supported = SUPPORTED_10000baseKR_Full,
113 .advertised = ADVERTISED_10000baseKR_Full,
116 [MLX5E_40GBASE_SR4] = {
117 .supported = SUPPORTED_40000baseSR4_Full,
118 .advertised = ADVERTISED_40000baseSR4_Full,
121 [MLX5E_40GBASE_LR4] = {
122 .supported = SUPPORTED_40000baseLR4_Full,
123 .advertised = ADVERTISED_40000baseLR4_Full,
126 [MLX5E_100GBASE_CR4] = {
129 [MLX5E_100GBASE_SR4] = {
132 [MLX5E_100GBASE_KR4] = {
135 [MLX5E_100GBASE_LR4] = {
138 [MLX5E_100BASE_TX] = {
141 [MLX5E_100BASE_T] = {
142 .supported = SUPPORTED_100baseT_Full,
143 .advertised = ADVERTISED_100baseT_Full,
146 [MLX5E_10GBASE_T] = {
147 .supported = SUPPORTED_10000baseT_Full,
148 .advertised = ADVERTISED_10000baseT_Full,
151 [MLX5E_25GBASE_CR] = {
154 [MLX5E_25GBASE_KR] = {
157 [MLX5E_25GBASE_SR] = {
160 [MLX5E_50GBASE_CR2] = {
163 [MLX5E_50GBASE_KR2] = {
168 static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv)
170 struct mlx5_core_dev *mdev = priv->mdev;
175 err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx);
177 return err ? 0 : pfc_en_tx | pfc_en_rx;
180 #define MLX5E_NUM_Q_CNTRS(priv) (NUM_Q_COUNTERS * (!!priv->q_counter))
181 #define MLX5E_NUM_RQ_STATS(priv) \
182 (NUM_RQ_STATS * priv->params.num_channels * \
183 test_bit(MLX5E_STATE_OPENED, &priv->state))
184 #define MLX5E_NUM_SQ_STATS(priv) \
185 (NUM_SQ_STATS * priv->params.num_channels * priv->params.num_tc * \
186 test_bit(MLX5E_STATE_OPENED, &priv->state))
187 #define MLX5E_NUM_PFC_COUNTERS(priv) hweight8(mlx5e_query_pfc_combined(priv))
189 static int mlx5e_get_sset_count(struct net_device *dev, int sset)
191 struct mlx5e_priv *priv = netdev_priv(dev);
195 return NUM_SW_COUNTERS +
196 MLX5E_NUM_Q_CNTRS(priv) +
197 NUM_VPORT_COUNTERS + NUM_PPORT_COUNTERS +
198 MLX5E_NUM_RQ_STATS(priv) +
199 MLX5E_NUM_SQ_STATS(priv) +
200 MLX5E_NUM_PFC_COUNTERS(priv);
207 static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, uint8_t *data)
209 int i, j, tc, prio, idx = 0;
210 unsigned long pfc_combined;
213 for (i = 0; i < NUM_SW_COUNTERS; i++)
214 strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].name);
217 for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
218 strcpy(data + (idx++) * ETH_GSTRING_LEN, q_stats_desc[i].name);
221 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
222 strcpy(data + (idx++) * ETH_GSTRING_LEN,
223 vport_stats_desc[i].name);
226 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
227 strcpy(data + (idx++) * ETH_GSTRING_LEN,
228 pport_802_3_stats_desc[i].name);
230 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
231 strcpy(data + (idx++) * ETH_GSTRING_LEN,
232 pport_2863_stats_desc[i].name);
234 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
235 strcpy(data + (idx++) * ETH_GSTRING_LEN,
236 pport_2819_stats_desc[i].name);
238 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
239 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
240 sprintf(data + (idx++) * ETH_GSTRING_LEN, "prio%d_%s",
242 pport_per_prio_traffic_stats_desc[i].name);
245 pfc_combined = mlx5e_query_pfc_combined(priv);
246 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
247 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
248 sprintf(data + (idx++) * ETH_GSTRING_LEN, "prio%d_%s",
249 prio, pport_per_prio_pfc_stats_desc[i].name);
253 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
256 /* per channel counters */
257 for (i = 0; i < priv->params.num_channels; i++)
258 for (j = 0; j < NUM_RQ_STATS; j++)
259 sprintf(data + (idx++) * ETH_GSTRING_LEN, "rx%d_%s", i,
260 rq_stats_desc[j].name);
262 for (tc = 0; tc < priv->params.num_tc; tc++)
263 for (i = 0; i < priv->params.num_channels; i++)
264 for (j = 0; j < NUM_SQ_STATS; j++)
265 sprintf(data + (idx++) * ETH_GSTRING_LEN,
267 priv->channeltc_to_txq_map[i][tc],
268 sq_stats_desc[j].name);
271 static void mlx5e_get_strings(struct net_device *dev,
272 uint32_t stringset, uint8_t *data)
274 struct mlx5e_priv *priv = netdev_priv(dev);
277 case ETH_SS_PRIV_FLAGS:
284 mlx5e_fill_stats_strings(priv, data);
289 static void mlx5e_get_ethtool_stats(struct net_device *dev,
290 struct ethtool_stats *stats, u64 *data)
292 struct mlx5e_priv *priv = netdev_priv(dev);
293 int i, j, tc, prio, idx = 0;
294 unsigned long pfc_combined;
299 mutex_lock(&priv->state_lock);
300 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
301 mlx5e_update_stats(priv);
302 mutex_unlock(&priv->state_lock);
304 for (i = 0; i < NUM_SW_COUNTERS; i++)
305 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw,
308 for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
309 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
312 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
313 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
314 vport_stats_desc, i);
316 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
317 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters,
318 pport_802_3_stats_desc, i);
320 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
321 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters,
322 pport_2863_stats_desc, i);
324 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
325 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters,
326 pport_2819_stats_desc, i);
328 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
329 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
330 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
331 pport_per_prio_traffic_stats_desc, i);
334 pfc_combined = mlx5e_query_pfc_combined(priv);
335 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
336 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
337 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
338 pport_per_prio_pfc_stats_desc, i);
342 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
345 /* per channel counters */
346 for (i = 0; i < priv->params.num_channels; i++)
347 for (j = 0; j < NUM_RQ_STATS; j++)
349 MLX5E_READ_CTR64_CPU(&priv->channel[i]->rq.stats,
352 for (tc = 0; tc < priv->params.num_tc; tc++)
353 for (i = 0; i < priv->params.num_channels; i++)
354 for (j = 0; j < NUM_SQ_STATS; j++)
355 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->channel[i]->sq[tc].stats,
359 static void mlx5e_get_ringparam(struct net_device *dev,
360 struct ethtool_ringparam *param)
362 struct mlx5e_priv *priv = netdev_priv(dev);
363 int rq_wq_type = priv->params.rq_wq_type;
365 param->rx_max_pending = 1 << mlx5_max_log_rq_size(rq_wq_type);
366 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
367 param->rx_pending = 1 << priv->params.log_rq_size;
368 param->tx_pending = 1 << priv->params.log_sq_size;
371 static int mlx5e_set_ringparam(struct net_device *dev,
372 struct ethtool_ringparam *param)
374 struct mlx5e_priv *priv = netdev_priv(dev);
376 int rq_wq_type = priv->params.rq_wq_type;
382 if (param->rx_jumbo_pending) {
383 netdev_info(dev, "%s: rx_jumbo_pending not supported\n",
387 if (param->rx_mini_pending) {
388 netdev_info(dev, "%s: rx_mini_pending not supported\n",
392 if (param->rx_pending < (1 << mlx5_min_log_rq_size(rq_wq_type))) {
393 netdev_info(dev, "%s: rx_pending (%d) < min (%d)\n",
394 __func__, param->rx_pending,
395 1 << mlx5_min_log_rq_size(rq_wq_type));
398 if (param->rx_pending > (1 << mlx5_max_log_rq_size(rq_wq_type))) {
399 netdev_info(dev, "%s: rx_pending (%d) > max (%d)\n",
400 __func__, param->rx_pending,
401 1 << mlx5_max_log_rq_size(rq_wq_type));
404 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
405 netdev_info(dev, "%s: tx_pending (%d) < min (%d)\n",
406 __func__, param->tx_pending,
407 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
410 if (param->tx_pending > (1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE)) {
411 netdev_info(dev, "%s: tx_pending (%d) > max (%d)\n",
412 __func__, param->tx_pending,
413 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE);
417 log_rq_size = order_base_2(param->rx_pending);
418 log_sq_size = order_base_2(param->tx_pending);
419 min_rx_wqes = mlx5_min_rx_wqes(rq_wq_type, param->rx_pending);
421 if (log_rq_size == priv->params.log_rq_size &&
422 log_sq_size == priv->params.log_sq_size &&
423 min_rx_wqes == priv->params.min_rx_wqes)
426 mutex_lock(&priv->state_lock);
428 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
430 mlx5e_close_locked(dev);
432 priv->params.log_rq_size = log_rq_size;
433 priv->params.log_sq_size = log_sq_size;
434 priv->params.min_rx_wqes = min_rx_wqes;
437 err = mlx5e_open_locked(dev);
439 mutex_unlock(&priv->state_lock);
444 static void mlx5e_get_channels(struct net_device *dev,
445 struct ethtool_channels *ch)
447 struct mlx5e_priv *priv = netdev_priv(dev);
449 ch->max_combined = mlx5e_get_max_num_channels(priv->mdev);
450 ch->combined_count = priv->params.num_channels;
453 static int mlx5e_set_channels(struct net_device *dev,
454 struct ethtool_channels *ch)
456 struct mlx5e_priv *priv = netdev_priv(dev);
457 int ncv = mlx5e_get_max_num_channels(priv->mdev);
458 unsigned int count = ch->combined_count;
463 netdev_info(dev, "%s: combined_count=0 not supported\n",
467 if (ch->rx_count || ch->tx_count) {
468 netdev_info(dev, "%s: separate rx/tx count not supported\n",
473 netdev_info(dev, "%s: count (%d) > max (%d)\n",
474 __func__, count, ncv);
478 if (priv->params.num_channels == count)
481 mutex_lock(&priv->state_lock);
483 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
485 mlx5e_close_locked(dev);
487 priv->params.num_channels = count;
488 mlx5e_build_default_indir_rqt(priv->mdev, priv->params.indirection_rqt,
489 MLX5E_INDIR_RQT_SIZE, count);
492 err = mlx5e_open_locked(dev);
494 mutex_unlock(&priv->state_lock);
499 static int mlx5e_get_coalesce(struct net_device *netdev,
500 struct ethtool_coalesce *coal)
502 struct mlx5e_priv *priv = netdev_priv(netdev);
504 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
507 coal->rx_coalesce_usecs = priv->params.rx_cq_moderation_usec;
508 coal->rx_max_coalesced_frames = priv->params.rx_cq_moderation_pkts;
509 coal->tx_coalesce_usecs = priv->params.tx_cq_moderation_usec;
510 coal->tx_max_coalesced_frames = priv->params.tx_cq_moderation_pkts;
515 static int mlx5e_set_coalesce(struct net_device *netdev,
516 struct ethtool_coalesce *coal)
518 struct mlx5e_priv *priv = netdev_priv(netdev);
519 struct mlx5_core_dev *mdev = priv->mdev;
520 struct mlx5e_channel *c;
524 if (!MLX5_CAP_GEN(mdev, cq_moderation))
527 mutex_lock(&priv->state_lock);
528 priv->params.tx_cq_moderation_usec = coal->tx_coalesce_usecs;
529 priv->params.tx_cq_moderation_pkts = coal->tx_max_coalesced_frames;
530 priv->params.rx_cq_moderation_usec = coal->rx_coalesce_usecs;
531 priv->params.rx_cq_moderation_pkts = coal->rx_max_coalesced_frames;
533 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
536 for (i = 0; i < priv->params.num_channels; ++i) {
537 c = priv->channel[i];
539 for (tc = 0; tc < c->num_tc; tc++) {
540 mlx5_core_modify_cq_moderation(mdev,
542 coal->tx_coalesce_usecs,
543 coal->tx_max_coalesced_frames);
546 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
547 coal->rx_coalesce_usecs,
548 coal->rx_max_coalesced_frames);
552 mutex_unlock(&priv->state_lock);
556 static u32 ptys2ethtool_supported_link(u32 eth_proto_cap)
559 u32 supported_modes = 0;
561 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
562 if (eth_proto_cap & MLX5E_PROT_MASK(i))
563 supported_modes |= ptys2ethtool_table[i].supported;
565 return supported_modes;
568 static u32 ptys2ethtool_adver_link(u32 eth_proto_cap)
571 u32 advertising_modes = 0;
573 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
574 if (eth_proto_cap & MLX5E_PROT_MASK(i))
575 advertising_modes |= ptys2ethtool_table[i].advertised;
577 return advertising_modes;
580 static u32 ptys2ethtool_supported_port(u32 eth_proto_cap)
582 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
583 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
584 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
585 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
586 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
587 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
588 return SUPPORTED_FIBRE;
591 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
592 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
593 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
594 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
595 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
596 return SUPPORTED_Backplane;
601 static void get_speed_duplex(struct net_device *netdev,
603 struct ethtool_cmd *cmd)
606 u32 speed = SPEED_UNKNOWN;
607 u8 duplex = DUPLEX_UNKNOWN;
609 if (!netif_carrier_ok(netdev))
612 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
613 if (eth_proto_oper & MLX5E_PROT_MASK(i)) {
614 speed = ptys2ethtool_table[i].speed;
615 duplex = DUPLEX_FULL;
620 ethtool_cmd_speed_set(cmd, speed);
621 cmd->duplex = duplex;
624 static void get_supported(u32 eth_proto_cap, u32 *supported)
626 *supported |= ptys2ethtool_supported_port(eth_proto_cap);
627 *supported |= ptys2ethtool_supported_link(eth_proto_cap);
628 *supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
631 static void get_advertising(u32 eth_proto_cap, u8 tx_pause,
632 u8 rx_pause, u32 *advertising)
634 *advertising |= ptys2ethtool_adver_link(eth_proto_cap);
635 *advertising |= tx_pause ? ADVERTISED_Pause : 0;
636 *advertising |= (tx_pause ^ rx_pause) ? ADVERTISED_Asym_Pause : 0;
639 static u8 get_connector_port(u32 eth_proto)
641 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
642 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
643 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
644 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
648 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
649 | MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
650 | MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
654 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
655 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
656 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
657 | MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
664 static void get_lp_advertising(u32 eth_proto_lp, u32 *lp_advertising)
666 *lp_advertising = ptys2ethtool_adver_link(eth_proto_lp);
669 static int mlx5e_get_settings(struct net_device *netdev,
670 struct ethtool_cmd *cmd)
672 struct mlx5e_priv *priv = netdev_priv(netdev);
673 struct mlx5_core_dev *mdev = priv->mdev;
674 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
681 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
684 netdev_err(netdev, "%s: query port ptys failed: %d\n",
689 eth_proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
690 eth_proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
691 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
692 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
695 cmd->advertising = 0;
697 get_supported(eth_proto_cap, &cmd->supported);
698 get_advertising(eth_proto_admin, 0, 0, &cmd->advertising);
699 get_speed_duplex(netdev, eth_proto_oper, cmd);
701 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
703 cmd->port = get_connector_port(eth_proto_oper);
704 get_lp_advertising(eth_proto_lp, &cmd->lp_advertising);
706 cmd->transceiver = XCVR_INTERNAL;
712 static u32 mlx5e_ethtool2ptys_adver_link(u32 link_modes)
714 u32 i, ptys_modes = 0;
716 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
717 if (ptys2ethtool_table[i].advertised & link_modes)
718 ptys_modes |= MLX5E_PROT_MASK(i);
724 static u32 mlx5e_ethtool2ptys_speed_link(u32 speed)
726 u32 i, speed_links = 0;
728 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
729 if (ptys2ethtool_table[i].speed == speed)
730 speed_links |= MLX5E_PROT_MASK(i);
736 static int mlx5e_set_settings(struct net_device *netdev,
737 struct ethtool_cmd *cmd)
739 struct mlx5e_priv *priv = netdev_priv(netdev);
740 struct mlx5_core_dev *mdev = priv->mdev;
743 u32 eth_proto_cap, eth_proto_admin;
744 enum mlx5_port_status ps;
747 speed = ethtool_cmd_speed(cmd);
749 link_modes = cmd->autoneg == AUTONEG_ENABLE ?
750 mlx5e_ethtool2ptys_adver_link(cmd->advertising) :
751 mlx5e_ethtool2ptys_speed_link(speed);
753 err = mlx5_query_port_proto_cap(mdev, ð_proto_cap, MLX5_PTYS_EN);
755 netdev_err(netdev, "%s: query port eth proto cap failed: %d\n",
760 link_modes = link_modes & eth_proto_cap;
762 netdev_err(netdev, "%s: Not supported link mode(s) requested",
768 err = mlx5_query_port_proto_admin(mdev, ð_proto_admin, MLX5_PTYS_EN);
770 netdev_err(netdev, "%s: query port eth proto admin failed: %d\n",
775 if (link_modes == eth_proto_admin)
778 mlx5_query_port_admin_status(mdev, &ps);
779 if (ps == MLX5_PORT_UP)
780 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
781 mlx5_set_port_proto(mdev, link_modes, MLX5_PTYS_EN);
782 if (ps == MLX5_PORT_UP)
783 mlx5_set_port_admin_status(mdev, MLX5_PORT_UP);
789 static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
791 struct mlx5e_priv *priv = netdev_priv(netdev);
793 return sizeof(priv->params.toeplitz_hash_key);
796 static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
798 return MLX5E_INDIR_RQT_SIZE;
801 static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
804 struct mlx5e_priv *priv = netdev_priv(netdev);
807 memcpy(indir, priv->params.indirection_rqt,
808 sizeof(priv->params.indirection_rqt));
811 memcpy(key, priv->params.toeplitz_hash_key,
812 sizeof(priv->params.toeplitz_hash_key));
815 *hfunc = priv->params.rss_hfunc;
820 static void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
822 struct mlx5_core_dev *mdev = priv->mdev;
823 void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
826 MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
827 mlx5e_build_tir_ctx_hash(tirc, priv);
829 for (i = 0; i < MLX5E_NUM_TT; i++)
830 if (IS_HASHING_TT(i))
831 mlx5_core_modify_tir(mdev, priv->tirn[i], in, inlen);
834 static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
835 const u8 *key, const u8 hfunc)
837 struct mlx5e_priv *priv = netdev_priv(dev);
838 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
841 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
842 (hfunc != ETH_RSS_HASH_XOR) &&
843 (hfunc != ETH_RSS_HASH_TOP))
846 in = mlx5_vzalloc(inlen);
850 mutex_lock(&priv->state_lock);
853 memcpy(priv->params.indirection_rqt, indir,
854 sizeof(priv->params.indirection_rqt));
855 mlx5e_redirect_rqt(priv, MLX5E_INDIRECTION_RQT);
859 memcpy(priv->params.toeplitz_hash_key, key,
860 sizeof(priv->params.toeplitz_hash_key));
862 if (hfunc != ETH_RSS_HASH_NO_CHANGE)
863 priv->params.rss_hfunc = hfunc;
865 mlx5e_modify_tirs_hash(priv, in, inlen);
867 mutex_unlock(&priv->state_lock);
874 static int mlx5e_get_rxnfc(struct net_device *netdev,
875 struct ethtool_rxnfc *info, u32 *rule_locs)
877 struct mlx5e_priv *priv = netdev_priv(netdev);
881 case ETHTOOL_GRXRINGS:
882 info->data = priv->params.num_channels;
892 static int mlx5e_get_tunable(struct net_device *dev,
893 const struct ethtool_tunable *tuna,
896 const struct mlx5e_priv *priv = netdev_priv(dev);
900 case ETHTOOL_TX_COPYBREAK:
901 *(u32 *)data = priv->params.tx_max_inline;
911 static int mlx5e_set_tunable(struct net_device *dev,
912 const struct ethtool_tunable *tuna,
915 struct mlx5e_priv *priv = netdev_priv(dev);
916 struct mlx5_core_dev *mdev = priv->mdev;
922 case ETHTOOL_TX_COPYBREAK:
924 if (val > mlx5e_get_max_inline_cap(mdev)) {
929 mutex_lock(&priv->state_lock);
931 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
933 mlx5e_close_locked(dev);
935 priv->params.tx_max_inline = val;
938 err = mlx5e_open_locked(dev);
940 mutex_unlock(&priv->state_lock);
950 static void mlx5e_get_pauseparam(struct net_device *netdev,
951 struct ethtool_pauseparam *pauseparam)
953 struct mlx5e_priv *priv = netdev_priv(netdev);
954 struct mlx5_core_dev *mdev = priv->mdev;
957 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
958 &pauseparam->tx_pause);
960 netdev_err(netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
965 static int mlx5e_set_pauseparam(struct net_device *netdev,
966 struct ethtool_pauseparam *pauseparam)
968 struct mlx5e_priv *priv = netdev_priv(netdev);
969 struct mlx5_core_dev *mdev = priv->mdev;
972 if (pauseparam->autoneg)
975 err = mlx5_set_port_pause(mdev,
976 pauseparam->rx_pause ? 1 : 0,
977 pauseparam->tx_pause ? 1 : 0);
979 netdev_err(netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
986 static int mlx5e_get_ts_info(struct net_device *dev,
987 struct ethtool_ts_info *info)
989 struct mlx5e_priv *priv = netdev_priv(dev);
992 ret = ethtool_op_get_ts_info(dev, info);
996 info->phc_index = priv->tstamp.ptp ?
997 ptp_clock_index(priv->tstamp.ptp) : -1;
999 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
1002 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
1003 SOF_TIMESTAMPING_RX_HARDWARE |
1004 SOF_TIMESTAMPING_RAW_HARDWARE;
1006 info->tx_types = (BIT(1) << HWTSTAMP_TX_OFF) |
1007 (BIT(1) << HWTSTAMP_TX_ON);
1009 info->rx_filters = (BIT(1) << HWTSTAMP_FILTER_NONE) |
1010 (BIT(1) << HWTSTAMP_FILTER_ALL);
1015 static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1019 if (MLX5_CAP_GEN(mdev, wol_g))
1022 if (MLX5_CAP_GEN(mdev, wol_s))
1023 ret |= WAKE_MAGICSECURE;
1025 if (MLX5_CAP_GEN(mdev, wol_a))
1028 if (MLX5_CAP_GEN(mdev, wol_b))
1031 if (MLX5_CAP_GEN(mdev, wol_m))
1034 if (MLX5_CAP_GEN(mdev, wol_u))
1037 if (MLX5_CAP_GEN(mdev, wol_p))
1043 static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode)
1047 if (mode & MLX5_WOL_MAGIC)
1050 if (mode & MLX5_WOL_SECURED_MAGIC)
1051 ret |= WAKE_MAGICSECURE;
1053 if (mode & MLX5_WOL_ARP)
1056 if (mode & MLX5_WOL_BROADCAST)
1059 if (mode & MLX5_WOL_MULTICAST)
1062 if (mode & MLX5_WOL_UNICAST)
1065 if (mode & MLX5_WOL_PHY_ACTIVITY)
1071 static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode)
1075 if (mode & WAKE_MAGIC)
1076 ret |= MLX5_WOL_MAGIC;
1078 if (mode & WAKE_MAGICSECURE)
1079 ret |= MLX5_WOL_SECURED_MAGIC;
1081 if (mode & WAKE_ARP)
1082 ret |= MLX5_WOL_ARP;
1084 if (mode & WAKE_BCAST)
1085 ret |= MLX5_WOL_BROADCAST;
1087 if (mode & WAKE_MCAST)
1088 ret |= MLX5_WOL_MULTICAST;
1090 if (mode & WAKE_UCAST)
1091 ret |= MLX5_WOL_UNICAST;
1093 if (mode & WAKE_PHY)
1094 ret |= MLX5_WOL_PHY_ACTIVITY;
1099 static void mlx5e_get_wol(struct net_device *netdev,
1100 struct ethtool_wolinfo *wol)
1102 struct mlx5e_priv *priv = netdev_priv(netdev);
1103 struct mlx5_core_dev *mdev = priv->mdev;
1107 memset(wol, 0, sizeof(*wol));
1109 wol->supported = mlx5e_get_wol_supported(mdev);
1110 if (!wol->supported)
1113 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1117 wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1120 static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1122 struct mlx5e_priv *priv = netdev_priv(netdev);
1123 struct mlx5_core_dev *mdev = priv->mdev;
1124 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1130 if (wol->wolopts & ~wol_supported)
1133 mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts);
1135 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1138 static int mlx5e_set_phys_id(struct net_device *dev,
1139 enum ethtool_phys_id_state state)
1141 struct mlx5e_priv *priv = netdev_priv(dev);
1142 struct mlx5_core_dev *mdev = priv->mdev;
1143 u16 beacon_duration;
1145 if (!MLX5_CAP_GEN(mdev, beacon_led))
1149 case ETHTOOL_ID_ACTIVE:
1150 beacon_duration = MLX5_BEACON_DURATION_INF;
1152 case ETHTOOL_ID_INACTIVE:
1153 beacon_duration = MLX5_BEACON_DURATION_OFF;
1159 return mlx5_set_port_beacon(mdev, beacon_duration);
1162 const struct ethtool_ops mlx5e_ethtool_ops = {
1163 .get_drvinfo = mlx5e_get_drvinfo,
1164 .get_link = ethtool_op_get_link,
1165 .get_strings = mlx5e_get_strings,
1166 .get_sset_count = mlx5e_get_sset_count,
1167 .get_ethtool_stats = mlx5e_get_ethtool_stats,
1168 .get_ringparam = mlx5e_get_ringparam,
1169 .set_ringparam = mlx5e_set_ringparam,
1170 .get_channels = mlx5e_get_channels,
1171 .set_channels = mlx5e_set_channels,
1172 .get_coalesce = mlx5e_get_coalesce,
1173 .set_coalesce = mlx5e_set_coalesce,
1174 .get_settings = mlx5e_get_settings,
1175 .set_settings = mlx5e_set_settings,
1176 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
1177 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
1178 .get_rxfh = mlx5e_get_rxfh,
1179 .set_rxfh = mlx5e_set_rxfh,
1180 .get_rxnfc = mlx5e_get_rxnfc,
1181 .get_tunable = mlx5e_get_tunable,
1182 .set_tunable = mlx5e_set_tunable,
1183 .get_pauseparam = mlx5e_get_pauseparam,
1184 .set_pauseparam = mlx5e_set_pauseparam,
1185 .get_ts_info = mlx5e_get_ts_info,
1186 .set_phys_id = mlx5e_set_phys_id,
1187 .get_wol = mlx5e_get_wol,
1188 .set_wol = mlx5e_set_wol,