2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 #include <linux/device.h>
33 #include <linux/netdevice.h>
36 #define MLX5E_MAX_PRIORITY 8
38 #define MLX5E_100MB (100000)
39 #define MLX5E_1GB (1000000)
41 #define MLX5E_CEE_STATE_UP 1
42 #define MLX5E_CEE_STATE_DOWN 0
45 MLX5E_VENDOR_TC_GROUP_NUM = 7,
46 MLX5E_LOWEST_PRIO_GROUP = 0,
49 #define MLX5_DSCP_SUPPORTED(mdev) (MLX5_CAP_GEN(mdev, qcam_reg) && \
50 MLX5_CAP_QCAM_REG(mdev, qpts) && \
51 MLX5_CAP_QCAM_REG(mdev, qpdpm))
53 static int mlx5e_set_trust_state(struct mlx5e_priv *priv, u8 trust_state);
54 static int mlx5e_set_dscp2prio(struct mlx5e_priv *priv, u8 dscp, u8 prio);
56 /* If dcbx mode is non-host set the dcbx mode to host.
58 static int mlx5e_dcbnl_set_dcbx_mode(struct mlx5e_priv *priv,
59 enum mlx5_dcbx_oper_mode mode)
61 struct mlx5_core_dev *mdev = priv->mdev;
62 u32 param[MLX5_ST_SZ_DW(dcbx_param)];
65 err = mlx5_query_port_dcbx_param(mdev, param);
69 MLX5_SET(dcbx_param, param, version_admin, mode);
70 if (mode != MLX5E_DCBX_PARAM_VER_OPER_HOST)
71 MLX5_SET(dcbx_param, param, willing_admin, 1);
73 return mlx5_set_port_dcbx_param(mdev, param);
76 static int mlx5e_dcbnl_switch_to_host_mode(struct mlx5e_priv *priv)
78 struct mlx5e_dcbx *dcbx = &priv->dcbx;
81 if (!MLX5_CAP_GEN(priv->mdev, dcbx))
84 if (dcbx->mode == MLX5E_DCBX_PARAM_VER_OPER_HOST)
87 err = mlx5e_dcbnl_set_dcbx_mode(priv, MLX5E_DCBX_PARAM_VER_OPER_HOST);
91 dcbx->mode = MLX5E_DCBX_PARAM_VER_OPER_HOST;
95 static int mlx5e_dcbnl_ieee_getets(struct net_device *netdev,
98 struct mlx5e_priv *priv = netdev_priv(netdev);
99 struct mlx5_core_dev *mdev = priv->mdev;
100 u8 tc_group[IEEE_8021QAZ_MAX_TCS];
101 bool is_tc_group_6_exist = false;
102 bool is_zero_bw_ets_tc = false;
106 if (!MLX5_CAP_GEN(priv->mdev, ets))
109 ets->ets_cap = mlx5_max_tc(priv->mdev) + 1;
110 for (i = 0; i < ets->ets_cap; i++) {
111 err = mlx5_query_port_prio_tc(mdev, i, &ets->prio_tc[i]);
115 err = mlx5_query_port_tc_group(mdev, i, &tc_group[i]);
119 err = mlx5_query_port_tc_bw_alloc(mdev, i, &ets->tc_tx_bw[i]);
123 if (ets->tc_tx_bw[i] < MLX5E_MAX_BW_ALLOC &&
124 tc_group[i] == (MLX5E_LOWEST_PRIO_GROUP + 1))
125 is_zero_bw_ets_tc = true;
127 if (tc_group[i] == (MLX5E_VENDOR_TC_GROUP_NUM - 1))
128 is_tc_group_6_exist = true;
131 /* Report 0% ets tc if exits*/
132 if (is_zero_bw_ets_tc) {
133 for (i = 0; i < ets->ets_cap; i++)
134 if (tc_group[i] == MLX5E_LOWEST_PRIO_GROUP)
135 ets->tc_tx_bw[i] = 0;
138 /* Update tc_tsa based on fw setting*/
139 for (i = 0; i < ets->ets_cap; i++) {
140 if (ets->tc_tx_bw[i] < MLX5E_MAX_BW_ALLOC)
141 priv->dcbx.tc_tsa[i] = IEEE_8021QAZ_TSA_ETS;
142 else if (tc_group[i] == MLX5E_VENDOR_TC_GROUP_NUM &&
143 !is_tc_group_6_exist)
144 priv->dcbx.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
146 memcpy(ets->tc_tsa, priv->dcbx.tc_tsa, sizeof(ets->tc_tsa));
151 static void mlx5e_build_tc_group(struct ieee_ets *ets, u8 *tc_group, int max_tc)
153 bool any_tc_mapped_to_ets = false;
154 bool ets_zero_bw = false;
158 for (i = 0; i <= max_tc; i++) {
159 if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS) {
160 any_tc_mapped_to_ets = true;
161 if (!ets->tc_tx_bw[i])
166 /* strict group has higher priority than ets group */
167 strict_group = MLX5E_LOWEST_PRIO_GROUP;
168 if (any_tc_mapped_to_ets)
173 for (i = 0; i <= max_tc; i++) {
174 switch (ets->tc_tsa[i]) {
175 case IEEE_8021QAZ_TSA_VENDOR:
176 tc_group[i] = MLX5E_VENDOR_TC_GROUP_NUM;
178 case IEEE_8021QAZ_TSA_STRICT:
179 tc_group[i] = strict_group++;
181 case IEEE_8021QAZ_TSA_ETS:
182 tc_group[i] = MLX5E_LOWEST_PRIO_GROUP;
183 if (ets->tc_tx_bw[i] && ets_zero_bw)
184 tc_group[i] = MLX5E_LOWEST_PRIO_GROUP + 1;
190 static void mlx5e_build_tc_tx_bw(struct ieee_ets *ets, u8 *tc_tx_bw,
191 u8 *tc_group, int max_tc)
193 int bw_for_ets_zero_bw_tc = 0;
194 int last_ets_zero_bw_tc = -1;
195 int num_ets_zero_bw = 0;
198 for (i = 0; i <= max_tc; i++) {
199 if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS &&
202 last_ets_zero_bw_tc = i;
207 bw_for_ets_zero_bw_tc = MLX5E_MAX_BW_ALLOC / num_ets_zero_bw;
209 for (i = 0; i <= max_tc; i++) {
210 switch (ets->tc_tsa[i]) {
211 case IEEE_8021QAZ_TSA_VENDOR:
212 tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
214 case IEEE_8021QAZ_TSA_STRICT:
215 tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
217 case IEEE_8021QAZ_TSA_ETS:
218 tc_tx_bw[i] = ets->tc_tx_bw[i] ?
220 bw_for_ets_zero_bw_tc;
225 /* Make sure the total bw for ets zero bw group is 100% */
226 if (last_ets_zero_bw_tc != -1)
227 tc_tx_bw[last_ets_zero_bw_tc] +=
228 MLX5E_MAX_BW_ALLOC % num_ets_zero_bw;
231 /* If there are ETS BW 0,
232 * Set ETS group # to 1 for all ETS non zero BW tcs. Their sum must be 100%.
233 * Set group #0 to all the ETS BW 0 tcs and
234 * equally splits the 100% BW between them
235 * Report both group #0 and #1 as ETS type.
236 * All the tcs in group #0 will be reported with 0% BW.
238 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets)
240 struct mlx5_core_dev *mdev = priv->mdev;
241 u8 tc_tx_bw[IEEE_8021QAZ_MAX_TCS];
242 u8 tc_group[IEEE_8021QAZ_MAX_TCS];
243 int max_tc = mlx5_max_tc(mdev);
246 mlx5e_build_tc_group(ets, tc_group, max_tc);
247 mlx5e_build_tc_tx_bw(ets, tc_tx_bw, tc_group, max_tc);
249 err = mlx5_set_port_prio_tc(mdev, ets->prio_tc);
253 err = mlx5_set_port_tc_group(mdev, tc_group);
257 err = mlx5_set_port_tc_bw_alloc(mdev, tc_tx_bw);
262 memcpy(priv->dcbx.tc_tsa, ets->tc_tsa, sizeof(ets->tc_tsa));
264 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
265 mlx5e_dbg(HW, priv, "%s: prio_%d <=> tc_%d\n",
266 __func__, i, ets->prio_tc[i]);
267 mlx5e_dbg(HW, priv, "%s: tc_%d <=> tx_bw_%d%%, group_%d\n",
268 __func__, i, tc_tx_bw[i], tc_group[i]);
274 static int mlx5e_dbcnl_validate_ets(struct net_device *netdev,
275 struct ieee_ets *ets)
280 /* Validate Priority */
281 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
282 if (ets->prio_tc[i] >= MLX5E_MAX_PRIORITY) {
284 "Failed to validate ETS: priority value greater than max(%d)\n",
290 /* Validate Bandwidth Sum */
291 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
292 if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS)
293 bw_sum += ets->tc_tx_bw[i];
295 if (bw_sum != 0 && bw_sum != 100) {
297 "Failed to validate ETS: BW sum is illegal\n");
303 static int mlx5e_dcbnl_ieee_setets(struct net_device *netdev,
304 struct ieee_ets *ets)
306 struct mlx5e_priv *priv = netdev_priv(netdev);
309 if (!MLX5_CAP_GEN(priv->mdev, ets))
312 err = mlx5e_dbcnl_validate_ets(netdev, ets);
316 err = mlx5e_dcbnl_ieee_setets_core(priv, ets);
323 static int mlx5e_dcbnl_ieee_getpfc(struct net_device *dev,
324 struct ieee_pfc *pfc)
326 struct mlx5e_priv *priv = netdev_priv(dev);
327 struct mlx5_core_dev *mdev = priv->mdev;
328 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
331 pfc->pfc_cap = mlx5_max_tc(mdev) + 1;
332 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
333 pfc->requests[i] = PPORT_PER_PRIO_GET(pstats, i, tx_pause);
334 pfc->indications[i] = PPORT_PER_PRIO_GET(pstats, i, rx_pause);
337 return mlx5_query_port_pfc(mdev, &pfc->pfc_en, NULL);
340 static int mlx5e_dcbnl_ieee_setpfc(struct net_device *dev,
341 struct ieee_pfc *pfc)
343 struct mlx5e_priv *priv = netdev_priv(dev);
344 struct mlx5_core_dev *mdev = priv->mdev;
348 mlx5_query_port_pfc(mdev, &curr_pfc_en, NULL);
350 if (pfc->pfc_en == curr_pfc_en)
353 ret = mlx5_set_port_pfc(mdev, pfc->pfc_en, pfc->pfc_en);
354 mlx5_toggle_port_link(mdev);
358 "%s: PFC per priority bit mask: 0x%x\n",
359 __func__, pfc->pfc_en);
364 static u8 mlx5e_dcbnl_getdcbx(struct net_device *dev)
366 struct mlx5e_priv *priv = netdev_priv(dev);
368 return priv->dcbx.cap;
371 static u8 mlx5e_dcbnl_setdcbx(struct net_device *dev, u8 mode)
373 struct mlx5e_priv *priv = netdev_priv(dev);
374 struct mlx5e_dcbx *dcbx = &priv->dcbx;
376 if (mode & DCB_CAP_DCBX_LLD_MANAGED)
379 if ((!mode) && MLX5_CAP_GEN(priv->mdev, dcbx)) {
380 if (dcbx->mode == MLX5E_DCBX_PARAM_VER_OPER_AUTO)
383 /* set dcbx to fw controlled */
384 if (!mlx5e_dcbnl_set_dcbx_mode(priv, MLX5E_DCBX_PARAM_VER_OPER_AUTO)) {
385 dcbx->mode = MLX5E_DCBX_PARAM_VER_OPER_AUTO;
386 dcbx->cap &= ~DCB_CAP_DCBX_HOST;
393 if (!(mode & DCB_CAP_DCBX_HOST))
396 if (mlx5e_dcbnl_switch_to_host_mode(netdev_priv(dev)))
404 static int mlx5e_dcbnl_ieee_setapp(struct net_device *dev, struct dcb_app *app)
406 struct mlx5e_priv *priv = netdev_priv(dev);
411 if (app->selector != IEEE_8021QAZ_APP_SEL_DSCP)
414 if (!MLX5_CAP_GEN(priv->mdev, vport_group_manager))
417 if (!MLX5_DSCP_SUPPORTED(priv->mdev))
420 if (app->protocol >= MLX5E_MAX_DSCP)
423 /* Save the old entry info */
424 temp.selector = IEEE_8021QAZ_APP_SEL_DSCP;
425 temp.protocol = app->protocol;
426 temp.priority = priv->dcbx_dp.dscp2prio[app->protocol];
428 /* Check if need to switch to dscp trust state */
429 if (!priv->dcbx.dscp_app_cnt) {
430 err = mlx5e_set_trust_state(priv, MLX5_QPTS_TRUST_DSCP);
435 /* Skip the fw command if new and old mapping are the same */
436 if (app->priority != priv->dcbx_dp.dscp2prio[app->protocol]) {
437 err = mlx5e_set_dscp2prio(priv, app->protocol, app->priority);
442 /* Delete the old entry if exists */
444 err = dcb_ieee_delapp(dev, &temp);
448 /* Add new entry and update counter */
449 err = dcb_ieee_setapp(dev, app);
454 priv->dcbx.dscp_app_cnt++;
459 mlx5e_set_trust_state(priv, MLX5_QPTS_TRUST_PCP);
463 static int mlx5e_dcbnl_ieee_delapp(struct net_device *dev, struct dcb_app *app)
465 struct mlx5e_priv *priv = netdev_priv(dev);
468 if (app->selector != IEEE_8021QAZ_APP_SEL_DSCP)
471 if (!MLX5_CAP_GEN(priv->mdev, vport_group_manager))
474 if (!MLX5_DSCP_SUPPORTED(priv->mdev))
477 if (app->protocol >= MLX5E_MAX_DSCP)
480 /* Skip if no dscp app entry */
481 if (!priv->dcbx.dscp_app_cnt)
484 /* Check if the entry matches fw setting */
485 if (app->priority != priv->dcbx_dp.dscp2prio[app->protocol])
488 /* Delete the app entry */
489 err = dcb_ieee_delapp(dev, app);
493 /* Reset the priority mapping back to zero */
494 err = mlx5e_set_dscp2prio(priv, app->protocol, 0);
498 priv->dcbx.dscp_app_cnt--;
500 /* Check if need to switch to pcp trust state */
501 if (!priv->dcbx.dscp_app_cnt)
502 err = mlx5e_set_trust_state(priv, MLX5_QPTS_TRUST_PCP);
507 mlx5e_set_trust_state(priv, MLX5_QPTS_TRUST_PCP);
511 static int mlx5e_dcbnl_ieee_getmaxrate(struct net_device *netdev,
512 struct ieee_maxrate *maxrate)
514 struct mlx5e_priv *priv = netdev_priv(netdev);
515 struct mlx5_core_dev *mdev = priv->mdev;
516 u8 max_bw_value[IEEE_8021QAZ_MAX_TCS];
517 u8 max_bw_unit[IEEE_8021QAZ_MAX_TCS];
521 err = mlx5_query_port_ets_rate_limit(mdev, max_bw_value, max_bw_unit);
525 memset(maxrate->tc_maxrate, 0, sizeof(maxrate->tc_maxrate));
527 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
528 switch (max_bw_unit[i]) {
529 case MLX5_100_MBPS_UNIT:
530 maxrate->tc_maxrate[i] = max_bw_value[i] * MLX5E_100MB;
533 maxrate->tc_maxrate[i] = max_bw_value[i] * MLX5E_1GB;
535 case MLX5_BW_NO_LIMIT:
538 WARN(true, "non-supported BW unit");
546 static int mlx5e_dcbnl_ieee_setmaxrate(struct net_device *netdev,
547 struct ieee_maxrate *maxrate)
549 struct mlx5e_priv *priv = netdev_priv(netdev);
550 struct mlx5_core_dev *mdev = priv->mdev;
551 u8 max_bw_value[IEEE_8021QAZ_MAX_TCS];
552 u8 max_bw_unit[IEEE_8021QAZ_MAX_TCS];
553 __u64 upper_limit_mbps = roundup(255 * MLX5E_100MB, MLX5E_1GB);
556 memset(max_bw_value, 0, sizeof(max_bw_value));
557 memset(max_bw_unit, 0, sizeof(max_bw_unit));
559 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
560 if (!maxrate->tc_maxrate[i]) {
561 max_bw_unit[i] = MLX5_BW_NO_LIMIT;
564 if (maxrate->tc_maxrate[i] < upper_limit_mbps) {
565 max_bw_value[i] = div_u64(maxrate->tc_maxrate[i],
567 max_bw_value[i] = max_bw_value[i] ? max_bw_value[i] : 1;
568 max_bw_unit[i] = MLX5_100_MBPS_UNIT;
570 max_bw_value[i] = div_u64(maxrate->tc_maxrate[i],
572 max_bw_unit[i] = MLX5_GBPS_UNIT;
576 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
577 mlx5e_dbg(HW, priv, "%s: tc_%d <=> max_bw %d Gbps\n",
578 __func__, i, max_bw_value[i]);
581 return mlx5_modify_port_ets_rate_limit(mdev, max_bw_value, max_bw_unit);
584 static u8 mlx5e_dcbnl_setall(struct net_device *netdev)
586 struct mlx5e_priv *priv = netdev_priv(netdev);
587 struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
588 struct mlx5_core_dev *mdev = priv->mdev;
591 int err = -EOPNOTSUPP;
594 if (!MLX5_CAP_GEN(mdev, ets))
597 memset(&ets, 0, sizeof(ets));
598 memset(&pfc, 0, sizeof(pfc));
600 ets.ets_cap = IEEE_8021QAZ_MAX_TCS;
601 for (i = 0; i < CEE_DCBX_MAX_PGS; i++) {
602 ets.tc_tx_bw[i] = cee_cfg->pg_bw_pct[i];
603 ets.tc_rx_bw[i] = cee_cfg->pg_bw_pct[i];
604 ets.tc_tsa[i] = IEEE_8021QAZ_TSA_ETS;
605 ets.prio_tc[i] = cee_cfg->prio_to_pg_map[i];
607 "%s: Priority group %d: tx_bw %d, rx_bw %d, prio_tc %d\n",
608 __func__, i, ets.tc_tx_bw[i], ets.tc_rx_bw[i],
612 err = mlx5e_dbcnl_validate_ets(netdev, &ets);
615 "%s, Failed to validate ETS: %d\n", __func__, err);
619 err = mlx5e_dcbnl_ieee_setets_core(priv, &ets);
622 "%s, Failed to set ETS: %d\n", __func__, err);
627 pfc.pfc_cap = mlx5_max_tc(mdev) + 1;
628 if (!cee_cfg->pfc_enable)
631 for (i = 0; i < CEE_DCBX_MAX_PRIO; i++)
632 pfc.pfc_en |= cee_cfg->pfc_setting[i] << i;
634 err = mlx5e_dcbnl_ieee_setpfc(netdev, &pfc);
637 "%s, Failed to set PFC: %d\n", __func__, err);
641 return err ? MLX5_DCB_NO_CHG : MLX5_DCB_CHG_RESET;
644 static u8 mlx5e_dcbnl_getstate(struct net_device *netdev)
646 return MLX5E_CEE_STATE_UP;
649 static void mlx5e_dcbnl_getpermhwaddr(struct net_device *netdev,
652 struct mlx5e_priv *priv = netdev_priv(netdev);
657 memset(perm_addr, 0xff, MAX_ADDR_LEN);
659 mlx5_query_nic_vport_mac_address(priv->mdev, 0, perm_addr);
662 static void mlx5e_dcbnl_setpgtccfgtx(struct net_device *netdev,
663 int priority, u8 prio_type,
664 u8 pgid, u8 bw_pct, u8 up_map)
666 struct mlx5e_priv *priv = netdev_priv(netdev);
667 struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
669 if (priority >= CEE_DCBX_MAX_PRIO) {
671 "%s, priority is out of range\n", __func__);
675 if (pgid >= CEE_DCBX_MAX_PGS) {
677 "%s, priority group is out of range\n", __func__);
681 cee_cfg->prio_to_pg_map[priority] = pgid;
684 static void mlx5e_dcbnl_setpgbwgcfgtx(struct net_device *netdev,
687 struct mlx5e_priv *priv = netdev_priv(netdev);
688 struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
690 if (pgid >= CEE_DCBX_MAX_PGS) {
692 "%s, priority group is out of range\n", __func__);
696 cee_cfg->pg_bw_pct[pgid] = bw_pct;
699 static void mlx5e_dcbnl_getpgtccfgtx(struct net_device *netdev,
700 int priority, u8 *prio_type,
701 u8 *pgid, u8 *bw_pct, u8 *up_map)
703 struct mlx5e_priv *priv = netdev_priv(netdev);
704 struct mlx5_core_dev *mdev = priv->mdev;
706 if (!MLX5_CAP_GEN(priv->mdev, ets)) {
707 netdev_err(netdev, "%s, ets is not supported\n", __func__);
711 if (priority >= CEE_DCBX_MAX_PRIO) {
713 "%s, priority is out of range\n", __func__);
721 if (mlx5_query_port_prio_tc(mdev, priority, pgid))
725 static void mlx5e_dcbnl_getpgbwgcfgtx(struct net_device *netdev,
726 int pgid, u8 *bw_pct)
730 if (pgid >= CEE_DCBX_MAX_PGS) {
732 "%s, priority group is out of range\n", __func__);
736 mlx5e_dcbnl_ieee_getets(netdev, &ets);
737 *bw_pct = ets.tc_tx_bw[pgid];
740 static void mlx5e_dcbnl_setpfccfg(struct net_device *netdev,
741 int priority, u8 setting)
743 struct mlx5e_priv *priv = netdev_priv(netdev);
744 struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
746 if (priority >= CEE_DCBX_MAX_PRIO) {
748 "%s, priority is out of range\n", __func__);
755 cee_cfg->pfc_setting[priority] = setting;
759 mlx5e_dcbnl_get_priority_pfc(struct net_device *netdev,
760 int priority, u8 *setting)
765 err = mlx5e_dcbnl_ieee_getpfc(netdev, &pfc);
770 *setting = (pfc.pfc_en >> priority) & 0x01;
775 static void mlx5e_dcbnl_getpfccfg(struct net_device *netdev,
776 int priority, u8 *setting)
778 if (priority >= CEE_DCBX_MAX_PRIO) {
780 "%s, priority is out of range\n", __func__);
787 mlx5e_dcbnl_get_priority_pfc(netdev, priority, setting);
790 static u8 mlx5e_dcbnl_getcap(struct net_device *netdev,
793 struct mlx5e_priv *priv = netdev_priv(netdev);
794 struct mlx5_core_dev *mdev = priv->mdev;
798 case DCB_CAP_ATTR_PG:
801 case DCB_CAP_ATTR_PFC:
804 case DCB_CAP_ATTR_UP2TC:
807 case DCB_CAP_ATTR_PG_TCS:
808 *cap = 1 << mlx5_max_tc(mdev);
810 case DCB_CAP_ATTR_PFC_TCS:
811 *cap = 1 << mlx5_max_tc(mdev);
813 case DCB_CAP_ATTR_GSP:
816 case DCB_CAP_ATTR_BCN:
819 case DCB_CAP_ATTR_DCBX:
820 *cap = priv->dcbx.cap |
821 DCB_CAP_DCBX_VER_CEE |
822 DCB_CAP_DCBX_VER_IEEE;
833 static int mlx5e_dcbnl_getnumtcs(struct net_device *netdev,
836 struct mlx5e_priv *priv = netdev_priv(netdev);
837 struct mlx5_core_dev *mdev = priv->mdev;
840 case DCB_NUMTCS_ATTR_PG:
841 case DCB_NUMTCS_ATTR_PFC:
842 *num = mlx5_max_tc(mdev) + 1;
851 static u8 mlx5e_dcbnl_getpfcstate(struct net_device *netdev)
855 if (mlx5e_dcbnl_ieee_getpfc(netdev, &pfc))
856 return MLX5E_CEE_STATE_DOWN;
858 return pfc.pfc_en ? MLX5E_CEE_STATE_UP : MLX5E_CEE_STATE_DOWN;
861 static void mlx5e_dcbnl_setpfcstate(struct net_device *netdev, u8 state)
863 struct mlx5e_priv *priv = netdev_priv(netdev);
864 struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
866 if ((state != MLX5E_CEE_STATE_UP) && (state != MLX5E_CEE_STATE_DOWN))
869 cee_cfg->pfc_enable = state;
872 const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops = {
873 .ieee_getets = mlx5e_dcbnl_ieee_getets,
874 .ieee_setets = mlx5e_dcbnl_ieee_setets,
875 .ieee_getmaxrate = mlx5e_dcbnl_ieee_getmaxrate,
876 .ieee_setmaxrate = mlx5e_dcbnl_ieee_setmaxrate,
877 .ieee_getpfc = mlx5e_dcbnl_ieee_getpfc,
878 .ieee_setpfc = mlx5e_dcbnl_ieee_setpfc,
879 .ieee_setapp = mlx5e_dcbnl_ieee_setapp,
880 .ieee_delapp = mlx5e_dcbnl_ieee_delapp,
881 .getdcbx = mlx5e_dcbnl_getdcbx,
882 .setdcbx = mlx5e_dcbnl_setdcbx,
885 .setall = mlx5e_dcbnl_setall,
886 .getstate = mlx5e_dcbnl_getstate,
887 .getpermhwaddr = mlx5e_dcbnl_getpermhwaddr,
889 .setpgtccfgtx = mlx5e_dcbnl_setpgtccfgtx,
890 .setpgbwgcfgtx = mlx5e_dcbnl_setpgbwgcfgtx,
891 .getpgtccfgtx = mlx5e_dcbnl_getpgtccfgtx,
892 .getpgbwgcfgtx = mlx5e_dcbnl_getpgbwgcfgtx,
894 .setpfccfg = mlx5e_dcbnl_setpfccfg,
895 .getpfccfg = mlx5e_dcbnl_getpfccfg,
896 .getcap = mlx5e_dcbnl_getcap,
897 .getnumtcs = mlx5e_dcbnl_getnumtcs,
898 .getpfcstate = mlx5e_dcbnl_getpfcstate,
899 .setpfcstate = mlx5e_dcbnl_setpfcstate,
902 static void mlx5e_dcbnl_query_dcbx_mode(struct mlx5e_priv *priv,
903 enum mlx5_dcbx_oper_mode *mode)
905 u32 out[MLX5_ST_SZ_DW(dcbx_param)];
907 *mode = MLX5E_DCBX_PARAM_VER_OPER_HOST;
909 if (!mlx5_query_port_dcbx_param(priv->mdev, out))
910 *mode = MLX5_GET(dcbx_param, out, version_oper);
912 /* From driver's point of view, we only care if the mode
913 * is host (HOST) or non-host (AUTO)
915 if (*mode != MLX5E_DCBX_PARAM_VER_OPER_HOST)
916 *mode = MLX5E_DCBX_PARAM_VER_OPER_AUTO;
919 static void mlx5e_ets_init(struct mlx5e_priv *priv)
924 if (!MLX5_CAP_GEN(priv->mdev, ets))
927 memset(&ets, 0, sizeof(ets));
928 ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
929 for (i = 0; i < ets.ets_cap; i++) {
930 ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
931 ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
935 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
939 mlx5e_dcbnl_ieee_setets_core(priv, &ets);
947 static void mlx5e_dcbnl_dscp_app(struct mlx5e_priv *priv, int action)
952 if (!MLX5_CAP_GEN(priv->mdev, vport_group_manager))
955 if (!MLX5_DSCP_SUPPORTED(priv->mdev))
958 /* No SEL_DSCP entry in non DSCP state */
959 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_DSCP)
962 temp.selector = IEEE_8021QAZ_APP_SEL_DSCP;
963 for (i = 0; i < MLX5E_MAX_DSCP; i++) {
965 temp.priority = priv->dcbx_dp.dscp2prio[i];
967 dcb_ieee_setapp(priv->netdev, &temp);
969 dcb_ieee_delapp(priv->netdev, &temp);
972 priv->dcbx.dscp_app_cnt = (action == INIT) ? MLX5E_MAX_DSCP : 0;
975 void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv)
977 mlx5e_dcbnl_dscp_app(priv, INIT);
980 void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv)
982 mlx5e_dcbnl_dscp_app(priv, DELETE);
985 static void mlx5e_trust_update_tx_min_inline_mode(struct mlx5e_priv *priv,
986 struct mlx5e_params *params)
988 params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(priv->mdev);
989 if (priv->dcbx_dp.trust_state == MLX5_QPTS_TRUST_DSCP &&
990 params->tx_min_inline_mode == MLX5_INLINE_MODE_L2)
991 params->tx_min_inline_mode = MLX5_INLINE_MODE_IP;
994 static void mlx5e_trust_update_sq_inline_mode(struct mlx5e_priv *priv)
996 struct mlx5e_channels new_channels = {};
998 mutex_lock(&priv->state_lock);
1000 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1003 new_channels.params = priv->channels.params;
1004 mlx5e_trust_update_tx_min_inline_mode(priv, &new_channels.params);
1006 /* Skip if tx_min_inline is the same */
1007 if (new_channels.params.tx_min_inline_mode ==
1008 priv->channels.params.tx_min_inline_mode)
1011 if (mlx5e_open_channels(priv, &new_channels))
1013 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
1016 mutex_unlock(&priv->state_lock);
1019 static int mlx5e_set_trust_state(struct mlx5e_priv *priv, u8 trust_state)
1023 err = mlx5_set_trust_state(priv->mdev, trust_state);
1026 priv->dcbx_dp.trust_state = trust_state;
1027 mlx5e_trust_update_sq_inline_mode(priv);
1032 static int mlx5e_set_dscp2prio(struct mlx5e_priv *priv, u8 dscp, u8 prio)
1036 err = mlx5_set_dscp2prio(priv->mdev, dscp, prio);
1040 priv->dcbx_dp.dscp2prio[dscp] = prio;
1044 static int mlx5e_trust_initialize(struct mlx5e_priv *priv)
1046 struct mlx5_core_dev *mdev = priv->mdev;
1049 if (!MLX5_DSCP_SUPPORTED(mdev))
1052 err = mlx5_query_trust_state(priv->mdev, &priv->dcbx_dp.trust_state);
1056 mlx5e_trust_update_tx_min_inline_mode(priv, &priv->channels.params);
1058 err = mlx5_query_dscp2prio(priv->mdev, priv->dcbx_dp.dscp2prio);
1065 void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv)
1067 struct mlx5e_dcbx *dcbx = &priv->dcbx;
1069 mlx5e_trust_initialize(priv);
1071 if (!MLX5_CAP_GEN(priv->mdev, qos))
1074 if (MLX5_CAP_GEN(priv->mdev, dcbx))
1075 mlx5e_dcbnl_query_dcbx_mode(priv, &dcbx->mode);
1077 priv->dcbx.cap = DCB_CAP_DCBX_VER_CEE |
1078 DCB_CAP_DCBX_VER_IEEE;
1079 if (priv->dcbx.mode == MLX5E_DCBX_PARAM_VER_OPER_HOST)
1080 priv->dcbx.cap |= DCB_CAP_DCBX_HOST;
1082 mlx5e_ets_init(priv);