2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
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21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/clocksource.h>
37 MLX5E_CYCLES_SHIFT = 23
40 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *tstamp, u64 timestamp,
41 struct skb_shared_hwtstamps *hwts)
45 read_lock(&tstamp->lock);
46 nsec = timecounter_cyc2time(&tstamp->clock, timestamp);
47 read_unlock(&tstamp->lock);
49 hwts->hwtstamp = ns_to_ktime(nsec);
52 static cycle_t mlx5e_read_internal_timer(const struct cyclecounter *cc)
54 struct mlx5e_tstamp *tstamp = container_of(cc, struct mlx5e_tstamp,
57 return mlx5_read_internal_timer(tstamp->mdev) & cc->mask;
60 static void mlx5e_timestamp_overflow(struct work_struct *work)
62 struct delayed_work *dwork = to_delayed_work(work);
63 struct mlx5e_tstamp *tstamp = container_of(dwork, struct mlx5e_tstamp,
66 write_lock(&tstamp->lock);
67 timecounter_read(&tstamp->clock);
68 write_unlock(&tstamp->lock);
69 schedule_delayed_work(&tstamp->overflow_work, tstamp->overflow_period);
72 int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr)
74 struct mlx5e_priv *priv = netdev_priv(dev);
75 struct hwtstamp_config config;
77 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
80 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
84 switch (config.tx_type) {
93 switch (config.rx_filter) {
94 case HWTSTAMP_FILTER_NONE:
96 case HWTSTAMP_FILTER_ALL:
97 case HWTSTAMP_FILTER_SOME:
98 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
99 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
100 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
101 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
102 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
103 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
104 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
105 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
106 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
107 case HWTSTAMP_FILTER_PTP_V2_EVENT:
108 case HWTSTAMP_FILTER_PTP_V2_SYNC:
109 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
110 config.rx_filter = HWTSTAMP_FILTER_ALL;
116 memcpy(&priv->tstamp.hwtstamp_config, &config, sizeof(config));
118 return copy_to_user(ifr->ifr_data, &config,
119 sizeof(config)) ? -EFAULT : 0;
122 int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr)
124 struct mlx5e_priv *priv = netdev_priv(dev);
125 struct hwtstamp_config *cfg = &priv->tstamp.hwtstamp_config;
127 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
130 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
133 static int mlx5e_ptp_settime(struct ptp_clock_info *ptp,
134 const struct timespec64 *ts)
136 struct mlx5e_tstamp *tstamp = container_of(ptp, struct mlx5e_tstamp,
138 u64 ns = timespec64_to_ns(ts);
140 write_lock(&tstamp->lock);
141 timecounter_init(&tstamp->clock, &tstamp->cycles, ns);
142 write_unlock(&tstamp->lock);
147 static int mlx5e_ptp_gettime(struct ptp_clock_info *ptp,
148 struct timespec64 *ts)
150 struct mlx5e_tstamp *tstamp = container_of(ptp, struct mlx5e_tstamp,
154 write_lock(&tstamp->lock);
155 ns = timecounter_read(&tstamp->clock);
156 write_unlock(&tstamp->lock);
158 *ts = ns_to_timespec64(ns);
163 static int mlx5e_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
165 struct mlx5e_tstamp *tstamp = container_of(ptp, struct mlx5e_tstamp,
168 write_lock(&tstamp->lock);
169 timecounter_adjtime(&tstamp->clock, delta);
170 write_unlock(&tstamp->lock);
175 static int mlx5e_ptp_adjfreq(struct ptp_clock_info *ptp, s32 delta)
180 struct mlx5e_tstamp *tstamp = container_of(ptp, struct mlx5e_tstamp,
188 adj = tstamp->nominal_c_mult;
190 diff = div_u64(adj, 1000000000ULL);
192 write_lock(&tstamp->lock);
193 timecounter_read(&tstamp->clock);
194 tstamp->cycles.mult = neg_adj ? tstamp->nominal_c_mult - diff :
195 tstamp->nominal_c_mult + diff;
196 write_unlock(&tstamp->lock);
201 static const struct ptp_clock_info mlx5e_ptp_clock_info = {
202 .owner = THIS_MODULE,
203 .max_adj = 100000000,
209 .adjfreq = mlx5e_ptp_adjfreq,
210 .adjtime = mlx5e_ptp_adjtime,
211 .gettime64 = mlx5e_ptp_gettime,
212 .settime64 = mlx5e_ptp_settime,
216 static void mlx5e_timestamp_init_config(struct mlx5e_tstamp *tstamp)
218 tstamp->hwtstamp_config.tx_type = HWTSTAMP_TX_OFF;
219 tstamp->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
222 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
224 struct mlx5e_tstamp *tstamp = &priv->tstamp;
229 mlx5e_timestamp_init_config(tstamp);
230 dev_freq = MLX5_CAP_GEN(priv->mdev, device_frequency_khz);
232 mlx5_core_warn(priv->mdev, "invalid device_frequency_khz, aborting HW clock init\n");
235 rwlock_init(&tstamp->lock);
236 tstamp->cycles.read = mlx5e_read_internal_timer;
237 tstamp->cycles.shift = MLX5E_CYCLES_SHIFT;
238 tstamp->cycles.mult = clocksource_khz2mult(dev_freq,
239 tstamp->cycles.shift);
240 tstamp->nominal_c_mult = tstamp->cycles.mult;
241 tstamp->cycles.mask = CLOCKSOURCE_MASK(41);
242 tstamp->mdev = priv->mdev;
244 timecounter_init(&tstamp->clock, &tstamp->cycles,
245 ktime_to_ns(ktime_get_real()));
247 /* Calculate period in seconds to call the overflow watchdog - to make
248 * sure counter is checked at least once every wrap around.
250 ns = cyclecounter_cyc2ns(&tstamp->cycles, tstamp->cycles.mask,
252 do_div(ns, NSEC_PER_SEC / 2 / HZ);
253 tstamp->overflow_period = ns;
255 INIT_DELAYED_WORK(&tstamp->overflow_work, mlx5e_timestamp_overflow);
256 if (tstamp->overflow_period)
257 schedule_delayed_work(&tstamp->overflow_work, 0);
259 mlx5_core_warn(priv->mdev, "invalid overflow period, overflow_work is not scheduled\n");
261 /* Configure the PHC */
262 tstamp->ptp_info = mlx5e_ptp_clock_info;
263 snprintf(tstamp->ptp_info.name, 16, "mlx5 ptp");
265 tstamp->ptp = ptp_clock_register(&tstamp->ptp_info,
266 &priv->mdev->pdev->dev);
267 if (IS_ERR_OR_NULL(tstamp->ptp)) {
268 mlx5_core_warn(priv->mdev, "ptp_clock_register failed %ld\n",
269 PTR_ERR(tstamp->ptp));
274 void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv)
276 struct mlx5e_tstamp *tstamp = &priv->tstamp;
278 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
281 if (priv->tstamp.ptp) {
282 ptp_clock_unregister(priv->tstamp.ptp);
283 priv->tstamp.ptp = NULL;
286 cancel_delayed_work_sync(&tstamp->overflow_work);