2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/if_vlan.h>
34 #include <linux/etherdevice.h>
35 #include <linux/timecounter.h>
36 #include <linux/net_tstamp.h>
37 #include <linux/ptp_clock_kernel.h>
38 #include <linux/mlx5/driver.h>
39 #include <linux/mlx5/qp.h>
40 #include <linux/mlx5/cq.h>
41 #include <linux/mlx5/vport.h>
42 #include <linux/mlx5/transobj.h>
44 #include "mlx5_core.h"
46 #define MLX5E_MAX_NUM_TC 8
48 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
49 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
50 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
52 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1
53 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
54 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
56 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
57 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
58 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
59 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
60 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
61 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
63 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
64 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
65 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
66 #define MLX5E_TX_CQ_POLL_BUDGET 128
67 #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */
68 #define MLX5E_SQ_BF_BUDGET 16
70 #define MLX5E_NUM_MAIN_GROUPS 9
72 static const char vport_strings[][ETH_GSTRING_LEN] = {
73 /* vport statistics */
86 "rx_multicast_packets",
88 "tx_multicast_packets",
90 "rx_broadcast_packets",
92 "tx_broadcast_packets",
110 struct mlx5e_vport_stats {
116 u64 rx_error_packets;
118 u64 tx_error_packets;
120 u64 rx_unicast_packets;
121 u64 rx_unicast_bytes;
122 u64 tx_unicast_packets;
123 u64 tx_unicast_bytes;
124 u64 rx_multicast_packets;
125 u64 rx_multicast_bytes;
126 u64 tx_multicast_packets;
127 u64 tx_multicast_bytes;
128 u64 rx_broadcast_packets;
129 u64 rx_broadcast_bytes;
130 u64 tx_broadcast_packets;
131 u64 tx_broadcast_bytes;
142 u64 tx_queue_stopped;
144 u64 tx_queue_dropped;
147 #define NUM_VPORT_COUNTERS 32
150 static const char pport_strings[][ETH_GSTRING_LEN] = {
151 /* IEEE802.3 counters */
162 "in_range_len_errors",
172 /* RFC2863 counters */
184 "out_multicast_pkts",
185 "out_broadcast_pkts",
187 /* RFC2819 counters */
208 "p8192to10239octets",
211 #define NUM_IEEE_802_3_COUNTERS 19
212 #define NUM_RFC_2863_COUNTERS 13
213 #define NUM_RFC_2819_COUNTERS 21
214 #define NUM_PPORT_COUNTERS (NUM_IEEE_802_3_COUNTERS + \
215 NUM_RFC_2863_COUNTERS + \
216 NUM_RFC_2819_COUNTERS)
218 struct mlx5e_pport_stats {
219 __be64 IEEE_802_3_counters[NUM_IEEE_802_3_COUNTERS];
220 __be64 RFC_2863_counters[NUM_RFC_2863_COUNTERS];
221 __be64 RFC_2819_counters[NUM_RFC_2819_COUNTERS];
224 static const char rq_stats_strings[][ETH_GSTRING_LEN] = {
233 struct mlx5e_rq_stats {
240 #define NUM_RQ_STATS 6
243 static const char sq_stats_strings[][ETH_GSTRING_LEN] = {
254 struct mlx5e_sq_stats {
258 u64 csum_offload_none;
263 #define NUM_SQ_STATS 8
267 struct mlx5e_vport_stats vport;
268 struct mlx5e_pport_stats pport;
271 struct mlx5e_params {
275 u8 default_vlan_prio;
277 u16 rx_cq_moderation_usec;
278 u16 rx_cq_moderation_pkts;
279 u16 tx_cq_moderation_usec;
280 u16 tx_cq_moderation_pkts;
286 u8 toeplitz_hash_key[40];
287 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
290 struct mlx5e_tstamp {
292 struct cyclecounter cycles;
293 struct timecounter clock;
294 struct hwtstamp_config hwtstamp_config;
296 unsigned long overflow_period;
297 struct delayed_work overflow_work;
298 struct mlx5_core_dev *mdev;
299 struct ptp_clock *ptp;
300 struct ptp_clock_info ptp_info;
304 MLX5E_RQ_STATE_POST_WQES_ENABLE,
308 /* data path - accessed per cqe */
311 /* data path - accessed per napi poll */
312 struct napi_struct *napi;
313 struct mlx5_core_cq mcq;
314 struct mlx5e_channel *channel;
315 struct mlx5e_priv *priv;
318 struct mlx5_wq_ctrl wq_ctrl;
319 } ____cacheline_aligned_in_smp;
323 struct mlx5_wq_ll wq;
325 struct sk_buff **skb;
328 struct net_device *netdev;
329 struct mlx5e_tstamp *tstamp;
330 struct mlx5e_rq_stats stats;
337 struct mlx5_wq_ctrl wq_ctrl;
339 struct mlx5e_channel *channel;
340 struct mlx5e_priv *priv;
341 } ____cacheline_aligned_in_smp;
343 struct mlx5e_tx_wqe_info {
349 enum mlx5e_dma_map_type {
350 MLX5E_DMA_MAP_SINGLE,
354 struct mlx5e_sq_dma {
357 enum mlx5e_dma_map_type type;
361 MLX5E_SQ_STATE_WAKE_TXQ_ENABLE,
367 /* dirtied @completion */
372 u16 pc ____cacheline_aligned_in_smp;
377 struct mlx5e_sq_stats stats;
381 /* pointers to per packet info: write@xmit, read@completion */
382 struct sk_buff **skb;
383 struct mlx5e_sq_dma *dma_fifo;
384 struct mlx5e_tx_wqe_info *wqe_info;
387 struct mlx5_wq_cyc wq;
389 void __iomem *uar_map;
390 void __iomem *uar_bf_map;
391 struct netdev_queue *txq;
397 struct mlx5e_tstamp *tstamp;
402 struct mlx5_wq_ctrl wq_ctrl;
404 struct mlx5e_channel *channel;
406 } ____cacheline_aligned_in_smp;
408 static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
410 return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) ||
415 MLX5E_CHANNEL_NAPI_SCHED = 1,
418 struct mlx5e_channel {
421 struct mlx5e_sq sq[MLX5E_MAX_NUM_TC];
422 struct napi_struct napi;
424 struct net_device *netdev;
430 struct mlx5e_priv *priv;
435 enum mlx5e_traffic_types {
440 MLX5E_TT_IPV4_IPSEC_AH,
441 MLX5E_TT_IPV6_IPSEC_AH,
442 MLX5E_TT_IPV4_IPSEC_ESP,
443 MLX5E_TT_IPV6_IPSEC_ESP,
450 #define IS_HASHING_TT(tt) (tt != MLX5E_TT_ANY)
453 MLX5E_INDIRECTION_RQT,
458 struct mlx5e_eth_addr_info {
459 u8 addr[ETH_ALEN + 2];
461 struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT];
464 #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE)
466 struct mlx5e_eth_addr_db {
467 struct hlist_head netdev_uc[MLX5E_ETH_ADDR_HASH_SIZE];
468 struct hlist_head netdev_mc[MLX5E_ETH_ADDR_HASH_SIZE];
469 struct mlx5e_eth_addr_info broadcast;
470 struct mlx5e_eth_addr_info allmulti;
471 struct mlx5e_eth_addr_info promisc;
472 bool broadcast_enabled;
473 bool allmulti_enabled;
474 bool promisc_enabled;
478 MLX5E_STATE_ASYNC_EVENTS_ENABLE,
480 MLX5E_STATE_DESTROYING,
483 struct mlx5e_vlan_db {
484 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
485 struct mlx5_flow_rule *active_vlans_rule[VLAN_N_VID];
486 struct mlx5_flow_rule *untagged_rule;
487 struct mlx5_flow_rule *any_vlan_rule;
488 bool filter_disabled;
491 struct mlx5e_flow_table {
493 struct mlx5_flow_table *t;
494 struct mlx5_flow_group **g;
497 struct mlx5e_flow_tables {
498 struct mlx5_flow_namespace *ns;
499 struct mlx5e_flow_table vlan;
500 struct mlx5e_flow_table main;
504 /* priv data path fields - start */
505 int default_vlan_prio;
506 struct mlx5e_sq **txq_to_sq_map;
507 int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
508 /* priv data path fields - end */
511 struct mutex state_lock; /* Protects Interface state */
512 struct mlx5_uar cq_uar;
515 struct mlx5_core_mr mr;
516 struct mlx5e_rq drop_rq;
518 struct mlx5e_channel **channel;
519 u32 tisn[MLX5E_MAX_NUM_TC];
520 u32 rqtn[MLX5E_NUM_RQT];
521 u32 tirn[MLX5E_NUM_TT];
523 struct mlx5e_flow_tables fts;
524 struct mlx5e_eth_addr_db eth_addr;
525 struct mlx5e_vlan_db vlan;
527 struct mlx5e_params params;
528 spinlock_t async_events_spinlock; /* sync hw events */
529 struct work_struct update_carrier_work;
530 struct work_struct set_rx_mode_work;
531 struct delayed_work update_stats_work;
533 struct mlx5_core_dev *mdev;
534 struct net_device *netdev;
535 struct mlx5e_stats stats;
536 struct mlx5e_tstamp tstamp;
539 #define MLX5E_NET_IP_ALIGN 2
541 struct mlx5e_tx_wqe {
542 struct mlx5_wqe_ctrl_seg ctrl;
543 struct mlx5_wqe_eth_seg eth;
546 struct mlx5e_rx_wqe {
547 struct mlx5_wqe_srq_next_seg next;
548 struct mlx5_wqe_data_seg data;
551 enum mlx5e_link_mode {
552 MLX5E_1000BASE_CX_SGMII = 0,
553 MLX5E_1000BASE_KX = 1,
554 MLX5E_10GBASE_CX4 = 2,
555 MLX5E_10GBASE_KX4 = 3,
556 MLX5E_10GBASE_KR = 4,
557 MLX5E_20GBASE_KR2 = 5,
558 MLX5E_40GBASE_CR4 = 6,
559 MLX5E_40GBASE_KR4 = 7,
560 MLX5E_56GBASE_R4 = 8,
561 MLX5E_10GBASE_CR = 12,
562 MLX5E_10GBASE_SR = 13,
563 MLX5E_10GBASE_ER = 14,
564 MLX5E_40GBASE_SR4 = 15,
565 MLX5E_40GBASE_LR4 = 16,
566 MLX5E_100GBASE_CR4 = 20,
567 MLX5E_100GBASE_SR4 = 21,
568 MLX5E_100GBASE_KR4 = 22,
569 MLX5E_100GBASE_LR4 = 23,
570 MLX5E_100BASE_TX = 24,
571 MLX5E_100BASE_T = 25,
572 MLX5E_10GBASE_T = 26,
573 MLX5E_25GBASE_CR = 27,
574 MLX5E_25GBASE_KR = 28,
575 MLX5E_25GBASE_SR = 29,
576 MLX5E_50GBASE_CR2 = 30,
577 MLX5E_50GBASE_KR2 = 31,
578 MLX5E_LINK_MODES_NUMBER,
581 #define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
583 void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);
584 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
585 void *accel_priv, select_queue_fallback_t fallback);
586 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
588 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
589 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
590 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
591 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq);
592 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
593 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
594 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
596 void mlx5e_update_stats(struct mlx5e_priv *priv);
598 int mlx5e_create_flow_tables(struct mlx5e_priv *priv);
599 void mlx5e_destroy_flow_tables(struct mlx5e_priv *priv);
600 void mlx5e_init_eth_addr(struct mlx5e_priv *priv);
601 void mlx5e_set_rx_mode_work(struct work_struct *work);
603 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
604 struct skb_shared_hwtstamps *hwts);
605 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
606 void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
607 int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr);
608 int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr);
610 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
612 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
614 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
615 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
617 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix);
618 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv);
620 int mlx5e_open_locked(struct net_device *netdev);
621 int mlx5e_close_locked(struct net_device *netdev);
623 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
624 struct mlx5e_tx_wqe *wqe, int bf_sz)
626 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
628 /* ensure wqe is visible to device before updating doorbell record */
631 *sq->wq.db = cpu_to_be32(sq->pc);
633 /* ensure doorbell record is visible to device before ringing the
639 __iowrite64_copy(sq->uar_bf_map + ofst, &wqe->ctrl, bf_sz);
641 /* flush the write-combining mapped buffer */
645 mlx5_write64((__be32 *)&wqe->ctrl, sq->uar_map + ofst, NULL);
648 sq->bf_offset ^= sq->bf_buf_size;
651 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
653 struct mlx5_core_cq *mcq;
656 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
659 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
661 return min_t(int, mdev->priv.eq_table.num_comp_vectors,
662 MLX5E_MAX_NUM_CHANNELS);
665 extern const struct ethtool_ops mlx5e_ethtool_ops;
666 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);