2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
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8 * OpenIB.org BSD license below:
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11 * without modification, are permitted provided that the following
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15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
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21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
47 #include "mlx5_core.h"
49 #define MLX5E_MAX_NUM_TC 8
51 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
52 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
53 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
55 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1
56 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
57 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
59 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
60 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
61 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
62 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
63 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
64 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
66 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
67 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
68 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
69 #define MLX5E_TX_CQ_POLL_BUDGET 128
70 #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */
71 #define MLX5E_SQ_BF_BUDGET 16
73 #define MLX5E_NUM_MAIN_GROUPS 9
75 #ifdef CONFIG_MLX5_CORE_EN_DCB
76 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
77 #define MLX5E_MIN_BW_ALLOC 1 /* Min percentage of BW allocation */
80 static const char vport_strings[][ETH_GSTRING_LEN] = {
81 /* vport statistics */
94 "rx_multicast_packets",
96 "tx_multicast_packets",
98 "rx_broadcast_packets",
100 "tx_broadcast_packets",
101 "tx_broadcast_bytes",
121 struct mlx5e_vport_stats {
127 u64 rx_error_packets;
129 u64 tx_error_packets;
131 u64 rx_unicast_packets;
132 u64 rx_unicast_bytes;
133 u64 tx_unicast_packets;
134 u64 tx_unicast_bytes;
135 u64 rx_multicast_packets;
136 u64 rx_multicast_bytes;
137 u64 tx_multicast_packets;
138 u64 tx_multicast_bytes;
139 u64 rx_broadcast_packets;
140 u64 rx_broadcast_bytes;
141 u64 tx_broadcast_packets;
142 u64 tx_broadcast_bytes;
147 u64 tso_inner_packets;
156 u64 tx_queue_stopped;
158 u64 tx_queue_dropped;
161 #define NUM_VPORT_COUNTERS 35
164 static const char pport_strings[][ETH_GSTRING_LEN] = {
165 /* IEEE802.3 counters */
176 "in_range_len_errors",
186 /* RFC2863 counters */
198 "out_multicast_pkts",
199 "out_broadcast_pkts",
201 /* RFC2819 counters */
222 "p8192to10239octets",
225 #define NUM_IEEE_802_3_COUNTERS 19
226 #define NUM_RFC_2863_COUNTERS 13
227 #define NUM_RFC_2819_COUNTERS 21
228 #define NUM_PPORT_COUNTERS (NUM_IEEE_802_3_COUNTERS + \
229 NUM_RFC_2863_COUNTERS + \
230 NUM_RFC_2819_COUNTERS)
232 struct mlx5e_pport_stats {
233 __be64 IEEE_802_3_counters[NUM_IEEE_802_3_COUNTERS];
234 __be64 RFC_2863_counters[NUM_RFC_2863_COUNTERS];
235 __be64 RFC_2819_counters[NUM_RFC_2819_COUNTERS];
238 static const char rq_stats_strings[][ETH_GSTRING_LEN] = {
248 struct mlx5e_rq_stats {
256 #define NUM_RQ_STATS 7
259 static const char sq_stats_strings[][ETH_GSTRING_LEN] = {
266 "csum_offload_inner",
274 struct mlx5e_sq_stats {
275 /* commonly accessed in data path */
280 u64 tso_inner_packets;
282 u64 csum_offload_inner;
284 /* less likely accessed in data path */
285 u64 csum_offload_none;
289 #define NUM_SQ_STATS 12
293 struct mlx5e_vport_stats vport;
294 struct mlx5e_pport_stats pport;
297 struct mlx5e_params {
302 u16 rx_cq_moderation_usec;
303 u16 rx_cq_moderation_pkts;
304 u16 tx_cq_moderation_usec;
305 u16 tx_cq_moderation_pkts;
311 u8 toeplitz_hash_key[40];
312 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
313 #ifdef CONFIG_MLX5_CORE_EN_DCB
318 struct mlx5e_tstamp {
320 struct cyclecounter cycles;
321 struct timecounter clock;
322 struct hwtstamp_config hwtstamp_config;
324 unsigned long overflow_period;
325 struct delayed_work overflow_work;
326 struct mlx5_core_dev *mdev;
327 struct ptp_clock *ptp;
328 struct ptp_clock_info ptp_info;
332 MLX5E_RQ_STATE_POST_WQES_ENABLE,
336 /* data path - accessed per cqe */
339 /* data path - accessed per napi poll */
340 struct napi_struct *napi;
341 struct mlx5_core_cq mcq;
342 struct mlx5e_channel *channel;
343 struct mlx5e_priv *priv;
346 struct mlx5_wq_ctrl wq_ctrl;
347 } ____cacheline_aligned_in_smp;
351 struct mlx5_wq_ll wq;
353 struct sk_buff **skb;
356 struct net_device *netdev;
357 struct mlx5e_tstamp *tstamp;
358 struct mlx5e_rq_stats stats;
365 struct mlx5_wq_ctrl wq_ctrl;
367 struct mlx5e_channel *channel;
368 struct mlx5e_priv *priv;
369 } ____cacheline_aligned_in_smp;
371 struct mlx5e_tx_wqe_info {
377 enum mlx5e_dma_map_type {
378 MLX5E_DMA_MAP_SINGLE,
382 struct mlx5e_sq_dma {
385 enum mlx5e_dma_map_type type;
389 MLX5E_SQ_STATE_WAKE_TXQ_ENABLE,
390 MLX5E_SQ_STATE_BF_ENABLE,
396 /* dirtied @completion */
401 u16 pc ____cacheline_aligned_in_smp;
406 struct mlx5e_sq_stats stats;
410 /* pointers to per packet info: write@xmit, read@completion */
411 struct sk_buff **skb;
412 struct mlx5e_sq_dma *dma_fifo;
413 struct mlx5e_tx_wqe_info *wqe_info;
416 struct mlx5_wq_cyc wq;
418 void __iomem *uar_map;
419 struct netdev_queue *txq;
425 struct mlx5e_tstamp *tstamp;
430 struct mlx5_wq_ctrl wq_ctrl;
432 struct mlx5e_channel *channel;
434 } ____cacheline_aligned_in_smp;
436 static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
438 return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) ||
443 MLX5E_CHANNEL_NAPI_SCHED = 1,
446 struct mlx5e_channel {
449 struct mlx5e_sq sq[MLX5E_MAX_NUM_TC];
450 struct napi_struct napi;
452 struct net_device *netdev;
458 struct mlx5e_priv *priv;
463 enum mlx5e_traffic_types {
468 MLX5E_TT_IPV4_IPSEC_AH,
469 MLX5E_TT_IPV6_IPSEC_AH,
470 MLX5E_TT_IPV4_IPSEC_ESP,
471 MLX5E_TT_IPV6_IPSEC_ESP,
478 #define IS_HASHING_TT(tt) (tt != MLX5E_TT_ANY)
481 MLX5E_INDIRECTION_RQT,
486 struct mlx5e_eth_addr_info {
487 u8 addr[ETH_ALEN + 2];
489 struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT];
492 #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE)
494 struct mlx5e_eth_addr_db {
495 struct hlist_head netdev_uc[MLX5E_ETH_ADDR_HASH_SIZE];
496 struct hlist_head netdev_mc[MLX5E_ETH_ADDR_HASH_SIZE];
497 struct mlx5e_eth_addr_info broadcast;
498 struct mlx5e_eth_addr_info allmulti;
499 struct mlx5e_eth_addr_info promisc;
500 bool broadcast_enabled;
501 bool allmulti_enabled;
502 bool promisc_enabled;
506 MLX5E_STATE_ASYNC_EVENTS_ENABLE,
508 MLX5E_STATE_DESTROYING,
511 struct mlx5e_vlan_db {
512 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
513 struct mlx5_flow_rule *active_vlans_rule[VLAN_N_VID];
514 struct mlx5_flow_rule *untagged_rule;
515 struct mlx5_flow_rule *any_vlan_rule;
516 bool filter_disabled;
519 struct mlx5e_vxlan_db {
520 spinlock_t lock; /* protect vxlan table */
521 struct radix_tree_root tree;
524 struct mlx5e_flow_table {
526 struct mlx5_flow_table *t;
527 struct mlx5_flow_group **g;
530 struct mlx5e_flow_tables {
531 struct mlx5_flow_namespace *ns;
532 struct mlx5e_flow_table vlan;
533 struct mlx5e_flow_table main;
537 /* priv data path fields - start */
538 struct mlx5e_sq **txq_to_sq_map;
539 int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
540 /* priv data path fields - end */
543 struct mutex state_lock; /* Protects Interface state */
544 struct mlx5_uar cq_uar;
547 struct mlx5_core_mr mr;
548 struct mlx5e_rq drop_rq;
550 struct mlx5e_channel **channel;
551 u32 tisn[MLX5E_MAX_NUM_TC];
552 u32 rqtn[MLX5E_NUM_RQT];
553 u32 tirn[MLX5E_NUM_TT];
555 struct mlx5e_flow_tables fts;
556 struct mlx5e_eth_addr_db eth_addr;
557 struct mlx5e_vlan_db vlan;
558 struct mlx5e_vxlan_db vxlan;
560 struct mlx5e_params params;
561 struct work_struct update_carrier_work;
562 struct work_struct set_rx_mode_work;
563 struct delayed_work update_stats_work;
565 struct mlx5_core_dev *mdev;
566 struct net_device *netdev;
567 struct mlx5e_stats stats;
568 struct mlx5e_tstamp tstamp;
571 #define MLX5E_NET_IP_ALIGN 2
573 struct mlx5e_tx_wqe {
574 struct mlx5_wqe_ctrl_seg ctrl;
575 struct mlx5_wqe_eth_seg eth;
578 struct mlx5e_rx_wqe {
579 struct mlx5_wqe_srq_next_seg next;
580 struct mlx5_wqe_data_seg data;
583 enum mlx5e_link_mode {
584 MLX5E_1000BASE_CX_SGMII = 0,
585 MLX5E_1000BASE_KX = 1,
586 MLX5E_10GBASE_CX4 = 2,
587 MLX5E_10GBASE_KX4 = 3,
588 MLX5E_10GBASE_KR = 4,
589 MLX5E_20GBASE_KR2 = 5,
590 MLX5E_40GBASE_CR4 = 6,
591 MLX5E_40GBASE_KR4 = 7,
592 MLX5E_56GBASE_R4 = 8,
593 MLX5E_10GBASE_CR = 12,
594 MLX5E_10GBASE_SR = 13,
595 MLX5E_10GBASE_ER = 14,
596 MLX5E_40GBASE_SR4 = 15,
597 MLX5E_40GBASE_LR4 = 16,
598 MLX5E_100GBASE_CR4 = 20,
599 MLX5E_100GBASE_SR4 = 21,
600 MLX5E_100GBASE_KR4 = 22,
601 MLX5E_100GBASE_LR4 = 23,
602 MLX5E_100BASE_TX = 24,
603 MLX5E_100BASE_T = 25,
604 MLX5E_10GBASE_T = 26,
605 MLX5E_25GBASE_CR = 27,
606 MLX5E_25GBASE_KR = 28,
607 MLX5E_25GBASE_SR = 29,
608 MLX5E_50GBASE_CR2 = 30,
609 MLX5E_50GBASE_KR2 = 31,
610 MLX5E_LINK_MODES_NUMBER,
613 #define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
615 void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);
616 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
617 void *accel_priv, select_queue_fallback_t fallback);
618 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
620 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
621 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
622 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
623 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq);
624 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
625 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
626 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
628 void mlx5e_update_stats(struct mlx5e_priv *priv);
630 int mlx5e_create_flow_tables(struct mlx5e_priv *priv);
631 void mlx5e_destroy_flow_tables(struct mlx5e_priv *priv);
632 void mlx5e_init_eth_addr(struct mlx5e_priv *priv);
633 void mlx5e_set_rx_mode_work(struct work_struct *work);
635 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
636 struct skb_shared_hwtstamps *hwts);
637 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
638 void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
639 int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr);
640 int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr);
642 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
644 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
646 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
647 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
649 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix);
650 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv);
652 int mlx5e_open_locked(struct net_device *netdev);
653 int mlx5e_close_locked(struct net_device *netdev);
654 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
657 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
658 struct mlx5e_tx_wqe *wqe, int bf_sz)
660 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
662 /* ensure wqe is visible to device before updating doorbell record */
665 *sq->wq.db = cpu_to_be32(sq->pc);
667 /* ensure doorbell record is visible to device before ringing the
672 __iowrite64_copy(sq->uar_map + ofst, &wqe->ctrl, bf_sz);
674 mlx5_write64((__be32 *)&wqe->ctrl, sq->uar_map + ofst, NULL);
675 /* flush the write-combining mapped buffer */
678 sq->bf_offset ^= sq->bf_buf_size;
681 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
683 struct mlx5_core_cq *mcq;
686 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
689 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
691 return min_t(int, mdev->priv.eq_table.num_comp_vectors,
692 MLX5E_MAX_NUM_CHANNELS);
695 extern const struct ethtool_ops mlx5e_ethtool_ops;
696 #ifdef CONFIG_MLX5_CORE_EN_DCB
697 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
698 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
701 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
703 #endif /* __MLX5_EN_H__ */