2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/rhashtable.h>
48 #include "mlx5_core.h"
51 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
53 #define MLX5E_MAX_NUM_TC 8
55 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
56 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
57 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
59 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1
60 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
61 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
63 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1
64 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x4
65 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6
67 #define MLX5_MPWRQ_LOG_STRIDE_SIZE 6 /* >= 6, HW restriction */
68 #define MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS 8 /* >= 6, HW restriction */
69 #define MLX5_MPWRQ_LOG_WQE_SZ 17
70 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
71 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
72 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
73 #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \
74 MLX5_MPWRQ_WQE_PAGE_ORDER)
75 #define MLX5_CHANNEL_MAX_NUM_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8) * \
76 BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW))
77 #define MLX5_UMR_ALIGN (2048)
78 #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128)
80 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
81 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
82 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
83 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
84 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
85 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
86 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
88 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
89 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
90 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
91 #define MLX5E_TX_CQ_POLL_BUDGET 128
92 #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */
93 #define MLX5E_SQ_BF_BUDGET 16
95 #define MLX5E_NUM_MAIN_GROUPS 9
97 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
100 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
101 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
104 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
109 static inline int mlx5_min_log_rq_size(int wq_type)
112 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
113 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
115 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE;
119 static inline int mlx5_max_log_rq_size(int wq_type)
122 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
123 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW;
125 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
129 struct mlx5e_tx_wqe {
130 struct mlx5_wqe_ctrl_seg ctrl;
131 struct mlx5_wqe_eth_seg eth;
134 struct mlx5e_rx_wqe {
135 struct mlx5_wqe_srq_next_seg next;
136 struct mlx5_wqe_data_seg data;
139 struct mlx5e_umr_wqe {
140 struct mlx5_wqe_ctrl_seg ctrl;
141 struct mlx5_wqe_umr_ctrl_seg uctrl;
142 struct mlx5_mkey_seg mkc;
143 struct mlx5_wqe_data_seg data;
146 #ifdef CONFIG_MLX5_CORE_EN_DCB
147 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
150 struct mlx5e_params {
153 u8 mpwqe_log_stride_sz;
154 u8 mpwqe_log_num_strides;
158 bool rx_cqe_compress_admin;
159 bool rx_cqe_compress;
160 u16 rx_cq_moderation_usec;
161 u16 rx_cq_moderation_pkts;
162 u16 tx_cq_moderation_usec;
163 u16 tx_cq_moderation_pkts;
169 u8 toeplitz_hash_key[40];
170 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
171 bool vlan_strip_disable;
172 #ifdef CONFIG_MLX5_CORE_EN_DCB
177 struct mlx5e_tstamp {
179 struct cyclecounter cycles;
180 struct timecounter clock;
181 struct hwtstamp_config hwtstamp_config;
183 unsigned long overflow_period;
184 struct delayed_work overflow_work;
185 struct mlx5_core_dev *mdev;
186 struct ptp_clock *ptp;
187 struct ptp_clock_info ptp_info;
191 MLX5E_RQ_STATE_POST_WQES_ENABLE,
192 MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS,
193 MLX5E_RQ_STATE_FLUSH_TIMEOUT,
197 /* data path - accessed per cqe */
200 /* data path - accessed per napi poll */
201 struct napi_struct *napi;
202 struct mlx5_core_cq mcq;
203 struct mlx5e_channel *channel;
204 struct mlx5e_priv *priv;
206 /* cqe decompression */
207 struct mlx5_cqe64 title;
208 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
211 u16 decmprs_wqe_counter;
214 struct mlx5_wq_ctrl wq_ctrl;
215 } ____cacheline_aligned_in_smp;
218 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq *rq,
219 struct mlx5_cqe64 *cqe);
220 typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe,
223 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq *rq, u16 ix);
225 struct mlx5e_dma_info {
232 struct mlx5_wq_ll wq;
234 struct sk_buff **skb;
235 struct mlx5e_mpw_info *wqe_info;
240 struct net_device *netdev;
241 struct mlx5e_tstamp *tstamp;
242 struct mlx5e_rq_stats stats;
244 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
245 mlx5e_fp_alloc_wqe alloc_wqe;
246 mlx5e_fp_dealloc_wqe dealloc_wqe;
252 struct mlx5_wq_ctrl wq_ctrl;
255 u32 mpwqe_num_strides;
257 struct mlx5e_channel *channel;
258 struct mlx5e_priv *priv;
259 } ____cacheline_aligned_in_smp;
261 struct mlx5e_umr_dma_info {
263 __be64 *mtt_no_align;
265 struct mlx5e_dma_info *dma_info;
268 struct mlx5e_mpw_info {
270 struct mlx5e_dma_info dma_info;
271 struct mlx5e_umr_dma_info umr;
273 u16 consumed_strides;
274 u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE];
276 void (*dma_pre_sync)(struct device *pdev,
277 struct mlx5e_mpw_info *wi,
278 u32 wqe_offset, u32 len);
279 void (*add_skb_frag)(struct mlx5e_rq *rq,
281 struct mlx5e_mpw_info *wi,
282 u32 page_idx, u32 frag_offset, u32 len);
283 void (*copy_skb_header)(struct device *pdev,
285 struct mlx5e_mpw_info *wi,
286 u32 page_idx, u32 offset,
288 void (*free_wqe)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi);
291 struct mlx5e_tx_wqe_info {
297 enum mlx5e_dma_map_type {
298 MLX5E_DMA_MAP_SINGLE,
302 struct mlx5e_sq_dma {
305 enum mlx5e_dma_map_type type;
309 MLX5E_SQ_STATE_WAKE_TXQ_ENABLE,
310 MLX5E_SQ_STATE_BF_ENABLE,
311 MLX5E_SQ_STATE_TX_TIMEOUT,
314 struct mlx5e_ico_wqe_info {
322 /* dirtied @completion */
327 u16 pc ____cacheline_aligned_in_smp;
332 struct mlx5e_sq_stats stats;
336 /* pointers to per packet info: write@xmit, read@completion */
337 struct sk_buff **skb;
338 struct mlx5e_sq_dma *dma_fifo;
339 struct mlx5e_tx_wqe_info *wqe_info;
342 struct mlx5_wq_cyc wq;
344 void __iomem *uar_map;
345 struct netdev_queue *txq;
351 struct mlx5e_tstamp *tstamp;
356 struct mlx5_wq_ctrl wq_ctrl;
358 struct mlx5e_channel *channel;
360 struct mlx5e_ico_wqe_info *ico_wqe_info;
361 } ____cacheline_aligned_in_smp;
363 static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
365 return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) ||
370 MLX5E_CHANNEL_NAPI_SCHED = 1,
373 struct mlx5e_channel {
376 struct mlx5e_sq sq[MLX5E_MAX_NUM_TC];
377 struct mlx5e_sq icosq; /* internal control operations */
378 struct napi_struct napi;
380 struct net_device *netdev;
386 struct mlx5e_priv *priv;
391 enum mlx5e_traffic_types {
396 MLX5E_TT_IPV4_IPSEC_AH,
397 MLX5E_TT_IPV6_IPSEC_AH,
398 MLX5E_TT_IPV4_IPSEC_ESP,
399 MLX5E_TT_IPV6_IPSEC_ESP,
404 MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY,
408 MLX5E_STATE_ASYNC_EVENTS_ENABLED,
410 MLX5E_STATE_DESTROYING,
413 struct mlx5e_vxlan_db {
414 spinlock_t lock; /* protect vxlan table */
415 struct radix_tree_root tree;
418 struct mlx5e_l2_rule {
419 u8 addr[ETH_ALEN + 2];
420 struct mlx5_flow_rule *rule;
423 struct mlx5e_flow_table {
425 struct mlx5_flow_table *t;
426 struct mlx5_flow_group **g;
429 #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE)
431 struct mlx5e_tc_table {
432 struct mlx5_flow_table *t;
434 struct rhashtable_params ht_params;
435 struct rhashtable ht;
438 struct mlx5e_vlan_table {
439 struct mlx5e_flow_table ft;
440 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
441 struct mlx5_flow_rule *active_vlans_rule[VLAN_N_VID];
442 struct mlx5_flow_rule *untagged_rule;
443 struct mlx5_flow_rule *any_vlan_rule;
444 bool filter_disabled;
447 struct mlx5e_l2_table {
448 struct mlx5e_flow_table ft;
449 struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE];
450 struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE];
451 struct mlx5e_l2_rule broadcast;
452 struct mlx5e_l2_rule allmulti;
453 struct mlx5e_l2_rule promisc;
454 bool broadcast_enabled;
455 bool allmulti_enabled;
456 bool promisc_enabled;
459 /* L3/L4 traffic type classifier */
460 struct mlx5e_ttc_table {
461 struct mlx5e_flow_table ft;
462 struct mlx5_flow_rule *rules[MLX5E_NUM_TT];
465 #define ARFS_HASH_SHIFT BITS_PER_BYTE
466 #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE)
468 struct mlx5e_flow_table ft;
469 struct mlx5_flow_rule *default_rule;
470 struct hlist_head rules_hash[ARFS_HASH_SIZE];
481 struct mlx5e_arfs_tables {
482 struct arfs_table arfs_tables[ARFS_NUM_TYPES];
483 /* Protect aRFS rules list */
484 spinlock_t arfs_lock;
485 struct list_head rules;
487 struct workqueue_struct *wq;
492 MLX5E_VLAN_FT_LEVEL = 0,
498 struct mlx5e_flow_steering {
499 struct mlx5_flow_namespace *ns;
500 struct mlx5e_tc_table tc;
501 struct mlx5e_vlan_table vlan;
502 struct mlx5e_l2_table l2;
503 struct mlx5e_ttc_table ttc;
504 struct mlx5e_arfs_tables arfs;
507 struct mlx5e_direct_tir {
518 /* priv data path fields - start */
519 struct mlx5e_sq **txq_to_sq_map;
520 int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
521 /* priv data path fields - end */
524 struct mutex state_lock; /* Protects Interface state */
525 struct mlx5_uar cq_uar;
528 struct mlx5_core_mkey mkey;
529 struct mlx5_core_mkey umr_mkey;
530 struct mlx5e_rq drop_rq;
532 struct mlx5e_channel **channel;
533 u32 tisn[MLX5E_MAX_NUM_TC];
535 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
536 struct mlx5e_direct_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
538 struct mlx5e_flow_steering fs;
539 struct mlx5e_vxlan_db vxlan;
541 struct mlx5e_params params;
542 struct workqueue_struct *wq;
543 struct work_struct update_carrier_work;
544 struct work_struct set_rx_mode_work;
545 struct work_struct tx_timeout_work;
546 struct delayed_work update_stats_work;
548 struct mlx5_core_dev *mdev;
549 struct net_device *netdev;
550 struct mlx5e_stats stats;
551 struct mlx5e_tstamp tstamp;
555 enum mlx5e_link_mode {
556 MLX5E_1000BASE_CX_SGMII = 0,
557 MLX5E_1000BASE_KX = 1,
558 MLX5E_10GBASE_CX4 = 2,
559 MLX5E_10GBASE_KX4 = 3,
560 MLX5E_10GBASE_KR = 4,
561 MLX5E_20GBASE_KR2 = 5,
562 MLX5E_40GBASE_CR4 = 6,
563 MLX5E_40GBASE_KR4 = 7,
564 MLX5E_56GBASE_R4 = 8,
565 MLX5E_10GBASE_CR = 12,
566 MLX5E_10GBASE_SR = 13,
567 MLX5E_10GBASE_ER = 14,
568 MLX5E_40GBASE_SR4 = 15,
569 MLX5E_40GBASE_LR4 = 16,
570 MLX5E_100GBASE_CR4 = 20,
571 MLX5E_100GBASE_SR4 = 21,
572 MLX5E_100GBASE_KR4 = 22,
573 MLX5E_100GBASE_LR4 = 23,
574 MLX5E_100BASE_TX = 24,
575 MLX5E_1000BASE_T = 25,
576 MLX5E_10GBASE_T = 26,
577 MLX5E_25GBASE_CR = 27,
578 MLX5E_25GBASE_KR = 28,
579 MLX5E_25GBASE_SR = 29,
580 MLX5E_50GBASE_CR2 = 30,
581 MLX5E_50GBASE_KR2 = 31,
582 MLX5E_LINK_MODES_NUMBER,
585 #define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
587 void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);
588 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
589 void *accel_priv, select_queue_fallback_t fallback);
590 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
592 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
593 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
594 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
595 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
596 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
597 void mlx5e_free_tx_descs(struct mlx5e_sq *sq);
598 void mlx5e_free_rx_descs(struct mlx5e_rq *rq);
600 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
601 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
602 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
603 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
604 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
605 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix);
606 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
607 void mlx5e_post_rx_fragmented_mpwqe(struct mlx5e_rq *rq);
608 void mlx5e_complete_rx_linear_mpwqe(struct mlx5e_rq *rq,
609 struct mlx5_cqe64 *cqe,
611 struct mlx5e_mpw_info *wi,
612 struct sk_buff *skb);
613 void mlx5e_complete_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
614 struct mlx5_cqe64 *cqe,
616 struct mlx5e_mpw_info *wi,
617 struct sk_buff *skb);
618 void mlx5e_free_rx_linear_mpwqe(struct mlx5e_rq *rq,
619 struct mlx5e_mpw_info *wi);
620 void mlx5e_free_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
621 struct mlx5e_mpw_info *wi);
622 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
624 void mlx5e_update_stats(struct mlx5e_priv *priv);
626 int mlx5e_create_flow_steering(struct mlx5e_priv *priv);
627 void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv);
628 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
629 void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft);
630 void mlx5e_set_rx_mode_work(struct work_struct *work);
632 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
633 struct skb_shared_hwtstamps *hwts);
634 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
635 void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
636 int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr);
637 int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr);
638 void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv *priv, bool val);
640 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
642 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
644 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
645 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
647 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd);
649 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix);
650 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv);
652 int mlx5e_open_locked(struct net_device *netdev);
653 int mlx5e_close_locked(struct net_device *netdev);
654 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
655 u32 *indirection_rqt, int len,
657 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed);
659 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
660 struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz)
662 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
664 /* ensure wqe is visible to device before updating doorbell record */
667 *sq->wq.db = cpu_to_be32(sq->pc);
669 /* ensure doorbell record is visible to device before ringing the
674 __iowrite64_copy(sq->uar_map + ofst, ctrl, bf_sz);
676 mlx5_write64((__be32 *)ctrl, sq->uar_map + ofst, NULL);
677 /* flush the write-combining mapped buffer */
680 sq->bf_offset ^= sq->bf_buf_size;
683 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
685 struct mlx5_core_cq *mcq;
688 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
691 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
693 return min_t(int, mdev->priv.eq_table.num_comp_vectors,
694 MLX5E_MAX_NUM_CHANNELS);
697 static inline int mlx5e_get_mtt_octw(int npages)
699 return ALIGN(npages, 8) / 2;
702 extern const struct ethtool_ops mlx5e_ethtool_ops;
703 #ifdef CONFIG_MLX5_CORE_EN_DCB
704 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
705 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
708 #ifndef CONFIG_RFS_ACCEL
709 static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv)
714 static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {}
716 static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv)
721 static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv)
726 int mlx5e_arfs_create_tables(struct mlx5e_priv *priv);
727 void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv);
728 int mlx5e_arfs_enable(struct mlx5e_priv *priv);
729 int mlx5e_arfs_disable(struct mlx5e_priv *priv);
730 int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
731 u16 rxq_index, u32 flow_id);
734 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
736 #endif /* __MLX5_EN_H__ */