2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/crash_dump.h>
41 #include <linux/mlx5/driver.h>
42 #include <linux/mlx5/qp.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/port.h>
45 #include <linux/mlx5/vport.h>
46 #include <linux/mlx5/transobj.h>
47 #include <linux/mlx5/fs.h>
48 #include <linux/rhashtable.h>
49 #include <net/switchdev.h>
51 #include <linux/dim.h>
52 #include <linux/bits.h>
54 #include "mlx5_core.h"
58 extern const struct net_device_ops mlx5e_netdev_ops;
61 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4)
62 #define MLX5E_METADATA_ETHER_LEN 8
64 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
66 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
68 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))
69 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))
71 #define MLX5E_MAX_PRIORITY 8
72 #define MLX5E_MAX_DSCP 64
73 #define MLX5E_MAX_NUM_TC 8
75 #define MLX5_RX_HEADROOM NET_SKB_PAD
76 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \
77 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
79 #define MLX5E_RX_MAX_HEAD (256)
81 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
82 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
83 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
84 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
85 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \
86 MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD))
88 #define MLX5_MPWRQ_LOG_WQE_SZ 18
89 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
90 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
91 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
93 #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)
94 #define MLX5E_REQUIRED_WQE_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8))
95 #define MLX5E_LOG_ALIGNED_MPWQE_PPW (ilog2(MLX5E_REQUIRED_WQE_MTTS))
96 #define MLX5E_REQUIRED_MTTS(wqes) (wqes * MLX5E_REQUIRED_WQE_MTTS)
97 #define MLX5E_MAX_RQ_NUM_MTTS \
98 ((1 << 16) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */
99 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024))
100 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW \
101 (ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS))
102 #define MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW \
103 (MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW + \
104 (MLX5_MPWRQ_LOG_WQE_SZ - MLX5E_ORDER2_MAX_PACKET_MTU))
106 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM))
107 #define MLX5E_LOG_MAX_RX_WQE_BULK \
108 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ)))
110 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
111 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
112 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
114 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK)
115 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
116 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE min_t(u8, 0xd, \
117 MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW)
119 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2
121 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
122 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
123 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
125 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
126 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
127 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
128 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
129 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
130 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
131 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
132 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
134 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
135 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
136 #define MLX5E_MIN_NUM_CHANNELS 0x1
137 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
138 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
139 #define MLX5E_TX_CQ_POLL_BUDGET 128
140 #define MLX5E_TX_XSK_POLL_BUDGET 64
141 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */
143 #define MLX5E_UMR_WQE_INLINE_SZ \
144 (sizeof(struct mlx5e_umr_wqe) + \
145 ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(struct mlx5_mtt), \
146 MLX5_UMR_MTT_ALIGNMENT))
147 #define MLX5E_UMR_WQEBBS \
148 (DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_BB))
150 #define MLX5E_MSG_LEVEL NETIF_MSG_LINK
152 #define mlx5e_dbg(mlevel, priv, format, ...) \
154 if (NETIF_MSG_##mlevel & (priv)->msglevel) \
155 netdev_warn(priv->netdev, format, \
159 enum mlx5e_rq_group {
160 MLX5E_RQ_GROUP_REGULAR,
162 #define MLX5E_NUM_RQ_GROUPS(g) (1 + MLX5E_RQ_GROUP_##g)
165 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
168 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
169 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
172 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
177 /* Use this function to get max num channels (rxqs/txqs) only to create netdev */
178 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
180 return is_kdump_kernel() ?
181 MLX5E_MIN_NUM_CHANNELS :
182 min_t(int, mlx5_comp_vectors_count(mdev), MLX5E_MAX_NUM_CHANNELS);
185 struct mlx5e_tx_wqe {
186 struct mlx5_wqe_ctrl_seg ctrl;
189 struct mlx5_wqe_eth_seg eth;
190 struct mlx5_wqe_data_seg data[0];
192 u8 tls_progress_params_ctx[0];
196 struct mlx5e_rx_wqe_ll {
197 struct mlx5_wqe_srq_next_seg next;
198 struct mlx5_wqe_data_seg data[0];
201 struct mlx5e_rx_wqe_cyc {
202 struct mlx5_wqe_data_seg data[0];
205 struct mlx5e_umr_wqe {
206 struct mlx5_wqe_ctrl_seg ctrl;
207 struct mlx5_wqe_umr_ctrl_seg uctrl;
208 struct mlx5_mkey_seg mkc;
210 struct mlx5_mtt inline_mtts[0];
211 u8 tls_static_params_ctx[0];
215 extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];
217 enum mlx5e_priv_flag {
218 MLX5E_PFLAG_RX_CQE_BASED_MODER,
219 MLX5E_PFLAG_TX_CQE_BASED_MODER,
220 MLX5E_PFLAG_RX_CQE_COMPRESS,
221 MLX5E_PFLAG_RX_STRIDING_RQ,
222 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE,
223 MLX5E_PFLAG_XDP_TX_MPWQE,
224 MLX5E_NUM_PFLAGS, /* Keep last */
227 #define MLX5E_SET_PFLAG(params, pflag, enable) \
230 (params)->pflags |= BIT(pflag); \
232 (params)->pflags &= ~(BIT(pflag)); \
235 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag))))
237 #ifdef CONFIG_MLX5_CORE_EN_DCB
238 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
241 struct mlx5e_params {
244 u8 log_rq_mtu_frames;
247 bool rx_cqe_compress_def;
248 bool tunneled_offload_en;
249 struct dim_cq_moder rx_cq_moderation;
250 struct dim_cq_moder tx_cq_moderation;
252 u8 tx_min_inline_mode;
253 bool vlan_strip_disable;
259 struct bpf_prog *xdp_prog;
260 struct mlx5e_xsk *xsk;
265 #ifdef CONFIG_MLX5_CORE_EN_DCB
266 struct mlx5e_cee_config {
267 /* bw pct for priority group */
268 u8 pg_bw_pct[CEE_DCBX_MAX_PGS];
269 u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO];
270 bool pfc_setting[CEE_DCBX_MAX_PRIO];
277 MLX5_DCB_CHG_NO_RESET,
281 enum mlx5_dcbx_oper_mode mode;
282 struct mlx5e_cee_config cee_cfg; /* pending configuration */
285 /* The only setting that cannot be read from FW */
286 u8 tc_tsa[IEEE_8021QAZ_MAX_TCS];
289 /* Buffer configuration */
295 struct mlx5e_dcbx_dp {
296 u8 dscp2prio[MLX5E_MAX_DSCP];
302 MLX5E_RQ_STATE_ENABLED,
304 MLX5E_RQ_STATE_NO_CSUM_COMPLETE,
305 MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */
309 /* data path - accessed per cqe */
312 /* data path - accessed per napi poll */
314 struct napi_struct *napi;
315 struct mlx5_core_cq mcq;
316 struct mlx5e_channel *channel;
319 struct mlx5_core_dev *mdev;
320 struct mlx5_wq_ctrl wq_ctrl;
321 } ____cacheline_aligned_in_smp;
323 struct mlx5e_cq_decomp {
324 /* cqe decompression */
325 struct mlx5_cqe64 title;
326 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
330 } ____cacheline_aligned_in_smp;
332 struct mlx5e_tx_wqe_info {
337 #ifdef CONFIG_MLX5_EN_TLS
338 skb_frag_t *resync_dump_frag;
342 enum mlx5e_dma_map_type {
343 MLX5E_DMA_MAP_SINGLE,
347 struct mlx5e_sq_dma {
350 enum mlx5e_dma_map_type type;
354 MLX5E_SQ_STATE_ENABLED,
355 MLX5E_SQ_STATE_RECOVERING,
356 MLX5E_SQ_STATE_IPSEC,
361 struct mlx5e_sq_wqe_info {
364 /* Auxiliary data for different opcodes. */
375 /* dirtied @completion */
378 struct dim dim; /* Adaptive Moderation */
381 u16 pc ____cacheline_aligned_in_smp;
387 struct mlx5_wq_cyc wq;
389 struct mlx5e_sq_stats *stats;
391 struct mlx5e_sq_dma *dma_fifo;
392 struct mlx5e_tx_wqe_info *wqe_info;
394 void __iomem *uar_map;
395 struct netdev_queue *txq;
402 struct hwtstamp_config *tstamp;
403 struct mlx5_clock *clock;
406 struct mlx5_wq_ctrl wq_ctrl;
407 struct mlx5e_channel *channel;
411 struct work_struct recover_work;
412 } ____cacheline_aligned_in_smp;
414 struct mlx5e_dma_info {
425 /* XDP packets can be transmitted in different ways. On completion, we need to
426 * distinguish between them to clean up things in a proper way.
428 enum mlx5e_xdp_xmit_mode {
429 /* An xdp_frame was transmitted due to either XDP_REDIRECT from another
430 * device or XDP_TX from an XSK RQ. The frame has to be unmapped and
433 MLX5E_XDP_XMIT_MODE_FRAME,
435 /* The xdp_frame was created in place as a result of XDP_TX from a
436 * regular RQ. No DMA remapping happened, and the page belongs to us.
438 MLX5E_XDP_XMIT_MODE_PAGE,
440 /* No xdp_frame was created at all, the transmit happened from a UMEM
441 * page. The UMEM Completion Ring producer pointer has to be increased.
443 MLX5E_XDP_XMIT_MODE_XSK,
446 struct mlx5e_xdp_info {
447 enum mlx5e_xdp_xmit_mode mode;
450 struct xdp_frame *xdpf;
455 struct mlx5e_dma_info di;
460 struct mlx5e_xdp_xmit_data {
466 struct mlx5e_xdp_info_fifo {
467 struct mlx5e_xdp_info *xi;
473 struct mlx5e_xdp_wqe_info {
478 struct mlx5e_xdp_mpwqe {
479 /* Current MPWQE session */
480 struct mlx5e_tx_wqe *wqe;
489 typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *);
490 typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *,
491 struct mlx5e_xdp_xmit_data *,
492 struct mlx5e_xdp_info *,
498 /* dirtied @completion */
503 u32 xdpi_fifo_pc ____cacheline_aligned_in_smp;
505 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
506 struct mlx5e_xdp_mpwqe mpwqe;
511 struct xdp_umem *umem;
512 struct mlx5_wq_cyc wq;
513 struct mlx5e_xdpsq_stats *stats;
514 mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check;
515 mlx5e_fp_xmit_xdp_frame xmit_xdp_frame;
517 struct mlx5e_xdp_wqe_info *wqe_info;
518 struct mlx5e_xdp_info_fifo xdpi_fifo;
520 void __iomem *uar_map;
529 struct mlx5_wq_ctrl wq_ctrl;
530 struct mlx5e_channel *channel;
531 } ____cacheline_aligned_in_smp;
538 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
541 /* write@xmit, read@completion */
543 struct mlx5e_sq_wqe_info *ico_wqe;
547 struct mlx5_wq_cyc wq;
548 void __iomem *uar_map;
553 struct mlx5_wq_ctrl wq_ctrl;
554 struct mlx5e_channel *channel;
555 } ____cacheline_aligned_in_smp;
557 struct mlx5e_wqe_frag_info {
558 struct mlx5e_dma_info *di;
563 struct mlx5e_umr_dma_info {
564 struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
567 struct mlx5e_mpw_info {
568 struct mlx5e_umr_dma_info umr;
569 u16 consumed_strides;
570 DECLARE_BITMAP(xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
573 #define MLX5E_MAX_RX_FRAGS 4
575 /* a single cache unit is capable to serve one napi call (for non-striding rq)
576 * or a MPWQE (for striding rq).
578 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
579 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
580 #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
581 struct mlx5e_page_cache {
584 struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
588 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
589 typedef struct sk_buff *
590 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
591 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
592 typedef struct sk_buff *
593 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
594 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
595 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq);
596 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
599 MLX5E_RQ_FLAG_XDP_XMIT,
600 MLX5E_RQ_FLAG_XDP_REDIRECT,
603 struct mlx5e_rq_frag_info {
608 struct mlx5e_rq_frags_info {
609 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS];
619 struct mlx5_wq_cyc wq;
620 struct mlx5e_wqe_frag_info *frags;
621 struct mlx5e_dma_info *di;
622 struct mlx5e_rq_frags_info info;
623 mlx5e_fp_skb_from_cqe skb_from_cqe;
626 struct mlx5_wq_ll wq;
627 struct mlx5e_umr_wqe umr_wqe;
628 struct mlx5e_mpw_info *info;
629 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq;
641 u8 map_dir; /* dma map direction */
644 struct mlx5e_channel *channel;
646 struct net_device *netdev;
647 struct mlx5e_rq_stats *stats;
649 struct mlx5e_cq_decomp cqd;
650 struct mlx5e_page_cache page_cache;
651 struct hwtstamp_config *tstamp;
652 struct mlx5_clock *clock;
654 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
655 mlx5e_fp_post_rx_wqes post_wqes;
656 mlx5e_fp_dealloc_wqe dealloc_wqe;
662 struct dim dim; /* Dynamic Interrupt Moderation */
665 struct bpf_prog *xdp_prog;
666 struct mlx5e_xdpsq *xdpsq;
667 DECLARE_BITMAP(flags, 8);
668 struct page_pool *page_pool;
670 /* AF_XDP zero-copy */
671 struct zero_copy_allocator zca;
672 struct xdp_umem *umem;
675 struct mlx5_wq_ctrl wq_ctrl;
679 struct mlx5_core_dev *mdev;
680 struct mlx5_core_mkey umr_mkey;
682 /* XDP read-mostly */
683 struct xdp_rxq_info xdp_rxq;
684 } ____cacheline_aligned_in_smp;
686 enum mlx5e_channel_state {
687 MLX5E_CHANNEL_STATE_XSK,
688 MLX5E_CHANNEL_NUM_STATES
691 struct mlx5e_channel {
694 struct mlx5e_xdpsq rq_xdpsq;
695 struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC];
696 struct mlx5e_icosq icosq; /* internal control operations */
698 struct napi_struct napi;
700 struct net_device *netdev;
705 struct mlx5e_xdpsq xdpsq;
707 /* AF_XDP zero-copy */
708 struct mlx5e_rq xskrq;
709 struct mlx5e_xdpsq xsksq;
710 struct mlx5e_icosq xskicosq;
711 /* xskicosq can be accessed from any CPU - the spinlock protects it. */
712 spinlock_t xskicosq_lock;
714 /* data path - accessed per napi poll */
715 struct irq_desc *irq_desc;
716 struct mlx5e_ch_stats *stats;
719 struct mlx5e_priv *priv;
720 struct mlx5_core_dev *mdev;
721 struct hwtstamp_config *tstamp;
722 DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES);
725 cpumask_var_t xps_cpumask;
728 struct mlx5e_channels {
729 struct mlx5e_channel **c;
731 struct mlx5e_params params;
734 struct mlx5e_channel_stats {
735 struct mlx5e_ch_stats ch;
736 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];
737 struct mlx5e_rq_stats rq;
738 struct mlx5e_rq_stats xskrq;
739 struct mlx5e_xdpsq_stats rq_xdpsq;
740 struct mlx5e_xdpsq_stats xdpsq;
741 struct mlx5e_xdpsq_stats xsksq;
742 } ____cacheline_aligned_in_smp;
746 MLX5E_STATE_DESTROYING,
747 MLX5E_STATE_XDP_TX_ENABLED,
748 MLX5E_STATE_XDP_OPEN,
758 struct mlx5e_rqt rqt;
759 struct list_head list;
767 struct mlx5e_rss_params {
768 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
769 u32 rx_hash_fields[MLX5E_NUM_INDIR_TIRS];
770 u8 toeplitz_hash_key[40];
774 struct mlx5e_modify_sq_param {
782 /* UMEMs are stored separately from channels, because we don't want to
783 * lose them when channels are recreated. The kernel also stores UMEMs,
784 * but it doesn't distinguish between zero-copy and non-zero-copy UMEMs,
785 * so rely on our mechanism.
787 struct xdp_umem **umems;
793 /* priv data path fields - start */
794 struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC];
795 int channel_tc2txq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
796 #ifdef CONFIG_MLX5_CORE_EN_DCB
797 struct mlx5e_dcbx_dp dcbx_dp;
799 /* priv data path fields - end */
803 struct mutex state_lock; /* Protects Interface state */
804 struct mlx5e_rq drop_rq;
806 struct mlx5e_channels channels;
807 u32 tisn[MLX5E_MAX_NUM_TC];
808 struct mlx5e_rqt indir_rqt;
809 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
810 struct mlx5e_tir inner_indir_tir[MLX5E_NUM_INDIR_TIRS];
811 struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
812 struct mlx5e_tir xsk_tir[MLX5E_MAX_NUM_CHANNELS];
813 struct mlx5e_rss_params rss_params;
814 u32 tx_rates[MLX5E_MAX_NUM_SQS];
816 struct mlx5e_flow_steering fs;
818 struct workqueue_struct *wq;
819 struct work_struct update_carrier_work;
820 struct work_struct set_rx_mode_work;
821 struct work_struct tx_timeout_work;
822 struct work_struct update_stats_work;
823 struct work_struct monitor_counters_work;
824 struct mlx5_nb monitor_counters_nb;
826 struct mlx5_core_dev *mdev;
827 struct net_device *netdev;
828 struct mlx5e_stats stats;
829 struct mlx5e_channel_stats channel_stats[MLX5E_MAX_NUM_CHANNELS];
832 struct hwtstamp_config tstamp;
834 u16 drop_rq_q_counter;
835 struct notifier_block events_nb;
837 #ifdef CONFIG_MLX5_CORE_EN_DCB
838 struct mlx5e_dcbx dcbx;
841 const struct mlx5e_profile *profile;
843 #ifdef CONFIG_MLX5_EN_IPSEC
844 struct mlx5e_ipsec *ipsec;
846 #ifdef CONFIG_MLX5_EN_TLS
847 struct mlx5e_tls *tls;
849 struct devlink_health_reporter *tx_reporter;
850 struct mlx5e_xsk xsk;
853 struct mlx5e_profile {
854 int (*init)(struct mlx5_core_dev *mdev,
855 struct net_device *netdev,
856 const struct mlx5e_profile *profile, void *ppriv);
857 void (*cleanup)(struct mlx5e_priv *priv);
858 int (*init_rx)(struct mlx5e_priv *priv);
859 void (*cleanup_rx)(struct mlx5e_priv *priv);
860 int (*init_tx)(struct mlx5e_priv *priv);
861 void (*cleanup_tx)(struct mlx5e_priv *priv);
862 void (*enable)(struct mlx5e_priv *priv);
863 void (*disable)(struct mlx5e_priv *priv);
864 int (*update_rx)(struct mlx5e_priv *priv);
865 void (*update_stats)(struct mlx5e_priv *priv);
866 void (*update_carrier)(struct mlx5e_priv *priv);
868 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
869 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
875 void mlx5e_build_ptys2ethtool_map(void);
877 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
878 struct net_device *sb_dev);
879 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
880 netdev_tx_t mlx5e_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb,
881 struct mlx5e_tx_wqe *wqe, u16 pi, bool xmit_more);
883 void mlx5e_trigger_irq(struct mlx5e_icosq *sq);
884 void mlx5e_completion_event(struct mlx5_core_cq *mcq, struct mlx5_eqe *eqe);
885 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
886 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
887 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
888 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
889 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq);
891 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev);
892 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
893 struct mlx5e_params *params);
895 void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info);
896 void mlx5e_page_release_dynamic(struct mlx5e_rq *rq,
897 struct mlx5e_dma_info *dma_info,
899 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
900 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
901 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
902 void mlx5e_poll_ico_cq(struct mlx5e_cq *cq);
903 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq);
904 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix);
905 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
907 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
908 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
910 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
911 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
913 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
914 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
916 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
917 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
919 void mlx5e_update_stats(struct mlx5e_priv *priv);
920 void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats);
921 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s);
923 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
924 int mlx5e_self_test_num(struct mlx5e_priv *priv);
925 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
927 void mlx5e_set_rx_mode_work(struct work_struct *work);
929 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);
930 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);
931 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val);
933 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
935 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
937 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
939 struct mlx5e_redirect_rqt_param {
942 u32 rqn; /* Direct RQN (Non-RSS) */
945 struct mlx5e_channels *channels;
946 } rss; /* RSS data */
950 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
951 struct mlx5e_redirect_rqt_param rrp);
952 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
953 const struct mlx5e_tirc_config *ttconfig,
954 void *tirc, bool inner);
955 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen);
956 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt);
958 struct mlx5e_xsk_param;
960 struct mlx5e_rq_param;
961 int mlx5e_open_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
962 struct mlx5e_rq_param *param, struct mlx5e_xsk_param *xsk,
963 struct xdp_umem *umem, struct mlx5e_rq *rq);
964 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time);
965 void mlx5e_deactivate_rq(struct mlx5e_rq *rq);
966 void mlx5e_close_rq(struct mlx5e_rq *rq);
968 struct mlx5e_sq_param;
969 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
970 struct mlx5e_sq_param *param, struct mlx5e_icosq *sq);
971 void mlx5e_close_icosq(struct mlx5e_icosq *sq);
972 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
973 struct mlx5e_sq_param *param, struct xdp_umem *umem,
974 struct mlx5e_xdpsq *sq, bool is_redirect);
975 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq);
977 struct mlx5e_cq_param;
978 int mlx5e_open_cq(struct mlx5e_channel *c, struct dim_cq_moder moder,
979 struct mlx5e_cq_param *param, struct mlx5e_cq *cq);
980 void mlx5e_close_cq(struct mlx5e_cq *cq);
982 int mlx5e_open_locked(struct net_device *netdev);
983 int mlx5e_close_locked(struct net_device *netdev);
985 int mlx5e_open_channels(struct mlx5e_priv *priv,
986 struct mlx5e_channels *chs);
987 void mlx5e_close_channels(struct mlx5e_channels *chs);
989 /* Function pointer to be used to modify WH settings while
992 typedef int (*mlx5e_fp_hw_modify)(struct mlx5e_priv *priv);
993 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv);
994 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
995 struct mlx5e_channels *new_chs,
996 mlx5e_fp_hw_modify hw_modify);
997 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
998 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
1000 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
1002 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params,
1004 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
1006 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params);
1007 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
1008 struct mlx5e_params *params);
1010 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1011 struct mlx5e_modify_sq_param *p);
1012 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq);
1013 void mlx5e_tx_disable_queue(struct netdev_queue *txq);
1015 static inline bool mlx5e_tunnel_inner_ft_supported(struct mlx5_core_dev *mdev)
1017 return (MLX5_CAP_ETH(mdev, tunnel_stateless_gre) &&
1018 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, ft_field_support.inner_ip_version));
1021 static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev)
1023 return MLX5_CAP_ETH(mdev, swp) &&
1024 MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso);
1027 extern const struct ethtool_ops mlx5e_ethtool_ops;
1028 #ifdef CONFIG_MLX5_CORE_EN_DCB
1029 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
1030 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
1031 void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv);
1032 void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv);
1033 void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv);
1036 int mlx5e_create_tir(struct mlx5_core_dev *mdev,
1037 struct mlx5e_tir *tir, u32 *in, int inlen);
1038 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
1039 struct mlx5e_tir *tir);
1040 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
1041 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
1042 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb);
1044 /* common netdev helpers */
1045 void mlx5e_create_q_counters(struct mlx5e_priv *priv);
1046 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv);
1047 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
1048 struct mlx5e_rq *drop_rq);
1049 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq);
1051 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv);
1053 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc);
1054 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc);
1056 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
1057 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
1058 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
1059 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
1060 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt);
1062 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn);
1063 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
1065 int mlx5e_create_tises(struct mlx5e_priv *priv);
1066 int mlx5e_update_nic_rx(struct mlx5e_priv *priv);
1067 void mlx5e_update_carrier(struct mlx5e_priv *priv);
1068 int mlx5e_close(struct net_device *netdev);
1069 int mlx5e_open(struct net_device *netdev);
1070 void mlx5e_update_ndo_stats(struct mlx5e_priv *priv);
1072 void mlx5e_queue_update_stats(struct mlx5e_priv *priv);
1073 int mlx5e_bits_invert(unsigned long a, int size);
1075 typedef int (*change_hw_mtu_cb)(struct mlx5e_priv *priv);
1076 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv);
1077 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
1078 change_hw_mtu_cb set_mtu_cb);
1080 /* ethtool helpers */
1081 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
1082 struct ethtool_drvinfo *drvinfo);
1083 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
1084 uint32_t stringset, uint8_t *data);
1085 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
1086 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
1087 struct ethtool_stats *stats, u64 *data);
1088 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
1089 struct ethtool_ringparam *param);
1090 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
1091 struct ethtool_ringparam *param);
1092 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
1093 struct ethtool_channels *ch);
1094 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
1095 struct ethtool_channels *ch);
1096 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
1097 struct ethtool_coalesce *coal);
1098 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
1099 struct ethtool_coalesce *coal);
1100 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
1101 struct ethtool_link_ksettings *link_ksettings);
1102 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1103 const struct ethtool_link_ksettings *link_ksettings);
1104 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv);
1105 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv);
1106 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1107 struct ethtool_ts_info *info);
1108 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1109 struct ethtool_flash *flash);
1110 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1111 struct ethtool_pauseparam *pauseparam);
1112 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1113 struct ethtool_pauseparam *pauseparam);
1115 /* mlx5e generic netdev management API */
1116 int mlx5e_netdev_init(struct net_device *netdev,
1117 struct mlx5e_priv *priv,
1118 struct mlx5_core_dev *mdev,
1119 const struct mlx5e_profile *profile,
1121 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv);
1123 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile,
1124 int nch, void *ppriv);
1125 int mlx5e_attach_netdev(struct mlx5e_priv *priv);
1126 void mlx5e_detach_netdev(struct mlx5e_priv *priv);
1127 void mlx5e_destroy_netdev(struct mlx5e_priv *priv);
1128 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv);
1129 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
1130 struct mlx5e_xsk *xsk,
1131 struct mlx5e_rss_params *rss_params,
1132 struct mlx5e_params *params,
1133 u16 max_channels, u16 mtu);
1134 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
1135 struct mlx5e_params *params);
1136 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
1138 u8 mlx5e_params_calculate_tx_min_inline(struct mlx5_core_dev *mdev);
1139 void mlx5e_rx_dim_work(struct work_struct *work);
1140 void mlx5e_tx_dim_work(struct work_struct *work);
1142 void mlx5e_add_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti);
1143 void mlx5e_del_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti);
1144 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
1145 struct net_device *netdev,
1146 netdev_features_t features);
1147 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features);
1148 #ifdef CONFIG_MLX5_ESWITCH
1149 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac);
1150 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate);
1151 int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi);
1152 int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats);
1154 #endif /* __MLX5_EN_H__ */