2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/crash_dump.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/mlx5/fs.h>
47 #include <linux/rhashtable.h>
48 #include <net/udp_tunnel.h>
49 #include <net/switchdev.h>
51 #include <linux/dim.h>
52 #include <linux/bits.h>
54 #include "mlx5_core.h"
59 #include "lib/hv_vhca.h"
61 extern const struct net_device_ops mlx5e_netdev_ops;
64 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4)
65 #define MLX5E_METADATA_ETHER_LEN 8
67 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
69 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
71 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))
72 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))
74 #define MLX5E_MAX_NUM_TC 8
76 #define MLX5_RX_HEADROOM NET_SKB_PAD
77 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \
78 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
80 #define MLX5E_RX_MAX_HEAD (256)
82 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
83 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
84 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
85 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
86 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \
87 MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD))
89 #define MLX5_MPWRQ_LOG_WQE_SZ 18
90 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
91 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
92 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
94 #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)
95 /* Add another page to MLX5E_REQUIRED_WQE_MTTS as a buffer between
96 * WQEs, This page will absorb write overflow by the hardware, when
97 * receiving packets larger than MTU. These oversize packets are
98 * dropped by the driver at a later stage.
100 #define MLX5E_REQUIRED_WQE_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE + 1, 8))
101 #define MLX5E_LOG_ALIGNED_MPWQE_PPW (ilog2(MLX5E_REQUIRED_WQE_MTTS))
102 #define MLX5E_REQUIRED_MTTS(wqes) (wqes * MLX5E_REQUIRED_WQE_MTTS)
103 #define MLX5E_MAX_RQ_NUM_MTTS \
104 ((1 << 16) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */
105 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024))
106 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW \
107 (ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS))
108 #define MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW \
109 (MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW + \
110 (MLX5_MPWRQ_LOG_WQE_SZ - MLX5E_ORDER2_MAX_PACKET_MTU))
112 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM))
113 #define MLX5E_LOG_MAX_RX_WQE_BULK \
114 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ)))
116 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
117 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
118 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
120 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK)
121 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
122 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE min_t(u8, 0xd, \
123 MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW)
125 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2
127 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
128 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
129 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
131 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
132 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
133 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
134 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
135 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
136 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
137 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
138 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
140 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
141 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
142 #define MLX5E_MIN_NUM_CHANNELS 0x1
143 #define MLX5E_MAX_NUM_CHANNELS MLX5E_INDIR_RQT_SIZE
144 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
145 #define MLX5E_TX_CQ_POLL_BUDGET 128
146 #define MLX5E_TX_XSK_POLL_BUDGET 64
147 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */
149 #define MLX5E_UMR_WQE_INLINE_SZ \
150 (sizeof(struct mlx5e_umr_wqe) + \
151 ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(struct mlx5_mtt), \
152 MLX5_UMR_MTT_ALIGNMENT))
153 #define MLX5E_UMR_WQEBBS \
154 (DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_BB))
156 #define MLX5E_MSG_LEVEL NETIF_MSG_LINK
158 #define mlx5e_dbg(mlevel, priv, format, ...) \
160 if (NETIF_MSG_##mlevel & (priv)->msglevel) \
161 netdev_warn(priv->netdev, format, \
165 #define mlx5e_state_dereference(priv, p) \
166 rcu_dereference_protected((p), lockdep_is_held(&(priv)->state_lock))
168 enum mlx5e_rq_group {
169 MLX5E_RQ_GROUP_REGULAR,
171 #define MLX5E_NUM_RQ_GROUPS(g) (1 + MLX5E_RQ_GROUP_##g)
174 static inline u8 mlx5e_get_num_lag_ports(struct mlx5_core_dev *mdev)
176 if (mlx5_lag_is_lacp_owner(mdev))
179 return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS);
182 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
185 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
186 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
189 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
194 /* Use this function to get max num channels (rxqs/txqs) only to create netdev */
195 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
197 return is_kdump_kernel() ?
198 MLX5E_MIN_NUM_CHANNELS :
199 min_t(int, mlx5_comp_vectors_count(mdev), MLX5E_MAX_NUM_CHANNELS);
202 struct mlx5e_tx_wqe {
203 struct mlx5_wqe_ctrl_seg ctrl;
204 struct mlx5_wqe_eth_seg eth;
205 struct mlx5_wqe_data_seg data[0];
208 struct mlx5e_rx_wqe_ll {
209 struct mlx5_wqe_srq_next_seg next;
210 struct mlx5_wqe_data_seg data[];
213 struct mlx5e_rx_wqe_cyc {
214 struct mlx5_wqe_data_seg data[0];
217 struct mlx5e_umr_wqe {
218 struct mlx5_wqe_ctrl_seg ctrl;
219 struct mlx5_wqe_umr_ctrl_seg uctrl;
220 struct mlx5_mkey_seg mkc;
221 struct mlx5_mtt inline_mtts[0];
224 extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];
226 enum mlx5e_priv_flag {
227 MLX5E_PFLAG_RX_CQE_BASED_MODER,
228 MLX5E_PFLAG_TX_CQE_BASED_MODER,
229 MLX5E_PFLAG_RX_CQE_COMPRESS,
230 MLX5E_PFLAG_RX_STRIDING_RQ,
231 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE,
232 MLX5E_PFLAG_XDP_TX_MPWQE,
233 MLX5E_PFLAG_SKB_TX_MPWQE,
234 MLX5E_PFLAG_TX_PORT_TS,
235 MLX5E_NUM_PFLAGS, /* Keep last */
238 #define MLX5E_SET_PFLAG(params, pflag, enable) \
241 (params)->pflags |= BIT(pflag); \
243 (params)->pflags &= ~(BIT(pflag)); \
246 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag))))
248 struct mlx5e_params {
251 u8 log_rq_mtu_frames;
254 bool rx_cqe_compress_def;
255 bool tunneled_offload_en;
256 struct dim_cq_moder rx_cq_moderation;
257 struct dim_cq_moder tx_cq_moderation;
259 u8 tx_min_inline_mode;
260 bool vlan_strip_disable;
266 struct bpf_prog *xdp_prog;
267 struct mlx5e_xsk *xsk;
273 MLX5E_RQ_STATE_ENABLED,
274 MLX5E_RQ_STATE_RECOVERING,
276 MLX5E_RQ_STATE_NO_CSUM_COMPLETE,
277 MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */
278 MLX5E_RQ_STATE_FPGA_TLS, /* FPGA TLS enabled */
279 MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX /* set when mini_cqe_resp_stride_index cap is used */
283 /* data path - accessed per cqe */
286 /* data path - accessed per napi poll */
288 struct napi_struct *napi;
289 struct mlx5_core_cq mcq;
290 struct mlx5e_ch_stats *ch_stats;
293 struct net_device *netdev;
294 struct mlx5_core_dev *mdev;
295 struct mlx5e_priv *priv;
296 struct mlx5_wq_ctrl wq_ctrl;
297 } ____cacheline_aligned_in_smp;
299 struct mlx5e_cq_decomp {
300 /* cqe decompression */
301 struct mlx5_cqe64 title;
302 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
306 } ____cacheline_aligned_in_smp;
308 enum mlx5e_dma_map_type {
309 MLX5E_DMA_MAP_SINGLE,
313 struct mlx5e_sq_dma {
316 enum mlx5e_dma_map_type type;
320 MLX5E_SQ_STATE_ENABLED,
321 MLX5E_SQ_STATE_MPWQE,
322 MLX5E_SQ_STATE_RECOVERING,
323 MLX5E_SQ_STATE_IPSEC,
326 MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE,
327 MLX5E_SQ_STATE_PENDING_XSK_TX,
330 struct mlx5e_tx_mpwqe {
331 /* Current MPWQE session */
332 struct mlx5e_tx_wqe *wqe;
339 struct mlx5e_skb_fifo {
340 struct sk_buff **fifo;
351 /* dirtied @completion */
355 struct dim dim; /* Adaptive Moderation */
358 u16 pc ____cacheline_aligned_in_smp;
361 struct mlx5e_tx_mpwqe mpwqe;
366 struct mlx5_wq_cyc wq;
368 struct mlx5e_sq_stats *stats;
370 struct mlx5e_sq_dma *dma_fifo;
371 struct mlx5e_skb_fifo skb_fifo;
372 struct mlx5e_tx_wqe_info *wqe_info;
374 void __iomem *uar_map;
375 struct netdev_queue *txq;
383 struct hwtstamp_config *tstamp;
384 struct mlx5_clock *clock;
385 struct net_device *netdev;
386 struct mlx5_core_dev *mdev;
387 struct mlx5e_priv *priv;
390 struct mlx5_wq_ctrl wq_ctrl;
394 struct work_struct recover_work;
395 struct mlx5e_ptpsq *ptpsq;
396 } ____cacheline_aligned_in_smp;
398 struct mlx5e_dma_info {
402 struct xdp_buff *xsk;
406 /* XDP packets can be transmitted in different ways. On completion, we need to
407 * distinguish between them to clean up things in a proper way.
409 enum mlx5e_xdp_xmit_mode {
410 /* An xdp_frame was transmitted due to either XDP_REDIRECT from another
411 * device or XDP_TX from an XSK RQ. The frame has to be unmapped and
414 MLX5E_XDP_XMIT_MODE_FRAME,
416 /* The xdp_frame was created in place as a result of XDP_TX from a
417 * regular RQ. No DMA remapping happened, and the page belongs to us.
419 MLX5E_XDP_XMIT_MODE_PAGE,
421 /* No xdp_frame was created at all, the transmit happened from a UMEM
422 * page. The UMEM Completion Ring producer pointer has to be increased.
424 MLX5E_XDP_XMIT_MODE_XSK,
427 struct mlx5e_xdp_info {
428 enum mlx5e_xdp_xmit_mode mode;
431 struct xdp_frame *xdpf;
436 struct mlx5e_dma_info di;
441 struct mlx5e_xmit_data {
447 struct mlx5e_xdp_info_fifo {
448 struct mlx5e_xdp_info *xi;
455 typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *);
456 typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *,
457 struct mlx5e_xmit_data *,
458 struct mlx5e_xdp_info *,
464 /* dirtied @completion */
469 u32 xdpi_fifo_pc ____cacheline_aligned_in_smp;
471 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
472 struct mlx5e_tx_mpwqe mpwqe;
477 struct xsk_buff_pool *xsk_pool;
478 struct mlx5_wq_cyc wq;
479 struct mlx5e_xdpsq_stats *stats;
480 mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check;
481 mlx5e_fp_xmit_xdp_frame xmit_xdp_frame;
483 struct mlx5e_xdp_wqe_info *wqe_info;
484 struct mlx5e_xdp_info_fifo xdpi_fifo;
486 void __iomem *uar_map;
495 struct mlx5_wq_ctrl wq_ctrl;
496 struct mlx5e_channel *channel;
497 } ____cacheline_aligned_in_smp;
504 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
507 /* write@xmit, read@completion */
509 struct mlx5e_icosq_wqe_info *wqe_info;
513 struct mlx5_wq_cyc wq;
514 void __iomem *uar_map;
519 struct mlx5_wq_ctrl wq_ctrl;
520 struct mlx5e_channel *channel;
522 struct work_struct recover_work;
523 } ____cacheline_aligned_in_smp;
525 struct mlx5e_wqe_frag_info {
526 struct mlx5e_dma_info *di;
531 struct mlx5e_umr_dma_info {
532 struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
535 struct mlx5e_mpw_info {
536 struct mlx5e_umr_dma_info umr;
537 u16 consumed_strides;
538 DECLARE_BITMAP(xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
541 #define MLX5E_MAX_RX_FRAGS 4
543 /* a single cache unit is capable to serve one napi call (for non-striding rq)
544 * or a MPWQE (for striding rq).
546 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
547 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
548 #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
549 struct mlx5e_page_cache {
552 struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
556 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
557 typedef struct sk_buff *
558 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
559 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
560 typedef struct sk_buff *
561 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
562 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
563 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq);
564 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
566 int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk);
567 void mlx5e_rq_set_trap_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params);
570 MLX5E_RQ_FLAG_XDP_XMIT,
571 MLX5E_RQ_FLAG_XDP_REDIRECT,
574 struct mlx5e_rq_frag_info {
579 struct mlx5e_rq_frags_info {
580 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS];
590 struct mlx5_wq_cyc wq;
591 struct mlx5e_wqe_frag_info *frags;
592 struct mlx5e_dma_info *di;
593 struct mlx5e_rq_frags_info info;
594 mlx5e_fp_skb_from_cqe skb_from_cqe;
597 struct mlx5_wq_ll wq;
598 struct mlx5e_umr_wqe umr_wqe;
599 struct mlx5e_mpw_info *info;
600 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq;
612 u8 map_dir; /* dma map direction */
616 struct net_device *netdev;
617 struct mlx5e_rq_stats *stats;
619 struct mlx5e_cq_decomp cqd;
620 struct mlx5e_page_cache page_cache;
621 struct hwtstamp_config *tstamp;
622 struct mlx5_clock *clock;
623 struct mlx5e_icosq *icosq;
624 struct mlx5e_priv *priv;
626 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
627 mlx5e_fp_post_rx_wqes post_wqes;
628 mlx5e_fp_dealloc_wqe dealloc_wqe;
634 struct dim dim; /* Dynamic Interrupt Moderation */
637 struct bpf_prog __rcu *xdp_prog;
638 struct mlx5e_xdpsq *xdpsq;
639 DECLARE_BITMAP(flags, 8);
640 struct page_pool *page_pool;
642 /* AF_XDP zero-copy */
643 struct xsk_buff_pool *xsk_pool;
645 struct work_struct recover_work;
648 struct mlx5_wq_ctrl wq_ctrl;
652 struct mlx5_core_dev *mdev;
653 struct mlx5_core_mkey umr_mkey;
654 struct mlx5e_dma_info wqe_overflow;
656 /* XDP read-mostly */
657 struct xdp_rxq_info xdp_rxq;
658 } ____cacheline_aligned_in_smp;
660 enum mlx5e_channel_state {
661 MLX5E_CHANNEL_STATE_XSK,
662 MLX5E_CHANNEL_NUM_STATES
665 struct mlx5e_channel {
668 struct mlx5e_xdpsq rq_xdpsq;
669 struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC];
670 struct mlx5e_icosq icosq; /* internal control operations */
671 struct mlx5e_txqsq __rcu * __rcu *qos_sqs;
673 struct napi_struct napi;
675 struct net_device *netdev;
682 struct mlx5e_xdpsq xdpsq;
684 /* AF_XDP zero-copy */
685 struct mlx5e_rq xskrq;
686 struct mlx5e_xdpsq xsksq;
689 struct mlx5e_icosq async_icosq;
690 /* async_icosq can be accessed from any CPU - the spinlock protects it. */
691 spinlock_t async_icosq_lock;
693 /* data path - accessed per napi poll */
694 const struct cpumask *aff_mask;
695 struct mlx5e_ch_stats *stats;
698 struct mlx5e_priv *priv;
699 struct mlx5_core_dev *mdev;
700 struct hwtstamp_config *tstamp;
701 DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES);
706 struct mlx5e_port_ptp;
708 struct mlx5e_channels {
709 struct mlx5e_channel **c;
710 struct mlx5e_port_ptp *port_ptp;
712 struct mlx5e_params params;
715 struct mlx5e_channel_stats {
716 struct mlx5e_ch_stats ch;
717 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];
718 struct mlx5e_rq_stats rq;
719 struct mlx5e_rq_stats xskrq;
720 struct mlx5e_xdpsq_stats rq_xdpsq;
721 struct mlx5e_xdpsq_stats xdpsq;
722 struct mlx5e_xdpsq_stats xsksq;
723 } ____cacheline_aligned_in_smp;
725 struct mlx5e_port_ptp_stats {
726 struct mlx5e_ch_stats ch;
727 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];
728 struct mlx5e_ptp_cq_stats cq[MLX5E_MAX_NUM_TC];
729 } ____cacheline_aligned_in_smp;
733 MLX5E_STATE_DESTROYING,
734 MLX5E_STATE_XDP_TX_ENABLED,
735 MLX5E_STATE_XDP_ACTIVE,
745 struct mlx5e_rqt rqt;
746 struct list_head list;
754 struct mlx5e_rss_params {
755 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
756 u32 rx_hash_fields[MLX5E_NUM_INDIR_TIRS];
757 u8 toeplitz_hash_key[40];
761 struct mlx5e_modify_sq_param {
767 u16 qos_queue_group_id;
770 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
771 struct mlx5e_hv_vhca_stats_agent {
772 struct mlx5_hv_vhca_agent *agent;
773 struct delayed_work work;
780 /* XSK buffer pools are stored separately from channels,
781 * because we don't want to lose them when channels are
782 * recreated. The kernel also stores buffer pool, but it doesn't
783 * distinguish between zero-copy and non-zero-copy UMEMs, so
784 * rely on our mechanism.
786 struct xsk_buff_pool **pools;
791 /* Temporary storage for variables that are allocated when struct mlx5e_priv is
792 * initialized, and used where we can't allocate them because that functions
793 * must not fail. Use with care and make sure the same variable is not used
794 * simultaneously by multiple users.
796 struct mlx5e_scratchpad {
797 cpumask_var_t cpumask;
801 DECLARE_HASHTABLE(qos_tc2node, order_base_2(MLX5E_QOS_MAX_LEAF_NODES));
802 DECLARE_BITMAP(qos_used_qids, MLX5E_QOS_MAX_LEAF_NODES);
803 struct mlx5e_sq_stats **qos_sq_stats;
812 /* priv data path fields - start */
813 /* +1 for port ptp ts */
814 struct mlx5e_txqsq *txq2sq[(MLX5E_MAX_NUM_CHANNELS + 1) * MLX5E_MAX_NUM_TC +
815 MLX5E_QOS_MAX_LEAF_NODES];
816 int channel_tc2realtxq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
817 int port_ptp_tc2realtxq[MLX5E_MAX_NUM_TC];
818 #ifdef CONFIG_MLX5_CORE_EN_DCB
819 struct mlx5e_dcbx_dp dcbx_dp;
821 /* priv data path fields - end */
825 struct mutex state_lock; /* Protects Interface state */
826 struct mlx5e_rq drop_rq;
828 struct mlx5e_channels channels;
829 u32 tisn[MLX5_MAX_PORTS][MLX5E_MAX_NUM_TC];
830 struct mlx5e_rqt indir_rqt;
831 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
832 struct mlx5e_tir inner_indir_tir[MLX5E_NUM_INDIR_TIRS];
833 struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
834 struct mlx5e_tir xsk_tir[MLX5E_MAX_NUM_CHANNELS];
835 struct mlx5e_rss_params rss_params;
836 u32 tx_rates[MLX5E_MAX_NUM_SQS];
838 struct mlx5e_flow_steering fs;
840 struct workqueue_struct *wq;
841 struct work_struct update_carrier_work;
842 struct work_struct set_rx_mode_work;
843 struct work_struct tx_timeout_work;
844 struct work_struct update_stats_work;
845 struct work_struct monitor_counters_work;
846 struct mlx5_nb monitor_counters_nb;
848 struct mlx5_core_dev *mdev;
849 struct net_device *netdev;
850 struct mlx5e_trap *en_trap;
851 struct mlx5e_stats stats;
852 struct mlx5e_channel_stats channel_stats[MLX5E_MAX_NUM_CHANNELS];
853 struct mlx5e_channel_stats trap_stats;
854 struct mlx5e_port_ptp_stats port_ptp_stats;
857 bool port_ptp_opened;
858 struct hwtstamp_config tstamp;
860 u16 drop_rq_q_counter;
861 struct notifier_block events_nb;
862 struct notifier_block blocking_events_nb;
865 struct udp_tunnel_nic_info nic_info;
866 #ifdef CONFIG_MLX5_CORE_EN_DCB
867 struct mlx5e_dcbx dcbx;
870 const struct mlx5e_profile *profile;
872 #ifdef CONFIG_MLX5_EN_IPSEC
873 struct mlx5e_ipsec *ipsec;
875 #ifdef CONFIG_MLX5_EN_TLS
876 struct mlx5e_tls *tls;
878 struct devlink_health_reporter *tx_reporter;
879 struct devlink_health_reporter *rx_reporter;
880 struct devlink_port dl_port;
881 struct mlx5e_xsk xsk;
882 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
883 struct mlx5e_hv_vhca_stats_agent stats_agent;
885 struct mlx5e_scratchpad scratchpad;
886 struct mlx5e_htb htb;
889 struct mlx5e_rx_handlers {
890 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
891 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
894 extern const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic;
896 struct mlx5e_profile {
897 int (*init)(struct mlx5_core_dev *mdev,
898 struct net_device *netdev,
899 const struct mlx5e_profile *profile, void *ppriv);
900 void (*cleanup)(struct mlx5e_priv *priv);
901 int (*init_rx)(struct mlx5e_priv *priv);
902 void (*cleanup_rx)(struct mlx5e_priv *priv);
903 int (*init_tx)(struct mlx5e_priv *priv);
904 void (*cleanup_tx)(struct mlx5e_priv *priv);
905 void (*enable)(struct mlx5e_priv *priv);
906 void (*disable)(struct mlx5e_priv *priv);
907 int (*update_rx)(struct mlx5e_priv *priv);
908 void (*update_stats)(struct mlx5e_priv *priv);
909 void (*update_carrier)(struct mlx5e_priv *priv);
910 unsigned int (*stats_grps_num)(struct mlx5e_priv *priv);
911 mlx5e_stats_grp_t *stats_grps;
912 const struct mlx5e_rx_handlers *rx_handlers;
917 void mlx5e_build_ptys2ethtool_map(void);
919 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev);
920 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
921 struct mlx5e_params *params);
923 void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats);
924 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s);
926 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
927 int mlx5e_self_test_num(struct mlx5e_priv *priv);
928 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
930 void mlx5e_set_rx_mode_work(struct work_struct *work);
932 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);
933 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);
934 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val);
936 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
938 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
940 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
942 struct mlx5e_redirect_rqt_param {
945 u32 rqn; /* Direct RQN (Non-RSS) */
948 struct mlx5e_channels *channels;
949 } rss; /* RSS data */
953 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
954 struct mlx5e_redirect_rqt_param rrp);
955 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
956 const struct mlx5e_tirc_config *ttconfig,
957 void *tirc, bool inner);
958 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in);
959 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt);
961 struct mlx5e_xsk_param;
963 struct mlx5e_rq_param;
964 int mlx5e_open_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
965 struct mlx5e_rq_param *param, struct mlx5e_xsk_param *xsk,
966 struct xsk_buff_pool *xsk_pool, struct mlx5e_rq *rq);
967 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time);
968 void mlx5e_deactivate_rq(struct mlx5e_rq *rq);
969 void mlx5e_close_rq(struct mlx5e_rq *rq);
970 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param);
971 void mlx5e_destroy_rq(struct mlx5e_rq *rq);
973 struct mlx5e_sq_param;
974 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
975 struct mlx5e_sq_param *param, struct mlx5e_icosq *sq);
976 void mlx5e_close_icosq(struct mlx5e_icosq *sq);
977 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
978 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
979 struct mlx5e_xdpsq *sq, bool is_redirect);
980 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq);
982 struct mlx5e_create_cq_param {
983 struct napi_struct *napi;
984 struct mlx5e_ch_stats *ch_stats;
989 struct mlx5e_cq_param;
990 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder,
991 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
992 struct mlx5e_cq *cq);
993 void mlx5e_close_cq(struct mlx5e_cq *cq);
995 int mlx5e_open_locked(struct net_device *netdev);
996 int mlx5e_close_locked(struct net_device *netdev);
998 int mlx5e_open_channels(struct mlx5e_priv *priv,
999 struct mlx5e_channels *chs);
1000 void mlx5e_close_channels(struct mlx5e_channels *chs);
1002 /* Function pointer to be used to modify HW or kernel settings while
1003 * switching channels
1005 typedef int (*mlx5e_fp_preactivate)(struct mlx5e_priv *priv, void *context);
1006 #define MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(fn) \
1007 int fn##_ctx(struct mlx5e_priv *priv, void *context) \
1011 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv);
1012 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
1013 struct mlx5e_channels *new_chs,
1014 mlx5e_fp_preactivate preactivate,
1016 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv);
1017 int mlx5e_num_channels_changed(struct mlx5e_priv *priv);
1018 int mlx5e_num_channels_changed_ctx(struct mlx5e_priv *priv, void *context);
1019 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
1020 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
1022 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
1025 void mlx5e_reset_tx_moderation(struct mlx5e_params *params, u8 cq_period_mode);
1026 void mlx5e_reset_rx_moderation(struct mlx5e_params *params, u8 cq_period_mode);
1027 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode);
1028 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode);
1030 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params);
1031 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
1032 struct mlx5e_params *params);
1033 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state);
1034 void mlx5e_activate_rq(struct mlx5e_rq *rq);
1035 void mlx5e_deactivate_rq(struct mlx5e_rq *rq);
1036 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq);
1037 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq);
1039 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1040 struct mlx5e_modify_sq_param *p);
1041 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1042 struct mlx5e_params *params, struct mlx5e_sq_param *param,
1043 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id, u16 qos_qid);
1044 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq);
1045 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq);
1046 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq);
1047 void mlx5e_tx_disable_queue(struct netdev_queue *txq);
1048 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa);
1049 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq);
1050 struct mlx5e_create_sq_param;
1051 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1052 struct mlx5e_sq_param *param,
1053 struct mlx5e_create_sq_param *csp,
1054 u16 qos_queue_group_id,
1056 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1057 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq);
1059 static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev)
1061 return MLX5_CAP_ETH(mdev, swp) &&
1062 MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso);
1065 extern const struct ethtool_ops mlx5e_ethtool_ops;
1067 int mlx5e_create_tir(struct mlx5_core_dev *mdev, struct mlx5e_tir *tir,
1069 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
1070 struct mlx5e_tir *tir);
1071 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
1072 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
1073 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb,
1075 void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc);
1077 /* common netdev helpers */
1078 void mlx5e_create_q_counters(struct mlx5e_priv *priv);
1079 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv);
1080 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
1081 struct mlx5e_rq *drop_rq);
1082 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq);
1083 int mlx5e_init_di_list(struct mlx5e_rq *rq, int wq_sz, int node);
1084 void mlx5e_free_di_list(struct mlx5e_rq *rq);
1086 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv);
1088 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc);
1089 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv);
1091 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
1092 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
1093 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
1094 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
1095 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt);
1097 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn);
1098 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
1100 int mlx5e_create_tises(struct mlx5e_priv *priv);
1101 void mlx5e_destroy_tises(struct mlx5e_priv *priv);
1102 int mlx5e_update_nic_rx(struct mlx5e_priv *priv);
1103 void mlx5e_update_carrier(struct mlx5e_priv *priv);
1104 int mlx5e_close(struct net_device *netdev);
1105 int mlx5e_open(struct net_device *netdev);
1107 void mlx5e_queue_update_stats(struct mlx5e_priv *priv);
1108 int mlx5e_bits_invert(unsigned long a, int size);
1110 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv);
1111 int mlx5e_set_dev_port_mtu_ctx(struct mlx5e_priv *priv, void *context);
1112 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
1113 mlx5e_fp_preactivate preactivate);
1114 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv);
1116 /* ethtool helpers */
1117 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
1118 struct ethtool_drvinfo *drvinfo);
1119 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
1120 uint32_t stringset, uint8_t *data);
1121 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
1122 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
1123 struct ethtool_stats *stats, u64 *data);
1124 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
1125 struct ethtool_ringparam *param);
1126 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
1127 struct ethtool_ringparam *param);
1128 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
1129 struct ethtool_channels *ch);
1130 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
1131 struct ethtool_channels *ch);
1132 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
1133 struct ethtool_coalesce *coal);
1134 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
1135 struct ethtool_coalesce *coal);
1136 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
1137 struct ethtool_link_ksettings *link_ksettings);
1138 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1139 const struct ethtool_link_ksettings *link_ksettings);
1140 int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, u8 *hfunc);
1141 int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key,
1143 int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
1145 int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd);
1146 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv);
1147 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv);
1148 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1149 struct ethtool_ts_info *info);
1150 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1151 struct ethtool_flash *flash);
1152 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1153 struct ethtool_pauseparam *pauseparam);
1154 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1155 struct ethtool_pauseparam *pauseparam);
1157 /* mlx5e generic netdev management API */
1158 int mlx5e_netdev_init(struct net_device *netdev,
1159 struct mlx5e_priv *priv,
1160 struct mlx5_core_dev *mdev,
1161 const struct mlx5e_profile *profile,
1163 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv);
1165 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile,
1166 int nch, void *ppriv);
1167 int mlx5e_attach_netdev(struct mlx5e_priv *priv);
1168 void mlx5e_detach_netdev(struct mlx5e_priv *priv);
1169 void mlx5e_destroy_netdev(struct mlx5e_priv *priv);
1170 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv);
1171 void mlx5e_build_nic_params(struct mlx5e_priv *priv,
1172 struct mlx5e_xsk *xsk,
1173 struct mlx5e_rss_params *rss_params,
1174 struct mlx5e_params *params,
1176 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
1177 struct mlx5e_params *params);
1178 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
1180 void mlx5e_rx_dim_work(struct work_struct *work);
1181 void mlx5e_tx_dim_work(struct work_struct *work);
1183 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
1184 struct net_device *netdev,
1185 netdev_features_t features);
1186 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features);
1187 #ifdef CONFIG_MLX5_ESWITCH
1188 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac);
1189 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate);
1190 int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi);
1191 int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats);
1193 #endif /* __MLX5_EN_H__ */