2 * Copyright (c) 2018, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/bpf_trace.h>
34 #include <net/xdp_sock_drv.h>
36 #include "en/params.h"
38 int mlx5e_xdp_max_mtu(struct mlx5e_params *params, struct mlx5e_xsk_param *xsk)
40 int hr = mlx5e_get_linear_rq_headroom(params, xsk);
42 /* Let S := SKB_DATA_ALIGN(sizeof(struct skb_shared_info)).
43 * The condition checked in mlx5e_rx_is_linear_skb is:
44 * SKB_DATA_ALIGN(sw_mtu + hard_mtu + hr) + S <= PAGE_SIZE (1)
45 * (Note that hw_mtu == sw_mtu + hard_mtu.)
46 * What is returned from this function is:
47 * max_mtu = PAGE_SIZE - S - hr - hard_mtu (2)
48 * After assigning sw_mtu := max_mtu, the left side of (1) turns to
49 * SKB_DATA_ALIGN(PAGE_SIZE - S) + S, which is equal to PAGE_SIZE,
50 * because both PAGE_SIZE and S are already aligned. Any number greater
51 * than max_mtu would make the left side of (1) greater than PAGE_SIZE,
52 * so max_mtu is the maximum MTU allowed.
55 return MLX5E_HW2SW_MTU(params, SKB_MAX_HEAD(hr));
59 mlx5e_xmit_xdp_buff(struct mlx5e_xdpsq *sq, struct mlx5e_rq *rq,
60 struct page *page, struct xdp_buff *xdp)
62 struct mlx5e_xmit_data xdptxd;
63 struct mlx5e_xdp_info xdpi;
64 struct xdp_frame *xdpf;
67 xdpf = xdp_convert_buff_to_frame(xdp);
71 if (unlikely(xdp_frame_has_frags(xdpf))) {
72 xdp_return_frame(xdpf);
76 xdptxd.data = xdpf->data;
77 xdptxd.len = xdpf->len;
79 if (xdp->rxq->mem.type == MEM_TYPE_XSK_BUFF_POOL) {
80 /* The xdp_buff was in the UMEM and was copied into a newly
81 * allocated page. The UMEM page was returned via the ZCA, and
82 * this new page has to be mapped at this point and has to be
83 * unmapped and returned via xdp_return_frame on completion.
86 /* Prevent double recycling of the UMEM page. Even in case this
87 * function returns false, the xdp_buff shouldn't be recycled,
88 * as it was already done in xdp_convert_zc_to_xdp_frame.
90 __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags); /* non-atomic */
92 xdpi.mode = MLX5E_XDP_XMIT_MODE_FRAME;
94 dma_addr = dma_map_single(sq->pdev, xdptxd.data, xdptxd.len,
96 if (dma_mapping_error(sq->pdev, dma_addr)) {
97 xdp_return_frame(xdpf);
101 xdptxd.dma_addr = dma_addr;
102 xdpi.frame.xdpf = xdpf;
103 xdpi.frame.dma_addr = dma_addr;
105 /* Driver assumes that xdp_convert_buff_to_frame returns
106 * an xdp_frame that points to the same memory region as
107 * the original xdp_buff. It allows to map the memory only
108 * once and to use the DMA_BIDIRECTIONAL mode.
111 xdpi.mode = MLX5E_XDP_XMIT_MODE_PAGE;
113 dma_addr = page_pool_get_dma_addr(page) + (xdpf->data - (void *)xdpf);
114 dma_sync_single_for_device(sq->pdev, dma_addr, xdptxd.len,
117 xdptxd.dma_addr = dma_addr;
119 xdpi.page.page = page;
122 if (unlikely(!INDIRECT_CALL_2(sq->xmit_xdp_frame, mlx5e_xmit_xdp_frame_mpwqe,
123 mlx5e_xmit_xdp_frame, sq, &xdptxd, NULL, 0)))
126 mlx5e_xdpi_fifo_push(&sq->db.xdpi_fifo, &xdpi);
130 /* returns true if packet was consumed by xdp */
131 bool mlx5e_xdp_handle(struct mlx5e_rq *rq, struct page *page,
132 struct bpf_prog *prog, struct xdp_buff *xdp)
137 act = bpf_prog_run_xdp(prog, xdp);
142 if (unlikely(!mlx5e_xmit_xdp_buff(rq->xdpsq, rq, page, xdp)))
144 __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags); /* non-atomic */
147 /* When XDP enabled then page-refcnt==1 here */
148 err = xdp_do_redirect(rq->netdev, xdp, prog);
151 __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags);
152 __set_bit(MLX5E_RQ_FLAG_XDP_REDIRECT, rq->flags);
153 if (xdp->rxq->mem.type != MEM_TYPE_XSK_BUFF_POOL)
154 mlx5e_page_dma_unmap(rq, page);
155 rq->stats->xdp_redirect++;
158 bpf_warn_invalid_xdp_action(rq->netdev, prog, act);
162 trace_xdp_exception(rq->netdev, prog, act);
165 rq->stats->xdp_drop++;
170 static u16 mlx5e_xdpsq_get_next_pi(struct mlx5e_xdpsq *sq, u16 size)
172 struct mlx5_wq_cyc *wq = &sq->wq;
173 u16 pi, contig_wqebbs;
175 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
176 contig_wqebbs = mlx5_wq_cyc_get_contig_wqebbs(wq, pi);
177 if (unlikely(contig_wqebbs < size)) {
178 struct mlx5e_xdp_wqe_info *wi, *edge_wi;
180 wi = &sq->db.wqe_info[pi];
181 edge_wi = wi + contig_wqebbs;
183 /* Fill SQ frag edge with NOPs to avoid WQE wrapping two pages. */
184 for (; wi < edge_wi; wi++) {
185 *wi = (struct mlx5e_xdp_wqe_info) {
189 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
191 sq->stats->nops += contig_wqebbs;
193 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
199 static void mlx5e_xdp_mpwqe_session_start(struct mlx5e_xdpsq *sq)
201 struct mlx5e_tx_mpwqe *session = &sq->mpwqe;
202 struct mlx5e_xdpsq_stats *stats = sq->stats;
203 struct mlx5e_tx_wqe *wqe;
206 pi = mlx5e_xdpsq_get_next_pi(sq, sq->max_sq_mpw_wqebbs);
207 wqe = MLX5E_TX_FETCH_WQE(sq, pi);
208 net_prefetchw(wqe->data);
210 *session = (struct mlx5e_tx_mpwqe) {
213 .ds_count = MLX5E_TX_WQE_EMPTY_DS_COUNT,
215 .inline_on = mlx5e_xdp_get_inline_state(sq, session->inline_on),
221 void mlx5e_xdp_mpwqe_complete(struct mlx5e_xdpsq *sq)
223 struct mlx5_wq_cyc *wq = &sq->wq;
224 struct mlx5e_tx_mpwqe *session = &sq->mpwqe;
225 struct mlx5_wqe_ctrl_seg *cseg = &session->wqe->ctrl;
226 u16 ds_count = session->ds_count;
227 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
228 struct mlx5e_xdp_wqe_info *wi = &sq->db.wqe_info[pi];
230 cseg->opmod_idx_opcode =
231 cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_ENHANCED_MPSW);
232 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_count);
234 wi->num_wqebbs = DIV_ROUND_UP(ds_count, MLX5_SEND_WQEBB_NUM_DS);
235 wi->num_pkts = session->pkt_count;
237 sq->pc += wi->num_wqebbs;
239 sq->doorbell_cseg = cseg;
241 session->wqe = NULL; /* Close session */
245 MLX5E_XDP_CHECK_OK = 1,
246 MLX5E_XDP_CHECK_START_MPWQE = 2,
249 INDIRECT_CALLABLE_SCOPE int mlx5e_xmit_xdp_frame_check_mpwqe(struct mlx5e_xdpsq *sq)
251 if (unlikely(!sq->mpwqe.wqe)) {
252 if (unlikely(!mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc,
254 /* SQ is full, ring doorbell */
255 mlx5e_xmit_xdp_doorbell(sq);
260 return MLX5E_XDP_CHECK_START_MPWQE;
263 return MLX5E_XDP_CHECK_OK;
266 INDIRECT_CALLABLE_SCOPE bool
267 mlx5e_xmit_xdp_frame(struct mlx5e_xdpsq *sq, struct mlx5e_xmit_data *xdptxd,
268 struct skb_shared_info *sinfo, int check_result);
270 INDIRECT_CALLABLE_SCOPE bool
271 mlx5e_xmit_xdp_frame_mpwqe(struct mlx5e_xdpsq *sq, struct mlx5e_xmit_data *xdptxd,
272 struct skb_shared_info *sinfo, int check_result)
274 struct mlx5e_tx_mpwqe *session = &sq->mpwqe;
275 struct mlx5e_xdpsq_stats *stats = sq->stats;
277 if (unlikely(sinfo)) {
278 /* MPWQE is enabled, but a multi-buffer packet is queued for
279 * transmission. MPWQE can't send fragmented packets, so close
280 * the current session and fall back to a regular WQE.
282 if (unlikely(sq->mpwqe.wqe))
283 mlx5e_xdp_mpwqe_complete(sq);
284 return mlx5e_xmit_xdp_frame(sq, xdptxd, sinfo, 0);
287 if (unlikely(xdptxd->len > sq->hw_mtu)) {
293 check_result = mlx5e_xmit_xdp_frame_check_mpwqe(sq);
294 if (unlikely(check_result < 0))
297 if (check_result == MLX5E_XDP_CHECK_START_MPWQE) {
298 /* Start the session when nothing can fail, so it's guaranteed
299 * that if there is an active session, it has at least one dseg,
300 * and it's safe to complete it at any time.
302 mlx5e_xdp_mpwqe_session_start(sq);
305 mlx5e_xdp_mpwqe_add_dseg(sq, xdptxd, stats);
307 if (unlikely(mlx5e_xdp_mpqwe_is_full(session, sq->max_sq_mpw_wqebbs)))
308 mlx5e_xdp_mpwqe_complete(sq);
314 static int mlx5e_xmit_xdp_frame_check_stop_room(struct mlx5e_xdpsq *sq, int stop_room)
316 if (unlikely(!mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, stop_room))) {
317 /* SQ is full, ring doorbell */
318 mlx5e_xmit_xdp_doorbell(sq);
323 return MLX5E_XDP_CHECK_OK;
326 INDIRECT_CALLABLE_SCOPE int mlx5e_xmit_xdp_frame_check(struct mlx5e_xdpsq *sq)
328 return mlx5e_xmit_xdp_frame_check_stop_room(sq, 1);
331 INDIRECT_CALLABLE_SCOPE bool
332 mlx5e_xmit_xdp_frame(struct mlx5e_xdpsq *sq, struct mlx5e_xmit_data *xdptxd,
333 struct skb_shared_info *sinfo, int check_result)
335 struct mlx5_wq_cyc *wq = &sq->wq;
336 struct mlx5_wqe_ctrl_seg *cseg;
337 struct mlx5_wqe_data_seg *dseg;
338 struct mlx5_wqe_eth_seg *eseg;
339 struct mlx5e_tx_wqe *wqe;
341 dma_addr_t dma_addr = xdptxd->dma_addr;
342 u32 dma_len = xdptxd->len;
343 u16 ds_cnt, inline_hdr_sz;
348 struct mlx5e_xdpsq_stats *stats = sq->stats;
350 if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE || sq->hw_mtu < dma_len)) {
355 ds_cnt = MLX5E_TX_WQE_EMPTY_DS_COUNT + 1;
356 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE)
359 /* check_result must be 0 if sinfo is passed. */
363 if (unlikely(sinfo)) {
364 ds_cnt += sinfo->nr_frags;
365 num_frags = sinfo->nr_frags;
366 num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS);
367 /* Assuming MLX5_CAP_GEN(mdev, max_wqe_sz_sq) is big
368 * enough to hold all fragments.
370 stop_room = MLX5E_STOP_ROOM(num_wqebbs);
373 check_result = mlx5e_xmit_xdp_frame_check_stop_room(sq, stop_room);
375 if (unlikely(check_result < 0))
378 pi = mlx5e_xdpsq_get_next_pi(sq, num_wqebbs);
379 wqe = mlx5_wq_cyc_get_wqe(wq, pi);
388 /* copy the inline part if required */
389 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
390 memcpy(eseg->inline_hdr.start, xdptxd->data, sizeof(eseg->inline_hdr.start));
391 memcpy(dseg, xdptxd->data + sizeof(eseg->inline_hdr.start),
392 MLX5E_XDP_MIN_INLINE - sizeof(eseg->inline_hdr.start));
393 dma_len -= MLX5E_XDP_MIN_INLINE;
394 dma_addr += MLX5E_XDP_MIN_INLINE;
395 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
399 /* write the dma part */
400 dseg->addr = cpu_to_be64(dma_addr);
401 dseg->byte_count = cpu_to_be32(dma_len);
403 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND);
405 if (unlikely(test_bit(MLX5E_SQ_STATE_XDP_MULTIBUF, &sq->state))) {
406 u8 num_pkts = 1 + num_frags;
409 memset(&cseg->signature, 0, sizeof(*cseg) -
410 sizeof(cseg->opmod_idx_opcode) - sizeof(cseg->qpn_ds));
411 memset(eseg, 0, sizeof(*eseg) - sizeof(eseg->trailer));
413 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
414 dseg->lkey = sq->mkey_be;
416 for (i = 0; i < num_frags; i++) {
417 skb_frag_t *frag = &sinfo->frags[i];
420 addr = page_pool_get_dma_addr(skb_frag_page(frag)) +
424 dseg->addr = cpu_to_be64(addr);
425 dseg->byte_count = cpu_to_be32(skb_frag_size(frag));
426 dseg->lkey = sq->mkey_be;
429 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
431 sq->db.wqe_info[pi] = (struct mlx5e_xdp_wqe_info) {
432 .num_wqebbs = num_wqebbs,
433 .num_pkts = num_pkts,
436 sq->pc += num_wqebbs;
443 sq->doorbell_cseg = cseg;
449 static void mlx5e_free_xdpsq_desc(struct mlx5e_xdpsq *sq,
450 struct mlx5e_xdp_wqe_info *wi,
453 struct xdp_frame_bulk *bq)
455 struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
458 for (i = 0; i < wi->num_pkts; i++) {
459 struct mlx5e_xdp_info xdpi = mlx5e_xdpi_fifo_pop(xdpi_fifo);
462 case MLX5E_XDP_XMIT_MODE_FRAME:
463 /* XDP_TX from the XSK RQ and XDP_REDIRECT */
464 dma_unmap_single(sq->pdev, xdpi.frame.dma_addr,
465 xdpi.frame.xdpf->len, DMA_TO_DEVICE);
466 xdp_return_frame_bulk(xdpi.frame.xdpf, bq);
468 case MLX5E_XDP_XMIT_MODE_PAGE:
469 /* XDP_TX from the regular RQ */
470 mlx5e_page_release_dynamic(xdpi.page.rq, xdpi.page.page, recycle);
472 case MLX5E_XDP_XMIT_MODE_XSK:
482 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq)
484 struct xdp_frame_bulk bq;
485 struct mlx5e_xdpsq *sq;
486 struct mlx5_cqe64 *cqe;
491 xdp_frame_bulk_init(&bq);
493 sq = container_of(cq, struct mlx5e_xdpsq, cq);
495 if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
498 cqe = mlx5_cqwq_get_cqe(&cq->wq);
502 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
503 * otherwise a cq overrun may occur
509 struct mlx5e_xdp_wqe_info *wi;
513 mlx5_cqwq_pop(&cq->wq);
515 wqe_counter = be16_to_cpu(cqe->wqe_counter);
518 last_wqe = (sqcc == wqe_counter);
519 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
520 wi = &sq->db.wqe_info[ci];
522 sqcc += wi->num_wqebbs;
524 mlx5e_free_xdpsq_desc(sq, wi, &xsk_frames, true, &bq);
527 if (unlikely(get_cqe_opcode(cqe) != MLX5_CQE_REQ)) {
528 netdev_WARN_ONCE(sq->channel->netdev,
529 "Bad OP in XDPSQ CQE: 0x%x\n",
530 get_cqe_opcode(cqe));
531 mlx5e_dump_error_cqe(&sq->cq, sq->sqn,
532 (struct mlx5_err_cqe *)cqe);
533 mlx5_wq_cyc_wqe_dump(&sq->wq, ci, wi->num_wqebbs);
535 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
537 xdp_flush_frame_bulk(&bq);
540 xsk_tx_completed(sq->xsk_pool, xsk_frames);
542 sq->stats->cqes += i;
544 mlx5_cqwq_update_db_record(&cq->wq);
546 /* ensure cq space is freed before enabling more cqes */
550 return (i == MLX5E_TX_CQ_POLL_BUDGET);
553 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq)
555 struct xdp_frame_bulk bq;
558 xdp_frame_bulk_init(&bq);
560 rcu_read_lock(); /* need for xdp_return_frame_bulk */
562 while (sq->cc != sq->pc) {
563 struct mlx5e_xdp_wqe_info *wi;
566 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sq->cc);
567 wi = &sq->db.wqe_info[ci];
569 sq->cc += wi->num_wqebbs;
571 mlx5e_free_xdpsq_desc(sq, wi, &xsk_frames, false, &bq);
574 xdp_flush_frame_bulk(&bq);
578 xsk_tx_completed(sq->xsk_pool, xsk_frames);
581 int mlx5e_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames,
584 struct mlx5e_priv *priv = netdev_priv(dev);
585 struct mlx5e_xdpsq *sq;
590 /* this flag is sufficient, no need to test internal sq state */
591 if (unlikely(!mlx5e_xdp_tx_is_enabled(priv)))
594 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
597 sq_num = smp_processor_id();
599 if (unlikely(sq_num >= priv->channels.num))
602 sq = &priv->channels.c[sq_num]->xdpsq;
604 for (i = 0; i < n; i++) {
605 struct xdp_frame *xdpf = frames[i];
606 struct mlx5e_xmit_data xdptxd;
607 struct mlx5e_xdp_info xdpi;
610 xdptxd.data = xdpf->data;
611 xdptxd.len = xdpf->len;
612 xdptxd.dma_addr = dma_map_single(sq->pdev, xdptxd.data,
613 xdptxd.len, DMA_TO_DEVICE);
615 if (unlikely(dma_mapping_error(sq->pdev, xdptxd.dma_addr)))
618 xdpi.mode = MLX5E_XDP_XMIT_MODE_FRAME;
619 xdpi.frame.xdpf = xdpf;
620 xdpi.frame.dma_addr = xdptxd.dma_addr;
622 ret = INDIRECT_CALL_2(sq->xmit_xdp_frame, mlx5e_xmit_xdp_frame_mpwqe,
623 mlx5e_xmit_xdp_frame, sq, &xdptxd, NULL, 0);
624 if (unlikely(!ret)) {
625 dma_unmap_single(sq->pdev, xdptxd.dma_addr,
626 xdptxd.len, DMA_TO_DEVICE);
629 mlx5e_xdpi_fifo_push(&sq->db.xdpi_fifo, &xdpi);
633 if (flags & XDP_XMIT_FLUSH) {
635 mlx5e_xdp_mpwqe_complete(sq);
636 mlx5e_xmit_xdp_doorbell(sq);
642 void mlx5e_xdp_rx_poll_complete(struct mlx5e_rq *rq)
644 struct mlx5e_xdpsq *xdpsq = rq->xdpsq;
646 if (xdpsq->mpwqe.wqe)
647 mlx5e_xdp_mpwqe_complete(xdpsq);
649 mlx5e_xmit_xdp_doorbell(xdpsq);
651 if (test_bit(MLX5E_RQ_FLAG_XDP_REDIRECT, rq->flags)) {
653 __clear_bit(MLX5E_RQ_FLAG_XDP_REDIRECT, rq->flags);
657 void mlx5e_set_xmit_fp(struct mlx5e_xdpsq *sq, bool is_mpw)
659 sq->xmit_xdp_frame_check = is_mpw ?
660 mlx5e_xmit_xdp_frame_check_mpwqe : mlx5e_xmit_xdp_frame_check;
661 sq->xmit_xdp_frame = is_mpw ?
662 mlx5e_xmit_xdp_frame_mpwqe : mlx5e_xmit_xdp_frame;