2 * Copyright (c) 2018, Mellanox Technologies. All rights reserved.
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23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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35 /* speed in units of 1Mb */
36 static const u32 mlx5e_link_speed[MLX5E_LINK_MODES_NUMBER] = {
37 [MLX5E_1000BASE_CX_SGMII] = 1000,
38 [MLX5E_1000BASE_KX] = 1000,
39 [MLX5E_10GBASE_CX4] = 10000,
40 [MLX5E_10GBASE_KX4] = 10000,
41 [MLX5E_10GBASE_KR] = 10000,
42 [MLX5E_20GBASE_KR2] = 20000,
43 [MLX5E_40GBASE_CR4] = 40000,
44 [MLX5E_40GBASE_KR4] = 40000,
45 [MLX5E_56GBASE_R4] = 56000,
46 [MLX5E_10GBASE_CR] = 10000,
47 [MLX5E_10GBASE_SR] = 10000,
48 [MLX5E_10GBASE_ER] = 10000,
49 [MLX5E_40GBASE_SR4] = 40000,
50 [MLX5E_40GBASE_LR4] = 40000,
51 [MLX5E_50GBASE_SR2] = 50000,
52 [MLX5E_100GBASE_CR4] = 100000,
53 [MLX5E_100GBASE_SR4] = 100000,
54 [MLX5E_100GBASE_KR4] = 100000,
55 [MLX5E_100GBASE_LR4] = 100000,
56 [MLX5E_100BASE_TX] = 100,
57 [MLX5E_1000BASE_T] = 1000,
58 [MLX5E_10GBASE_T] = 10000,
59 [MLX5E_25GBASE_CR] = 25000,
60 [MLX5E_25GBASE_KR] = 25000,
61 [MLX5E_25GBASE_SR] = 25000,
62 [MLX5E_50GBASE_CR2] = 50000,
63 [MLX5E_50GBASE_KR2] = 50000,
66 u32 mlx5e_port_ptys2speed(u32 eth_proto_oper)
68 unsigned long temp = eth_proto_oper;
72 i = find_first_bit(&temp, MLX5E_LINK_MODES_NUMBER);
73 if (i < MLX5E_LINK_MODES_NUMBER)
74 speed = mlx5e_link_speed[i];
79 int mlx5e_port_linkspeed(struct mlx5_core_dev *mdev, u32 *speed)
81 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {};
85 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
89 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
90 *speed = mlx5e_port_ptys2speed(eth_proto_oper);
92 mlx5_core_warn(mdev, "cannot get port speed\n");
99 int mlx5e_port_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed)
106 err = mlx5_query_port_proto_cap(mdev, &proto_cap, MLX5_PTYS_EN);
110 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i)
111 if (proto_cap & MLX5E_PROT_MASK(i))
112 max_speed = max(max_speed, mlx5e_link_speed[i]);
118 u32 mlx5e_port_speed2linkmodes(u32 speed)
123 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
124 if (mlx5e_link_speed[i] == speed)
125 link_modes |= MLX5E_PROT_MASK(i);
131 int mlx5e_port_query_pbmc(struct mlx5_core_dev *mdev, void *out)
133 int sz = MLX5_ST_SZ_BYTES(pbmc_reg);
137 in = kzalloc(sz, GFP_KERNEL);
141 MLX5_SET(pbmc_reg, in, local_port, 1);
142 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PBMC, 0, 0);
148 int mlx5e_port_set_pbmc(struct mlx5_core_dev *mdev, void *in)
150 int sz = MLX5_ST_SZ_BYTES(pbmc_reg);
154 out = kzalloc(sz, GFP_KERNEL);
158 MLX5_SET(pbmc_reg, in, local_port, 1);
159 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PBMC, 0, 1);
165 /* buffer[i]: buffer that priority i mapped to */
166 int mlx5e_port_query_priority2buffer(struct mlx5_core_dev *mdev, u8 *buffer)
168 int sz = MLX5_ST_SZ_BYTES(pptb_reg);
175 in = kzalloc(sz, GFP_KERNEL);
176 out = kzalloc(sz, GFP_KERNEL);
182 MLX5_SET(pptb_reg, in, local_port, 1);
183 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPTB, 0, 0);
187 prio_x_buff = MLX5_GET(pptb_reg, out, prio_x_buff);
188 for (prio = 0; prio < 8; prio++) {
189 buffer[prio] = (u8)(prio_x_buff >> (4 * prio)) & 0xF;
190 mlx5_core_dbg(mdev, "prio %d, buffer %d\n", prio, buffer[prio]);
198 int mlx5e_port_set_priority2buffer(struct mlx5_core_dev *mdev, u8 *buffer)
200 int sz = MLX5_ST_SZ_BYTES(pptb_reg);
207 in = kzalloc(sz, GFP_KERNEL);
208 out = kzalloc(sz, GFP_KERNEL);
214 /* First query the pptb register */
215 MLX5_SET(pptb_reg, in, local_port, 1);
216 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPTB, 0, 0);
221 MLX5_SET(pptb_reg, in, local_port, 1);
223 /* Update the pm and prio_x_buff */
224 MLX5_SET(pptb_reg, in, pm, 0xFF);
227 for (prio = 0; prio < 8; prio++)
228 prio_x_buff |= (buffer[prio] << (4 * prio));
229 MLX5_SET(pptb_reg, in, prio_x_buff, prio_x_buff);
231 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPTB, 0, 1);
239 static u32 fec_supported_speeds[] = {
248 #define MLX5E_FEC_SUPPORTED_SPEEDS ARRAY_SIZE(fec_supported_speeds)
250 /* get/set FEC admin field for a given speed */
251 static int mlx5e_fec_admin_field(u32 *pplm,
260 *fec_policy = MLX5_GET(pplm_reg, pplm,
261 fec_override_cap_10g_40g);
263 MLX5_SET(pplm_reg, pplm,
264 fec_override_admin_10g_40g, *fec_policy);
268 *fec_policy = MLX5_GET(pplm_reg, pplm,
269 fec_override_admin_25g);
271 MLX5_SET(pplm_reg, pplm,
272 fec_override_admin_25g, *fec_policy);
276 *fec_policy = MLX5_GET(pplm_reg, pplm,
277 fec_override_admin_50g);
279 MLX5_SET(pplm_reg, pplm,
280 fec_override_admin_50g, *fec_policy);
284 *fec_policy = MLX5_GET(pplm_reg, pplm,
285 fec_override_admin_56g);
287 MLX5_SET(pplm_reg, pplm,
288 fec_override_admin_56g, *fec_policy);
292 *fec_policy = MLX5_GET(pplm_reg, pplm,
293 fec_override_admin_100g);
295 MLX5_SET(pplm_reg, pplm,
296 fec_override_admin_100g, *fec_policy);
304 /* returns FEC capabilities for a given speed */
305 static int mlx5e_get_fec_cap_field(u32 *pplm,
312 *fec_cap = MLX5_GET(pplm_reg, pplm,
313 fec_override_admin_10g_40g);
316 *fec_cap = MLX5_GET(pplm_reg, pplm,
317 fec_override_cap_25g);
320 *fec_cap = MLX5_GET(pplm_reg, pplm,
321 fec_override_cap_50g);
324 *fec_cap = MLX5_GET(pplm_reg, pplm,
325 fec_override_cap_56g);
328 *fec_cap = MLX5_GET(pplm_reg, pplm,
329 fec_override_cap_100g);
337 int mlx5e_get_fec_caps(struct mlx5_core_dev *dev, u8 *fec_caps)
339 u32 out[MLX5_ST_SZ_DW(pplm_reg)] = {};
340 u32 in[MLX5_ST_SZ_DW(pplm_reg)] = {};
341 int sz = MLX5_ST_SZ_BYTES(pplm_reg);
342 u32 current_fec_speed;
345 if (!MLX5_CAP_GEN(dev, pcam_reg))
348 if (!MLX5_CAP_PCAM_REG(dev, pplm))
351 MLX5_SET(pplm_reg, in, local_port, 1);
352 err = mlx5_core_access_reg(dev, in, sz, out, sz, MLX5_REG_PPLM, 0, 0);
356 err = mlx5e_port_linkspeed(dev, ¤t_fec_speed);
360 return mlx5e_get_fec_cap_field(out, fec_caps, current_fec_speed);
363 int mlx5e_get_fec_mode(struct mlx5_core_dev *dev, u32 *fec_mode_active,
364 u8 *fec_configured_mode)
366 u32 out[MLX5_ST_SZ_DW(pplm_reg)] = {};
367 u32 in[MLX5_ST_SZ_DW(pplm_reg)] = {};
368 int sz = MLX5_ST_SZ_BYTES(pplm_reg);
372 if (!MLX5_CAP_GEN(dev, pcam_reg))
375 if (!MLX5_CAP_PCAM_REG(dev, pplm))
378 MLX5_SET(pplm_reg, in, local_port, 1);
379 err = mlx5_core_access_reg(dev, in, sz, out, sz, MLX5_REG_PPLM, 0, 0);
383 *fec_mode_active = MLX5_GET(pplm_reg, out, fec_mode_active);
385 if (!fec_configured_mode)
388 err = mlx5e_port_linkspeed(dev, &link_speed);
392 return mlx5e_fec_admin_field(out, fec_configured_mode, 0, link_speed);
395 int mlx5e_set_fec_mode(struct mlx5_core_dev *dev, u8 fec_policy)
397 bool fec_mode_not_supp_in_speed = false;
398 u8 no_fec_policy = BIT(MLX5E_FEC_NOFEC);
399 u32 out[MLX5_ST_SZ_DW(pplm_reg)] = {};
400 u32 in[MLX5_ST_SZ_DW(pplm_reg)] = {};
401 int sz = MLX5_ST_SZ_BYTES(pplm_reg);
402 u32 current_fec_speed;
407 if (!MLX5_CAP_GEN(dev, pcam_reg))
410 if (!MLX5_CAP_PCAM_REG(dev, pplm))
413 MLX5_SET(pplm_reg, in, local_port, 1);
414 err = mlx5_core_access_reg(dev, in, sz, out, sz, MLX5_REG_PPLM, 0, 0);
418 err = mlx5e_port_linkspeed(dev, ¤t_fec_speed);
423 MLX5_SET(pplm_reg, in, local_port, 1);
424 for (i = 0; i < MLX5E_FEC_SUPPORTED_SPEEDS && !!fec_policy; i++) {
425 mlx5e_get_fec_cap_field(out, &fec_caps, fec_supported_speeds[i]);
426 /* policy supported for link speed */
427 if (!!(fec_caps & fec_policy)) {
428 mlx5e_fec_admin_field(in, &fec_policy, 1,
429 fec_supported_speeds[i]);
431 if (fec_supported_speeds[i] == current_fec_speed)
433 mlx5e_fec_admin_field(in, &no_fec_policy, 1,
434 fec_supported_speeds[i]);
435 fec_mode_not_supp_in_speed = true;
439 if (fec_mode_not_supp_in_speed)
441 "FEC policy 0x%x is not supported for some speeds",
444 return mlx5_core_access_reg(dev, in, sz, out, sz, MLX5_REG_PPLM, 0, 1);