2 * Copyright (c) 2018, Mellanox Technologies. All rights reserved.
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23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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35 /* speed in units of 1Mb */
36 static const u32 mlx5e_link_speed[MLX5E_LINK_MODES_NUMBER] = {
37 [MLX5E_1000BASE_CX_SGMII] = 1000,
38 [MLX5E_1000BASE_KX] = 1000,
39 [MLX5E_10GBASE_CX4] = 10000,
40 [MLX5E_10GBASE_KX4] = 10000,
41 [MLX5E_10GBASE_KR] = 10000,
42 [MLX5E_20GBASE_KR2] = 20000,
43 [MLX5E_40GBASE_CR4] = 40000,
44 [MLX5E_40GBASE_KR4] = 40000,
45 [MLX5E_56GBASE_R4] = 56000,
46 [MLX5E_10GBASE_CR] = 10000,
47 [MLX5E_10GBASE_SR] = 10000,
48 [MLX5E_10GBASE_ER] = 10000,
49 [MLX5E_40GBASE_SR4] = 40000,
50 [MLX5E_40GBASE_LR4] = 40000,
51 [MLX5E_50GBASE_SR2] = 50000,
52 [MLX5E_100GBASE_CR4] = 100000,
53 [MLX5E_100GBASE_SR4] = 100000,
54 [MLX5E_100GBASE_KR4] = 100000,
55 [MLX5E_100GBASE_LR4] = 100000,
56 [MLX5E_100BASE_TX] = 100,
57 [MLX5E_1000BASE_T] = 1000,
58 [MLX5E_10GBASE_T] = 10000,
59 [MLX5E_25GBASE_CR] = 25000,
60 [MLX5E_25GBASE_KR] = 25000,
61 [MLX5E_25GBASE_SR] = 25000,
62 [MLX5E_50GBASE_CR2] = 50000,
63 [MLX5E_50GBASE_KR2] = 50000,
66 u32 mlx5e_port_ptys2speed(u32 eth_proto_oper)
68 unsigned long temp = eth_proto_oper;
72 i = find_first_bit(&temp, MLX5E_LINK_MODES_NUMBER);
73 if (i < MLX5E_LINK_MODES_NUMBER)
74 speed = mlx5e_link_speed[i];
79 int mlx5e_port_linkspeed(struct mlx5_core_dev *mdev, u32 *speed)
81 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {};
85 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
89 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
90 *speed = mlx5e_port_ptys2speed(eth_proto_oper);
97 int mlx5e_port_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed)
104 err = mlx5_query_port_proto_cap(mdev, &proto_cap, MLX5_PTYS_EN);
108 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i)
109 if (proto_cap & MLX5E_PROT_MASK(i))
110 max_speed = max(max_speed, mlx5e_link_speed[i]);
116 u32 mlx5e_port_speed2linkmodes(u32 speed)
121 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
122 if (mlx5e_link_speed[i] == speed)
123 link_modes |= MLX5E_PROT_MASK(i);
129 int mlx5e_port_query_pbmc(struct mlx5_core_dev *mdev, void *out)
131 int sz = MLX5_ST_SZ_BYTES(pbmc_reg);
135 in = kzalloc(sz, GFP_KERNEL);
139 MLX5_SET(pbmc_reg, in, local_port, 1);
140 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PBMC, 0, 0);
146 int mlx5e_port_set_pbmc(struct mlx5_core_dev *mdev, void *in)
148 int sz = MLX5_ST_SZ_BYTES(pbmc_reg);
152 out = kzalloc(sz, GFP_KERNEL);
156 MLX5_SET(pbmc_reg, in, local_port, 1);
157 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PBMC, 0, 1);
163 /* buffer[i]: buffer that priority i mapped to */
164 int mlx5e_port_query_priority2buffer(struct mlx5_core_dev *mdev, u8 *buffer)
166 int sz = MLX5_ST_SZ_BYTES(pptb_reg);
173 in = kzalloc(sz, GFP_KERNEL);
174 out = kzalloc(sz, GFP_KERNEL);
180 MLX5_SET(pptb_reg, in, local_port, 1);
181 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPTB, 0, 0);
185 prio_x_buff = MLX5_GET(pptb_reg, out, prio_x_buff);
186 for (prio = 0; prio < 8; prio++) {
187 buffer[prio] = (u8)(prio_x_buff >> (4 * prio)) & 0xF;
188 mlx5_core_dbg(mdev, "prio %d, buffer %d\n", prio, buffer[prio]);
196 int mlx5e_port_set_priority2buffer(struct mlx5_core_dev *mdev, u8 *buffer)
198 int sz = MLX5_ST_SZ_BYTES(pptb_reg);
205 in = kzalloc(sz, GFP_KERNEL);
206 out = kzalloc(sz, GFP_KERNEL);
212 /* First query the pptb register */
213 MLX5_SET(pptb_reg, in, local_port, 1);
214 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPTB, 0, 0);
219 MLX5_SET(pptb_reg, in, local_port, 1);
221 /* Update the pm and prio_x_buff */
222 MLX5_SET(pptb_reg, in, pm, 0xFF);
225 for (prio = 0; prio < 8; prio++)
226 prio_x_buff |= (buffer[prio] << (4 * prio));
227 MLX5_SET(pptb_reg, in, prio_x_buff, prio_x_buff);
229 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPTB, 0, 1);
237 static u32 fec_supported_speeds[] = {
246 #define MLX5E_FEC_SUPPORTED_SPEEDS ARRAY_SIZE(fec_supported_speeds)
248 /* get/set FEC admin field for a given speed */
249 static int mlx5e_fec_admin_field(u32 *pplm,
258 *fec_policy = MLX5_GET(pplm_reg, pplm,
259 fec_override_admin_10g_40g);
261 MLX5_SET(pplm_reg, pplm,
262 fec_override_admin_10g_40g, *fec_policy);
266 *fec_policy = MLX5_GET(pplm_reg, pplm,
267 fec_override_admin_25g);
269 MLX5_SET(pplm_reg, pplm,
270 fec_override_admin_25g, *fec_policy);
274 *fec_policy = MLX5_GET(pplm_reg, pplm,
275 fec_override_admin_50g);
277 MLX5_SET(pplm_reg, pplm,
278 fec_override_admin_50g, *fec_policy);
282 *fec_policy = MLX5_GET(pplm_reg, pplm,
283 fec_override_admin_56g);
285 MLX5_SET(pplm_reg, pplm,
286 fec_override_admin_56g, *fec_policy);
290 *fec_policy = MLX5_GET(pplm_reg, pplm,
291 fec_override_admin_100g);
293 MLX5_SET(pplm_reg, pplm,
294 fec_override_admin_100g, *fec_policy);
302 /* returns FEC capabilities for a given speed */
303 static int mlx5e_get_fec_cap_field(u32 *pplm,
310 *fec_cap = MLX5_GET(pplm_reg, pplm,
311 fec_override_cap_10g_40g);
314 *fec_cap = MLX5_GET(pplm_reg, pplm,
315 fec_override_cap_25g);
318 *fec_cap = MLX5_GET(pplm_reg, pplm,
319 fec_override_cap_50g);
322 *fec_cap = MLX5_GET(pplm_reg, pplm,
323 fec_override_cap_56g);
326 *fec_cap = MLX5_GET(pplm_reg, pplm,
327 fec_override_cap_100g);
335 int mlx5e_get_fec_caps(struct mlx5_core_dev *dev, u8 *fec_caps)
337 u32 out[MLX5_ST_SZ_DW(pplm_reg)] = {};
338 u32 in[MLX5_ST_SZ_DW(pplm_reg)] = {};
339 int sz = MLX5_ST_SZ_BYTES(pplm_reg);
340 u32 current_fec_speed;
343 if (!MLX5_CAP_GEN(dev, pcam_reg))
346 if (!MLX5_CAP_PCAM_REG(dev, pplm))
349 MLX5_SET(pplm_reg, in, local_port, 1);
350 err = mlx5_core_access_reg(dev, in, sz, out, sz, MLX5_REG_PPLM, 0, 0);
354 err = mlx5e_port_linkspeed(dev, ¤t_fec_speed);
358 return mlx5e_get_fec_cap_field(out, fec_caps, current_fec_speed);
361 int mlx5e_get_fec_mode(struct mlx5_core_dev *dev, u32 *fec_mode_active,
362 u8 *fec_configured_mode)
364 u32 out[MLX5_ST_SZ_DW(pplm_reg)] = {};
365 u32 in[MLX5_ST_SZ_DW(pplm_reg)] = {};
366 int sz = MLX5_ST_SZ_BYTES(pplm_reg);
370 if (!MLX5_CAP_GEN(dev, pcam_reg))
373 if (!MLX5_CAP_PCAM_REG(dev, pplm))
376 MLX5_SET(pplm_reg, in, local_port, 1);
377 err = mlx5_core_access_reg(dev, in, sz, out, sz, MLX5_REG_PPLM, 0, 0);
381 *fec_mode_active = MLX5_GET(pplm_reg, out, fec_mode_active);
383 if (!fec_configured_mode)
386 err = mlx5e_port_linkspeed(dev, &link_speed);
390 return mlx5e_fec_admin_field(out, fec_configured_mode, 0, link_speed);
393 int mlx5e_set_fec_mode(struct mlx5_core_dev *dev, u8 fec_policy)
395 u8 fec_policy_nofec = BIT(MLX5E_FEC_NOFEC);
396 bool fec_mode_not_supp_in_speed = false;
397 u32 out[MLX5_ST_SZ_DW(pplm_reg)] = {};
398 u32 in[MLX5_ST_SZ_DW(pplm_reg)] = {};
399 int sz = MLX5_ST_SZ_BYTES(pplm_reg);
400 u8 fec_policy_auto = 0;
405 if (!MLX5_CAP_GEN(dev, pcam_reg))
408 if (!MLX5_CAP_PCAM_REG(dev, pplm))
411 MLX5_SET(pplm_reg, in, local_port, 1);
412 err = mlx5_core_access_reg(dev, in, sz, out, sz, MLX5_REG_PPLM, 0, 0);
416 MLX5_SET(pplm_reg, out, local_port, 1);
418 for (i = 0; i < MLX5E_FEC_SUPPORTED_SPEEDS; i++) {
419 mlx5e_get_fec_cap_field(out, &fec_caps, fec_supported_speeds[i]);
420 /* policy supported for link speed, or policy is auto */
421 if (fec_caps & fec_policy || fec_policy == fec_policy_auto) {
422 mlx5e_fec_admin_field(out, &fec_policy, 1,
423 fec_supported_speeds[i]);
425 /* turn off FEC if supported. Else, leave it the same */
426 if (fec_caps & fec_policy_nofec)
427 mlx5e_fec_admin_field(out, &fec_policy_nofec, 1,
428 fec_supported_speeds[i]);
429 fec_mode_not_supp_in_speed = true;
433 if (fec_mode_not_supp_in_speed)
435 "FEC policy 0x%x is not supported for some speeds",
438 return mlx5_core_access_reg(dev, out, sz, out, sz, MLX5_REG_PPLM, 0, 1);