2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <asm-generic/kmap_types.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/delay.h>
41 #include <linux/random.h>
42 #include <linux/io-mapping.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/debugfs.h>
46 #include "mlx5_core.h"
60 LONG_LIST_SIZE = (2ULL * 1024 * 1024 * 1024 / PAGE_SIZE) * 8 + 16 +
61 MLX5_CMD_DATA_BLOCK_SIZE,
62 MED_LIST_SIZE = 16 + MLX5_CMD_DATA_BLOCK_SIZE,
66 MLX5_CMD_DELIVERY_STAT_OK = 0x0,
67 MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR = 0x1,
68 MLX5_CMD_DELIVERY_STAT_TOK_ERR = 0x2,
69 MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR = 0x3,
70 MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR = 0x4,
71 MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR = 0x5,
72 MLX5_CMD_DELIVERY_STAT_FW_ERR = 0x6,
73 MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR = 0x7,
74 MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR = 0x8,
75 MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR = 0x9,
76 MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR = 0x10,
80 MLX5_CMD_STAT_OK = 0x0,
81 MLX5_CMD_STAT_INT_ERR = 0x1,
82 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
83 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
84 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
85 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
86 MLX5_CMD_STAT_RES_BUSY = 0x6,
87 MLX5_CMD_STAT_LIM_ERR = 0x8,
88 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
89 MLX5_CMD_STAT_IX_ERR = 0xa,
90 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
91 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
92 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
93 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
94 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
95 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
98 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
99 struct mlx5_cmd_msg *in,
100 struct mlx5_cmd_msg *out,
102 void *context, int page_queue)
104 gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
105 struct mlx5_cmd_work_ent *ent;
107 ent = kzalloc(sizeof(*ent), alloc_flags);
109 return ERR_PTR(-ENOMEM);
114 ent->context = context;
116 ent->page_queue = page_queue;
121 static u8 alloc_token(struct mlx5_cmd *cmd)
125 spin_lock(&cmd->token_lock);
126 token = cmd->token++ % 255 + 1;
127 spin_unlock(&cmd->token_lock);
132 static int alloc_ent(struct mlx5_cmd *cmd)
137 spin_lock_irqsave(&cmd->alloc_lock, flags);
138 ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
139 if (ret < cmd->max_reg_cmds)
140 clear_bit(ret, &cmd->bitmask);
141 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
143 return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
146 static void free_ent(struct mlx5_cmd *cmd, int idx)
150 spin_lock_irqsave(&cmd->alloc_lock, flags);
151 set_bit(idx, &cmd->bitmask);
152 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
155 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
157 return cmd->cmd_buf + (idx << cmd->log_stride);
160 static u8 xor8_buf(void *buf, int len)
166 for (i = 0; i < len; i++)
172 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
174 if (xor8_buf(block->rsvd0, sizeof(*block) - sizeof(block->data) - 1) != 0xff)
177 if (xor8_buf(block, sizeof(*block)) != 0xff)
183 static void calc_block_sig(struct mlx5_cmd_prot_block *block, u8 token)
185 block->token = token;
186 block->ctrl_sig = ~xor8_buf(block->rsvd0, sizeof(*block) - sizeof(block->data) - 2);
187 block->sig = ~xor8_buf(block, sizeof(*block) - 1);
190 static void calc_chain_sig(struct mlx5_cmd_msg *msg, u8 token)
192 struct mlx5_cmd_mailbox *next = msg->next;
195 calc_block_sig(next->buf, token);
200 static void set_signature(struct mlx5_cmd_work_ent *ent)
202 ent->lay->sig = ~xor8_buf(ent->lay, sizeof(*ent->lay));
203 calc_chain_sig(ent->in, ent->token);
204 calc_chain_sig(ent->out, ent->token);
207 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
209 unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
213 own = ent->lay->status_own;
214 if (!(own & CMD_OWNER_HW)) {
218 usleep_range(5000, 10000);
219 } while (time_before(jiffies, poll_end));
221 ent->ret = -ETIMEDOUT;
224 static void free_cmd(struct mlx5_cmd_work_ent *ent)
230 static int verify_signature(struct mlx5_cmd_work_ent *ent)
232 struct mlx5_cmd_mailbox *next = ent->out->next;
236 sig = xor8_buf(ent->lay, sizeof(*ent->lay));
241 err = verify_block_sig(next->buf);
251 static void dump_buf(void *buf, int size, int data_only, int offset)
256 for (i = 0; i < size; i += 16) {
257 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
258 be32_to_cpu(p[1]), be32_to_cpu(p[2]),
267 const char *mlx5_command_str(int command)
270 case MLX5_CMD_OP_QUERY_HCA_CAP:
271 return "QUERY_HCA_CAP";
273 case MLX5_CMD_OP_SET_HCA_CAP:
274 return "SET_HCA_CAP";
276 case MLX5_CMD_OP_QUERY_ADAPTER:
277 return "QUERY_ADAPTER";
279 case MLX5_CMD_OP_INIT_HCA:
282 case MLX5_CMD_OP_TEARDOWN_HCA:
283 return "TEARDOWN_HCA";
285 case MLX5_CMD_OP_ENABLE_HCA:
286 return "MLX5_CMD_OP_ENABLE_HCA";
288 case MLX5_CMD_OP_DISABLE_HCA:
289 return "MLX5_CMD_OP_DISABLE_HCA";
291 case MLX5_CMD_OP_QUERY_PAGES:
292 return "QUERY_PAGES";
294 case MLX5_CMD_OP_MANAGE_PAGES:
295 return "MANAGE_PAGES";
297 case MLX5_CMD_OP_CREATE_MKEY:
298 return "CREATE_MKEY";
300 case MLX5_CMD_OP_QUERY_MKEY:
303 case MLX5_CMD_OP_DESTROY_MKEY:
304 return "DESTROY_MKEY";
306 case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
307 return "QUERY_SPECIAL_CONTEXTS";
309 case MLX5_CMD_OP_CREATE_EQ:
312 case MLX5_CMD_OP_DESTROY_EQ:
315 case MLX5_CMD_OP_QUERY_EQ:
318 case MLX5_CMD_OP_CREATE_CQ:
321 case MLX5_CMD_OP_DESTROY_CQ:
324 case MLX5_CMD_OP_QUERY_CQ:
327 case MLX5_CMD_OP_MODIFY_CQ:
330 case MLX5_CMD_OP_CREATE_QP:
333 case MLX5_CMD_OP_DESTROY_QP:
336 case MLX5_CMD_OP_RST2INIT_QP:
337 return "RST2INIT_QP";
339 case MLX5_CMD_OP_INIT2RTR_QP:
340 return "INIT2RTR_QP";
342 case MLX5_CMD_OP_RTR2RTS_QP:
345 case MLX5_CMD_OP_RTS2RTS_QP:
348 case MLX5_CMD_OP_SQERR2RTS_QP:
349 return "SQERR2RTS_QP";
351 case MLX5_CMD_OP_2ERR_QP:
354 case MLX5_CMD_OP_RTS2SQD_QP:
357 case MLX5_CMD_OP_SQD2RTS_QP:
360 case MLX5_CMD_OP_2RST_QP:
363 case MLX5_CMD_OP_QUERY_QP:
366 case MLX5_CMD_OP_CONF_SQP:
369 case MLX5_CMD_OP_MAD_IFC:
372 case MLX5_CMD_OP_INIT2INIT_QP:
373 return "INIT2INIT_QP";
375 case MLX5_CMD_OP_SUSPEND_QP:
378 case MLX5_CMD_OP_UNSUSPEND_QP:
379 return "UNSUSPEND_QP";
381 case MLX5_CMD_OP_SQD2SQD_QP:
384 case MLX5_CMD_OP_ALLOC_QP_COUNTER_SET:
385 return "ALLOC_QP_COUNTER_SET";
387 case MLX5_CMD_OP_DEALLOC_QP_COUNTER_SET:
388 return "DEALLOC_QP_COUNTER_SET";
390 case MLX5_CMD_OP_QUERY_QP_COUNTER_SET:
391 return "QUERY_QP_COUNTER_SET";
393 case MLX5_CMD_OP_CREATE_PSV:
396 case MLX5_CMD_OP_DESTROY_PSV:
397 return "DESTROY_PSV";
399 case MLX5_CMD_OP_QUERY_PSV:
402 case MLX5_CMD_OP_QUERY_SIG_RULE_TABLE:
403 return "QUERY_SIG_RULE_TABLE";
405 case MLX5_CMD_OP_QUERY_BLOCK_SIZE_TABLE:
406 return "QUERY_BLOCK_SIZE_TABLE";
408 case MLX5_CMD_OP_CREATE_SRQ:
411 case MLX5_CMD_OP_DESTROY_SRQ:
412 return "DESTROY_SRQ";
414 case MLX5_CMD_OP_QUERY_SRQ:
417 case MLX5_CMD_OP_ARM_RQ:
420 case MLX5_CMD_OP_RESIZE_SRQ:
423 case MLX5_CMD_OP_ALLOC_PD:
426 case MLX5_CMD_OP_DEALLOC_PD:
429 case MLX5_CMD_OP_ALLOC_UAR:
432 case MLX5_CMD_OP_DEALLOC_UAR:
433 return "DEALLOC_UAR";
435 case MLX5_CMD_OP_ATTACH_TO_MCG:
436 return "ATTACH_TO_MCG";
438 case MLX5_CMD_OP_DETACH_FROM_MCG:
439 return "DETACH_FROM_MCG";
441 case MLX5_CMD_OP_ALLOC_XRCD:
444 case MLX5_CMD_OP_DEALLOC_XRCD:
445 return "DEALLOC_XRCD";
447 case MLX5_CMD_OP_ACCESS_REG:
448 return "MLX5_CMD_OP_ACCESS_REG";
450 default: return "unknown command opcode";
454 static void dump_command(struct mlx5_core_dev *dev,
455 struct mlx5_cmd_work_ent *ent, int input)
457 u16 op = be16_to_cpu(((struct mlx5_inbox_hdr *)(ent->lay->in))->opcode);
458 struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
459 struct mlx5_cmd_mailbox *next = msg->next;
464 data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
467 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
468 "dump command data %s(0x%x) %s\n",
469 mlx5_command_str(op), op,
470 input ? "INPUT" : "OUTPUT");
472 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
473 mlx5_command_str(op), op,
474 input ? "INPUT" : "OUTPUT");
478 dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
479 offset += sizeof(ent->lay->in);
481 dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
482 offset += sizeof(ent->lay->out);
485 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
486 offset += sizeof(*ent->lay);
489 while (next && offset < msg->len) {
491 dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
492 dump_buf(next->buf, dump_len, 1, offset);
493 offset += MLX5_CMD_DATA_BLOCK_SIZE;
495 mlx5_core_dbg(dev, "command block:\n");
496 dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
497 offset += sizeof(struct mlx5_cmd_prot_block);
506 static void cmd_work_handler(struct work_struct *work)
508 struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
509 struct mlx5_cmd *cmd = ent->cmd;
510 struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
511 struct mlx5_cmd_layout *lay;
512 struct semaphore *sem;
514 sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
516 if (!ent->page_queue) {
517 ent->idx = alloc_ent(cmd);
519 mlx5_core_err(dev, "failed to allocate command entry\n");
524 ent->idx = cmd->max_reg_cmds;
527 ent->token = alloc_token(cmd);
528 cmd->ent_arr[ent->idx] = ent;
529 lay = get_inst(cmd, ent->idx);
531 memset(lay, 0, sizeof(*lay));
532 memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
534 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
535 lay->inlen = cpu_to_be32(ent->in->len);
537 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
538 lay->outlen = cpu_to_be32(ent->out->len);
539 lay->type = MLX5_PCI_CMD_XPORT;
540 lay->token = ent->token;
541 lay->status_own = CMD_OWNER_HW;
542 if (!cmd->checksum_disabled)
544 dump_command(dev, ent, 1);
545 ktime_get_ts(&ent->ts1);
547 /* ring doorbell after the descriptor is valid */
549 iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
550 mlx5_core_dbg(dev, "write 0x%x to command doorbell\n", 1 << ent->idx);
552 if (cmd->mode == CMD_MODE_POLLING) {
554 /* make sure we read the descriptor after ownership is SW */
556 mlx5_cmd_comp_handler(dev, 1UL << ent->idx);
560 static const char *deliv_status_to_str(u8 status)
563 case MLX5_CMD_DELIVERY_STAT_OK:
565 case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
566 return "signature error";
567 case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
568 return "token error";
569 case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
570 return "bad block number";
571 case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
572 return "output pointer not aligned to block size";
573 case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
574 return "input pointer not aligned to block size";
575 case MLX5_CMD_DELIVERY_STAT_FW_ERR:
576 return "firmware internal error";
577 case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
578 return "command input length error";
579 case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
580 return "command ouput length error";
581 case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
582 return "reserved fields not cleared";
583 case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
584 return "bad command descriptor type";
586 return "unknown status code";
590 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
592 struct mlx5_inbox_hdr *hdr = (struct mlx5_inbox_hdr *)(in->first.data);
594 return be16_to_cpu(hdr->opcode);
597 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
599 unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
600 struct mlx5_cmd *cmd = &dev->cmd;
603 if (cmd->mode == CMD_MODE_POLLING) {
604 wait_for_completion(&ent->done);
607 if (!wait_for_completion_timeout(&ent->done, timeout))
612 if (err == -ETIMEDOUT) {
613 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
614 mlx5_command_str(msg_to_opcode(ent->in)),
615 msg_to_opcode(ent->in));
617 mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n", err,
618 deliv_status_to_str(ent->status), ent->status);
624 * 1. Callback functions may not sleep
625 * 2. page queue commands do not support asynchrous completion
627 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
628 struct mlx5_cmd_msg *out, mlx5_cmd_cbk_t callback,
629 void *context, int page_queue, u8 *status)
631 struct mlx5_cmd *cmd = &dev->cmd;
632 struct mlx5_cmd_work_ent *ent;
633 ktime_t t1, t2, delta;
634 struct mlx5_cmd_stats *stats;
639 if (callback && page_queue)
642 ent = alloc_cmd(cmd, in, out, callback, context, page_queue);
647 init_completion(&ent->done);
649 INIT_WORK(&ent->work, cmd_work_handler);
651 cmd_work_handler(&ent->work);
652 } else if (!queue_work(cmd->wq, &ent->work)) {
653 mlx5_core_warn(dev, "failed to queue work\n");
659 err = wait_func(dev, ent);
660 if (err == -ETIMEDOUT)
663 t1 = timespec_to_ktime(ent->ts1);
664 t2 = timespec_to_ktime(ent->ts2);
665 delta = ktime_sub(t2, t1);
666 ds = ktime_to_ns(delta);
667 op = be16_to_cpu(((struct mlx5_inbox_hdr *)in->first.data)->opcode);
668 if (op < ARRAY_SIZE(cmd->stats)) {
669 stats = &cmd->stats[op];
670 spin_lock(&stats->lock);
673 spin_unlock(&stats->lock);
675 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
676 "fw exec time for %s is %lld nsec\n",
677 mlx5_command_str(op), ds);
678 *status = ent->status;
690 static ssize_t dbg_write(struct file *filp, const char __user *buf,
691 size_t count, loff_t *pos)
693 struct mlx5_core_dev *dev = filp->private_data;
694 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
698 if (!dbg->in_msg || !dbg->out_msg)
701 if (copy_from_user(lbuf, buf, sizeof(lbuf)))
704 lbuf[sizeof(lbuf) - 1] = 0;
706 if (strcmp(lbuf, "go"))
709 err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
711 return err ? err : count;
715 static const struct file_operations fops = {
716 .owner = THIS_MODULE,
721 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size)
723 struct mlx5_cmd_prot_block *block;
724 struct mlx5_cmd_mailbox *next;
730 copy = min_t(int, size, sizeof(to->first.data));
731 memcpy(to->first.data, from, copy);
742 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
744 memcpy(block->data, from, copy);
753 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
755 struct mlx5_cmd_prot_block *block;
756 struct mlx5_cmd_mailbox *next;
762 copy = min_t(int, size, sizeof(from->first.data));
763 memcpy(to, from->first.data, copy);
774 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
776 if (xor8_buf(block, sizeof(*block)) != 0xff)
779 memcpy(to, block->data, copy);
788 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
791 struct mlx5_cmd_mailbox *mailbox;
793 mailbox = kmalloc(sizeof(*mailbox), flags);
795 return ERR_PTR(-ENOMEM);
797 mailbox->buf = pci_pool_alloc(dev->cmd.pool, flags,
800 mlx5_core_dbg(dev, "failed allocation\n");
802 return ERR_PTR(-ENOMEM);
804 memset(mailbox->buf, 0, sizeof(struct mlx5_cmd_prot_block));
805 mailbox->next = NULL;
810 static void free_cmd_box(struct mlx5_core_dev *dev,
811 struct mlx5_cmd_mailbox *mailbox)
813 pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
817 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
818 gfp_t flags, int size)
820 struct mlx5_cmd_mailbox *tmp, *head = NULL;
821 struct mlx5_cmd_prot_block *block;
822 struct mlx5_cmd_msg *msg;
828 msg = kzalloc(sizeof(*msg), GFP_KERNEL);
830 return ERR_PTR(-ENOMEM);
832 blen = size - min_t(int, sizeof(msg->first.data), size);
833 n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1) / MLX5_CMD_DATA_BLOCK_SIZE;
835 for (i = 0; i < n; i++) {
836 tmp = alloc_cmd_box(dev, flags);
838 mlx5_core_warn(dev, "failed allocating block\n");
845 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
846 block->block_num = cpu_to_be32(n - i - 1);
856 free_cmd_box(dev, head);
864 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
865 struct mlx5_cmd_msg *msg)
867 struct mlx5_cmd_mailbox *head = msg->next;
868 struct mlx5_cmd_mailbox *next;
872 free_cmd_box(dev, head);
878 static ssize_t data_write(struct file *filp, const char __user *buf,
879 size_t count, loff_t *pos)
881 struct mlx5_core_dev *dev = filp->private_data;
882 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
893 ptr = kzalloc(count, GFP_KERNEL);
897 if (copy_from_user(ptr, buf, count)) {
913 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
916 struct mlx5_core_dev *dev = filp->private_data;
917 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
926 copy = min_t(int, count, dbg->outlen);
927 if (copy_to_user(buf, dbg->out_msg, copy))
935 static const struct file_operations dfops = {
936 .owner = THIS_MODULE,
942 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
945 struct mlx5_core_dev *dev = filp->private_data;
946 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
953 err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
957 if (copy_to_user(buf, &outlen, err))
965 static ssize_t outlen_write(struct file *filp, const char __user *buf,
966 size_t count, loff_t *pos)
968 struct mlx5_core_dev *dev = filp->private_data;
969 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
975 if (*pos != 0 || count > 6)
982 if (copy_from_user(outlen_str, buf, count))
987 err = sscanf(outlen_str, "%d", &outlen);
991 ptr = kzalloc(outlen, GFP_KERNEL);
996 dbg->outlen = outlen;
1003 static const struct file_operations olfops = {
1004 .owner = THIS_MODULE,
1005 .open = simple_open,
1006 .write = outlen_write,
1007 .read = outlen_read,
1010 static void set_wqname(struct mlx5_core_dev *dev)
1012 struct mlx5_cmd *cmd = &dev->cmd;
1014 snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1015 dev_name(&dev->pdev->dev));
1018 static void clean_debug_files(struct mlx5_core_dev *dev)
1020 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1022 if (!mlx5_debugfs_root)
1025 mlx5_cmdif_debugfs_cleanup(dev);
1026 debugfs_remove_recursive(dbg->dbg_root);
1029 static int create_debugfs_files(struct mlx5_core_dev *dev)
1031 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1034 if (!mlx5_debugfs_root)
1037 dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1041 dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1046 dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1051 dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1053 if (!dbg->dbg_outlen)
1056 dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1058 if (!dbg->dbg_status)
1061 dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1065 mlx5_cmdif_debugfs_init(dev);
1070 clean_debug_files(dev);
1074 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1076 struct mlx5_cmd *cmd = &dev->cmd;
1079 for (i = 0; i < cmd->max_reg_cmds; i++)
1082 down(&cmd->pages_sem);
1084 flush_workqueue(cmd->wq);
1086 cmd->mode = CMD_MODE_EVENTS;
1088 up(&cmd->pages_sem);
1089 for (i = 0; i < cmd->max_reg_cmds; i++)
1093 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1095 struct mlx5_cmd *cmd = &dev->cmd;
1098 for (i = 0; i < cmd->max_reg_cmds; i++)
1101 down(&cmd->pages_sem);
1103 flush_workqueue(cmd->wq);
1104 cmd->mode = CMD_MODE_POLLING;
1106 up(&cmd->pages_sem);
1107 for (i = 0; i < cmd->max_reg_cmds; i++)
1111 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, unsigned long vector)
1113 struct mlx5_cmd *cmd = &dev->cmd;
1114 struct mlx5_cmd_work_ent *ent;
1115 mlx5_cmd_cbk_t callback;
1120 for (i = 0; i < (1 << cmd->log_sz); i++) {
1121 if (test_bit(i, &vector)) {
1122 struct semaphore *sem;
1124 ent = cmd->ent_arr[i];
1125 if (ent->page_queue)
1126 sem = &cmd->pages_sem;
1129 ktime_get_ts(&ent->ts2);
1130 memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1131 dump_command(dev, ent, 0);
1133 if (!cmd->checksum_disabled)
1134 ent->ret = verify_signature(ent);
1137 ent->status = ent->lay->status_own >> 1;
1138 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1139 ent->ret, deliv_status_to_str(ent->status), ent->status);
1141 free_ent(cmd, ent->idx);
1142 if (ent->callback) {
1143 callback = ent->callback;
1144 context = ent->context;
1147 callback(err, context);
1149 complete(&ent->done);
1155 EXPORT_SYMBOL(mlx5_cmd_comp_handler);
1157 static int status_to_err(u8 status)
1159 return status ? -1 : 0; /* TBD more meaningful codes */
1162 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size)
1164 struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1165 struct mlx5_cmd *cmd = &dev->cmd;
1166 struct cache_ent *ent = NULL;
1168 if (in_size > MED_LIST_SIZE && in_size <= LONG_LIST_SIZE)
1169 ent = &cmd->cache.large;
1170 else if (in_size > 16 && in_size <= MED_LIST_SIZE)
1171 ent = &cmd->cache.med;
1174 spin_lock(&ent->lock);
1175 if (!list_empty(&ent->head)) {
1176 msg = list_entry(ent->head.next, typeof(*msg), list);
1177 /* For cached lists, we must explicitly state what is
1181 list_del(&msg->list);
1183 spin_unlock(&ent->lock);
1187 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, in_size);
1192 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1195 spin_lock(&msg->cache->lock);
1196 list_add_tail(&msg->list, &msg->cache->head);
1197 spin_unlock(&msg->cache->lock);
1199 mlx5_free_cmd_msg(dev, msg);
1203 static int is_manage_pages(struct mlx5_inbox_hdr *in)
1205 return be16_to_cpu(in->opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1208 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1211 struct mlx5_cmd_msg *inb;
1212 struct mlx5_cmd_msg *outb;
1217 pages_queue = is_manage_pages(in);
1219 inb = alloc_msg(dev, in_size);
1225 err = mlx5_copy_to_msg(inb, in, in_size);
1227 mlx5_core_warn(dev, "err %d\n", err);
1231 outb = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, out_size);
1233 err = PTR_ERR(outb);
1237 err = mlx5_cmd_invoke(dev, inb, outb, NULL, NULL, pages_queue, &status);
1241 mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1243 err = status_to_err(status);
1247 err = mlx5_copy_from_msg(out, outb, out_size);
1250 mlx5_free_cmd_msg(dev, outb);
1256 EXPORT_SYMBOL(mlx5_cmd_exec);
1258 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1260 struct mlx5_cmd *cmd = &dev->cmd;
1261 struct mlx5_cmd_msg *msg;
1262 struct mlx5_cmd_msg *n;
1264 list_for_each_entry_safe(msg, n, &cmd->cache.large.head, list) {
1265 list_del(&msg->list);
1266 mlx5_free_cmd_msg(dev, msg);
1269 list_for_each_entry_safe(msg, n, &cmd->cache.med.head, list) {
1270 list_del(&msg->list);
1271 mlx5_free_cmd_msg(dev, msg);
1275 static int create_msg_cache(struct mlx5_core_dev *dev)
1277 struct mlx5_cmd *cmd = &dev->cmd;
1278 struct mlx5_cmd_msg *msg;
1282 spin_lock_init(&cmd->cache.large.lock);
1283 INIT_LIST_HEAD(&cmd->cache.large.head);
1284 spin_lock_init(&cmd->cache.med.lock);
1285 INIT_LIST_HEAD(&cmd->cache.med.head);
1287 for (i = 0; i < NUM_LONG_LISTS; i++) {
1288 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, LONG_LIST_SIZE);
1293 msg->cache = &cmd->cache.large;
1294 list_add_tail(&msg->list, &cmd->cache.large.head);
1297 for (i = 0; i < NUM_MED_LISTS; i++) {
1298 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, MED_LIST_SIZE);
1303 msg->cache = &cmd->cache.med;
1304 list_add_tail(&msg->list, &cmd->cache.med.head);
1310 destroy_msg_cache(dev);
1314 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1316 int size = sizeof(struct mlx5_cmd_prot_block);
1317 int align = roundup_pow_of_two(size);
1318 struct mlx5_cmd *cmd = &dev->cmd;
1324 cmd_if_rev = cmdif_rev(dev);
1325 if (cmd_if_rev != CMD_IF_REV) {
1326 dev_err(&dev->pdev->dev,
1327 "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1328 CMD_IF_REV, cmd_if_rev);
1332 cmd->pool = pci_pool_create("mlx5_cmd", dev->pdev, size, align, 0);
1336 cmd->cmd_buf = (void *)__get_free_pages(GFP_ATOMIC, 0);
1337 if (!cmd->cmd_buf) {
1341 cmd->dma = dma_map_single(&dev->pdev->dev, cmd->cmd_buf, PAGE_SIZE,
1343 if (dma_mapping_error(&dev->pdev->dev, cmd->dma)) {
1348 cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1349 cmd->log_sz = cmd_l >> 4 & 0xf;
1350 cmd->log_stride = cmd_l & 0xf;
1351 if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1352 dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1358 if (cmd->log_sz + cmd->log_stride > PAGE_SHIFT) {
1359 dev_err(&dev->pdev->dev, "command queue size overflow\n");
1364 cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1365 cmd->bitmask = (1 << cmd->max_reg_cmds) - 1;
1367 cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1368 if (cmd->cmdif_rev > CMD_IF_REV) {
1369 dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1370 CMD_IF_REV, cmd->cmdif_rev);
1375 spin_lock_init(&cmd->alloc_lock);
1376 spin_lock_init(&cmd->token_lock);
1377 for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1378 spin_lock_init(&cmd->stats[i].lock);
1380 sema_init(&cmd->sem, cmd->max_reg_cmds);
1381 sema_init(&cmd->pages_sem, 1);
1383 cmd_h = (u32)((u64)(cmd->dma) >> 32);
1384 cmd_l = (u32)(cmd->dma);
1385 if (cmd_l & 0xfff) {
1386 dev_err(&dev->pdev->dev, "invalid command queue address\n");
1391 iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1392 iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1394 /* Make sure firmware sees the complete address before we proceed */
1397 mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1399 cmd->mode = CMD_MODE_POLLING;
1401 err = create_msg_cache(dev);
1403 dev_err(&dev->pdev->dev, "failed to create command cache\n");
1408 cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1410 dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1415 err = create_debugfs_files(dev);
1424 destroy_workqueue(cmd->wq);
1427 destroy_msg_cache(dev);
1430 dma_unmap_single(&dev->pdev->dev, cmd->dma, PAGE_SIZE,
1433 free_pages((unsigned long)cmd->cmd_buf, 0);
1436 pci_pool_destroy(cmd->pool);
1440 EXPORT_SYMBOL(mlx5_cmd_init);
1442 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
1444 struct mlx5_cmd *cmd = &dev->cmd;
1446 clean_debug_files(dev);
1447 destroy_workqueue(cmd->wq);
1448 destroy_msg_cache(dev);
1449 dma_unmap_single(&dev->pdev->dev, cmd->dma, PAGE_SIZE,
1451 free_pages((unsigned long)cmd->cmd_buf, 0);
1452 pci_pool_destroy(cmd->pool);
1454 EXPORT_SYMBOL(mlx5_cmd_cleanup);
1456 static const char *cmd_status_str(u8 status)
1459 case MLX5_CMD_STAT_OK:
1461 case MLX5_CMD_STAT_INT_ERR:
1462 return "internal error";
1463 case MLX5_CMD_STAT_BAD_OP_ERR:
1464 return "bad operation";
1465 case MLX5_CMD_STAT_BAD_PARAM_ERR:
1466 return "bad parameter";
1467 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
1468 return "bad system state";
1469 case MLX5_CMD_STAT_BAD_RES_ERR:
1470 return "bad resource";
1471 case MLX5_CMD_STAT_RES_BUSY:
1472 return "resource busy";
1473 case MLX5_CMD_STAT_LIM_ERR:
1474 return "limits exceeded";
1475 case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
1476 return "bad resource state";
1477 case MLX5_CMD_STAT_IX_ERR:
1479 case MLX5_CMD_STAT_NO_RES_ERR:
1480 return "no resources";
1481 case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
1482 return "bad input length";
1483 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
1484 return "bad output length";
1485 case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
1486 return "bad QP state";
1487 case MLX5_CMD_STAT_BAD_PKT_ERR:
1488 return "bad packet (discarded)";
1489 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
1490 return "bad size too many outstanding CQEs";
1492 return "unknown status";
1496 int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr)
1501 pr_warn("command failed, status %s(0x%x), syndrome 0x%x\n",
1502 cmd_status_str(hdr->status), hdr->status,
1503 be32_to_cpu(hdr->syndrome));
1505 switch (hdr->status) {
1506 case MLX5_CMD_STAT_OK: return 0;
1507 case MLX5_CMD_STAT_INT_ERR: return -EIO;
1508 case MLX5_CMD_STAT_BAD_OP_ERR: return -EINVAL;
1509 case MLX5_CMD_STAT_BAD_PARAM_ERR: return -EINVAL;
1510 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR: return -EIO;
1511 case MLX5_CMD_STAT_BAD_RES_ERR: return -EINVAL;
1512 case MLX5_CMD_STAT_RES_BUSY: return -EBUSY;
1513 case MLX5_CMD_STAT_LIM_ERR: return -EINVAL;
1514 case MLX5_CMD_STAT_BAD_RES_STATE_ERR: return -EINVAL;
1515 case MLX5_CMD_STAT_IX_ERR: return -EINVAL;
1516 case MLX5_CMD_STAT_NO_RES_ERR: return -EAGAIN;
1517 case MLX5_CMD_STAT_BAD_INP_LEN_ERR: return -EIO;
1518 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR: return -EIO;
1519 case MLX5_CMD_STAT_BAD_QP_STATE_ERR: return -EINVAL;
1520 case MLX5_CMD_STAT_BAD_PKT_ERR: return -EINVAL;
1521 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR: return -EINVAL;
1522 default: return -EIO;