2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies.
5 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/sched.h>
37 #include <linux/pci.h>
38 #include <linux/errno.h>
39 #include <linux/kernel.h>
41 #include <linux/slab.h>
42 #include <linux/mlx4/cmd.h>
43 #include <linux/mlx4/qp.h>
44 #include <linux/if_ether.h>
45 #include <linux/etherdevice.h>
49 #include "mlx4_stats.h"
51 #define MLX4_MAC_VALID (1ull << 63)
52 #define MLX4_PF_COUNTERS_PER_PORT 2
53 #define MLX4_VF_COUNTERS_PER_PORT 1
56 struct list_head list;
64 struct list_head list;
72 struct list_head list;
87 struct list_head list;
89 enum mlx4_protocol prot;
90 enum mlx4_steer_type steer;
95 RES_QP_BUSY = RES_ANY_BUSY,
97 /* QP number was allocated */
100 /* ICM memory for QP context was mapped */
103 /* QP is in hw ownership */
108 struct res_common com;
113 struct list_head mcg_list;
118 /* saved qp params before VST enforcement in order to restore on VGT */
128 enum res_mtt_states {
129 RES_MTT_BUSY = RES_ANY_BUSY,
133 static inline const char *mtt_states_str(enum res_mtt_states state)
136 case RES_MTT_BUSY: return "RES_MTT_BUSY";
137 case RES_MTT_ALLOCATED: return "RES_MTT_ALLOCATED";
138 default: return "Unknown";
143 struct res_common com;
148 enum res_mpt_states {
149 RES_MPT_BUSY = RES_ANY_BUSY,
156 struct res_common com;
162 RES_EQ_BUSY = RES_ANY_BUSY,
168 struct res_common com;
173 RES_CQ_BUSY = RES_ANY_BUSY,
179 struct res_common com;
184 enum res_srq_states {
185 RES_SRQ_BUSY = RES_ANY_BUSY,
191 struct res_common com;
197 enum res_counter_states {
198 RES_COUNTER_BUSY = RES_ANY_BUSY,
199 RES_COUNTER_ALLOCATED,
203 struct res_common com;
207 enum res_xrcdn_states {
208 RES_XRCD_BUSY = RES_ANY_BUSY,
213 struct res_common com;
217 enum res_fs_rule_states {
218 RES_FS_RULE_BUSY = RES_ANY_BUSY,
219 RES_FS_RULE_ALLOCATED,
223 struct res_common com;
225 /* VF DMFS mbox with port flipped */
227 /* > 0 --> apply mirror when getting into HA mode */
228 /* = 0 --> un-apply mirror when getting out of HA mode */
230 struct list_head mirr_list;
234 static void *res_tracker_lookup(struct rb_root *root, u64 res_id)
236 struct rb_node *node = root->rb_node;
239 struct res_common *res = container_of(node, struct res_common,
242 if (res_id < res->res_id)
243 node = node->rb_left;
244 else if (res_id > res->res_id)
245 node = node->rb_right;
252 static int res_tracker_insert(struct rb_root *root, struct res_common *res)
254 struct rb_node **new = &(root->rb_node), *parent = NULL;
256 /* Figure out where to put new node */
258 struct res_common *this = container_of(*new, struct res_common,
262 if (res->res_id < this->res_id)
263 new = &((*new)->rb_left);
264 else if (res->res_id > this->res_id)
265 new = &((*new)->rb_right);
270 /* Add new node and rebalance tree. */
271 rb_link_node(&res->node, parent, new);
272 rb_insert_color(&res->node, root);
287 static const char *resource_str(enum mlx4_resource rt)
290 case RES_QP: return "RES_QP";
291 case RES_CQ: return "RES_CQ";
292 case RES_SRQ: return "RES_SRQ";
293 case RES_MPT: return "RES_MPT";
294 case RES_MTT: return "RES_MTT";
295 case RES_MAC: return "RES_MAC";
296 case RES_VLAN: return "RES_VLAN";
297 case RES_EQ: return "RES_EQ";
298 case RES_COUNTER: return "RES_COUNTER";
299 case RES_FS_RULE: return "RES_FS_RULE";
300 case RES_XRCD: return "RES_XRCD";
301 default: return "Unknown resource type !!!";
305 static void rem_slave_vlans(struct mlx4_dev *dev, int slave);
306 static inline int mlx4_grant_resource(struct mlx4_dev *dev, int slave,
307 enum mlx4_resource res_type, int count,
310 struct mlx4_priv *priv = mlx4_priv(dev);
311 struct resource_allocator *res_alloc =
312 &priv->mfunc.master.res_tracker.res_alloc[res_type];
314 int allocated, free, reserved, guaranteed, from_free;
317 if (slave > dev->persist->num_vfs)
320 spin_lock(&res_alloc->alloc_lock);
321 allocated = (port > 0) ?
322 res_alloc->allocated[(port - 1) *
323 (dev->persist->num_vfs + 1) + slave] :
324 res_alloc->allocated[slave];
325 free = (port > 0) ? res_alloc->res_port_free[port - 1] :
327 reserved = (port > 0) ? res_alloc->res_port_rsvd[port - 1] :
328 res_alloc->res_reserved;
329 guaranteed = res_alloc->guaranteed[slave];
331 if (allocated + count > res_alloc->quota[slave]) {
332 mlx4_warn(dev, "VF %d port %d res %s: quota exceeded, count %d alloc %d quota %d\n",
333 slave, port, resource_str(res_type), count,
334 allocated, res_alloc->quota[slave]);
338 if (allocated + count <= guaranteed) {
342 /* portion may need to be obtained from free area */
343 if (guaranteed - allocated > 0)
344 from_free = count - (guaranteed - allocated);
348 from_rsvd = count - from_free;
350 if (free - from_free >= reserved)
353 mlx4_warn(dev, "VF %d port %d res %s: free pool empty, free %d from_free %d rsvd %d\n",
354 slave, port, resource_str(res_type), free,
355 from_free, reserved);
359 /* grant the request */
361 res_alloc->allocated[(port - 1) *
362 (dev->persist->num_vfs + 1) + slave] += count;
363 res_alloc->res_port_free[port - 1] -= count;
364 res_alloc->res_port_rsvd[port - 1] -= from_rsvd;
366 res_alloc->allocated[slave] += count;
367 res_alloc->res_free -= count;
368 res_alloc->res_reserved -= from_rsvd;
373 spin_unlock(&res_alloc->alloc_lock);
377 static inline void mlx4_release_resource(struct mlx4_dev *dev, int slave,
378 enum mlx4_resource res_type, int count,
381 struct mlx4_priv *priv = mlx4_priv(dev);
382 struct resource_allocator *res_alloc =
383 &priv->mfunc.master.res_tracker.res_alloc[res_type];
384 int allocated, guaranteed, from_rsvd;
386 if (slave > dev->persist->num_vfs)
389 spin_lock(&res_alloc->alloc_lock);
391 allocated = (port > 0) ?
392 res_alloc->allocated[(port - 1) *
393 (dev->persist->num_vfs + 1) + slave] :
394 res_alloc->allocated[slave];
395 guaranteed = res_alloc->guaranteed[slave];
397 if (allocated - count >= guaranteed) {
400 /* portion may need to be returned to reserved area */
401 if (allocated - guaranteed > 0)
402 from_rsvd = count - (allocated - guaranteed);
408 res_alloc->allocated[(port - 1) *
409 (dev->persist->num_vfs + 1) + slave] -= count;
410 res_alloc->res_port_free[port - 1] += count;
411 res_alloc->res_port_rsvd[port - 1] += from_rsvd;
413 res_alloc->allocated[slave] -= count;
414 res_alloc->res_free += count;
415 res_alloc->res_reserved += from_rsvd;
418 spin_unlock(&res_alloc->alloc_lock);
422 static inline void initialize_res_quotas(struct mlx4_dev *dev,
423 struct resource_allocator *res_alloc,
424 enum mlx4_resource res_type,
425 int vf, int num_instances)
427 res_alloc->guaranteed[vf] = num_instances /
428 (2 * (dev->persist->num_vfs + 1));
429 res_alloc->quota[vf] = (num_instances / 2) + res_alloc->guaranteed[vf];
430 if (vf == mlx4_master_func_num(dev)) {
431 res_alloc->res_free = num_instances;
432 if (res_type == RES_MTT) {
433 /* reserved mtts will be taken out of the PF allocation */
434 res_alloc->res_free += dev->caps.reserved_mtts;
435 res_alloc->guaranteed[vf] += dev->caps.reserved_mtts;
436 res_alloc->quota[vf] += dev->caps.reserved_mtts;
441 void mlx4_init_quotas(struct mlx4_dev *dev)
443 struct mlx4_priv *priv = mlx4_priv(dev);
446 /* quotas for VFs are initialized in mlx4_slave_cap */
447 if (mlx4_is_slave(dev))
450 if (!mlx4_is_mfunc(dev)) {
451 dev->quotas.qp = dev->caps.num_qps - dev->caps.reserved_qps -
452 mlx4_num_reserved_sqps(dev);
453 dev->quotas.cq = dev->caps.num_cqs - dev->caps.reserved_cqs;
454 dev->quotas.srq = dev->caps.num_srqs - dev->caps.reserved_srqs;
455 dev->quotas.mtt = dev->caps.num_mtts - dev->caps.reserved_mtts;
456 dev->quotas.mpt = dev->caps.num_mpts - dev->caps.reserved_mrws;
460 pf = mlx4_master_func_num(dev);
462 priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[pf];
464 priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[pf];
466 priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[pf];
468 priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[pf];
470 priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[pf];
473 static int get_max_gauranteed_vfs_counter(struct mlx4_dev *dev)
475 /* reduce the sink counter */
476 return (dev->caps.max_counters - 1 -
477 (MLX4_PF_COUNTERS_PER_PORT * MLX4_MAX_PORTS))
481 int mlx4_init_resource_tracker(struct mlx4_dev *dev)
483 struct mlx4_priv *priv = mlx4_priv(dev);
486 int max_vfs_guarantee_counter = get_max_gauranteed_vfs_counter(dev);
488 priv->mfunc.master.res_tracker.slave_list =
489 kzalloc(dev->num_slaves * sizeof(struct slave_list),
491 if (!priv->mfunc.master.res_tracker.slave_list)
494 for (i = 0 ; i < dev->num_slaves; i++) {
495 for (t = 0; t < MLX4_NUM_OF_RESOURCE_TYPE; ++t)
496 INIT_LIST_HEAD(&priv->mfunc.master.res_tracker.
497 slave_list[i].res_list[t]);
498 mutex_init(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
501 mlx4_dbg(dev, "Started init_resource_tracker: %ld slaves\n",
503 for (i = 0 ; i < MLX4_NUM_OF_RESOURCE_TYPE; i++)
504 priv->mfunc.master.res_tracker.res_tree[i] = RB_ROOT;
506 for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
507 struct resource_allocator *res_alloc =
508 &priv->mfunc.master.res_tracker.res_alloc[i];
509 res_alloc->quota = kmalloc((dev->persist->num_vfs + 1) *
510 sizeof(int), GFP_KERNEL);
511 res_alloc->guaranteed = kmalloc((dev->persist->num_vfs + 1) *
512 sizeof(int), GFP_KERNEL);
513 if (i == RES_MAC || i == RES_VLAN)
514 res_alloc->allocated = kzalloc(MLX4_MAX_PORTS *
515 (dev->persist->num_vfs
517 sizeof(int), GFP_KERNEL);
519 res_alloc->allocated = kzalloc((dev->persist->
521 sizeof(int), GFP_KERNEL);
522 /* Reduce the sink counter */
523 if (i == RES_COUNTER)
524 res_alloc->res_free = dev->caps.max_counters - 1;
526 if (!res_alloc->quota || !res_alloc->guaranteed ||
527 !res_alloc->allocated)
530 spin_lock_init(&res_alloc->alloc_lock);
531 for (t = 0; t < dev->persist->num_vfs + 1; t++) {
532 struct mlx4_active_ports actv_ports =
533 mlx4_get_active_ports(dev, t);
536 initialize_res_quotas(dev, res_alloc, RES_QP,
537 t, dev->caps.num_qps -
538 dev->caps.reserved_qps -
539 mlx4_num_reserved_sqps(dev));
542 initialize_res_quotas(dev, res_alloc, RES_CQ,
543 t, dev->caps.num_cqs -
544 dev->caps.reserved_cqs);
547 initialize_res_quotas(dev, res_alloc, RES_SRQ,
548 t, dev->caps.num_srqs -
549 dev->caps.reserved_srqs);
552 initialize_res_quotas(dev, res_alloc, RES_MPT,
553 t, dev->caps.num_mpts -
554 dev->caps.reserved_mrws);
557 initialize_res_quotas(dev, res_alloc, RES_MTT,
558 t, dev->caps.num_mtts -
559 dev->caps.reserved_mtts);
562 if (t == mlx4_master_func_num(dev)) {
563 int max_vfs_pport = 0;
564 /* Calculate the max vfs per port for */
566 for (j = 0; j < dev->caps.num_ports;
568 struct mlx4_slaves_pport slaves_pport =
569 mlx4_phys_to_slaves_pport(dev, j + 1);
570 unsigned current_slaves =
571 bitmap_weight(slaves_pport.slaves,
572 dev->caps.num_ports) - 1;
573 if (max_vfs_pport < current_slaves)
577 res_alloc->quota[t] =
580 res_alloc->guaranteed[t] = 2;
581 for (j = 0; j < MLX4_MAX_PORTS; j++)
582 res_alloc->res_port_free[j] =
585 res_alloc->quota[t] = MLX4_MAX_MAC_NUM;
586 res_alloc->guaranteed[t] = 2;
590 if (t == mlx4_master_func_num(dev)) {
591 res_alloc->quota[t] = MLX4_MAX_VLAN_NUM;
592 res_alloc->guaranteed[t] = MLX4_MAX_VLAN_NUM / 2;
593 for (j = 0; j < MLX4_MAX_PORTS; j++)
594 res_alloc->res_port_free[j] =
597 res_alloc->quota[t] = MLX4_MAX_VLAN_NUM / 2;
598 res_alloc->guaranteed[t] = 0;
602 res_alloc->quota[t] = dev->caps.max_counters;
603 if (t == mlx4_master_func_num(dev))
604 res_alloc->guaranteed[t] =
605 MLX4_PF_COUNTERS_PER_PORT *
607 else if (t <= max_vfs_guarantee_counter)
608 res_alloc->guaranteed[t] =
609 MLX4_VF_COUNTERS_PER_PORT *
612 res_alloc->guaranteed[t] = 0;
613 res_alloc->res_free -= res_alloc->guaranteed[t];
618 if (i == RES_MAC || i == RES_VLAN) {
619 for (j = 0; j < dev->caps.num_ports; j++)
620 if (test_bit(j, actv_ports.ports))
621 res_alloc->res_port_rsvd[j] +=
622 res_alloc->guaranteed[t];
624 res_alloc->res_reserved += res_alloc->guaranteed[t];
628 spin_lock_init(&priv->mfunc.master.res_tracker.lock);
632 for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
633 kfree(priv->mfunc.master.res_tracker.res_alloc[i].allocated);
634 priv->mfunc.master.res_tracker.res_alloc[i].allocated = NULL;
635 kfree(priv->mfunc.master.res_tracker.res_alloc[i].guaranteed);
636 priv->mfunc.master.res_tracker.res_alloc[i].guaranteed = NULL;
637 kfree(priv->mfunc.master.res_tracker.res_alloc[i].quota);
638 priv->mfunc.master.res_tracker.res_alloc[i].quota = NULL;
643 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
644 enum mlx4_res_tracker_free_type type)
646 struct mlx4_priv *priv = mlx4_priv(dev);
649 if (priv->mfunc.master.res_tracker.slave_list) {
650 if (type != RES_TR_FREE_STRUCTS_ONLY) {
651 for (i = 0; i < dev->num_slaves; i++) {
652 if (type == RES_TR_FREE_ALL ||
653 dev->caps.function != i)
654 mlx4_delete_all_resources_for_slave(dev, i);
656 /* free master's vlans */
657 i = dev->caps.function;
658 mlx4_reset_roce_gids(dev, i);
659 mutex_lock(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
660 rem_slave_vlans(dev, i);
661 mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
664 if (type != RES_TR_FREE_SLAVES_ONLY) {
665 for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
666 kfree(priv->mfunc.master.res_tracker.res_alloc[i].allocated);
667 priv->mfunc.master.res_tracker.res_alloc[i].allocated = NULL;
668 kfree(priv->mfunc.master.res_tracker.res_alloc[i].guaranteed);
669 priv->mfunc.master.res_tracker.res_alloc[i].guaranteed = NULL;
670 kfree(priv->mfunc.master.res_tracker.res_alloc[i].quota);
671 priv->mfunc.master.res_tracker.res_alloc[i].quota = NULL;
673 kfree(priv->mfunc.master.res_tracker.slave_list);
674 priv->mfunc.master.res_tracker.slave_list = NULL;
679 static void update_pkey_index(struct mlx4_dev *dev, int slave,
680 struct mlx4_cmd_mailbox *inbox)
682 u8 sched = *(u8 *)(inbox->buf + 64);
683 u8 orig_index = *(u8 *)(inbox->buf + 35);
685 struct mlx4_priv *priv = mlx4_priv(dev);
688 port = (sched >> 6 & 1) + 1;
690 new_index = priv->virt2phys_pkey[slave][port - 1][orig_index];
691 *(u8 *)(inbox->buf + 35) = new_index;
694 static void update_gid(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *inbox,
697 struct mlx4_qp_context *qp_ctx = inbox->buf + 8;
698 enum mlx4_qp_optpar optpar = be32_to_cpu(*(__be32 *) inbox->buf);
699 u32 ts = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
702 if (MLX4_QP_ST_UD == ts) {
703 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
704 if (mlx4_is_eth(dev, port))
705 qp_ctx->pri_path.mgid_index =
706 mlx4_get_base_gid_ix(dev, slave, port) | 0x80;
708 qp_ctx->pri_path.mgid_index = slave | 0x80;
710 } else if (MLX4_QP_ST_RC == ts || MLX4_QP_ST_XRC == ts || MLX4_QP_ST_UC == ts) {
711 if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH) {
712 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
713 if (mlx4_is_eth(dev, port)) {
714 qp_ctx->pri_path.mgid_index +=
715 mlx4_get_base_gid_ix(dev, slave, port);
716 qp_ctx->pri_path.mgid_index &= 0x7f;
718 qp_ctx->pri_path.mgid_index = slave & 0x7F;
721 if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) {
722 port = (qp_ctx->alt_path.sched_queue >> 6 & 1) + 1;
723 if (mlx4_is_eth(dev, port)) {
724 qp_ctx->alt_path.mgid_index +=
725 mlx4_get_base_gid_ix(dev, slave, port);
726 qp_ctx->alt_path.mgid_index &= 0x7f;
728 qp_ctx->alt_path.mgid_index = slave & 0x7F;
734 static int handle_counter(struct mlx4_dev *dev, struct mlx4_qp_context *qpc,
737 static int update_vport_qp_param(struct mlx4_dev *dev,
738 struct mlx4_cmd_mailbox *inbox,
741 struct mlx4_qp_context *qpc = inbox->buf + 8;
742 struct mlx4_vport_oper_state *vp_oper;
743 struct mlx4_priv *priv;
747 port = (qpc->pri_path.sched_queue & 0x40) ? 2 : 1;
748 priv = mlx4_priv(dev);
749 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
750 qp_type = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
752 err = handle_counter(dev, qpc, slave, port);
756 if (MLX4_VGT != vp_oper->state.default_vlan) {
757 /* the reserved QPs (special, proxy, tunnel)
758 * do not operate over vlans
760 if (mlx4_is_qp_reserved(dev, qpn))
763 /* force strip vlan by clear vsd, MLX QP refers to Raw Ethernet */
764 if (qp_type == MLX4_QP_ST_UD ||
765 (qp_type == MLX4_QP_ST_MLX && mlx4_is_eth(dev, port))) {
766 if (dev->caps.bmme_flags & MLX4_BMME_FLAG_VSD_INIT2RTR) {
767 *(__be32 *)inbox->buf =
768 cpu_to_be32(be32_to_cpu(*(__be32 *)inbox->buf) |
769 MLX4_QP_OPTPAR_VLAN_STRIPPING);
770 qpc->param3 &= ~cpu_to_be32(MLX4_STRIP_VLAN);
772 struct mlx4_update_qp_params params = {.flags = 0};
774 err = mlx4_update_qp(dev, qpn, MLX4_UPDATE_QP_VSD, ¶ms);
780 /* preserve IF_COUNTER flag */
781 qpc->pri_path.vlan_control &=
782 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
783 if (vp_oper->state.link_state == IFLA_VF_LINK_STATE_DISABLE &&
784 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP) {
785 qpc->pri_path.vlan_control |=
786 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
787 MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED |
788 MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED |
789 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
790 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED |
791 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
792 } else if (0 != vp_oper->state.default_vlan) {
793 qpc->pri_path.vlan_control |=
794 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
795 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
796 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
797 } else { /* priority tagged */
798 qpc->pri_path.vlan_control |=
799 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
800 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
803 qpc->pri_path.fvl_rx |= MLX4_FVL_RX_FORCE_ETH_VLAN;
804 qpc->pri_path.vlan_index = vp_oper->vlan_idx;
805 qpc->pri_path.fl |= MLX4_FL_CV | MLX4_FL_ETH_HIDE_CQE_VLAN;
806 qpc->pri_path.feup |= MLX4_FEUP_FORCE_ETH_UP | MLX4_FVL_FORCE_ETH_VLAN;
807 qpc->pri_path.sched_queue &= 0xC7;
808 qpc->pri_path.sched_queue |= (vp_oper->state.default_qos) << 3;
809 qpc->qos_vport = vp_oper->state.qos_vport;
811 if (vp_oper->state.spoofchk) {
812 qpc->pri_path.feup |= MLX4_FSM_FORCE_ETH_SRC_MAC;
813 qpc->pri_path.grh_mylmc = (0x80 & qpc->pri_path.grh_mylmc) + vp_oper->mac_idx;
819 static int mpt_mask(struct mlx4_dev *dev)
821 return dev->caps.num_mpts - 1;
824 static void *find_res(struct mlx4_dev *dev, u64 res_id,
825 enum mlx4_resource type)
827 struct mlx4_priv *priv = mlx4_priv(dev);
829 return res_tracker_lookup(&priv->mfunc.master.res_tracker.res_tree[type],
833 static int get_res(struct mlx4_dev *dev, int slave, u64 res_id,
834 enum mlx4_resource type,
837 struct res_common *r;
840 spin_lock_irq(mlx4_tlock(dev));
841 r = find_res(dev, res_id, type);
847 if (r->state == RES_ANY_BUSY) {
852 if (r->owner != slave) {
857 r->from_state = r->state;
858 r->state = RES_ANY_BUSY;
861 *((struct res_common **)res) = r;
864 spin_unlock_irq(mlx4_tlock(dev));
868 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
869 enum mlx4_resource type,
870 u64 res_id, int *slave)
873 struct res_common *r;
879 spin_lock(mlx4_tlock(dev));
881 r = find_res(dev, id, type);
886 spin_unlock(mlx4_tlock(dev));
891 static void put_res(struct mlx4_dev *dev, int slave, u64 res_id,
892 enum mlx4_resource type)
894 struct res_common *r;
896 spin_lock_irq(mlx4_tlock(dev));
897 r = find_res(dev, res_id, type);
899 r->state = r->from_state;
900 spin_unlock_irq(mlx4_tlock(dev));
903 static int counter_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
904 u64 in_param, u64 *out_param, int port);
906 static int handle_existing_counter(struct mlx4_dev *dev, u8 slave, int port,
909 struct res_common *r;
910 struct res_counter *counter;
913 if (counter_index == MLX4_SINK_COUNTER_INDEX(dev))
916 spin_lock_irq(mlx4_tlock(dev));
917 r = find_res(dev, counter_index, RES_COUNTER);
918 if (!r || r->owner != slave) {
921 counter = container_of(r, struct res_counter, com);
923 counter->port = port;
926 spin_unlock_irq(mlx4_tlock(dev));
930 static int handle_unexisting_counter(struct mlx4_dev *dev,
931 struct mlx4_qp_context *qpc, u8 slave,
934 struct mlx4_priv *priv = mlx4_priv(dev);
935 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
936 struct res_common *tmp;
937 struct res_counter *counter;
938 u64 counter_idx = MLX4_SINK_COUNTER_INDEX(dev);
941 spin_lock_irq(mlx4_tlock(dev));
942 list_for_each_entry(tmp,
943 &tracker->slave_list[slave].res_list[RES_COUNTER],
945 counter = container_of(tmp, struct res_counter, com);
946 if (port == counter->port) {
947 qpc->pri_path.counter_index = counter->com.res_id;
948 spin_unlock_irq(mlx4_tlock(dev));
952 spin_unlock_irq(mlx4_tlock(dev));
954 /* No existing counter, need to allocate a new counter */
955 err = counter_alloc_res(dev, slave, RES_OP_RESERVE, 0, 0, &counter_idx,
957 if (err == -ENOENT) {
959 } else if (err && err != -ENOSPC) {
960 mlx4_err(dev, "%s: failed to create new counter for slave %d err %d\n",
961 __func__, slave, err);
963 qpc->pri_path.counter_index = counter_idx;
964 mlx4_dbg(dev, "%s: alloc new counter for slave %d index %d\n",
965 __func__, slave, qpc->pri_path.counter_index);
972 static int handle_counter(struct mlx4_dev *dev, struct mlx4_qp_context *qpc,
975 if (qpc->pri_path.counter_index != MLX4_SINK_COUNTER_INDEX(dev))
976 return handle_existing_counter(dev, slave, port,
977 qpc->pri_path.counter_index);
979 return handle_unexisting_counter(dev, qpc, slave, port);
982 static struct res_common *alloc_qp_tr(int id)
986 ret = kzalloc(sizeof *ret, GFP_KERNEL);
990 ret->com.res_id = id;
991 ret->com.state = RES_QP_RESERVED;
993 INIT_LIST_HEAD(&ret->mcg_list);
994 spin_lock_init(&ret->mcg_spl);
995 atomic_set(&ret->ref_count, 0);
1000 static struct res_common *alloc_mtt_tr(int id, int order)
1002 struct res_mtt *ret;
1004 ret = kzalloc(sizeof *ret, GFP_KERNEL);
1008 ret->com.res_id = id;
1010 ret->com.state = RES_MTT_ALLOCATED;
1011 atomic_set(&ret->ref_count, 0);
1016 static struct res_common *alloc_mpt_tr(int id, int key)
1018 struct res_mpt *ret;
1020 ret = kzalloc(sizeof *ret, GFP_KERNEL);
1024 ret->com.res_id = id;
1025 ret->com.state = RES_MPT_RESERVED;
1031 static struct res_common *alloc_eq_tr(int id)
1035 ret = kzalloc(sizeof *ret, GFP_KERNEL);
1039 ret->com.res_id = id;
1040 ret->com.state = RES_EQ_RESERVED;
1045 static struct res_common *alloc_cq_tr(int id)
1049 ret = kzalloc(sizeof *ret, GFP_KERNEL);
1053 ret->com.res_id = id;
1054 ret->com.state = RES_CQ_ALLOCATED;
1055 atomic_set(&ret->ref_count, 0);
1060 static struct res_common *alloc_srq_tr(int id)
1062 struct res_srq *ret;
1064 ret = kzalloc(sizeof *ret, GFP_KERNEL);
1068 ret->com.res_id = id;
1069 ret->com.state = RES_SRQ_ALLOCATED;
1070 atomic_set(&ret->ref_count, 0);
1075 static struct res_common *alloc_counter_tr(int id, int port)
1077 struct res_counter *ret;
1079 ret = kzalloc(sizeof *ret, GFP_KERNEL);
1083 ret->com.res_id = id;
1084 ret->com.state = RES_COUNTER_ALLOCATED;
1090 static struct res_common *alloc_xrcdn_tr(int id)
1092 struct res_xrcdn *ret;
1094 ret = kzalloc(sizeof *ret, GFP_KERNEL);
1098 ret->com.res_id = id;
1099 ret->com.state = RES_XRCD_ALLOCATED;
1104 static struct res_common *alloc_fs_rule_tr(u64 id, int qpn)
1106 struct res_fs_rule *ret;
1108 ret = kzalloc(sizeof *ret, GFP_KERNEL);
1112 ret->com.res_id = id;
1113 ret->com.state = RES_FS_RULE_ALLOCATED;
1118 static struct res_common *alloc_tr(u64 id, enum mlx4_resource type, int slave,
1121 struct res_common *ret;
1125 ret = alloc_qp_tr(id);
1128 ret = alloc_mpt_tr(id, extra);
1131 ret = alloc_mtt_tr(id, extra);
1134 ret = alloc_eq_tr(id);
1137 ret = alloc_cq_tr(id);
1140 ret = alloc_srq_tr(id);
1143 pr_err("implementation missing\n");
1146 ret = alloc_counter_tr(id, extra);
1149 ret = alloc_xrcdn_tr(id);
1152 ret = alloc_fs_rule_tr(id, extra);
1163 int mlx4_calc_vf_counters(struct mlx4_dev *dev, int slave, int port,
1164 struct mlx4_counter *data)
1166 struct mlx4_priv *priv = mlx4_priv(dev);
1167 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1168 struct res_common *tmp;
1169 struct res_counter *counter;
1173 memset(data, 0, sizeof(*data));
1175 counters_arr = kmalloc_array(dev->caps.max_counters,
1176 sizeof(*counters_arr), GFP_KERNEL);
1180 spin_lock_irq(mlx4_tlock(dev));
1181 list_for_each_entry(tmp,
1182 &tracker->slave_list[slave].res_list[RES_COUNTER],
1184 counter = container_of(tmp, struct res_counter, com);
1185 if (counter->port == port) {
1186 counters_arr[i] = (int)tmp->res_id;
1190 spin_unlock_irq(mlx4_tlock(dev));
1191 counters_arr[i] = -1;
1195 while (counters_arr[i] != -1) {
1196 err = mlx4_get_counter_stats(dev, counters_arr[i], data,
1199 memset(data, 0, sizeof(*data));
1206 kfree(counters_arr);
1210 static int add_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
1211 enum mlx4_resource type, int extra)
1215 struct mlx4_priv *priv = mlx4_priv(dev);
1216 struct res_common **res_arr;
1217 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1218 struct rb_root *root = &tracker->res_tree[type];
1220 res_arr = kzalloc(count * sizeof *res_arr, GFP_KERNEL);
1224 for (i = 0; i < count; ++i) {
1225 res_arr[i] = alloc_tr(base + i, type, slave, extra);
1227 for (--i; i >= 0; --i)
1235 spin_lock_irq(mlx4_tlock(dev));
1236 for (i = 0; i < count; ++i) {
1237 if (find_res(dev, base + i, type)) {
1241 err = res_tracker_insert(root, res_arr[i]);
1244 list_add_tail(&res_arr[i]->list,
1245 &tracker->slave_list[slave].res_list[type]);
1247 spin_unlock_irq(mlx4_tlock(dev));
1253 for (--i; i >= 0; --i) {
1254 rb_erase(&res_arr[i]->node, root);
1255 list_del_init(&res_arr[i]->list);
1258 spin_unlock_irq(mlx4_tlock(dev));
1260 for (i = 0; i < count; ++i)
1268 static int remove_qp_ok(struct res_qp *res)
1270 if (res->com.state == RES_QP_BUSY || atomic_read(&res->ref_count) ||
1271 !list_empty(&res->mcg_list)) {
1272 pr_err("resource tracker: fail to remove qp, state %d, ref_count %d\n",
1273 res->com.state, atomic_read(&res->ref_count));
1275 } else if (res->com.state != RES_QP_RESERVED) {
1282 static int remove_mtt_ok(struct res_mtt *res, int order)
1284 if (res->com.state == RES_MTT_BUSY ||
1285 atomic_read(&res->ref_count)) {
1286 pr_devel("%s-%d: state %s, ref_count %d\n",
1288 mtt_states_str(res->com.state),
1289 atomic_read(&res->ref_count));
1291 } else if (res->com.state != RES_MTT_ALLOCATED)
1293 else if (res->order != order)
1299 static int remove_mpt_ok(struct res_mpt *res)
1301 if (res->com.state == RES_MPT_BUSY)
1303 else if (res->com.state != RES_MPT_RESERVED)
1309 static int remove_eq_ok(struct res_eq *res)
1311 if (res->com.state == RES_MPT_BUSY)
1313 else if (res->com.state != RES_MPT_RESERVED)
1319 static int remove_counter_ok(struct res_counter *res)
1321 if (res->com.state == RES_COUNTER_BUSY)
1323 else if (res->com.state != RES_COUNTER_ALLOCATED)
1329 static int remove_xrcdn_ok(struct res_xrcdn *res)
1331 if (res->com.state == RES_XRCD_BUSY)
1333 else if (res->com.state != RES_XRCD_ALLOCATED)
1339 static int remove_fs_rule_ok(struct res_fs_rule *res)
1341 if (res->com.state == RES_FS_RULE_BUSY)
1343 else if (res->com.state != RES_FS_RULE_ALLOCATED)
1349 static int remove_cq_ok(struct res_cq *res)
1351 if (res->com.state == RES_CQ_BUSY)
1353 else if (res->com.state != RES_CQ_ALLOCATED)
1359 static int remove_srq_ok(struct res_srq *res)
1361 if (res->com.state == RES_SRQ_BUSY)
1363 else if (res->com.state != RES_SRQ_ALLOCATED)
1369 static int remove_ok(struct res_common *res, enum mlx4_resource type, int extra)
1373 return remove_qp_ok((struct res_qp *)res);
1375 return remove_cq_ok((struct res_cq *)res);
1377 return remove_srq_ok((struct res_srq *)res);
1379 return remove_mpt_ok((struct res_mpt *)res);
1381 return remove_mtt_ok((struct res_mtt *)res, extra);
1385 return remove_eq_ok((struct res_eq *)res);
1387 return remove_counter_ok((struct res_counter *)res);
1389 return remove_xrcdn_ok((struct res_xrcdn *)res);
1391 return remove_fs_rule_ok((struct res_fs_rule *)res);
1397 static int rem_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
1398 enum mlx4_resource type, int extra)
1402 struct mlx4_priv *priv = mlx4_priv(dev);
1403 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1404 struct res_common *r;
1406 spin_lock_irq(mlx4_tlock(dev));
1407 for (i = base; i < base + count; ++i) {
1408 r = res_tracker_lookup(&tracker->res_tree[type], i);
1413 if (r->owner != slave) {
1417 err = remove_ok(r, type, extra);
1422 for (i = base; i < base + count; ++i) {
1423 r = res_tracker_lookup(&tracker->res_tree[type], i);
1424 rb_erase(&r->node, &tracker->res_tree[type]);
1431 spin_unlock_irq(mlx4_tlock(dev));
1436 static int qp_res_start_move_to(struct mlx4_dev *dev, int slave, int qpn,
1437 enum res_qp_states state, struct res_qp **qp,
1440 struct mlx4_priv *priv = mlx4_priv(dev);
1441 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1445 spin_lock_irq(mlx4_tlock(dev));
1446 r = res_tracker_lookup(&tracker->res_tree[RES_QP], qpn);
1449 else if (r->com.owner != slave)
1454 mlx4_dbg(dev, "%s: failed RES_QP, 0x%llx\n",
1455 __func__, r->com.res_id);
1459 case RES_QP_RESERVED:
1460 if (r->com.state == RES_QP_MAPPED && !alloc)
1463 mlx4_dbg(dev, "failed RES_QP, 0x%llx\n", r->com.res_id);
1468 if ((r->com.state == RES_QP_RESERVED && alloc) ||
1469 r->com.state == RES_QP_HW)
1472 mlx4_dbg(dev, "failed RES_QP, 0x%llx\n",
1480 if (r->com.state != RES_QP_MAPPED)
1488 r->com.from_state = r->com.state;
1489 r->com.to_state = state;
1490 r->com.state = RES_QP_BUSY;
1496 spin_unlock_irq(mlx4_tlock(dev));
1501 static int mr_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
1502 enum res_mpt_states state, struct res_mpt **mpt)
1504 struct mlx4_priv *priv = mlx4_priv(dev);
1505 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1509 spin_lock_irq(mlx4_tlock(dev));
1510 r = res_tracker_lookup(&tracker->res_tree[RES_MPT], index);
1513 else if (r->com.owner != slave)
1521 case RES_MPT_RESERVED:
1522 if (r->com.state != RES_MPT_MAPPED)
1526 case RES_MPT_MAPPED:
1527 if (r->com.state != RES_MPT_RESERVED &&
1528 r->com.state != RES_MPT_HW)
1533 if (r->com.state != RES_MPT_MAPPED)
1541 r->com.from_state = r->com.state;
1542 r->com.to_state = state;
1543 r->com.state = RES_MPT_BUSY;
1549 spin_unlock_irq(mlx4_tlock(dev));
1554 static int eq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
1555 enum res_eq_states state, struct res_eq **eq)
1557 struct mlx4_priv *priv = mlx4_priv(dev);
1558 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1562 spin_lock_irq(mlx4_tlock(dev));
1563 r = res_tracker_lookup(&tracker->res_tree[RES_EQ], index);
1566 else if (r->com.owner != slave)
1574 case RES_EQ_RESERVED:
1575 if (r->com.state != RES_EQ_HW)
1580 if (r->com.state != RES_EQ_RESERVED)
1589 r->com.from_state = r->com.state;
1590 r->com.to_state = state;
1591 r->com.state = RES_EQ_BUSY;
1597 spin_unlock_irq(mlx4_tlock(dev));
1602 static int cq_res_start_move_to(struct mlx4_dev *dev, int slave, int cqn,
1603 enum res_cq_states state, struct res_cq **cq)
1605 struct mlx4_priv *priv = mlx4_priv(dev);
1606 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1610 spin_lock_irq(mlx4_tlock(dev));
1611 r = res_tracker_lookup(&tracker->res_tree[RES_CQ], cqn);
1614 } else if (r->com.owner != slave) {
1616 } else if (state == RES_CQ_ALLOCATED) {
1617 if (r->com.state != RES_CQ_HW)
1619 else if (atomic_read(&r->ref_count))
1623 } else if (state != RES_CQ_HW || r->com.state != RES_CQ_ALLOCATED) {
1630 r->com.from_state = r->com.state;
1631 r->com.to_state = state;
1632 r->com.state = RES_CQ_BUSY;
1637 spin_unlock_irq(mlx4_tlock(dev));
1642 static int srq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
1643 enum res_srq_states state, struct res_srq **srq)
1645 struct mlx4_priv *priv = mlx4_priv(dev);
1646 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1650 spin_lock_irq(mlx4_tlock(dev));
1651 r = res_tracker_lookup(&tracker->res_tree[RES_SRQ], index);
1654 } else if (r->com.owner != slave) {
1656 } else if (state == RES_SRQ_ALLOCATED) {
1657 if (r->com.state != RES_SRQ_HW)
1659 else if (atomic_read(&r->ref_count))
1661 } else if (state != RES_SRQ_HW || r->com.state != RES_SRQ_ALLOCATED) {
1666 r->com.from_state = r->com.state;
1667 r->com.to_state = state;
1668 r->com.state = RES_SRQ_BUSY;
1673 spin_unlock_irq(mlx4_tlock(dev));
1678 static void res_abort_move(struct mlx4_dev *dev, int slave,
1679 enum mlx4_resource type, int id)
1681 struct mlx4_priv *priv = mlx4_priv(dev);
1682 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1683 struct res_common *r;
1685 spin_lock_irq(mlx4_tlock(dev));
1686 r = res_tracker_lookup(&tracker->res_tree[type], id);
1687 if (r && (r->owner == slave))
1688 r->state = r->from_state;
1689 spin_unlock_irq(mlx4_tlock(dev));
1692 static void res_end_move(struct mlx4_dev *dev, int slave,
1693 enum mlx4_resource type, int id)
1695 struct mlx4_priv *priv = mlx4_priv(dev);
1696 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1697 struct res_common *r;
1699 spin_lock_irq(mlx4_tlock(dev));
1700 r = res_tracker_lookup(&tracker->res_tree[type], id);
1701 if (r && (r->owner == slave))
1702 r->state = r->to_state;
1703 spin_unlock_irq(mlx4_tlock(dev));
1706 static int valid_reserved(struct mlx4_dev *dev, int slave, int qpn)
1708 return mlx4_is_qp_reserved(dev, qpn) &&
1709 (mlx4_is_master(dev) || mlx4_is_guest_proxy(dev, slave, qpn));
1712 static int fw_reserved(struct mlx4_dev *dev, int qpn)
1714 return qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
1717 static int qp_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1718 u64 in_param, u64 *out_param)
1728 case RES_OP_RESERVE:
1729 count = get_param_l(&in_param) & 0xffffff;
1730 /* Turn off all unsupported QP allocation flags that the
1731 * slave tries to set.
1733 flags = (get_param_l(&in_param) >> 24) & dev->caps.alloc_res_qp_mask;
1734 align = get_param_h(&in_param);
1735 err = mlx4_grant_resource(dev, slave, RES_QP, count, 0);
1739 err = __mlx4_qp_reserve_range(dev, count, align, &base, flags);
1741 mlx4_release_resource(dev, slave, RES_QP, count, 0);
1745 err = add_res_range(dev, slave, base, count, RES_QP, 0);
1747 mlx4_release_resource(dev, slave, RES_QP, count, 0);
1748 __mlx4_qp_release_range(dev, base, count);
1751 set_param_l(out_param, base);
1753 case RES_OP_MAP_ICM:
1754 qpn = get_param_l(&in_param) & 0x7fffff;
1755 if (valid_reserved(dev, slave, qpn)) {
1756 err = add_res_range(dev, slave, qpn, 1, RES_QP, 0);
1761 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED,
1766 if (!fw_reserved(dev, qpn)) {
1767 err = __mlx4_qp_alloc_icm(dev, qpn, GFP_KERNEL);
1769 res_abort_move(dev, slave, RES_QP, qpn);
1774 res_end_move(dev, slave, RES_QP, qpn);
1784 static int mtt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1785 u64 in_param, u64 *out_param)
1791 if (op != RES_OP_RESERVE_AND_MAP)
1794 order = get_param_l(&in_param);
1796 err = mlx4_grant_resource(dev, slave, RES_MTT, 1 << order, 0);
1800 base = __mlx4_alloc_mtt_range(dev, order);
1802 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
1806 err = add_res_range(dev, slave, base, 1, RES_MTT, order);
1808 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
1809 __mlx4_free_mtt_range(dev, base, order);
1811 set_param_l(out_param, base);
1817 static int mpt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1818 u64 in_param, u64 *out_param)
1823 struct res_mpt *mpt;
1826 case RES_OP_RESERVE:
1827 err = mlx4_grant_resource(dev, slave, RES_MPT, 1, 0);
1831 index = __mlx4_mpt_reserve(dev);
1833 mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
1836 id = index & mpt_mask(dev);
1838 err = add_res_range(dev, slave, id, 1, RES_MPT, index);
1840 mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
1841 __mlx4_mpt_release(dev, index);
1844 set_param_l(out_param, index);
1846 case RES_OP_MAP_ICM:
1847 index = get_param_l(&in_param);
1848 id = index & mpt_mask(dev);
1849 err = mr_res_start_move_to(dev, slave, id,
1850 RES_MPT_MAPPED, &mpt);
1854 err = __mlx4_mpt_alloc_icm(dev, mpt->key, GFP_KERNEL);
1856 res_abort_move(dev, slave, RES_MPT, id);
1860 res_end_move(dev, slave, RES_MPT, id);
1866 static int cq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1867 u64 in_param, u64 *out_param)
1873 case RES_OP_RESERVE_AND_MAP:
1874 err = mlx4_grant_resource(dev, slave, RES_CQ, 1, 0);
1878 err = __mlx4_cq_alloc_icm(dev, &cqn);
1880 mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
1884 err = add_res_range(dev, slave, cqn, 1, RES_CQ, 0);
1886 mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
1887 __mlx4_cq_free_icm(dev, cqn);
1891 set_param_l(out_param, cqn);
1901 static int srq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1902 u64 in_param, u64 *out_param)
1908 case RES_OP_RESERVE_AND_MAP:
1909 err = mlx4_grant_resource(dev, slave, RES_SRQ, 1, 0);
1913 err = __mlx4_srq_alloc_icm(dev, &srqn);
1915 mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
1919 err = add_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
1921 mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
1922 __mlx4_srq_free_icm(dev, srqn);
1926 set_param_l(out_param, srqn);
1936 static int mac_find_smac_ix_in_slave(struct mlx4_dev *dev, int slave, int port,
1937 u8 smac_index, u64 *mac)
1939 struct mlx4_priv *priv = mlx4_priv(dev);
1940 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1941 struct list_head *mac_list =
1942 &tracker->slave_list[slave].res_list[RES_MAC];
1943 struct mac_res *res, *tmp;
1945 list_for_each_entry_safe(res, tmp, mac_list, list) {
1946 if (res->smac_index == smac_index && res->port == (u8) port) {
1954 static int mac_add_to_slave(struct mlx4_dev *dev, int slave, u64 mac, int port, u8 smac_index)
1956 struct mlx4_priv *priv = mlx4_priv(dev);
1957 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1958 struct list_head *mac_list =
1959 &tracker->slave_list[slave].res_list[RES_MAC];
1960 struct mac_res *res, *tmp;
1962 list_for_each_entry_safe(res, tmp, mac_list, list) {
1963 if (res->mac == mac && res->port == (u8) port) {
1964 /* mac found. update ref count */
1970 if (mlx4_grant_resource(dev, slave, RES_MAC, 1, port))
1972 res = kzalloc(sizeof *res, GFP_KERNEL);
1974 mlx4_release_resource(dev, slave, RES_MAC, 1, port);
1978 res->port = (u8) port;
1979 res->smac_index = smac_index;
1981 list_add_tail(&res->list,
1982 &tracker->slave_list[slave].res_list[RES_MAC]);
1986 static void mac_del_from_slave(struct mlx4_dev *dev, int slave, u64 mac,
1989 struct mlx4_priv *priv = mlx4_priv(dev);
1990 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1991 struct list_head *mac_list =
1992 &tracker->slave_list[slave].res_list[RES_MAC];
1993 struct mac_res *res, *tmp;
1995 list_for_each_entry_safe(res, tmp, mac_list, list) {
1996 if (res->mac == mac && res->port == (u8) port) {
1997 if (!--res->ref_count) {
1998 list_del(&res->list);
1999 mlx4_release_resource(dev, slave, RES_MAC, 1, port);
2007 static void rem_slave_macs(struct mlx4_dev *dev, int slave)
2009 struct mlx4_priv *priv = mlx4_priv(dev);
2010 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2011 struct list_head *mac_list =
2012 &tracker->slave_list[slave].res_list[RES_MAC];
2013 struct mac_res *res, *tmp;
2016 list_for_each_entry_safe(res, tmp, mac_list, list) {
2017 list_del(&res->list);
2018 /* dereference the mac the num times the slave referenced it */
2019 for (i = 0; i < res->ref_count; i++)
2020 __mlx4_unregister_mac(dev, res->port, res->mac);
2021 mlx4_release_resource(dev, slave, RES_MAC, 1, res->port);
2026 static int mac_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2027 u64 in_param, u64 *out_param, int in_port)
2034 if (op != RES_OP_RESERVE_AND_MAP)
2037 port = !in_port ? get_param_l(out_param) : in_port;
2038 port = mlx4_slave_convert_port(
2045 err = __mlx4_register_mac(dev, port, mac);
2048 set_param_l(out_param, err);
2053 err = mac_add_to_slave(dev, slave, mac, port, smac_index);
2055 __mlx4_unregister_mac(dev, port, mac);
2060 static int vlan_add_to_slave(struct mlx4_dev *dev, int slave, u16 vlan,
2061 int port, int vlan_index)
2063 struct mlx4_priv *priv = mlx4_priv(dev);
2064 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2065 struct list_head *vlan_list =
2066 &tracker->slave_list[slave].res_list[RES_VLAN];
2067 struct vlan_res *res, *tmp;
2069 list_for_each_entry_safe(res, tmp, vlan_list, list) {
2070 if (res->vlan == vlan && res->port == (u8) port) {
2071 /* vlan found. update ref count */
2077 if (mlx4_grant_resource(dev, slave, RES_VLAN, 1, port))
2079 res = kzalloc(sizeof(*res), GFP_KERNEL);
2081 mlx4_release_resource(dev, slave, RES_VLAN, 1, port);
2085 res->port = (u8) port;
2086 res->vlan_index = vlan_index;
2088 list_add_tail(&res->list,
2089 &tracker->slave_list[slave].res_list[RES_VLAN]);
2094 static void vlan_del_from_slave(struct mlx4_dev *dev, int slave, u16 vlan,
2097 struct mlx4_priv *priv = mlx4_priv(dev);
2098 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2099 struct list_head *vlan_list =
2100 &tracker->slave_list[slave].res_list[RES_VLAN];
2101 struct vlan_res *res, *tmp;
2103 list_for_each_entry_safe(res, tmp, vlan_list, list) {
2104 if (res->vlan == vlan && res->port == (u8) port) {
2105 if (!--res->ref_count) {
2106 list_del(&res->list);
2107 mlx4_release_resource(dev, slave, RES_VLAN,
2116 static void rem_slave_vlans(struct mlx4_dev *dev, int slave)
2118 struct mlx4_priv *priv = mlx4_priv(dev);
2119 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2120 struct list_head *vlan_list =
2121 &tracker->slave_list[slave].res_list[RES_VLAN];
2122 struct vlan_res *res, *tmp;
2125 list_for_each_entry_safe(res, tmp, vlan_list, list) {
2126 list_del(&res->list);
2127 /* dereference the vlan the num times the slave referenced it */
2128 for (i = 0; i < res->ref_count; i++)
2129 __mlx4_unregister_vlan(dev, res->port, res->vlan);
2130 mlx4_release_resource(dev, slave, RES_VLAN, 1, res->port);
2135 static int vlan_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2136 u64 in_param, u64 *out_param, int in_port)
2138 struct mlx4_priv *priv = mlx4_priv(dev);
2139 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
2145 port = !in_port ? get_param_l(out_param) : in_port;
2147 if (!port || op != RES_OP_RESERVE_AND_MAP)
2150 port = mlx4_slave_convert_port(
2155 /* upstream kernels had NOP for reg/unreg vlan. Continue this. */
2156 if (!in_port && port > 0 && port <= dev->caps.num_ports) {
2157 slave_state[slave].old_vlan_api = true;
2161 vlan = (u16) in_param;
2163 err = __mlx4_register_vlan(dev, port, vlan, &vlan_index);
2165 set_param_l(out_param, (u32) vlan_index);
2166 err = vlan_add_to_slave(dev, slave, vlan, port, vlan_index);
2168 __mlx4_unregister_vlan(dev, port, vlan);
2173 static int counter_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2174 u64 in_param, u64 *out_param, int port)
2179 if (op != RES_OP_RESERVE)
2182 err = mlx4_grant_resource(dev, slave, RES_COUNTER, 1, 0);
2186 err = __mlx4_counter_alloc(dev, &index);
2188 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
2192 err = add_res_range(dev, slave, index, 1, RES_COUNTER, port);
2194 __mlx4_counter_free(dev, index);
2195 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
2197 set_param_l(out_param, index);
2203 static int xrcdn_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2204 u64 in_param, u64 *out_param)
2209 if (op != RES_OP_RESERVE)
2212 err = __mlx4_xrcd_alloc(dev, &xrcdn);
2216 err = add_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
2218 __mlx4_xrcd_free(dev, xrcdn);
2220 set_param_l(out_param, xrcdn);
2225 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
2226 struct mlx4_vhcr *vhcr,
2227 struct mlx4_cmd_mailbox *inbox,
2228 struct mlx4_cmd_mailbox *outbox,
2229 struct mlx4_cmd_info *cmd)
2232 int alop = vhcr->op_modifier;
2234 switch (vhcr->in_modifier & 0xFF) {
2236 err = qp_alloc_res(dev, slave, vhcr->op_modifier, alop,
2237 vhcr->in_param, &vhcr->out_param);
2241 err = mtt_alloc_res(dev, slave, vhcr->op_modifier, alop,
2242 vhcr->in_param, &vhcr->out_param);
2246 err = mpt_alloc_res(dev, slave, vhcr->op_modifier, alop,
2247 vhcr->in_param, &vhcr->out_param);
2251 err = cq_alloc_res(dev, slave, vhcr->op_modifier, alop,
2252 vhcr->in_param, &vhcr->out_param);
2256 err = srq_alloc_res(dev, slave, vhcr->op_modifier, alop,
2257 vhcr->in_param, &vhcr->out_param);
2261 err = mac_alloc_res(dev, slave, vhcr->op_modifier, alop,
2262 vhcr->in_param, &vhcr->out_param,
2263 (vhcr->in_modifier >> 8) & 0xFF);
2267 err = vlan_alloc_res(dev, slave, vhcr->op_modifier, alop,
2268 vhcr->in_param, &vhcr->out_param,
2269 (vhcr->in_modifier >> 8) & 0xFF);
2273 err = counter_alloc_res(dev, slave, vhcr->op_modifier, alop,
2274 vhcr->in_param, &vhcr->out_param, 0);
2278 err = xrcdn_alloc_res(dev, slave, vhcr->op_modifier, alop,
2279 vhcr->in_param, &vhcr->out_param);
2290 static int qp_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2299 case RES_OP_RESERVE:
2300 base = get_param_l(&in_param) & 0x7fffff;
2301 count = get_param_h(&in_param);
2302 err = rem_res_range(dev, slave, base, count, RES_QP, 0);
2305 mlx4_release_resource(dev, slave, RES_QP, count, 0);
2306 __mlx4_qp_release_range(dev, base, count);
2308 case RES_OP_MAP_ICM:
2309 qpn = get_param_l(&in_param) & 0x7fffff;
2310 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_RESERVED,
2315 if (!fw_reserved(dev, qpn))
2316 __mlx4_qp_free_icm(dev, qpn);
2318 res_end_move(dev, slave, RES_QP, qpn);
2320 if (valid_reserved(dev, slave, qpn))
2321 err = rem_res_range(dev, slave, qpn, 1, RES_QP, 0);
2330 static int mtt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2331 u64 in_param, u64 *out_param)
2337 if (op != RES_OP_RESERVE_AND_MAP)
2340 base = get_param_l(&in_param);
2341 order = get_param_h(&in_param);
2342 err = rem_res_range(dev, slave, base, 1, RES_MTT, order);
2344 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
2345 __mlx4_free_mtt_range(dev, base, order);
2350 static int mpt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2356 struct res_mpt *mpt;
2359 case RES_OP_RESERVE:
2360 index = get_param_l(&in_param);
2361 id = index & mpt_mask(dev);
2362 err = get_res(dev, slave, id, RES_MPT, &mpt);
2366 put_res(dev, slave, id, RES_MPT);
2368 err = rem_res_range(dev, slave, id, 1, RES_MPT, 0);
2371 mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
2372 __mlx4_mpt_release(dev, index);
2374 case RES_OP_MAP_ICM:
2375 index = get_param_l(&in_param);
2376 id = index & mpt_mask(dev);
2377 err = mr_res_start_move_to(dev, slave, id,
2378 RES_MPT_RESERVED, &mpt);
2382 __mlx4_mpt_free_icm(dev, mpt->key);
2383 res_end_move(dev, slave, RES_MPT, id);
2392 static int cq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2393 u64 in_param, u64 *out_param)
2399 case RES_OP_RESERVE_AND_MAP:
2400 cqn = get_param_l(&in_param);
2401 err = rem_res_range(dev, slave, cqn, 1, RES_CQ, 0);
2405 mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
2406 __mlx4_cq_free_icm(dev, cqn);
2417 static int srq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2418 u64 in_param, u64 *out_param)
2424 case RES_OP_RESERVE_AND_MAP:
2425 srqn = get_param_l(&in_param);
2426 err = rem_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
2430 mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
2431 __mlx4_srq_free_icm(dev, srqn);
2442 static int mac_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2443 u64 in_param, u64 *out_param, int in_port)
2449 case RES_OP_RESERVE_AND_MAP:
2450 port = !in_port ? get_param_l(out_param) : in_port;
2451 port = mlx4_slave_convert_port(
2456 mac_del_from_slave(dev, slave, in_param, port);
2457 __mlx4_unregister_mac(dev, port, in_param);
2468 static int vlan_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2469 u64 in_param, u64 *out_param, int port)
2471 struct mlx4_priv *priv = mlx4_priv(dev);
2472 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
2475 port = mlx4_slave_convert_port(
2481 case RES_OP_RESERVE_AND_MAP:
2482 if (slave_state[slave].old_vlan_api)
2486 vlan_del_from_slave(dev, slave, in_param, port);
2487 __mlx4_unregister_vlan(dev, port, in_param);
2497 static int counter_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2498 u64 in_param, u64 *out_param)
2503 if (op != RES_OP_RESERVE)
2506 index = get_param_l(&in_param);
2507 if (index == MLX4_SINK_COUNTER_INDEX(dev))
2510 err = rem_res_range(dev, slave, index, 1, RES_COUNTER, 0);
2514 __mlx4_counter_free(dev, index);
2515 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
2520 static int xrcdn_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2521 u64 in_param, u64 *out_param)
2526 if (op != RES_OP_RESERVE)
2529 xrcdn = get_param_l(&in_param);
2530 err = rem_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
2534 __mlx4_xrcd_free(dev, xrcdn);
2539 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
2540 struct mlx4_vhcr *vhcr,
2541 struct mlx4_cmd_mailbox *inbox,
2542 struct mlx4_cmd_mailbox *outbox,
2543 struct mlx4_cmd_info *cmd)
2546 int alop = vhcr->op_modifier;
2548 switch (vhcr->in_modifier & 0xFF) {
2550 err = qp_free_res(dev, slave, vhcr->op_modifier, alop,
2555 err = mtt_free_res(dev, slave, vhcr->op_modifier, alop,
2556 vhcr->in_param, &vhcr->out_param);
2560 err = mpt_free_res(dev, slave, vhcr->op_modifier, alop,
2565 err = cq_free_res(dev, slave, vhcr->op_modifier, alop,
2566 vhcr->in_param, &vhcr->out_param);
2570 err = srq_free_res(dev, slave, vhcr->op_modifier, alop,
2571 vhcr->in_param, &vhcr->out_param);
2575 err = mac_free_res(dev, slave, vhcr->op_modifier, alop,
2576 vhcr->in_param, &vhcr->out_param,
2577 (vhcr->in_modifier >> 8) & 0xFF);
2581 err = vlan_free_res(dev, slave, vhcr->op_modifier, alop,
2582 vhcr->in_param, &vhcr->out_param,
2583 (vhcr->in_modifier >> 8) & 0xFF);
2587 err = counter_free_res(dev, slave, vhcr->op_modifier, alop,
2588 vhcr->in_param, &vhcr->out_param);
2592 err = xrcdn_free_res(dev, slave, vhcr->op_modifier, alop,
2593 vhcr->in_param, &vhcr->out_param);
2601 /* ugly but other choices are uglier */
2602 static int mr_phys_mpt(struct mlx4_mpt_entry *mpt)
2604 return (be32_to_cpu(mpt->flags) >> 9) & 1;
2607 static int mr_get_mtt_addr(struct mlx4_mpt_entry *mpt)
2609 return (int)be64_to_cpu(mpt->mtt_addr) & 0xfffffff8;
2612 static int mr_get_mtt_size(struct mlx4_mpt_entry *mpt)
2614 return be32_to_cpu(mpt->mtt_sz);
2617 static u32 mr_get_pd(struct mlx4_mpt_entry *mpt)
2619 return be32_to_cpu(mpt->pd_flags) & 0x00ffffff;
2622 static int mr_is_fmr(struct mlx4_mpt_entry *mpt)
2624 return be32_to_cpu(mpt->pd_flags) & MLX4_MPT_PD_FLAG_FAST_REG;
2627 static int mr_is_bind_enabled(struct mlx4_mpt_entry *mpt)
2629 return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_BIND_ENABLE;
2632 static int mr_is_region(struct mlx4_mpt_entry *mpt)
2634 return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_REGION;
2637 static int qp_get_mtt_addr(struct mlx4_qp_context *qpc)
2639 return be32_to_cpu(qpc->mtt_base_addr_l) & 0xfffffff8;
2642 static int srq_get_mtt_addr(struct mlx4_srq_context *srqc)
2644 return be32_to_cpu(srqc->mtt_base_addr_l) & 0xfffffff8;
2647 static int qp_get_mtt_size(struct mlx4_qp_context *qpc)
2649 int page_shift = (qpc->log_page_size & 0x3f) + 12;
2650 int log_sq_size = (qpc->sq_size_stride >> 3) & 0xf;
2651 int log_sq_sride = qpc->sq_size_stride & 7;
2652 int log_rq_size = (qpc->rq_size_stride >> 3) & 0xf;
2653 int log_rq_stride = qpc->rq_size_stride & 7;
2654 int srq = (be32_to_cpu(qpc->srqn) >> 24) & 1;
2655 int rss = (be32_to_cpu(qpc->flags) >> 13) & 1;
2656 u32 ts = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
2657 int xrc = (ts == MLX4_QP_ST_XRC) ? 1 : 0;
2662 int page_offset = (be32_to_cpu(qpc->params2) >> 6) & 0x3f;
2664 sq_size = 1 << (log_sq_size + log_sq_sride + 4);
2665 rq_size = (srq|rss|xrc) ? 0 : (1 << (log_rq_size + log_rq_stride + 4));
2666 total_mem = sq_size + rq_size;
2668 roundup_pow_of_two((total_mem + (page_offset << 6)) >>
2674 static int check_mtt_range(struct mlx4_dev *dev, int slave, int start,
2675 int size, struct res_mtt *mtt)
2677 int res_start = mtt->com.res_id;
2678 int res_size = (1 << mtt->order);
2680 if (start < res_start || start + size > res_start + res_size)
2685 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
2686 struct mlx4_vhcr *vhcr,
2687 struct mlx4_cmd_mailbox *inbox,
2688 struct mlx4_cmd_mailbox *outbox,
2689 struct mlx4_cmd_info *cmd)
2692 int index = vhcr->in_modifier;
2693 struct res_mtt *mtt;
2694 struct res_mpt *mpt;
2695 int mtt_base = mr_get_mtt_addr(inbox->buf) / dev->caps.mtt_entry_sz;
2701 id = index & mpt_mask(dev);
2702 err = mr_res_start_move_to(dev, slave, id, RES_MPT_HW, &mpt);
2706 /* Disable memory windows for VFs. */
2707 if (!mr_is_region(inbox->buf)) {
2712 /* Make sure that the PD bits related to the slave id are zeros. */
2713 pd = mr_get_pd(inbox->buf);
2714 pd_slave = (pd >> 17) & 0x7f;
2715 if (pd_slave != 0 && --pd_slave != slave) {
2720 if (mr_is_fmr(inbox->buf)) {
2721 /* FMR and Bind Enable are forbidden in slave devices. */
2722 if (mr_is_bind_enabled(inbox->buf)) {
2726 /* FMR and Memory Windows are also forbidden. */
2727 if (!mr_is_region(inbox->buf)) {
2733 phys = mr_phys_mpt(inbox->buf);
2735 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
2739 err = check_mtt_range(dev, slave, mtt_base,
2740 mr_get_mtt_size(inbox->buf), mtt);
2747 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2752 atomic_inc(&mtt->ref_count);
2753 put_res(dev, slave, mtt->com.res_id, RES_MTT);
2756 res_end_move(dev, slave, RES_MPT, id);
2761 put_res(dev, slave, mtt->com.res_id, RES_MTT);
2763 res_abort_move(dev, slave, RES_MPT, id);
2768 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
2769 struct mlx4_vhcr *vhcr,
2770 struct mlx4_cmd_mailbox *inbox,
2771 struct mlx4_cmd_mailbox *outbox,
2772 struct mlx4_cmd_info *cmd)
2775 int index = vhcr->in_modifier;
2776 struct res_mpt *mpt;
2779 id = index & mpt_mask(dev);
2780 err = mr_res_start_move_to(dev, slave, id, RES_MPT_MAPPED, &mpt);
2784 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2789 atomic_dec(&mpt->mtt->ref_count);
2791 res_end_move(dev, slave, RES_MPT, id);
2795 res_abort_move(dev, slave, RES_MPT, id);
2800 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
2801 struct mlx4_vhcr *vhcr,
2802 struct mlx4_cmd_mailbox *inbox,
2803 struct mlx4_cmd_mailbox *outbox,
2804 struct mlx4_cmd_info *cmd)
2807 int index = vhcr->in_modifier;
2808 struct res_mpt *mpt;
2811 id = index & mpt_mask(dev);
2812 err = get_res(dev, slave, id, RES_MPT, &mpt);
2816 if (mpt->com.from_state == RES_MPT_MAPPED) {
2817 /* In order to allow rereg in SRIOV, we need to alter the MPT entry. To do
2818 * that, the VF must read the MPT. But since the MPT entry memory is not
2819 * in the VF's virtual memory space, it must use QUERY_MPT to obtain the
2820 * entry contents. To guarantee that the MPT cannot be changed, the driver
2821 * must perform HW2SW_MPT before this query and return the MPT entry to HW
2822 * ownership fofollowing the change. The change here allows the VF to
2823 * perform QUERY_MPT also when the entry is in SW ownership.
2825 struct mlx4_mpt_entry *mpt_entry = mlx4_table_find(
2826 &mlx4_priv(dev)->mr_table.dmpt_table,
2829 if (NULL == mpt_entry || NULL == outbox->buf) {
2834 memcpy(outbox->buf, mpt_entry, sizeof(*mpt_entry));
2837 } else if (mpt->com.from_state == RES_MPT_HW) {
2838 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2846 put_res(dev, slave, id, RES_MPT);
2850 static int qp_get_rcqn(struct mlx4_qp_context *qpc)
2852 return be32_to_cpu(qpc->cqn_recv) & 0xffffff;
2855 static int qp_get_scqn(struct mlx4_qp_context *qpc)
2857 return be32_to_cpu(qpc->cqn_send) & 0xffffff;
2860 static u32 qp_get_srqn(struct mlx4_qp_context *qpc)
2862 return be32_to_cpu(qpc->srqn) & 0x1ffffff;
2865 static void adjust_proxy_tun_qkey(struct mlx4_dev *dev, struct mlx4_vhcr *vhcr,
2866 struct mlx4_qp_context *context)
2868 u32 qpn = vhcr->in_modifier & 0xffffff;
2871 if (mlx4_get_parav_qkey(dev, qpn, &qkey))
2874 /* adjust qkey in qp context */
2875 context->qkey = cpu_to_be32(qkey);
2878 static int adjust_qp_sched_queue(struct mlx4_dev *dev, int slave,
2879 struct mlx4_qp_context *qpc,
2880 struct mlx4_cmd_mailbox *inbox);
2882 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
2883 struct mlx4_vhcr *vhcr,
2884 struct mlx4_cmd_mailbox *inbox,
2885 struct mlx4_cmd_mailbox *outbox,
2886 struct mlx4_cmd_info *cmd)
2889 int qpn = vhcr->in_modifier & 0x7fffff;
2890 struct res_mtt *mtt;
2892 struct mlx4_qp_context *qpc = inbox->buf + 8;
2893 int mtt_base = qp_get_mtt_addr(qpc) / dev->caps.mtt_entry_sz;
2894 int mtt_size = qp_get_mtt_size(qpc);
2897 int rcqn = qp_get_rcqn(qpc);
2898 int scqn = qp_get_scqn(qpc);
2899 u32 srqn = qp_get_srqn(qpc) & 0xffffff;
2900 int use_srq = (qp_get_srqn(qpc) >> 24) & 1;
2901 struct res_srq *srq;
2902 int local_qpn = be32_to_cpu(qpc->local_qpn) & 0xffffff;
2904 err = adjust_qp_sched_queue(dev, slave, qpc, inbox);
2908 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_HW, &qp, 0);
2911 qp->local_qpn = local_qpn;
2912 qp->sched_queue = 0;
2914 qp->vlan_control = 0;
2916 qp->pri_path_fl = 0;
2919 qp->qpc_flags = be32_to_cpu(qpc->flags);
2921 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
2925 err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
2929 err = get_res(dev, slave, rcqn, RES_CQ, &rcq);
2934 err = get_res(dev, slave, scqn, RES_CQ, &scq);
2941 err = get_res(dev, slave, srqn, RES_SRQ, &srq);
2946 adjust_proxy_tun_qkey(dev, vhcr, qpc);
2947 update_pkey_index(dev, slave, inbox);
2948 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2951 atomic_inc(&mtt->ref_count);
2953 atomic_inc(&rcq->ref_count);
2955 atomic_inc(&scq->ref_count);
2959 put_res(dev, slave, scqn, RES_CQ);
2962 atomic_inc(&srq->ref_count);
2963 put_res(dev, slave, srqn, RES_SRQ);
2966 put_res(dev, slave, rcqn, RES_CQ);
2967 put_res(dev, slave, mtt_base, RES_MTT);
2968 res_end_move(dev, slave, RES_QP, qpn);
2974 put_res(dev, slave, srqn, RES_SRQ);
2977 put_res(dev, slave, scqn, RES_CQ);
2979 put_res(dev, slave, rcqn, RES_CQ);
2981 put_res(dev, slave, mtt_base, RES_MTT);
2983 res_abort_move(dev, slave, RES_QP, qpn);
2988 static int eq_get_mtt_addr(struct mlx4_eq_context *eqc)
2990 return be32_to_cpu(eqc->mtt_base_addr_l) & 0xfffffff8;
2993 static int eq_get_mtt_size(struct mlx4_eq_context *eqc)
2995 int log_eq_size = eqc->log_eq_size & 0x1f;
2996 int page_shift = (eqc->log_page_size & 0x3f) + 12;
2998 if (log_eq_size + 5 < page_shift)
3001 return 1 << (log_eq_size + 5 - page_shift);
3004 static int cq_get_mtt_addr(struct mlx4_cq_context *cqc)
3006 return be32_to_cpu(cqc->mtt_base_addr_l) & 0xfffffff8;
3009 static int cq_get_mtt_size(struct mlx4_cq_context *cqc)
3011 int log_cq_size = (be32_to_cpu(cqc->logsize_usrpage) >> 24) & 0x1f;
3012 int page_shift = (cqc->log_page_size & 0x3f) + 12;
3014 if (log_cq_size + 5 < page_shift)
3017 return 1 << (log_cq_size + 5 - page_shift);
3020 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
3021 struct mlx4_vhcr *vhcr,
3022 struct mlx4_cmd_mailbox *inbox,
3023 struct mlx4_cmd_mailbox *outbox,
3024 struct mlx4_cmd_info *cmd)
3027 int eqn = vhcr->in_modifier;
3028 int res_id = (slave << 10) | eqn;
3029 struct mlx4_eq_context *eqc = inbox->buf;
3030 int mtt_base = eq_get_mtt_addr(eqc) / dev->caps.mtt_entry_sz;
3031 int mtt_size = eq_get_mtt_size(eqc);
3033 struct res_mtt *mtt;
3035 err = add_res_range(dev, slave, res_id, 1, RES_EQ, 0);
3038 err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_HW, &eq);
3042 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
3046 err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
3050 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3054 atomic_inc(&mtt->ref_count);
3056 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3057 res_end_move(dev, slave, RES_EQ, res_id);
3061 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3063 res_abort_move(dev, slave, RES_EQ, res_id);
3065 rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
3069 int mlx4_CONFIG_DEV_wrapper(struct mlx4_dev *dev, int slave,
3070 struct mlx4_vhcr *vhcr,
3071 struct mlx4_cmd_mailbox *inbox,
3072 struct mlx4_cmd_mailbox *outbox,
3073 struct mlx4_cmd_info *cmd)
3076 u8 get = vhcr->op_modifier;
3081 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3086 static int get_containing_mtt(struct mlx4_dev *dev, int slave, int start,
3087 int len, struct res_mtt **res)
3089 struct mlx4_priv *priv = mlx4_priv(dev);
3090 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
3091 struct res_mtt *mtt;
3094 spin_lock_irq(mlx4_tlock(dev));
3095 list_for_each_entry(mtt, &tracker->slave_list[slave].res_list[RES_MTT],
3097 if (!check_mtt_range(dev, slave, start, len, mtt)) {
3099 mtt->com.from_state = mtt->com.state;
3100 mtt->com.state = RES_MTT_BUSY;
3105 spin_unlock_irq(mlx4_tlock(dev));
3110 static int verify_qp_parameters(struct mlx4_dev *dev,
3111 struct mlx4_vhcr *vhcr,
3112 struct mlx4_cmd_mailbox *inbox,
3113 enum qp_transition transition, u8 slave)
3117 struct mlx4_qp_context *qp_ctx;
3118 enum mlx4_qp_optpar optpar;
3122 qp_ctx = inbox->buf + 8;
3123 qp_type = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
3124 optpar = be32_to_cpu(*(__be32 *) inbox->buf);
3126 if (slave != mlx4_master_func_num(dev)) {
3127 qp_ctx->params2 &= ~MLX4_QP_BIT_FPP;
3128 /* setting QP rate-limit is disallowed for VFs */
3129 if (qp_ctx->rate_limit_params)
3135 case MLX4_QP_ST_XRC:
3137 switch (transition) {
3138 case QP_TRANS_INIT2RTR:
3139 case QP_TRANS_RTR2RTS:
3140 case QP_TRANS_RTS2RTS:
3141 case QP_TRANS_SQD2SQD:
3142 case QP_TRANS_SQD2RTS:
3143 if (slave != mlx4_master_func_num(dev)) {
3144 if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH) {
3145 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
3146 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB)
3147 num_gids = mlx4_get_slave_num_gids(dev, slave, port);
3150 if (qp_ctx->pri_path.mgid_index >= num_gids)
3153 if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) {
3154 port = (qp_ctx->alt_path.sched_queue >> 6 & 1) + 1;
3155 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB)
3156 num_gids = mlx4_get_slave_num_gids(dev, slave, port);
3159 if (qp_ctx->alt_path.mgid_index >= num_gids)
3169 case MLX4_QP_ST_MLX:
3170 qpn = vhcr->in_modifier & 0x7fffff;
3171 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
3172 if (transition == QP_TRANS_INIT2RTR &&
3173 slave != mlx4_master_func_num(dev) &&
3174 mlx4_is_qp_reserved(dev, qpn) &&
3175 !mlx4_vf_smi_enabled(dev, slave, port)) {
3176 /* only enabled VFs may create MLX proxy QPs */
3177 mlx4_err(dev, "%s: unprivileged slave %d attempting to create an MLX proxy special QP on port %d\n",
3178 __func__, slave, port);
3190 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
3191 struct mlx4_vhcr *vhcr,
3192 struct mlx4_cmd_mailbox *inbox,
3193 struct mlx4_cmd_mailbox *outbox,
3194 struct mlx4_cmd_info *cmd)
3196 struct mlx4_mtt mtt;
3197 __be64 *page_list = inbox->buf;
3198 u64 *pg_list = (u64 *)page_list;
3200 struct res_mtt *rmtt = NULL;
3201 int start = be64_to_cpu(page_list[0]);
3202 int npages = vhcr->in_modifier;
3205 err = get_containing_mtt(dev, slave, start, npages, &rmtt);
3209 /* Call the SW implementation of write_mtt:
3210 * - Prepare a dummy mtt struct
3211 * - Translate inbox contents to simple addresses in host endianness */
3212 mtt.offset = 0; /* TBD this is broken but I don't handle it since
3213 we don't really use it */
3216 for (i = 0; i < npages; ++i)
3217 pg_list[i + 2] = (be64_to_cpu(page_list[i + 2]) & ~1ULL);
3219 err = __mlx4_write_mtt(dev, &mtt, be64_to_cpu(page_list[0]), npages,
3220 ((u64 *)page_list + 2));
3223 put_res(dev, slave, rmtt->com.res_id, RES_MTT);
3228 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
3229 struct mlx4_vhcr *vhcr,
3230 struct mlx4_cmd_mailbox *inbox,
3231 struct mlx4_cmd_mailbox *outbox,
3232 struct mlx4_cmd_info *cmd)
3234 int eqn = vhcr->in_modifier;
3235 int res_id = eqn | (slave << 10);
3239 err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_RESERVED, &eq);
3243 err = get_res(dev, slave, eq->mtt->com.res_id, RES_MTT, NULL);
3247 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3251 atomic_dec(&eq->mtt->ref_count);
3252 put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
3253 res_end_move(dev, slave, RES_EQ, res_id);
3254 rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
3259 put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
3261 res_abort_move(dev, slave, RES_EQ, res_id);
3266 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe)
3268 struct mlx4_priv *priv = mlx4_priv(dev);
3269 struct mlx4_slave_event_eq_info *event_eq;
3270 struct mlx4_cmd_mailbox *mailbox;
3271 u32 in_modifier = 0;
3276 if (!priv->mfunc.master.slave_state)
3279 /* check for slave valid, slave not PF, and slave active */
3280 if (slave < 0 || slave > dev->persist->num_vfs ||
3281 slave == dev->caps.function ||
3282 !priv->mfunc.master.slave_state[slave].active)
3285 event_eq = &priv->mfunc.master.slave_state[slave].event_eq[eqe->type];
3287 /* Create the event only if the slave is registered */
3288 if (event_eq->eqn < 0)
3291 mutex_lock(&priv->mfunc.master.gen_eqe_mutex[slave]);
3292 res_id = (slave << 10) | event_eq->eqn;
3293 err = get_res(dev, slave, res_id, RES_EQ, &req);
3297 if (req->com.from_state != RES_EQ_HW) {
3302 mailbox = mlx4_alloc_cmd_mailbox(dev);
3303 if (IS_ERR(mailbox)) {
3304 err = PTR_ERR(mailbox);
3308 if (eqe->type == MLX4_EVENT_TYPE_CMD) {
3310 eqe->event.cmd.token = cpu_to_be16(event_eq->token);
3313 memcpy(mailbox->buf, (u8 *) eqe, 28);
3315 in_modifier = (slave & 0xff) | ((event_eq->eqn & 0x3ff) << 16);
3317 err = mlx4_cmd(dev, mailbox->dma, in_modifier, 0,
3318 MLX4_CMD_GEN_EQE, MLX4_CMD_TIME_CLASS_B,
3321 put_res(dev, slave, res_id, RES_EQ);
3322 mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
3323 mlx4_free_cmd_mailbox(dev, mailbox);
3327 put_res(dev, slave, res_id, RES_EQ);
3330 mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
3334 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
3335 struct mlx4_vhcr *vhcr,
3336 struct mlx4_cmd_mailbox *inbox,
3337 struct mlx4_cmd_mailbox *outbox,
3338 struct mlx4_cmd_info *cmd)
3340 int eqn = vhcr->in_modifier;
3341 int res_id = eqn | (slave << 10);
3345 err = get_res(dev, slave, res_id, RES_EQ, &eq);
3349 if (eq->com.from_state != RES_EQ_HW) {
3354 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3357 put_res(dev, slave, res_id, RES_EQ);
3361 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
3362 struct mlx4_vhcr *vhcr,
3363 struct mlx4_cmd_mailbox *inbox,
3364 struct mlx4_cmd_mailbox *outbox,
3365 struct mlx4_cmd_info *cmd)
3368 int cqn = vhcr->in_modifier;
3369 struct mlx4_cq_context *cqc = inbox->buf;
3370 int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
3371 struct res_cq *cq = NULL;
3372 struct res_mtt *mtt;
3374 err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_HW, &cq);
3377 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
3380 err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
3383 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3386 atomic_inc(&mtt->ref_count);
3388 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3389 res_end_move(dev, slave, RES_CQ, cqn);
3393 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3395 res_abort_move(dev, slave, RES_CQ, cqn);
3399 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
3400 struct mlx4_vhcr *vhcr,
3401 struct mlx4_cmd_mailbox *inbox,
3402 struct mlx4_cmd_mailbox *outbox,
3403 struct mlx4_cmd_info *cmd)
3406 int cqn = vhcr->in_modifier;
3407 struct res_cq *cq = NULL;
3409 err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_ALLOCATED, &cq);
3412 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3415 atomic_dec(&cq->mtt->ref_count);
3416 res_end_move(dev, slave, RES_CQ, cqn);
3420 res_abort_move(dev, slave, RES_CQ, cqn);
3424 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
3425 struct mlx4_vhcr *vhcr,
3426 struct mlx4_cmd_mailbox *inbox,
3427 struct mlx4_cmd_mailbox *outbox,
3428 struct mlx4_cmd_info *cmd)
3430 int cqn = vhcr->in_modifier;
3434 err = get_res(dev, slave, cqn, RES_CQ, &cq);
3438 if (cq->com.from_state != RES_CQ_HW)
3441 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3443 put_res(dev, slave, cqn, RES_CQ);
3448 static int handle_resize(struct mlx4_dev *dev, int slave,
3449 struct mlx4_vhcr *vhcr,
3450 struct mlx4_cmd_mailbox *inbox,
3451 struct mlx4_cmd_mailbox *outbox,
3452 struct mlx4_cmd_info *cmd,
3456 struct res_mtt *orig_mtt;
3457 struct res_mtt *mtt;
3458 struct mlx4_cq_context *cqc = inbox->buf;
3459 int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
3461 err = get_res(dev, slave, cq->mtt->com.res_id, RES_MTT, &orig_mtt);
3465 if (orig_mtt != cq->mtt) {
3470 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
3474 err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
3477 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3480 atomic_dec(&orig_mtt->ref_count);
3481 put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
3482 atomic_inc(&mtt->ref_count);
3484 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3488 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3490 put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
3496 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
3497 struct mlx4_vhcr *vhcr,
3498 struct mlx4_cmd_mailbox *inbox,
3499 struct mlx4_cmd_mailbox *outbox,
3500 struct mlx4_cmd_info *cmd)
3502 int cqn = vhcr->in_modifier;
3506 err = get_res(dev, slave, cqn, RES_CQ, &cq);
3510 if (cq->com.from_state != RES_CQ_HW)
3513 if (vhcr->op_modifier == 0) {
3514 err = handle_resize(dev, slave, vhcr, inbox, outbox, cmd, cq);
3518 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3520 put_res(dev, slave, cqn, RES_CQ);
3525 static int srq_get_mtt_size(struct mlx4_srq_context *srqc)
3527 int log_srq_size = (be32_to_cpu(srqc->state_logsize_srqn) >> 24) & 0xf;
3528 int log_rq_stride = srqc->logstride & 7;
3529 int page_shift = (srqc->log_page_size & 0x3f) + 12;
3531 if (log_srq_size + log_rq_stride + 4 < page_shift)
3534 return 1 << (log_srq_size + log_rq_stride + 4 - page_shift);
3537 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3538 struct mlx4_vhcr *vhcr,
3539 struct mlx4_cmd_mailbox *inbox,
3540 struct mlx4_cmd_mailbox *outbox,
3541 struct mlx4_cmd_info *cmd)
3544 int srqn = vhcr->in_modifier;
3545 struct res_mtt *mtt;
3546 struct res_srq *srq = NULL;
3547 struct mlx4_srq_context *srqc = inbox->buf;
3548 int mtt_base = srq_get_mtt_addr(srqc) / dev->caps.mtt_entry_sz;
3550 if (srqn != (be32_to_cpu(srqc->state_logsize_srqn) & 0xffffff))
3553 err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_HW, &srq);
3556 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
3559 err = check_mtt_range(dev, slave, mtt_base, srq_get_mtt_size(srqc),
3564 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3568 atomic_inc(&mtt->ref_count);
3570 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3571 res_end_move(dev, slave, RES_SRQ, srqn);
3575 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3577 res_abort_move(dev, slave, RES_SRQ, srqn);
3582 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3583 struct mlx4_vhcr *vhcr,
3584 struct mlx4_cmd_mailbox *inbox,
3585 struct mlx4_cmd_mailbox *outbox,
3586 struct mlx4_cmd_info *cmd)
3589 int srqn = vhcr->in_modifier;
3590 struct res_srq *srq = NULL;
3592 err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_ALLOCATED, &srq);
3595 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3598 atomic_dec(&srq->mtt->ref_count);
3600 atomic_dec(&srq->cq->ref_count);
3601 res_end_move(dev, slave, RES_SRQ, srqn);
3606 res_abort_move(dev, slave, RES_SRQ, srqn);
3611 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3612 struct mlx4_vhcr *vhcr,
3613 struct mlx4_cmd_mailbox *inbox,
3614 struct mlx4_cmd_mailbox *outbox,
3615 struct mlx4_cmd_info *cmd)
3618 int srqn = vhcr->in_modifier;
3619 struct res_srq *srq;
3621 err = get_res(dev, slave, srqn, RES_SRQ, &srq);
3624 if (srq->com.from_state != RES_SRQ_HW) {
3628 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3630 put_res(dev, slave, srqn, RES_SRQ);
3634 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3635 struct mlx4_vhcr *vhcr,
3636 struct mlx4_cmd_mailbox *inbox,
3637 struct mlx4_cmd_mailbox *outbox,
3638 struct mlx4_cmd_info *cmd)
3641 int srqn = vhcr->in_modifier;
3642 struct res_srq *srq;
3644 err = get_res(dev, slave, srqn, RES_SRQ, &srq);
3648 if (srq->com.from_state != RES_SRQ_HW) {
3653 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3655 put_res(dev, slave, srqn, RES_SRQ);
3659 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
3660 struct mlx4_vhcr *vhcr,
3661 struct mlx4_cmd_mailbox *inbox,
3662 struct mlx4_cmd_mailbox *outbox,
3663 struct mlx4_cmd_info *cmd)
3666 int qpn = vhcr->in_modifier & 0x7fffff;
3669 err = get_res(dev, slave, qpn, RES_QP, &qp);
3672 if (qp->com.from_state != RES_QP_HW) {
3677 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3679 put_res(dev, slave, qpn, RES_QP);
3683 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
3684 struct mlx4_vhcr *vhcr,
3685 struct mlx4_cmd_mailbox *inbox,
3686 struct mlx4_cmd_mailbox *outbox,
3687 struct mlx4_cmd_info *cmd)
3689 struct mlx4_qp_context *context = inbox->buf + 8;
3690 adjust_proxy_tun_qkey(dev, vhcr, context);
3691 update_pkey_index(dev, slave, inbox);
3692 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3695 static int adjust_qp_sched_queue(struct mlx4_dev *dev, int slave,
3696 struct mlx4_qp_context *qpc,
3697 struct mlx4_cmd_mailbox *inbox)
3699 enum mlx4_qp_optpar optpar = be32_to_cpu(*(__be32 *)inbox->buf);
3701 int port = mlx4_slave_convert_port(
3702 dev, slave, (qpc->pri_path.sched_queue >> 6 & 1) + 1) - 1;
3707 pri_sched_queue = (qpc->pri_path.sched_queue & ~(1 << 6)) |
3710 if (optpar & (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH | MLX4_QP_OPTPAR_SCHED_QUEUE) ||
3711 qpc->pri_path.sched_queue || mlx4_is_eth(dev, port + 1)) {
3712 qpc->pri_path.sched_queue = pri_sched_queue;
3715 if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) {
3716 port = mlx4_slave_convert_port(
3717 dev, slave, (qpc->alt_path.sched_queue >> 6 & 1)
3721 qpc->alt_path.sched_queue =
3722 (qpc->alt_path.sched_queue & ~(1 << 6)) |
3728 static int roce_verify_mac(struct mlx4_dev *dev, int slave,
3729 struct mlx4_qp_context *qpc,
3730 struct mlx4_cmd_mailbox *inbox)
3734 u32 ts = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
3735 u8 sched = *(u8 *)(inbox->buf + 64);
3738 port = (sched >> 6 & 1) + 1;
3739 if (mlx4_is_eth(dev, port) && (ts != MLX4_QP_ST_MLX)) {
3740 smac_ix = qpc->pri_path.grh_mylmc & 0x7f;
3741 if (mac_find_smac_ix_in_slave(dev, slave, port, smac_ix, &mac))
3747 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
3748 struct mlx4_vhcr *vhcr,
3749 struct mlx4_cmd_mailbox *inbox,
3750 struct mlx4_cmd_mailbox *outbox,
3751 struct mlx4_cmd_info *cmd)
3754 struct mlx4_qp_context *qpc = inbox->buf + 8;
3755 int qpn = vhcr->in_modifier & 0x7fffff;
3757 u8 orig_sched_queue;
3758 __be32 orig_param3 = qpc->param3;
3759 u8 orig_vlan_control = qpc->pri_path.vlan_control;
3760 u8 orig_fvl_rx = qpc->pri_path.fvl_rx;
3761 u8 orig_pri_path_fl = qpc->pri_path.fl;
3762 u8 orig_vlan_index = qpc->pri_path.vlan_index;
3763 u8 orig_feup = qpc->pri_path.feup;
3765 err = adjust_qp_sched_queue(dev, slave, qpc, inbox);
3768 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_INIT2RTR, slave);
3772 if (roce_verify_mac(dev, slave, qpc, inbox))
3775 update_pkey_index(dev, slave, inbox);
3776 update_gid(dev, inbox, (u8)slave);
3777 adjust_proxy_tun_qkey(dev, vhcr, qpc);
3778 orig_sched_queue = qpc->pri_path.sched_queue;
3780 err = get_res(dev, slave, qpn, RES_QP, &qp);
3783 if (qp->com.from_state != RES_QP_HW) {
3788 err = update_vport_qp_param(dev, inbox, slave, qpn);
3792 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3794 /* if no error, save sched queue value passed in by VF. This is
3795 * essentially the QOS value provided by the VF. This will be useful
3796 * if we allow dynamic changes from VST back to VGT
3799 qp->sched_queue = orig_sched_queue;
3800 qp->param3 = orig_param3;
3801 qp->vlan_control = orig_vlan_control;
3802 qp->fvl_rx = orig_fvl_rx;
3803 qp->pri_path_fl = orig_pri_path_fl;
3804 qp->vlan_index = orig_vlan_index;
3805 qp->feup = orig_feup;
3807 put_res(dev, slave, qpn, RES_QP);
3811 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3812 struct mlx4_vhcr *vhcr,
3813 struct mlx4_cmd_mailbox *inbox,
3814 struct mlx4_cmd_mailbox *outbox,
3815 struct mlx4_cmd_info *cmd)
3818 struct mlx4_qp_context *context = inbox->buf + 8;
3820 err = adjust_qp_sched_queue(dev, slave, context, inbox);
3823 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_RTR2RTS, slave);
3827 update_pkey_index(dev, slave, inbox);
3828 update_gid(dev, inbox, (u8)slave);
3829 adjust_proxy_tun_qkey(dev, vhcr, context);
3830 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3833 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3834 struct mlx4_vhcr *vhcr,
3835 struct mlx4_cmd_mailbox *inbox,
3836 struct mlx4_cmd_mailbox *outbox,
3837 struct mlx4_cmd_info *cmd)
3840 struct mlx4_qp_context *context = inbox->buf + 8;
3842 err = adjust_qp_sched_queue(dev, slave, context, inbox);
3845 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_RTS2RTS, slave);
3849 update_pkey_index(dev, slave, inbox);
3850 update_gid(dev, inbox, (u8)slave);
3851 adjust_proxy_tun_qkey(dev, vhcr, context);
3852 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3856 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3857 struct mlx4_vhcr *vhcr,
3858 struct mlx4_cmd_mailbox *inbox,
3859 struct mlx4_cmd_mailbox *outbox,
3860 struct mlx4_cmd_info *cmd)
3862 struct mlx4_qp_context *context = inbox->buf + 8;
3863 int err = adjust_qp_sched_queue(dev, slave, context, inbox);
3866 adjust_proxy_tun_qkey(dev, vhcr, context);
3867 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3870 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
3871 struct mlx4_vhcr *vhcr,
3872 struct mlx4_cmd_mailbox *inbox,
3873 struct mlx4_cmd_mailbox *outbox,
3874 struct mlx4_cmd_info *cmd)
3877 struct mlx4_qp_context *context = inbox->buf + 8;
3879 err = adjust_qp_sched_queue(dev, slave, context, inbox);
3882 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_SQD2SQD, slave);
3886 adjust_proxy_tun_qkey(dev, vhcr, context);
3887 update_gid(dev, inbox, (u8)slave);
3888 update_pkey_index(dev, slave, inbox);
3889 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3892 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3893 struct mlx4_vhcr *vhcr,
3894 struct mlx4_cmd_mailbox *inbox,
3895 struct mlx4_cmd_mailbox *outbox,
3896 struct mlx4_cmd_info *cmd)
3899 struct mlx4_qp_context *context = inbox->buf + 8;
3901 err = adjust_qp_sched_queue(dev, slave, context, inbox);
3904 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_SQD2RTS, slave);
3908 adjust_proxy_tun_qkey(dev, vhcr, context);
3909 update_gid(dev, inbox, (u8)slave);
3910 update_pkey_index(dev, slave, inbox);
3911 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3914 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
3915 struct mlx4_vhcr *vhcr,
3916 struct mlx4_cmd_mailbox *inbox,
3917 struct mlx4_cmd_mailbox *outbox,
3918 struct mlx4_cmd_info *cmd)
3921 int qpn = vhcr->in_modifier & 0x7fffff;
3924 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED, &qp, 0);
3927 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3931 atomic_dec(&qp->mtt->ref_count);
3932 atomic_dec(&qp->rcq->ref_count);
3933 atomic_dec(&qp->scq->ref_count);
3935 atomic_dec(&qp->srq->ref_count);
3936 res_end_move(dev, slave, RES_QP, qpn);
3940 res_abort_move(dev, slave, RES_QP, qpn);
3945 static struct res_gid *find_gid(struct mlx4_dev *dev, int slave,
3946 struct res_qp *rqp, u8 *gid)
3948 struct res_gid *res;
3950 list_for_each_entry(res, &rqp->mcg_list, list) {
3951 if (!memcmp(res->gid, gid, 16))
3957 static int add_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
3958 u8 *gid, enum mlx4_protocol prot,
3959 enum mlx4_steer_type steer, u64 reg_id)
3961 struct res_gid *res;
3964 res = kzalloc(sizeof *res, GFP_KERNEL);
3968 spin_lock_irq(&rqp->mcg_spl);
3969 if (find_gid(dev, slave, rqp, gid)) {
3973 memcpy(res->gid, gid, 16);
3976 res->reg_id = reg_id;
3977 list_add_tail(&res->list, &rqp->mcg_list);
3980 spin_unlock_irq(&rqp->mcg_spl);
3985 static int rem_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
3986 u8 *gid, enum mlx4_protocol prot,
3987 enum mlx4_steer_type steer, u64 *reg_id)
3989 struct res_gid *res;
3992 spin_lock_irq(&rqp->mcg_spl);
3993 res = find_gid(dev, slave, rqp, gid);
3994 if (!res || res->prot != prot || res->steer != steer)
3997 *reg_id = res->reg_id;
3998 list_del(&res->list);
4002 spin_unlock_irq(&rqp->mcg_spl);
4007 static int qp_attach(struct mlx4_dev *dev, int slave, struct mlx4_qp *qp,
4008 u8 gid[16], int block_loopback, enum mlx4_protocol prot,
4009 enum mlx4_steer_type type, u64 *reg_id)
4011 switch (dev->caps.steering_mode) {
4012 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
4013 int port = mlx4_slave_convert_port(dev, slave, gid[5]);
4016 return mlx4_trans_to_dmfs_attach(dev, qp, gid, port,
4017 block_loopback, prot,
4020 case MLX4_STEERING_MODE_B0:
4021 if (prot == MLX4_PROT_ETH) {
4022 int port = mlx4_slave_convert_port(dev, slave, gid[5]);
4027 return mlx4_qp_attach_common(dev, qp, gid,
4028 block_loopback, prot, type);
4034 static int qp_detach(struct mlx4_dev *dev, struct mlx4_qp *qp,
4035 u8 gid[16], enum mlx4_protocol prot,
4036 enum mlx4_steer_type type, u64 reg_id)
4038 switch (dev->caps.steering_mode) {
4039 case MLX4_STEERING_MODE_DEVICE_MANAGED:
4040 return mlx4_flow_detach(dev, reg_id);
4041 case MLX4_STEERING_MODE_B0:
4042 return mlx4_qp_detach_common(dev, qp, gid, prot, type);
4048 static int mlx4_adjust_port(struct mlx4_dev *dev, int slave,
4049 u8 *gid, enum mlx4_protocol prot)
4053 if (prot != MLX4_PROT_ETH)
4056 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0 ||
4057 dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
4058 real_port = mlx4_slave_convert_port(dev, slave, gid[5]);
4067 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
4068 struct mlx4_vhcr *vhcr,
4069 struct mlx4_cmd_mailbox *inbox,
4070 struct mlx4_cmd_mailbox *outbox,
4071 struct mlx4_cmd_info *cmd)
4073 struct mlx4_qp qp; /* dummy for calling attach/detach */
4074 u8 *gid = inbox->buf;
4075 enum mlx4_protocol prot = (vhcr->in_modifier >> 28) & 0x7;
4080 int attach = vhcr->op_modifier;
4081 int block_loopback = vhcr->in_modifier >> 31;
4082 u8 steer_type_mask = 2;
4083 enum mlx4_steer_type type = (gid[7] & steer_type_mask) >> 1;
4085 qpn = vhcr->in_modifier & 0xffffff;
4086 err = get_res(dev, slave, qpn, RES_QP, &rqp);
4092 err = qp_attach(dev, slave, &qp, gid, block_loopback, prot,
4095 pr_err("Fail to attach rule to qp 0x%x\n", qpn);
4098 err = add_mcg_res(dev, slave, rqp, gid, prot, type, reg_id);
4102 err = mlx4_adjust_port(dev, slave, gid, prot);
4106 err = rem_mcg_res(dev, slave, rqp, gid, prot, type, ®_id);
4110 err = qp_detach(dev, &qp, gid, prot, type, reg_id);
4112 pr_err("Fail to detach rule from qp 0x%x reg_id = 0x%llx\n",
4115 put_res(dev, slave, qpn, RES_QP);
4119 qp_detach(dev, &qp, gid, prot, type, reg_id);
4121 put_res(dev, slave, qpn, RES_QP);
4126 * MAC validation for Flow Steering rules.
4127 * VF can attach rules only with a mac address which is assigned to it.
4129 static int validate_eth_header_mac(int slave, struct _rule_hw *eth_header,
4130 struct list_head *rlist)
4132 struct mac_res *res, *tmp;
4135 /* make sure it isn't multicast or broadcast mac*/
4136 if (!is_multicast_ether_addr(eth_header->eth.dst_mac) &&
4137 !is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
4138 list_for_each_entry_safe(res, tmp, rlist, list) {
4139 be_mac = cpu_to_be64(res->mac << 16);
4140 if (ether_addr_equal((u8 *)&be_mac, eth_header->eth.dst_mac))
4143 pr_err("MAC %pM doesn't belong to VF %d, Steering rule rejected\n",
4144 eth_header->eth.dst_mac, slave);
4150 static void handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl,
4151 struct _rule_hw *eth_header)
4153 if (is_multicast_ether_addr(eth_header->eth.dst_mac) ||
4154 is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
4155 struct mlx4_net_trans_rule_hw_eth *eth =
4156 (struct mlx4_net_trans_rule_hw_eth *)eth_header;
4157 struct _rule_hw *next_rule = (struct _rule_hw *)(eth + 1);
4158 bool last_rule = next_rule->size == 0 && next_rule->id == 0 &&
4159 next_rule->rsvd == 0;
4162 ctrl->prio = cpu_to_be16(MLX4_DOMAIN_NIC);
4167 * In case of missing eth header, append eth header with a MAC address
4168 * assigned to the VF.
4170 static int add_eth_header(struct mlx4_dev *dev, int slave,
4171 struct mlx4_cmd_mailbox *inbox,
4172 struct list_head *rlist, int header_id)
4174 struct mac_res *res, *tmp;
4176 struct mlx4_net_trans_rule_hw_ctrl *ctrl;
4177 struct mlx4_net_trans_rule_hw_eth *eth_header;
4178 struct mlx4_net_trans_rule_hw_ipv4 *ip_header;
4179 struct mlx4_net_trans_rule_hw_tcp_udp *l4_header;
4181 __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16);
4183 ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
4185 eth_header = (struct mlx4_net_trans_rule_hw_eth *)(ctrl + 1);
4187 /* Clear a space in the inbox for eth header */
4188 switch (header_id) {
4189 case MLX4_NET_TRANS_RULE_ID_IPV4:
4191 (struct mlx4_net_trans_rule_hw_ipv4 *)(eth_header + 1);
4192 memmove(ip_header, eth_header,
4193 sizeof(*ip_header) + sizeof(*l4_header));
4195 case MLX4_NET_TRANS_RULE_ID_TCP:
4196 case MLX4_NET_TRANS_RULE_ID_UDP:
4197 l4_header = (struct mlx4_net_trans_rule_hw_tcp_udp *)
4199 memmove(l4_header, eth_header, sizeof(*l4_header));
4204 list_for_each_entry_safe(res, tmp, rlist, list) {
4205 if (port == res->port) {
4206 be_mac = cpu_to_be64(res->mac << 16);
4211 pr_err("Failed adding eth header to FS rule, Can't find matching MAC for port %d\n",
4216 memset(eth_header, 0, sizeof(*eth_header));
4217 eth_header->size = sizeof(*eth_header) >> 2;
4218 eth_header->id = cpu_to_be16(__sw_id_hw[MLX4_NET_TRANS_RULE_ID_ETH]);
4219 memcpy(eth_header->dst_mac, &be_mac, ETH_ALEN);
4220 memcpy(eth_header->dst_mac_msk, &mac_msk, ETH_ALEN);
4226 #define MLX4_UPD_QP_PATH_MASK_SUPPORTED ( \
4227 1ULL << MLX4_UPD_QP_PATH_MASK_MAC_INDEX |\
4228 1ULL << MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB)
4229 int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave,
4230 struct mlx4_vhcr *vhcr,
4231 struct mlx4_cmd_mailbox *inbox,
4232 struct mlx4_cmd_mailbox *outbox,
4233 struct mlx4_cmd_info *cmd_info)
4236 u32 qpn = vhcr->in_modifier & 0xffffff;
4240 u64 pri_addr_path_mask;
4241 struct mlx4_update_qp_context *cmd;
4244 cmd = (struct mlx4_update_qp_context *)inbox->buf;
4246 pri_addr_path_mask = be64_to_cpu(cmd->primary_addr_path_mask);
4247 if (cmd->qp_mask || cmd->secondary_addr_path_mask ||
4248 (pri_addr_path_mask & ~MLX4_UPD_QP_PATH_MASK_SUPPORTED))
4251 if ((pri_addr_path_mask &
4252 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB)) &&
4253 !(dev->caps.flags2 &
4254 MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB)) {
4255 mlx4_warn(dev, "Src check LB for slave %d isn't supported\n",
4260 /* Just change the smac for the QP */
4261 err = get_res(dev, slave, qpn, RES_QP, &rqp);
4263 mlx4_err(dev, "Updating qpn 0x%x for slave %d rejected\n", qpn, slave);
4267 port = (rqp->sched_queue >> 6 & 1) + 1;
4269 if (pri_addr_path_mask & (1ULL << MLX4_UPD_QP_PATH_MASK_MAC_INDEX)) {
4270 smac_index = cmd->qp_context.pri_path.grh_mylmc;
4271 err = mac_find_smac_ix_in_slave(dev, slave, port,
4275 mlx4_err(dev, "Failed to update qpn 0x%x, MAC is invalid. smac_ix: %d\n",
4281 err = mlx4_cmd(dev, inbox->dma,
4282 vhcr->in_modifier, 0,
4283 MLX4_CMD_UPDATE_QP, MLX4_CMD_TIME_CLASS_A,
4286 mlx4_err(dev, "Failed to update qpn on qpn 0x%x, command failed\n", qpn);
4291 put_res(dev, slave, qpn, RES_QP);
4295 static u32 qp_attach_mbox_size(void *mbox)
4297 u32 size = sizeof(struct mlx4_net_trans_rule_hw_ctrl);
4298 struct _rule_hw *rule_header;
4300 rule_header = (struct _rule_hw *)(mbox + size);
4302 while (rule_header->size) {
4303 size += rule_header->size * sizeof(u32);
4309 static int mlx4_do_mirror_rule(struct mlx4_dev *dev, struct res_fs_rule *fs_rule);
4311 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
4312 struct mlx4_vhcr *vhcr,
4313 struct mlx4_cmd_mailbox *inbox,
4314 struct mlx4_cmd_mailbox *outbox,
4315 struct mlx4_cmd_info *cmd)
4318 struct mlx4_priv *priv = mlx4_priv(dev);
4319 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4320 struct list_head *rlist = &tracker->slave_list[slave].res_list[RES_MAC];
4324 struct mlx4_net_trans_rule_hw_ctrl *ctrl;
4325 struct _rule_hw *rule_header;
4327 struct res_fs_rule *rrule;
4330 if (dev->caps.steering_mode !=
4331 MLX4_STEERING_MODE_DEVICE_MANAGED)
4334 ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
4335 err = mlx4_slave_convert_port(dev, slave, ctrl->port);
4339 qpn = be32_to_cpu(ctrl->qpn) & 0xffffff;
4340 err = get_res(dev, slave, qpn, RES_QP, &rqp);
4342 pr_err("Steering rule with qpn 0x%x rejected\n", qpn);
4345 rule_header = (struct _rule_hw *)(ctrl + 1);
4346 header_id = map_hw_to_sw_id(be16_to_cpu(rule_header->id));
4348 if (header_id == MLX4_NET_TRANS_RULE_ID_ETH)
4349 handle_eth_header_mcast_prio(ctrl, rule_header);
4351 if (slave == dev->caps.function)
4354 switch (header_id) {
4355 case MLX4_NET_TRANS_RULE_ID_ETH:
4356 if (validate_eth_header_mac(slave, rule_header, rlist)) {
4361 case MLX4_NET_TRANS_RULE_ID_IB:
4363 case MLX4_NET_TRANS_RULE_ID_IPV4:
4364 case MLX4_NET_TRANS_RULE_ID_TCP:
4365 case MLX4_NET_TRANS_RULE_ID_UDP:
4366 pr_warn("Can't attach FS rule without L2 headers, adding L2 header\n");
4367 if (add_eth_header(dev, slave, inbox, rlist, header_id)) {
4371 vhcr->in_modifier +=
4372 sizeof(struct mlx4_net_trans_rule_hw_eth) >> 2;
4375 pr_err("Corrupted mailbox\n");
4381 err = mlx4_cmd_imm(dev, inbox->dma, &vhcr->out_param,
4382 vhcr->in_modifier, 0,
4383 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
4389 err = add_res_range(dev, slave, vhcr->out_param, 1, RES_FS_RULE, qpn);
4391 mlx4_err(dev, "Fail to add flow steering resources\n");
4395 err = get_res(dev, slave, vhcr->out_param, RES_FS_RULE, &rrule);
4399 mbox_size = qp_attach_mbox_size(inbox->buf);
4400 rrule->mirr_mbox = kmalloc(mbox_size, GFP_KERNEL);
4401 if (!rrule->mirr_mbox) {
4405 rrule->mirr_mbox_size = mbox_size;
4406 rrule->mirr_rule_id = 0;
4407 memcpy(rrule->mirr_mbox, inbox->buf, mbox_size);
4409 /* set different port */
4410 ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)rrule->mirr_mbox;
4411 if (ctrl->port == 1)
4416 if (mlx4_is_bonded(dev))
4417 mlx4_do_mirror_rule(dev, rrule);
4419 atomic_inc(&rqp->ref_count);
4422 put_res(dev, slave, vhcr->out_param, RES_FS_RULE);
4424 /* detach rule on error */
4426 mlx4_cmd(dev, vhcr->out_param, 0, 0,
4427 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
4430 put_res(dev, slave, qpn, RES_QP);
4434 static int mlx4_undo_mirror_rule(struct mlx4_dev *dev, struct res_fs_rule *fs_rule)
4438 err = rem_res_range(dev, fs_rule->com.owner, fs_rule->com.res_id, 1, RES_FS_RULE, 0);
4440 mlx4_err(dev, "Fail to remove flow steering resources\n");
4444 mlx4_cmd(dev, fs_rule->com.res_id, 0, 0, MLX4_QP_FLOW_STEERING_DETACH,
4445 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
4449 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
4450 struct mlx4_vhcr *vhcr,
4451 struct mlx4_cmd_mailbox *inbox,
4452 struct mlx4_cmd_mailbox *outbox,
4453 struct mlx4_cmd_info *cmd)
4457 struct res_fs_rule *rrule;
4460 if (dev->caps.steering_mode !=
4461 MLX4_STEERING_MODE_DEVICE_MANAGED)
4464 err = get_res(dev, slave, vhcr->in_param, RES_FS_RULE, &rrule);
4468 if (!rrule->mirr_mbox) {
4469 mlx4_err(dev, "Mirror rules cannot be removed explicitly\n");
4470 put_res(dev, slave, vhcr->in_param, RES_FS_RULE);
4473 mirr_reg_id = rrule->mirr_rule_id;
4474 kfree(rrule->mirr_mbox);
4476 /* Release the rule form busy state before removal */
4477 put_res(dev, slave, vhcr->in_param, RES_FS_RULE);
4478 err = get_res(dev, slave, rrule->qpn, RES_QP, &rqp);
4482 if (mirr_reg_id && mlx4_is_bonded(dev)) {
4483 err = get_res(dev, slave, mirr_reg_id, RES_FS_RULE, &rrule);
4485 mlx4_err(dev, "Fail to get resource of mirror rule\n");
4487 put_res(dev, slave, mirr_reg_id, RES_FS_RULE);
4488 mlx4_undo_mirror_rule(dev, rrule);
4491 err = rem_res_range(dev, slave, vhcr->in_param, 1, RES_FS_RULE, 0);
4493 mlx4_err(dev, "Fail to remove flow steering resources\n");
4497 err = mlx4_cmd(dev, vhcr->in_param, 0, 0,
4498 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
4501 atomic_dec(&rqp->ref_count);
4503 put_res(dev, slave, rrule->qpn, RES_QP);
4508 BUSY_MAX_RETRIES = 10
4511 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
4512 struct mlx4_vhcr *vhcr,
4513 struct mlx4_cmd_mailbox *inbox,
4514 struct mlx4_cmd_mailbox *outbox,
4515 struct mlx4_cmd_info *cmd)
4518 int index = vhcr->in_modifier & 0xffff;
4520 err = get_res(dev, slave, index, RES_COUNTER, NULL);
4524 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
4525 put_res(dev, slave, index, RES_COUNTER);
4529 static void detach_qp(struct mlx4_dev *dev, int slave, struct res_qp *rqp)
4531 struct res_gid *rgid;
4532 struct res_gid *tmp;
4533 struct mlx4_qp qp; /* dummy for calling attach/detach */
4535 list_for_each_entry_safe(rgid, tmp, &rqp->mcg_list, list) {
4536 switch (dev->caps.steering_mode) {
4537 case MLX4_STEERING_MODE_DEVICE_MANAGED:
4538 mlx4_flow_detach(dev, rgid->reg_id);
4540 case MLX4_STEERING_MODE_B0:
4541 qp.qpn = rqp->local_qpn;
4542 (void) mlx4_qp_detach_common(dev, &qp, rgid->gid,
4543 rgid->prot, rgid->steer);
4546 list_del(&rgid->list);
4551 static int _move_all_busy(struct mlx4_dev *dev, int slave,
4552 enum mlx4_resource type, int print)
4554 struct mlx4_priv *priv = mlx4_priv(dev);
4555 struct mlx4_resource_tracker *tracker =
4556 &priv->mfunc.master.res_tracker;
4557 struct list_head *rlist = &tracker->slave_list[slave].res_list[type];
4558 struct res_common *r;
4559 struct res_common *tmp;
4563 spin_lock_irq(mlx4_tlock(dev));
4564 list_for_each_entry_safe(r, tmp, rlist, list) {
4565 if (r->owner == slave) {
4567 if (r->state == RES_ANY_BUSY) {
4570 "%s id 0x%llx is busy\n",
4575 r->from_state = r->state;
4576 r->state = RES_ANY_BUSY;
4582 spin_unlock_irq(mlx4_tlock(dev));
4587 static int move_all_busy(struct mlx4_dev *dev, int slave,
4588 enum mlx4_resource type)
4590 unsigned long begin;
4595 busy = _move_all_busy(dev, slave, type, 0);
4596 if (time_after(jiffies, begin + 5 * HZ))
4603 busy = _move_all_busy(dev, slave, type, 1);
4607 static void rem_slave_qps(struct mlx4_dev *dev, int slave)
4609 struct mlx4_priv *priv = mlx4_priv(dev);
4610 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4611 struct list_head *qp_list =
4612 &tracker->slave_list[slave].res_list[RES_QP];
4620 err = move_all_busy(dev, slave, RES_QP);
4622 mlx4_warn(dev, "rem_slave_qps: Could not move all qps to busy for slave %d\n",
4625 spin_lock_irq(mlx4_tlock(dev));
4626 list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
4627 spin_unlock_irq(mlx4_tlock(dev));
4628 if (qp->com.owner == slave) {
4629 qpn = qp->com.res_id;
4630 detach_qp(dev, slave, qp);
4631 state = qp->com.from_state;
4632 while (state != 0) {
4634 case RES_QP_RESERVED:
4635 spin_lock_irq(mlx4_tlock(dev));
4636 rb_erase(&qp->com.node,
4637 &tracker->res_tree[RES_QP]);
4638 list_del(&qp->com.list);
4639 spin_unlock_irq(mlx4_tlock(dev));
4640 if (!valid_reserved(dev, slave, qpn)) {
4641 __mlx4_qp_release_range(dev, qpn, 1);
4642 mlx4_release_resource(dev, slave,
4649 if (!valid_reserved(dev, slave, qpn))
4650 __mlx4_qp_free_icm(dev, qpn);
4651 state = RES_QP_RESERVED;
4655 err = mlx4_cmd(dev, in_param,
4658 MLX4_CMD_TIME_CLASS_A,
4661 mlx4_dbg(dev, "rem_slave_qps: failed to move slave %d qpn %d to reset\n",
4662 slave, qp->local_qpn);
4663 atomic_dec(&qp->rcq->ref_count);
4664 atomic_dec(&qp->scq->ref_count);
4665 atomic_dec(&qp->mtt->ref_count);
4667 atomic_dec(&qp->srq->ref_count);
4668 state = RES_QP_MAPPED;
4675 spin_lock_irq(mlx4_tlock(dev));
4677 spin_unlock_irq(mlx4_tlock(dev));
4680 static void rem_slave_srqs(struct mlx4_dev *dev, int slave)
4682 struct mlx4_priv *priv = mlx4_priv(dev);
4683 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4684 struct list_head *srq_list =
4685 &tracker->slave_list[slave].res_list[RES_SRQ];
4686 struct res_srq *srq;
4687 struct res_srq *tmp;
4694 err = move_all_busy(dev, slave, RES_SRQ);
4696 mlx4_warn(dev, "rem_slave_srqs: Could not move all srqs - too busy for slave %d\n",
4699 spin_lock_irq(mlx4_tlock(dev));
4700 list_for_each_entry_safe(srq, tmp, srq_list, com.list) {
4701 spin_unlock_irq(mlx4_tlock(dev));
4702 if (srq->com.owner == slave) {
4703 srqn = srq->com.res_id;
4704 state = srq->com.from_state;
4705 while (state != 0) {
4707 case RES_SRQ_ALLOCATED:
4708 __mlx4_srq_free_icm(dev, srqn);
4709 spin_lock_irq(mlx4_tlock(dev));
4710 rb_erase(&srq->com.node,
4711 &tracker->res_tree[RES_SRQ]);
4712 list_del(&srq->com.list);
4713 spin_unlock_irq(mlx4_tlock(dev));
4714 mlx4_release_resource(dev, slave,
4722 err = mlx4_cmd(dev, in_param, srqn, 1,
4724 MLX4_CMD_TIME_CLASS_A,
4727 mlx4_dbg(dev, "rem_slave_srqs: failed to move slave %d srq %d to SW ownership\n",
4730 atomic_dec(&srq->mtt->ref_count);
4732 atomic_dec(&srq->cq->ref_count);
4733 state = RES_SRQ_ALLOCATED;
4741 spin_lock_irq(mlx4_tlock(dev));
4743 spin_unlock_irq(mlx4_tlock(dev));
4746 static void rem_slave_cqs(struct mlx4_dev *dev, int slave)
4748 struct mlx4_priv *priv = mlx4_priv(dev);
4749 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4750 struct list_head *cq_list =
4751 &tracker->slave_list[slave].res_list[RES_CQ];
4760 err = move_all_busy(dev, slave, RES_CQ);
4762 mlx4_warn(dev, "rem_slave_cqs: Could not move all cqs - too busy for slave %d\n",
4765 spin_lock_irq(mlx4_tlock(dev));
4766 list_for_each_entry_safe(cq, tmp, cq_list, com.list) {
4767 spin_unlock_irq(mlx4_tlock(dev));
4768 if (cq->com.owner == slave && !atomic_read(&cq->ref_count)) {
4769 cqn = cq->com.res_id;
4770 state = cq->com.from_state;
4771 while (state != 0) {
4773 case RES_CQ_ALLOCATED:
4774 __mlx4_cq_free_icm(dev, cqn);
4775 spin_lock_irq(mlx4_tlock(dev));
4776 rb_erase(&cq->com.node,
4777 &tracker->res_tree[RES_CQ]);
4778 list_del(&cq->com.list);
4779 spin_unlock_irq(mlx4_tlock(dev));
4780 mlx4_release_resource(dev, slave,
4788 err = mlx4_cmd(dev, in_param, cqn, 1,
4790 MLX4_CMD_TIME_CLASS_A,
4793 mlx4_dbg(dev, "rem_slave_cqs: failed to move slave %d cq %d to SW ownership\n",
4795 atomic_dec(&cq->mtt->ref_count);
4796 state = RES_CQ_ALLOCATED;
4804 spin_lock_irq(mlx4_tlock(dev));
4806 spin_unlock_irq(mlx4_tlock(dev));
4809 static void rem_slave_mrs(struct mlx4_dev *dev, int slave)
4811 struct mlx4_priv *priv = mlx4_priv(dev);
4812 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4813 struct list_head *mpt_list =
4814 &tracker->slave_list[slave].res_list[RES_MPT];
4815 struct res_mpt *mpt;
4816 struct res_mpt *tmp;
4823 err = move_all_busy(dev, slave, RES_MPT);
4825 mlx4_warn(dev, "rem_slave_mrs: Could not move all mpts - too busy for slave %d\n",
4828 spin_lock_irq(mlx4_tlock(dev));
4829 list_for_each_entry_safe(mpt, tmp, mpt_list, com.list) {
4830 spin_unlock_irq(mlx4_tlock(dev));
4831 if (mpt->com.owner == slave) {
4832 mptn = mpt->com.res_id;
4833 state = mpt->com.from_state;
4834 while (state != 0) {
4836 case RES_MPT_RESERVED:
4837 __mlx4_mpt_release(dev, mpt->key);
4838 spin_lock_irq(mlx4_tlock(dev));
4839 rb_erase(&mpt->com.node,
4840 &tracker->res_tree[RES_MPT]);
4841 list_del(&mpt->com.list);
4842 spin_unlock_irq(mlx4_tlock(dev));
4843 mlx4_release_resource(dev, slave,
4849 case RES_MPT_MAPPED:
4850 __mlx4_mpt_free_icm(dev, mpt->key);
4851 state = RES_MPT_RESERVED;
4856 err = mlx4_cmd(dev, in_param, mptn, 0,
4858 MLX4_CMD_TIME_CLASS_A,
4861 mlx4_dbg(dev, "rem_slave_mrs: failed to move slave %d mpt %d to SW ownership\n",
4864 atomic_dec(&mpt->mtt->ref_count);
4865 state = RES_MPT_MAPPED;
4872 spin_lock_irq(mlx4_tlock(dev));
4874 spin_unlock_irq(mlx4_tlock(dev));
4877 static void rem_slave_mtts(struct mlx4_dev *dev, int slave)
4879 struct mlx4_priv *priv = mlx4_priv(dev);
4880 struct mlx4_resource_tracker *tracker =
4881 &priv->mfunc.master.res_tracker;
4882 struct list_head *mtt_list =
4883 &tracker->slave_list[slave].res_list[RES_MTT];
4884 struct res_mtt *mtt;
4885 struct res_mtt *tmp;
4891 err = move_all_busy(dev, slave, RES_MTT);
4893 mlx4_warn(dev, "rem_slave_mtts: Could not move all mtts - too busy for slave %d\n",
4896 spin_lock_irq(mlx4_tlock(dev));
4897 list_for_each_entry_safe(mtt, tmp, mtt_list, com.list) {
4898 spin_unlock_irq(mlx4_tlock(dev));
4899 if (mtt->com.owner == slave) {
4900 base = mtt->com.res_id;
4901 state = mtt->com.from_state;
4902 while (state != 0) {
4904 case RES_MTT_ALLOCATED:
4905 __mlx4_free_mtt_range(dev, base,
4907 spin_lock_irq(mlx4_tlock(dev));
4908 rb_erase(&mtt->com.node,
4909 &tracker->res_tree[RES_MTT]);
4910 list_del(&mtt->com.list);
4911 spin_unlock_irq(mlx4_tlock(dev));
4912 mlx4_release_resource(dev, slave, RES_MTT,
4913 1 << mtt->order, 0);
4923 spin_lock_irq(mlx4_tlock(dev));
4925 spin_unlock_irq(mlx4_tlock(dev));
4928 static int mlx4_do_mirror_rule(struct mlx4_dev *dev, struct res_fs_rule *fs_rule)
4930 struct mlx4_cmd_mailbox *mailbox;
4932 struct res_fs_rule *mirr_rule;
4935 mailbox = mlx4_alloc_cmd_mailbox(dev);
4936 if (IS_ERR(mailbox))
4937 return PTR_ERR(mailbox);
4939 if (!fs_rule->mirr_mbox) {
4940 mlx4_err(dev, "rule mirroring mailbox is null\n");
4943 memcpy(mailbox->buf, fs_rule->mirr_mbox, fs_rule->mirr_mbox_size);
4944 err = mlx4_cmd_imm(dev, mailbox->dma, ®_id, fs_rule->mirr_mbox_size >> 2, 0,
4945 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
4947 mlx4_free_cmd_mailbox(dev, mailbox);
4952 err = add_res_range(dev, fs_rule->com.owner, reg_id, 1, RES_FS_RULE, fs_rule->qpn);
4956 err = get_res(dev, fs_rule->com.owner, reg_id, RES_FS_RULE, &mirr_rule);
4960 fs_rule->mirr_rule_id = reg_id;
4961 mirr_rule->mirr_rule_id = 0;
4962 mirr_rule->mirr_mbox_size = 0;
4963 mirr_rule->mirr_mbox = NULL;
4964 put_res(dev, fs_rule->com.owner, reg_id, RES_FS_RULE);
4968 rem_res_range(dev, fs_rule->com.owner, reg_id, 1, RES_FS_RULE, 0);
4970 mlx4_cmd(dev, reg_id, 0, 0, MLX4_QP_FLOW_STEERING_DETACH,
4971 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
4976 static int mlx4_mirror_fs_rules(struct mlx4_dev *dev, bool bond)
4978 struct mlx4_priv *priv = mlx4_priv(dev);
4979 struct mlx4_resource_tracker *tracker =
4980 &priv->mfunc.master.res_tracker;
4981 struct rb_root *root = &tracker->res_tree[RES_FS_RULE];
4983 struct res_fs_rule *fs_rule;
4985 LIST_HEAD(mirr_list);
4987 for (p = rb_first(root); p; p = rb_next(p)) {
4988 fs_rule = rb_entry(p, struct res_fs_rule, com.node);
4989 if ((bond && fs_rule->mirr_mbox_size) ||
4990 (!bond && !fs_rule->mirr_mbox_size))
4991 list_add_tail(&fs_rule->mirr_list, &mirr_list);
4994 list_for_each_entry(fs_rule, &mirr_list, mirr_list) {
4996 err += mlx4_do_mirror_rule(dev, fs_rule);
4998 err += mlx4_undo_mirror_rule(dev, fs_rule);
5003 int mlx4_bond_fs_rules(struct mlx4_dev *dev)
5005 return mlx4_mirror_fs_rules(dev, true);
5008 int mlx4_unbond_fs_rules(struct mlx4_dev *dev)
5010 return mlx4_mirror_fs_rules(dev, false);
5013 static void rem_slave_fs_rule(struct mlx4_dev *dev, int slave)
5015 struct mlx4_priv *priv = mlx4_priv(dev);
5016 struct mlx4_resource_tracker *tracker =
5017 &priv->mfunc.master.res_tracker;
5018 struct list_head *fs_rule_list =
5019 &tracker->slave_list[slave].res_list[RES_FS_RULE];
5020 struct res_fs_rule *fs_rule;
5021 struct res_fs_rule *tmp;
5026 err = move_all_busy(dev, slave, RES_FS_RULE);
5028 mlx4_warn(dev, "rem_slave_fs_rule: Could not move all mtts to busy for slave %d\n",
5031 spin_lock_irq(mlx4_tlock(dev));
5032 list_for_each_entry_safe(fs_rule, tmp, fs_rule_list, com.list) {
5033 spin_unlock_irq(mlx4_tlock(dev));
5034 if (fs_rule->com.owner == slave) {
5035 base = fs_rule->com.res_id;
5036 state = fs_rule->com.from_state;
5037 while (state != 0) {
5039 case RES_FS_RULE_ALLOCATED:
5041 err = mlx4_cmd(dev, base, 0, 0,
5042 MLX4_QP_FLOW_STEERING_DETACH,
5043 MLX4_CMD_TIME_CLASS_A,
5046 spin_lock_irq(mlx4_tlock(dev));
5047 rb_erase(&fs_rule->com.node,
5048 &tracker->res_tree[RES_FS_RULE]);
5049 list_del(&fs_rule->com.list);
5050 spin_unlock_irq(mlx4_tlock(dev));
5060 spin_lock_irq(mlx4_tlock(dev));
5062 spin_unlock_irq(mlx4_tlock(dev));
5065 static void rem_slave_eqs(struct mlx4_dev *dev, int slave)
5067 struct mlx4_priv *priv = mlx4_priv(dev);
5068 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
5069 struct list_head *eq_list =
5070 &tracker->slave_list[slave].res_list[RES_EQ];
5078 err = move_all_busy(dev, slave, RES_EQ);
5080 mlx4_warn(dev, "rem_slave_eqs: Could not move all eqs - too busy for slave %d\n",
5083 spin_lock_irq(mlx4_tlock(dev));
5084 list_for_each_entry_safe(eq, tmp, eq_list, com.list) {
5085 spin_unlock_irq(mlx4_tlock(dev));
5086 if (eq->com.owner == slave) {
5087 eqn = eq->com.res_id;
5088 state = eq->com.from_state;
5089 while (state != 0) {
5091 case RES_EQ_RESERVED:
5092 spin_lock_irq(mlx4_tlock(dev));
5093 rb_erase(&eq->com.node,
5094 &tracker->res_tree[RES_EQ]);
5095 list_del(&eq->com.list);
5096 spin_unlock_irq(mlx4_tlock(dev));
5102 err = mlx4_cmd(dev, slave, eqn & 0x3ff,
5103 1, MLX4_CMD_HW2SW_EQ,
5104 MLX4_CMD_TIME_CLASS_A,
5107 mlx4_dbg(dev, "rem_slave_eqs: failed to move slave %d eqs %d to SW ownership\n",
5108 slave, eqn & 0x3ff);
5109 atomic_dec(&eq->mtt->ref_count);
5110 state = RES_EQ_RESERVED;
5118 spin_lock_irq(mlx4_tlock(dev));
5120 spin_unlock_irq(mlx4_tlock(dev));
5123 static void rem_slave_counters(struct mlx4_dev *dev, int slave)
5125 struct mlx4_priv *priv = mlx4_priv(dev);
5126 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
5127 struct list_head *counter_list =
5128 &tracker->slave_list[slave].res_list[RES_COUNTER];
5129 struct res_counter *counter;
5130 struct res_counter *tmp;
5132 int *counters_arr = NULL;
5135 err = move_all_busy(dev, slave, RES_COUNTER);
5137 mlx4_warn(dev, "rem_slave_counters: Could not move all counters - too busy for slave %d\n",
5140 counters_arr = kmalloc_array(dev->caps.max_counters,
5141 sizeof(*counters_arr), GFP_KERNEL);
5148 spin_lock_irq(mlx4_tlock(dev));
5149 list_for_each_entry_safe(counter, tmp, counter_list, com.list) {
5150 if (counter->com.owner == slave) {
5151 counters_arr[i++] = counter->com.res_id;
5152 rb_erase(&counter->com.node,
5153 &tracker->res_tree[RES_COUNTER]);
5154 list_del(&counter->com.list);
5158 spin_unlock_irq(mlx4_tlock(dev));
5161 __mlx4_counter_free(dev, counters_arr[j++]);
5162 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
5166 kfree(counters_arr);
5169 static void rem_slave_xrcdns(struct mlx4_dev *dev, int slave)
5171 struct mlx4_priv *priv = mlx4_priv(dev);
5172 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
5173 struct list_head *xrcdn_list =
5174 &tracker->slave_list[slave].res_list[RES_XRCD];
5175 struct res_xrcdn *xrcd;
5176 struct res_xrcdn *tmp;
5180 err = move_all_busy(dev, slave, RES_XRCD);
5182 mlx4_warn(dev, "rem_slave_xrcdns: Could not move all xrcdns - too busy for slave %d\n",
5185 spin_lock_irq(mlx4_tlock(dev));
5186 list_for_each_entry_safe(xrcd, tmp, xrcdn_list, com.list) {
5187 if (xrcd->com.owner == slave) {
5188 xrcdn = xrcd->com.res_id;
5189 rb_erase(&xrcd->com.node, &tracker->res_tree[RES_XRCD]);
5190 list_del(&xrcd->com.list);
5192 __mlx4_xrcd_free(dev, xrcdn);
5195 spin_unlock_irq(mlx4_tlock(dev));
5198 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave)
5200 struct mlx4_priv *priv = mlx4_priv(dev);
5201 mlx4_reset_roce_gids(dev, slave);
5202 mutex_lock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
5203 rem_slave_vlans(dev, slave);
5204 rem_slave_macs(dev, slave);
5205 rem_slave_fs_rule(dev, slave);
5206 rem_slave_qps(dev, slave);
5207 rem_slave_srqs(dev, slave);
5208 rem_slave_cqs(dev, slave);
5209 rem_slave_mrs(dev, slave);
5210 rem_slave_eqs(dev, slave);
5211 rem_slave_mtts(dev, slave);
5212 rem_slave_counters(dev, slave);
5213 rem_slave_xrcdns(dev, slave);
5214 mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
5217 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work)
5219 struct mlx4_vf_immed_vlan_work *work =
5220 container_of(_work, struct mlx4_vf_immed_vlan_work, work);
5221 struct mlx4_cmd_mailbox *mailbox;
5222 struct mlx4_update_qp_context *upd_context;
5223 struct mlx4_dev *dev = &work->priv->dev;
5224 struct mlx4_resource_tracker *tracker =
5225 &work->priv->mfunc.master.res_tracker;
5226 struct list_head *qp_list =
5227 &tracker->slave_list[work->slave].res_list[RES_QP];
5230 u64 qp_path_mask_vlan_ctrl =
5231 ((1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED) |
5232 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P) |
5233 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED) |
5234 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED) |
5235 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P) |
5236 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED));
5238 u64 qp_path_mask = ((1ULL << MLX4_UPD_QP_PATH_MASK_VLAN_INDEX) |
5239 (1ULL << MLX4_UPD_QP_PATH_MASK_FVL) |
5240 (1ULL << MLX4_UPD_QP_PATH_MASK_CV) |
5241 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN) |
5242 (1ULL << MLX4_UPD_QP_PATH_MASK_FEUP) |
5243 (1ULL << MLX4_UPD_QP_PATH_MASK_FVL_RX) |
5244 (1ULL << MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE));
5247 int port, errors = 0;
5250 if (mlx4_is_slave(dev)) {
5251 mlx4_warn(dev, "Trying to update-qp in slave %d\n",
5256 mailbox = mlx4_alloc_cmd_mailbox(dev);
5257 if (IS_ERR(mailbox))
5259 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE) /* block all */
5260 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
5261 MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED |
5262 MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED |
5263 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
5264 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED |
5265 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
5266 else if (!work->vlan_id)
5267 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
5268 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
5270 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
5271 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
5272 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
5274 upd_context = mailbox->buf;
5275 upd_context->qp_mask = cpu_to_be64(1ULL << MLX4_UPD_QP_MASK_VSD);
5277 spin_lock_irq(mlx4_tlock(dev));
5278 list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
5279 spin_unlock_irq(mlx4_tlock(dev));
5280 if (qp->com.owner == work->slave) {
5281 if (qp->com.from_state != RES_QP_HW ||
5282 !qp->sched_queue || /* no INIT2RTR trans yet */
5283 mlx4_is_qp_reserved(dev, qp->local_qpn) ||
5284 qp->qpc_flags & (1 << MLX4_RSS_QPC_FLAG_OFFSET)) {
5285 spin_lock_irq(mlx4_tlock(dev));
5288 port = (qp->sched_queue >> 6 & 1) + 1;
5289 if (port != work->port) {
5290 spin_lock_irq(mlx4_tlock(dev));
5293 if (MLX4_QP_ST_RC == ((qp->qpc_flags >> 16) & 0xff))
5294 upd_context->primary_addr_path_mask = cpu_to_be64(qp_path_mask);
5296 upd_context->primary_addr_path_mask =
5297 cpu_to_be64(qp_path_mask | qp_path_mask_vlan_ctrl);
5298 if (work->vlan_id == MLX4_VGT) {
5299 upd_context->qp_context.param3 = qp->param3;
5300 upd_context->qp_context.pri_path.vlan_control = qp->vlan_control;
5301 upd_context->qp_context.pri_path.fvl_rx = qp->fvl_rx;
5302 upd_context->qp_context.pri_path.vlan_index = qp->vlan_index;
5303 upd_context->qp_context.pri_path.fl = qp->pri_path_fl;
5304 upd_context->qp_context.pri_path.feup = qp->feup;
5305 upd_context->qp_context.pri_path.sched_queue =
5308 upd_context->qp_context.param3 = qp->param3 & ~cpu_to_be32(MLX4_STRIP_VLAN);
5309 upd_context->qp_context.pri_path.vlan_control = vlan_control;
5310 upd_context->qp_context.pri_path.vlan_index = work->vlan_ix;
5311 upd_context->qp_context.pri_path.fvl_rx =
5312 qp->fvl_rx | MLX4_FVL_RX_FORCE_ETH_VLAN;
5313 upd_context->qp_context.pri_path.fl =
5314 qp->pri_path_fl | MLX4_FL_CV | MLX4_FL_ETH_HIDE_CQE_VLAN;
5315 upd_context->qp_context.pri_path.feup =
5316 qp->feup | MLX4_FEUP_FORCE_ETH_UP | MLX4_FVL_FORCE_ETH_VLAN;
5317 upd_context->qp_context.pri_path.sched_queue =
5318 qp->sched_queue & 0xC7;
5319 upd_context->qp_context.pri_path.sched_queue |=
5320 ((work->qos & 0x7) << 3);
5321 upd_context->qp_mask |=
5323 MLX4_UPD_QP_MASK_QOS_VPP);
5324 upd_context->qp_context.qos_vport =
5328 err = mlx4_cmd(dev, mailbox->dma,
5329 qp->local_qpn & 0xffffff,
5330 0, MLX4_CMD_UPDATE_QP,
5331 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
5333 mlx4_info(dev, "UPDATE_QP failed for slave %d, port %d, qpn %d (%d)\n",
5334 work->slave, port, qp->local_qpn, err);
5338 spin_lock_irq(mlx4_tlock(dev));
5340 spin_unlock_irq(mlx4_tlock(dev));
5341 mlx4_free_cmd_mailbox(dev, mailbox);
5344 mlx4_err(dev, "%d UPDATE_QP failures for slave %d, port %d\n",
5345 errors, work->slave, work->port);
5347 /* unregister previous vlan_id if needed and we had no errors
5348 * while updating the QPs
5350 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN && !errors &&
5351 NO_INDX != work->orig_vlan_ix)
5352 __mlx4_unregister_vlan(&work->priv->dev, work->port,
5353 work->orig_vlan_id);