2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/gfp.h>
37 #include <linux/export.h>
39 #include <linux/mlx4/cmd.h>
40 #include <linux/mlx4/qp.h>
45 /* QP to support BF should have bits 6,7 cleared */
46 #define MLX4_BF_QP_SKIP_MASK 0xc0
47 #define MLX4_MAX_BF_QP_RANGE 0x40
49 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type)
51 struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
54 spin_lock(&qp_table->lock);
56 qp = __mlx4_qp_lookup(dev, qpn);
58 atomic_inc(&qp->refcount);
60 spin_unlock(&qp_table->lock);
63 mlx4_dbg(dev, "Async event for none existent QP %08x\n", qpn);
67 qp->event(qp, event_type);
69 if (atomic_dec_and_test(&qp->refcount))
73 /* used for INIT/CLOSE port logic */
74 static int is_master_qp0(struct mlx4_dev *dev, struct mlx4_qp *qp, int *real_qp0, int *proxy_qp0)
76 /* this procedure is called after we already know we are on the master */
77 /* qp0 is either the proxy qp0, or the real qp0 */
78 u32 pf_proxy_offset = dev->phys_caps.base_proxy_sqpn + 8 * mlx4_master_func_num(dev);
79 *proxy_qp0 = qp->qpn >= pf_proxy_offset && qp->qpn <= pf_proxy_offset + 1;
81 *real_qp0 = qp->qpn >= dev->phys_caps.base_sqpn &&
82 qp->qpn <= dev->phys_caps.base_sqpn + 1;
84 return *real_qp0 || *proxy_qp0;
87 static int __mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
88 enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
89 struct mlx4_qp_context *context,
90 enum mlx4_qp_optpar optpar,
91 int sqd_event, struct mlx4_qp *qp, int native)
93 static const u16 op[MLX4_QP_NUM_STATE][MLX4_QP_NUM_STATE] = {
94 [MLX4_QP_STATE_RST] = {
95 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
96 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
97 [MLX4_QP_STATE_INIT] = MLX4_CMD_RST2INIT_QP,
99 [MLX4_QP_STATE_INIT] = {
100 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
101 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
102 [MLX4_QP_STATE_INIT] = MLX4_CMD_INIT2INIT_QP,
103 [MLX4_QP_STATE_RTR] = MLX4_CMD_INIT2RTR_QP,
105 [MLX4_QP_STATE_RTR] = {
106 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
107 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
108 [MLX4_QP_STATE_RTS] = MLX4_CMD_RTR2RTS_QP,
110 [MLX4_QP_STATE_RTS] = {
111 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
112 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
113 [MLX4_QP_STATE_RTS] = MLX4_CMD_RTS2RTS_QP,
114 [MLX4_QP_STATE_SQD] = MLX4_CMD_RTS2SQD_QP,
116 [MLX4_QP_STATE_SQD] = {
117 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
118 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
119 [MLX4_QP_STATE_RTS] = MLX4_CMD_SQD2RTS_QP,
120 [MLX4_QP_STATE_SQD] = MLX4_CMD_SQD2SQD_QP,
122 [MLX4_QP_STATE_SQER] = {
123 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
124 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
125 [MLX4_QP_STATE_RTS] = MLX4_CMD_SQERR2RTS_QP,
127 [MLX4_QP_STATE_ERR] = {
128 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
129 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
133 struct mlx4_priv *priv = mlx4_priv(dev);
134 struct mlx4_cmd_mailbox *mailbox;
140 if (cur_state >= MLX4_QP_NUM_STATE || new_state >= MLX4_QP_NUM_STATE ||
141 !op[cur_state][new_state])
144 if (op[cur_state][new_state] == MLX4_CMD_2RST_QP) {
145 ret = mlx4_cmd(dev, 0, qp->qpn, 2,
146 MLX4_CMD_2RST_QP, MLX4_CMD_TIME_CLASS_A, native);
147 if (mlx4_is_master(dev) && cur_state != MLX4_QP_STATE_ERR &&
148 cur_state != MLX4_QP_STATE_RST &&
149 is_master_qp0(dev, qp, &real_qp0, &proxy_qp0)) {
150 port = (qp->qpn & 1) + 1;
152 priv->mfunc.master.qp0_state[port].proxy_qp0_active = 0;
154 priv->mfunc.master.qp0_state[port].qp0_active = 0;
159 mailbox = mlx4_alloc_cmd_mailbox(dev);
161 return PTR_ERR(mailbox);
163 if (cur_state == MLX4_QP_STATE_RST && new_state == MLX4_QP_STATE_INIT) {
164 u64 mtt_addr = mlx4_mtt_addr(dev, mtt);
165 context->mtt_base_addr_h = mtt_addr >> 32;
166 context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
167 context->log_page_size = mtt->page_shift - MLX4_ICM_PAGE_SHIFT;
170 *(__be32 *) mailbox->buf = cpu_to_be32(optpar);
171 memcpy(mailbox->buf + 8, context, sizeof *context);
173 ((struct mlx4_qp_context *) (mailbox->buf + 8))->local_qpn =
174 cpu_to_be32(qp->qpn);
176 ret = mlx4_cmd(dev, mailbox->dma,
177 qp->qpn | (!!sqd_event << 31),
178 new_state == MLX4_QP_STATE_RST ? 2 : 0,
179 op[cur_state][new_state], MLX4_CMD_TIME_CLASS_C, native);
181 if (mlx4_is_master(dev) && is_master_qp0(dev, qp, &real_qp0, &proxy_qp0)) {
182 port = (qp->qpn & 1) + 1;
183 if (cur_state != MLX4_QP_STATE_ERR &&
184 cur_state != MLX4_QP_STATE_RST &&
185 new_state == MLX4_QP_STATE_ERR) {
187 priv->mfunc.master.qp0_state[port].proxy_qp0_active = 0;
189 priv->mfunc.master.qp0_state[port].qp0_active = 0;
190 } else if (new_state == MLX4_QP_STATE_RTR) {
192 priv->mfunc.master.qp0_state[port].proxy_qp0_active = 1;
194 priv->mfunc.master.qp0_state[port].qp0_active = 1;
198 mlx4_free_cmd_mailbox(dev, mailbox);
202 int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
203 enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
204 struct mlx4_qp_context *context,
205 enum mlx4_qp_optpar optpar,
206 int sqd_event, struct mlx4_qp *qp)
208 return __mlx4_qp_modify(dev, mtt, cur_state, new_state, context,
209 optpar, sqd_event, qp, 0);
211 EXPORT_SYMBOL_GPL(mlx4_qp_modify);
213 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
216 int bf_qp = !!(flags & (u8)MLX4_RESERVE_ETH_BF_QP);
218 struct mlx4_priv *priv = mlx4_priv(dev);
219 struct mlx4_qp_table *qp_table = &priv->qp_table;
221 if (cnt > MLX4_MAX_BF_QP_RANGE && bf_qp)
224 *base = mlx4_bitmap_alloc_range(&qp_table->bitmap, cnt, align,
225 bf_qp ? MLX4_BF_QP_SKIP_MASK : 0);
232 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
239 /* Turn off all unsupported QP allocation flags */
240 flags &= dev->caps.alloc_res_qp_mask;
242 if (mlx4_is_mfunc(dev)) {
243 set_param_l(&in_param, (((u32)flags) << 24) | (u32)cnt);
244 set_param_h(&in_param, align);
245 err = mlx4_cmd_imm(dev, in_param, &out_param,
246 RES_QP, RES_OP_RESERVE,
248 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
252 *base = get_param_l(&out_param);
255 return __mlx4_qp_reserve_range(dev, cnt, align, base, flags);
257 EXPORT_SYMBOL_GPL(mlx4_qp_reserve_range);
259 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt)
261 struct mlx4_priv *priv = mlx4_priv(dev);
262 struct mlx4_qp_table *qp_table = &priv->qp_table;
264 if (mlx4_is_qp_reserved(dev, (u32) base_qpn))
266 mlx4_bitmap_free_range(&qp_table->bitmap, base_qpn, cnt, MLX4_USE_RR);
269 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt)
274 if (mlx4_is_mfunc(dev)) {
275 set_param_l(&in_param, base_qpn);
276 set_param_h(&in_param, cnt);
277 err = mlx4_cmd(dev, in_param, RES_QP, RES_OP_RESERVE,
279 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
281 mlx4_warn(dev, "Failed to release qp range base:%d cnt:%d\n",
285 __mlx4_qp_release_range(dev, base_qpn, cnt);
287 EXPORT_SYMBOL_GPL(mlx4_qp_release_range);
289 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn, gfp_t gfp)
291 struct mlx4_priv *priv = mlx4_priv(dev);
292 struct mlx4_qp_table *qp_table = &priv->qp_table;
295 err = mlx4_table_get(dev, &qp_table->qp_table, qpn, gfp);
299 err = mlx4_table_get(dev, &qp_table->auxc_table, qpn, gfp);
303 err = mlx4_table_get(dev, &qp_table->altc_table, qpn, gfp);
307 err = mlx4_table_get(dev, &qp_table->rdmarc_table, qpn, gfp);
311 err = mlx4_table_get(dev, &qp_table->cmpt_table, qpn, gfp);
318 mlx4_table_put(dev, &qp_table->rdmarc_table, qpn);
321 mlx4_table_put(dev, &qp_table->altc_table, qpn);
324 mlx4_table_put(dev, &qp_table->auxc_table, qpn);
327 mlx4_table_put(dev, &qp_table->qp_table, qpn);
333 static int mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn, gfp_t gfp)
337 if (mlx4_is_mfunc(dev)) {
338 set_param_l(¶m, qpn);
339 return mlx4_cmd_imm(dev, param, ¶m, RES_QP, RES_OP_MAP_ICM,
340 MLX4_CMD_ALLOC_RES, MLX4_CMD_TIME_CLASS_A,
343 return __mlx4_qp_alloc_icm(dev, qpn, gfp);
346 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn)
348 struct mlx4_priv *priv = mlx4_priv(dev);
349 struct mlx4_qp_table *qp_table = &priv->qp_table;
351 mlx4_table_put(dev, &qp_table->cmpt_table, qpn);
352 mlx4_table_put(dev, &qp_table->rdmarc_table, qpn);
353 mlx4_table_put(dev, &qp_table->altc_table, qpn);
354 mlx4_table_put(dev, &qp_table->auxc_table, qpn);
355 mlx4_table_put(dev, &qp_table->qp_table, qpn);
358 static void mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn)
362 if (mlx4_is_mfunc(dev)) {
363 set_param_l(&in_param, qpn);
364 if (mlx4_cmd(dev, in_param, RES_QP, RES_OP_MAP_ICM,
365 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
367 mlx4_warn(dev, "Failed to free icm of qp:%d\n", qpn);
369 __mlx4_qp_free_icm(dev, qpn);
372 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp, gfp_t gfp)
374 struct mlx4_priv *priv = mlx4_priv(dev);
375 struct mlx4_qp_table *qp_table = &priv->qp_table;
383 err = mlx4_qp_alloc_icm(dev, qpn, gfp);
387 spin_lock_irq(&qp_table->lock);
388 err = radix_tree_insert(&dev->qp_table_tree, qp->qpn &
389 (dev->caps.num_qps - 1), qp);
390 spin_unlock_irq(&qp_table->lock);
394 atomic_set(&qp->refcount, 1);
395 init_completion(&qp->free);
400 mlx4_qp_free_icm(dev, qpn);
404 EXPORT_SYMBOL_GPL(mlx4_qp_alloc);
406 #define MLX4_UPDATE_QP_SUPPORTED_ATTRS MLX4_UPDATE_QP_SMAC
407 int mlx4_update_qp(struct mlx4_dev *dev, u32 qpn,
408 enum mlx4_update_qp_attr attr,
409 struct mlx4_update_qp_params *params)
411 struct mlx4_cmd_mailbox *mailbox;
412 struct mlx4_update_qp_context *cmd;
413 u64 pri_addr_path_mask = 0;
417 mailbox = mlx4_alloc_cmd_mailbox(dev);
419 return PTR_ERR(mailbox);
421 cmd = (struct mlx4_update_qp_context *)mailbox->buf;
423 if (!attr || (attr & ~MLX4_UPDATE_QP_SUPPORTED_ATTRS))
426 if (attr & MLX4_UPDATE_QP_SMAC) {
427 pri_addr_path_mask |= 1ULL << MLX4_UPD_QP_PATH_MASK_MAC_INDEX;
428 cmd->qp_context.pri_path.grh_mylmc = params->smac_index;
431 if (attr & MLX4_UPDATE_QP_VSD) {
432 qp_mask |= 1ULL << MLX4_UPD_QP_MASK_VSD;
433 if (params->flags & MLX4_UPDATE_QP_PARAMS_FLAGS_VSD_ENABLE)
434 cmd->qp_context.param3 |= cpu_to_be32(MLX4_STRIP_VLAN);
437 cmd->primary_addr_path_mask = cpu_to_be64(pri_addr_path_mask);
438 cmd->qp_mask = cpu_to_be64(qp_mask);
440 err = mlx4_cmd(dev, mailbox->dma, qpn & 0xffffff, 0,
441 MLX4_CMD_UPDATE_QP, MLX4_CMD_TIME_CLASS_A,
444 mlx4_free_cmd_mailbox(dev, mailbox);
447 EXPORT_SYMBOL_GPL(mlx4_update_qp);
449 void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp)
451 struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
454 spin_lock_irqsave(&qp_table->lock, flags);
455 radix_tree_delete(&dev->qp_table_tree, qp->qpn & (dev->caps.num_qps - 1));
456 spin_unlock_irqrestore(&qp_table->lock, flags);
458 EXPORT_SYMBOL_GPL(mlx4_qp_remove);
460 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp)
462 if (atomic_dec_and_test(&qp->refcount))
464 wait_for_completion(&qp->free);
466 mlx4_qp_free_icm(dev, qp->qpn);
468 EXPORT_SYMBOL_GPL(mlx4_qp_free);
470 static int mlx4_CONF_SPECIAL_QP(struct mlx4_dev *dev, u32 base_qpn)
472 return mlx4_cmd(dev, 0, base_qpn, 0, MLX4_CMD_CONF_SPECIAL_QP,
473 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
476 int mlx4_init_qp_table(struct mlx4_dev *dev)
478 struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
480 int reserved_from_top = 0;
483 spin_lock_init(&qp_table->lock);
484 INIT_RADIX_TREE(&dev->qp_table_tree, GFP_ATOMIC);
485 if (mlx4_is_slave(dev))
489 * We reserve 2 extra QPs per port for the special QPs. The
490 * block of special QPs must be aligned to a multiple of 8, so
493 * We also reserve the MSB of the 24-bit QP number to indicate
494 * that a QP is an XRC QP.
496 dev->phys_caps.base_sqpn =
497 ALIGN(dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 8);
500 int sort[MLX4_NUM_QP_REGION];
502 int last_base = dev->caps.num_qps;
504 for (i = 1; i < MLX4_NUM_QP_REGION; ++i)
507 for (i = MLX4_NUM_QP_REGION; i > 0; --i) {
508 for (j = 2; j < i; ++j) {
509 if (dev->caps.reserved_qps_cnt[sort[j]] >
510 dev->caps.reserved_qps_cnt[sort[j - 1]]) {
512 sort[j] = sort[j - 1];
518 for (i = 1; i < MLX4_NUM_QP_REGION; ++i) {
519 last_base -= dev->caps.reserved_qps_cnt[sort[i]];
520 dev->caps.reserved_qps_base[sort[i]] = last_base;
522 dev->caps.reserved_qps_cnt[sort[i]];
527 /* Reserve 8 real SQPs in both native and SRIOV modes.
528 * In addition, in SRIOV mode, reserve 8 proxy SQPs per function
529 * (for all PFs and VFs), and 8 corresponding tunnel QPs.
530 * Each proxy SQP works opposite its own tunnel QP.
532 * The QPs are arranged as follows:
534 * b. All the proxy SQPs (8 per function)
535 * c. All the tunnel QPs (8 per function)
538 err = mlx4_bitmap_init(&qp_table->bitmap, dev->caps.num_qps,
539 (1 << 23) - 1, mlx4_num_reserved_sqps(dev),
544 if (mlx4_is_mfunc(dev)) {
546 dev->phys_caps.base_proxy_sqpn = dev->phys_caps.base_sqpn + 8;
547 dev->phys_caps.base_tunnel_sqpn = dev->phys_caps.base_sqpn + 8 + 8 * MLX4_MFUNC_MAX;
549 /* In mfunc, calculate proxy and tunnel qp offsets for the PF here,
550 * since the PF does not call mlx4_slave_caps */
551 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
552 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
553 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
554 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
556 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
557 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy) {
562 for (k = 0; k < dev->caps.num_ports; k++) {
563 dev->caps.qp0_proxy[k] = dev->phys_caps.base_proxy_sqpn +
564 8 * mlx4_master_func_num(dev) + k;
565 dev->caps.qp0_tunnel[k] = dev->caps.qp0_proxy[k] + 8 * MLX4_MFUNC_MAX;
566 dev->caps.qp1_proxy[k] = dev->phys_caps.base_proxy_sqpn +
567 8 * mlx4_master_func_num(dev) + MLX4_MAX_PORTS + k;
568 dev->caps.qp1_tunnel[k] = dev->caps.qp1_proxy[k] + 8 * MLX4_MFUNC_MAX;
573 err = mlx4_CONF_SPECIAL_QP(dev, dev->phys_caps.base_sqpn);
579 kfree(dev->caps.qp0_tunnel);
580 kfree(dev->caps.qp0_proxy);
581 kfree(dev->caps.qp1_tunnel);
582 kfree(dev->caps.qp1_proxy);
583 dev->caps.qp0_tunnel = dev->caps.qp0_proxy =
584 dev->caps.qp1_tunnel = dev->caps.qp1_proxy = NULL;
588 void mlx4_cleanup_qp_table(struct mlx4_dev *dev)
590 if (mlx4_is_slave(dev))
593 mlx4_CONF_SPECIAL_QP(dev, 0);
594 mlx4_bitmap_cleanup(&mlx4_priv(dev)->qp_table.bitmap);
597 int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp,
598 struct mlx4_qp_context *context)
600 struct mlx4_cmd_mailbox *mailbox;
603 mailbox = mlx4_alloc_cmd_mailbox(dev);
605 return PTR_ERR(mailbox);
607 err = mlx4_cmd_box(dev, 0, mailbox->dma, qp->qpn, 0,
608 MLX4_CMD_QUERY_QP, MLX4_CMD_TIME_CLASS_A,
611 memcpy(context, mailbox->buf + 8, sizeof *context);
613 mlx4_free_cmd_mailbox(dev, mailbox);
616 EXPORT_SYMBOL_GPL(mlx4_qp_query);
618 int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
619 struct mlx4_qp_context *context,
620 struct mlx4_qp *qp, enum mlx4_qp_state *qp_state)
624 enum mlx4_qp_state states[] = {
631 for (i = 0; i < ARRAY_SIZE(states) - 1; i++) {
632 context->flags &= cpu_to_be32(~(0xf << 28));
633 context->flags |= cpu_to_be32(states[i + 1] << 28);
634 err = mlx4_qp_modify(dev, mtt, states[i], states[i + 1],
637 mlx4_err(dev, "Failed to bring QP to state: %d with error: %d\n",
642 *qp_state = states[i + 1];
647 EXPORT_SYMBOL_GPL(mlx4_qp_to_ready);