2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/errno.h>
36 #include <linux/export.h>
37 #include <linux/slab.h>
38 #include <linux/kernel.h>
39 #include <linux/vmalloc.h>
41 #include <linux/mlx4/cmd.h>
46 static u32 mlx4_buddy_alloc(struct mlx4_buddy *buddy, int order)
52 spin_lock(&buddy->lock);
54 for (o = order; o <= buddy->max_order; ++o)
55 if (buddy->num_free[o]) {
56 m = 1 << (buddy->max_order - o);
57 seg = find_first_bit(buddy->bits[o], m);
62 spin_unlock(&buddy->lock);
66 clear_bit(seg, buddy->bits[o]);
72 set_bit(seg ^ 1, buddy->bits[o]);
76 spin_unlock(&buddy->lock);
83 static void mlx4_buddy_free(struct mlx4_buddy *buddy, u32 seg, int order)
87 spin_lock(&buddy->lock);
89 while (test_bit(seg ^ 1, buddy->bits[order])) {
90 clear_bit(seg ^ 1, buddy->bits[order]);
91 --buddy->num_free[order];
96 set_bit(seg, buddy->bits[order]);
97 ++buddy->num_free[order];
99 spin_unlock(&buddy->lock);
102 static int mlx4_buddy_init(struct mlx4_buddy *buddy, int max_order)
106 buddy->max_order = max_order;
107 spin_lock_init(&buddy->lock);
109 buddy->bits = kcalloc(buddy->max_order + 1, sizeof (long *),
111 buddy->num_free = kcalloc((buddy->max_order + 1), sizeof *buddy->num_free,
113 if (!buddy->bits || !buddy->num_free)
116 for (i = 0; i <= buddy->max_order; ++i) {
117 s = BITS_TO_LONGS(1 << (buddy->max_order - i));
118 buddy->bits[i] = kcalloc(s, sizeof (long), GFP_KERNEL | __GFP_NOWARN);
119 if (!buddy->bits[i]) {
120 buddy->bits[i] = vzalloc(s * sizeof(long));
126 set_bit(0, buddy->bits[buddy->max_order]);
127 buddy->num_free[buddy->max_order] = 1;
132 for (i = 0; i <= buddy->max_order; ++i)
133 if (buddy->bits[i] && is_vmalloc_addr(buddy->bits[i]))
134 vfree(buddy->bits[i]);
136 kfree(buddy->bits[i]);
140 kfree(buddy->num_free);
145 static void mlx4_buddy_cleanup(struct mlx4_buddy *buddy)
149 for (i = 0; i <= buddy->max_order; ++i)
150 if (is_vmalloc_addr(buddy->bits[i]))
151 vfree(buddy->bits[i]);
153 kfree(buddy->bits[i]);
156 kfree(buddy->num_free);
159 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order)
161 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
166 seg_order = max_t(int, order - log_mtts_per_seg, 0);
168 seg = mlx4_buddy_alloc(&mr_table->mtt_buddy, seg_order);
172 offset = seg * (1 << log_mtts_per_seg);
174 if (mlx4_table_get_range(dev, &mr_table->mtt_table, offset,
175 offset + (1 << order) - 1)) {
176 mlx4_buddy_free(&mr_table->mtt_buddy, seg, seg_order);
183 static u32 mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order)
189 if (mlx4_is_mfunc(dev)) {
190 set_param_l(&in_param, order);
191 err = mlx4_cmd_imm(dev, in_param, &out_param, RES_MTT,
192 RES_OP_RESERVE_AND_MAP,
194 MLX4_CMD_TIME_CLASS_A,
198 return get_param_l(&out_param);
200 return __mlx4_alloc_mtt_range(dev, order);
203 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
204 struct mlx4_mtt *mtt)
210 mtt->page_shift = MLX4_ICM_PAGE_SHIFT;
213 mtt->page_shift = page_shift;
215 for (mtt->order = 0, i = 1; i < npages; i <<= 1)
218 mtt->offset = mlx4_alloc_mtt_range(dev, mtt->order);
219 if (mtt->offset == -1)
224 EXPORT_SYMBOL_GPL(mlx4_mtt_init);
226 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 offset, int order)
230 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
232 seg_order = max_t(int, order - log_mtts_per_seg, 0);
233 first_seg = offset / (1 << log_mtts_per_seg);
235 mlx4_buddy_free(&mr_table->mtt_buddy, first_seg, seg_order);
236 mlx4_table_put_range(dev, &mr_table->mtt_table, offset,
237 offset + (1 << order) - 1);
240 static void mlx4_free_mtt_range(struct mlx4_dev *dev, u32 offset, int order)
245 if (mlx4_is_mfunc(dev)) {
246 set_param_l(&in_param, offset);
247 set_param_h(&in_param, order);
248 err = mlx4_cmd(dev, in_param, RES_MTT, RES_OP_RESERVE_AND_MAP,
250 MLX4_CMD_TIME_CLASS_A,
253 mlx4_warn(dev, "Failed to free mtt range at:%d order:%d\n",
257 __mlx4_free_mtt_range(dev, offset, order);
260 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt)
265 mlx4_free_mtt_range(dev, mtt->offset, mtt->order);
267 EXPORT_SYMBOL_GPL(mlx4_mtt_cleanup);
269 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt)
271 return (u64) mtt->offset * dev->caps.mtt_entry_sz;
273 EXPORT_SYMBOL_GPL(mlx4_mtt_addr);
275 static u32 hw_index_to_key(u32 ind)
277 return (ind >> 24) | (ind << 8);
280 static u32 key_to_hw_index(u32 key)
282 return (key << 24) | (key >> 8);
285 static int mlx4_SW2HW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
288 return mlx4_cmd(dev, mailbox->dma, mpt_index,
289 0, MLX4_CMD_SW2HW_MPT, MLX4_CMD_TIME_CLASS_B,
293 static int mlx4_HW2SW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
296 return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index,
297 !mailbox, MLX4_CMD_HW2SW_MPT,
298 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
301 static int mlx4_mr_alloc_reserved(struct mlx4_dev *dev, u32 mridx, u32 pd,
302 u64 iova, u64 size, u32 access, int npages,
303 int page_shift, struct mlx4_mr *mr)
309 mr->enabled = MLX4_MPT_DISABLED;
310 mr->key = hw_index_to_key(mridx);
312 return mlx4_mtt_init(dev, npages, page_shift, &mr->mtt);
315 static int mlx4_WRITE_MTT(struct mlx4_dev *dev,
316 struct mlx4_cmd_mailbox *mailbox,
319 return mlx4_cmd(dev, mailbox->dma, num_entries, 0, MLX4_CMD_WRITE_MTT,
320 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
323 int __mlx4_mpt_reserve(struct mlx4_dev *dev)
325 struct mlx4_priv *priv = mlx4_priv(dev);
327 return mlx4_bitmap_alloc(&priv->mr_table.mpt_bitmap);
330 static int mlx4_mpt_reserve(struct mlx4_dev *dev)
334 if (mlx4_is_mfunc(dev)) {
335 if (mlx4_cmd_imm(dev, 0, &out_param, RES_MPT, RES_OP_RESERVE,
337 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED))
339 return get_param_l(&out_param);
341 return __mlx4_mpt_reserve(dev);
344 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index)
346 struct mlx4_priv *priv = mlx4_priv(dev);
348 mlx4_bitmap_free(&priv->mr_table.mpt_bitmap, index, MLX4_NO_RR);
351 static void mlx4_mpt_release(struct mlx4_dev *dev, u32 index)
355 if (mlx4_is_mfunc(dev)) {
356 set_param_l(&in_param, index);
357 if (mlx4_cmd(dev, in_param, RES_MPT, RES_OP_RESERVE,
359 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED))
360 mlx4_warn(dev, "Failed to release mr index:%d\n",
364 __mlx4_mpt_release(dev, index);
367 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index, gfp_t gfp)
369 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
371 return mlx4_table_get(dev, &mr_table->dmpt_table, index, gfp);
374 static int mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index, gfp_t gfp)
378 if (mlx4_is_mfunc(dev)) {
379 set_param_l(¶m, index);
380 return mlx4_cmd_imm(dev, param, ¶m, RES_MPT, RES_OP_MAP_ICM,
382 MLX4_CMD_TIME_CLASS_A,
385 return __mlx4_mpt_alloc_icm(dev, index, gfp);
388 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index)
390 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
392 mlx4_table_put(dev, &mr_table->dmpt_table, index);
395 static void mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index)
399 if (mlx4_is_mfunc(dev)) {
400 set_param_l(&in_param, index);
401 if (mlx4_cmd(dev, in_param, RES_MPT, RES_OP_MAP_ICM,
402 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
404 mlx4_warn(dev, "Failed to free icm of mr index:%d\n",
408 return __mlx4_mpt_free_icm(dev, index);
411 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
412 int npages, int page_shift, struct mlx4_mr *mr)
417 index = mlx4_mpt_reserve(dev);
421 err = mlx4_mr_alloc_reserved(dev, index, pd, iova, size,
422 access, npages, page_shift, mr);
424 mlx4_mpt_release(dev, index);
428 EXPORT_SYMBOL_GPL(mlx4_mr_alloc);
430 static int mlx4_mr_free_reserved(struct mlx4_dev *dev, struct mlx4_mr *mr)
434 if (mr->enabled == MLX4_MPT_EN_HW) {
435 err = mlx4_HW2SW_MPT(dev, NULL,
436 key_to_hw_index(mr->key) &
437 (dev->caps.num_mpts - 1));
439 mlx4_warn(dev, "HW2SW_MPT failed (%d), MR has MWs bound to it\n",
444 mr->enabled = MLX4_MPT_EN_SW;
446 mlx4_mtt_cleanup(dev, &mr->mtt);
451 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr)
455 ret = mlx4_mr_free_reserved(dev, mr);
459 mlx4_mpt_free_icm(dev, key_to_hw_index(mr->key));
460 mlx4_mpt_release(dev, key_to_hw_index(mr->key));
464 EXPORT_SYMBOL_GPL(mlx4_mr_free);
466 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr)
468 struct mlx4_cmd_mailbox *mailbox;
469 struct mlx4_mpt_entry *mpt_entry;
472 err = mlx4_mpt_alloc_icm(dev, key_to_hw_index(mr->key), GFP_KERNEL);
476 mailbox = mlx4_alloc_cmd_mailbox(dev);
477 if (IS_ERR(mailbox)) {
478 err = PTR_ERR(mailbox);
481 mpt_entry = mailbox->buf;
482 mpt_entry->flags = cpu_to_be32(MLX4_MPT_FLAG_MIO |
483 MLX4_MPT_FLAG_REGION |
486 mpt_entry->key = cpu_to_be32(key_to_hw_index(mr->key));
487 mpt_entry->pd_flags = cpu_to_be32(mr->pd | MLX4_MPT_PD_FLAG_EN_INV);
488 mpt_entry->start = cpu_to_be64(mr->iova);
489 mpt_entry->length = cpu_to_be64(mr->size);
490 mpt_entry->entity_size = cpu_to_be32(mr->mtt.page_shift);
492 if (mr->mtt.order < 0) {
493 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_PHYSICAL);
494 mpt_entry->mtt_addr = 0;
496 mpt_entry->mtt_addr = cpu_to_be64(mlx4_mtt_addr(dev,
500 if (mr->mtt.order >= 0 && mr->mtt.page_shift == 0) {
501 /* fast register MR in free state */
502 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_FREE);
503 mpt_entry->pd_flags |= cpu_to_be32(MLX4_MPT_PD_FLAG_FAST_REG |
504 MLX4_MPT_PD_FLAG_RAE);
505 mpt_entry->mtt_sz = cpu_to_be32(1 << mr->mtt.order);
507 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_SW_OWNS);
510 err = mlx4_SW2HW_MPT(dev, mailbox,
511 key_to_hw_index(mr->key) & (dev->caps.num_mpts - 1));
513 mlx4_warn(dev, "SW2HW_MPT failed (%d)\n", err);
516 mr->enabled = MLX4_MPT_EN_HW;
518 mlx4_free_cmd_mailbox(dev, mailbox);
523 mlx4_free_cmd_mailbox(dev, mailbox);
526 mlx4_mpt_free_icm(dev, key_to_hw_index(mr->key));
529 EXPORT_SYMBOL_GPL(mlx4_mr_enable);
531 static int mlx4_write_mtt_chunk(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
532 int start_index, int npages, u64 *page_list)
534 struct mlx4_priv *priv = mlx4_priv(dev);
536 dma_addr_t dma_handle;
539 mtts = mlx4_table_find(&priv->mr_table.mtt_table, mtt->offset +
540 start_index, &dma_handle);
545 dma_sync_single_for_cpu(&dev->pdev->dev, dma_handle,
546 npages * sizeof (u64), DMA_TO_DEVICE);
548 for (i = 0; i < npages; ++i)
549 mtts[i] = cpu_to_be64(page_list[i] | MLX4_MTT_FLAG_PRESENT);
551 dma_sync_single_for_device(&dev->pdev->dev, dma_handle,
552 npages * sizeof (u64), DMA_TO_DEVICE);
557 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
558 int start_index, int npages, u64 *page_list)
563 int max_mtts_first_page;
565 /* compute how may mtts fit in the first page */
566 mtts_per_page = PAGE_SIZE / sizeof(u64);
567 max_mtts_first_page = mtts_per_page - (mtt->offset + start_index)
570 chunk = min_t(int, max_mtts_first_page, npages);
573 err = mlx4_write_mtt_chunk(dev, mtt, start_index, chunk, page_list);
577 start_index += chunk;
580 chunk = min_t(int, mtts_per_page, npages);
585 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
586 int start_index, int npages, u64 *page_list)
588 struct mlx4_cmd_mailbox *mailbox = NULL;
589 __be64 *inbox = NULL;
597 if (mlx4_is_mfunc(dev)) {
598 mailbox = mlx4_alloc_cmd_mailbox(dev);
600 return PTR_ERR(mailbox);
601 inbox = mailbox->buf;
604 chunk = min_t(int, MLX4_MAILBOX_SIZE / sizeof(u64) - 2,
606 inbox[0] = cpu_to_be64(mtt->offset + start_index);
608 for (i = 0; i < chunk; ++i)
609 inbox[i + 2] = cpu_to_be64(page_list[i] |
610 MLX4_MTT_FLAG_PRESENT);
611 err = mlx4_WRITE_MTT(dev, mailbox, chunk);
613 mlx4_free_cmd_mailbox(dev, mailbox);
618 start_index += chunk;
621 mlx4_free_cmd_mailbox(dev, mailbox);
625 return __mlx4_write_mtt(dev, mtt, start_index, npages, page_list);
627 EXPORT_SYMBOL_GPL(mlx4_write_mtt);
629 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
630 struct mlx4_buf *buf, gfp_t gfp)
636 page_list = kmalloc(buf->npages * sizeof *page_list,
641 for (i = 0; i < buf->npages; ++i)
643 page_list[i] = buf->direct.map + (i << buf->page_shift);
645 page_list[i] = buf->page_list[i].map;
647 err = mlx4_write_mtt(dev, mtt, 0, buf->npages, page_list);
652 EXPORT_SYMBOL_GPL(mlx4_buf_write_mtt);
654 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
659 if ((type == MLX4_MW_TYPE_1 &&
660 !(dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW)) ||
661 (type == MLX4_MW_TYPE_2 &&
662 !(dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)))
665 index = mlx4_mpt_reserve(dev);
669 mw->key = hw_index_to_key(index);
672 mw->enabled = MLX4_MPT_DISABLED;
676 EXPORT_SYMBOL_GPL(mlx4_mw_alloc);
678 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw)
680 struct mlx4_cmd_mailbox *mailbox;
681 struct mlx4_mpt_entry *mpt_entry;
684 err = mlx4_mpt_alloc_icm(dev, key_to_hw_index(mw->key), GFP_KERNEL);
688 mailbox = mlx4_alloc_cmd_mailbox(dev);
689 if (IS_ERR(mailbox)) {
690 err = PTR_ERR(mailbox);
693 mpt_entry = mailbox->buf;
695 /* Note that the MLX4_MPT_FLAG_REGION bit in mpt_entry->flags is turned
696 * off, thus creating a memory window and not a memory region.
698 mpt_entry->key = cpu_to_be32(key_to_hw_index(mw->key));
699 mpt_entry->pd_flags = cpu_to_be32(mw->pd);
700 if (mw->type == MLX4_MW_TYPE_2) {
701 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_FREE);
702 mpt_entry->qpn = cpu_to_be32(MLX4_MPT_QP_FLAG_BOUND_QP);
703 mpt_entry->pd_flags |= cpu_to_be32(MLX4_MPT_PD_FLAG_EN_INV);
706 err = mlx4_SW2HW_MPT(dev, mailbox,
707 key_to_hw_index(mw->key) &
708 (dev->caps.num_mpts - 1));
710 mlx4_warn(dev, "SW2HW_MPT failed (%d)\n", err);
713 mw->enabled = MLX4_MPT_EN_HW;
715 mlx4_free_cmd_mailbox(dev, mailbox);
720 mlx4_free_cmd_mailbox(dev, mailbox);
723 mlx4_mpt_free_icm(dev, key_to_hw_index(mw->key));
726 EXPORT_SYMBOL_GPL(mlx4_mw_enable);
728 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw)
732 if (mw->enabled == MLX4_MPT_EN_HW) {
733 err = mlx4_HW2SW_MPT(dev, NULL,
734 key_to_hw_index(mw->key) &
735 (dev->caps.num_mpts - 1));
737 mlx4_warn(dev, "xxx HW2SW_MPT failed (%d)\n", err);
739 mw->enabled = MLX4_MPT_EN_SW;
742 mlx4_mpt_free_icm(dev, key_to_hw_index(mw->key));
743 mlx4_mpt_release(dev, key_to_hw_index(mw->key));
745 EXPORT_SYMBOL_GPL(mlx4_mw_free);
747 int mlx4_init_mr_table(struct mlx4_dev *dev)
749 struct mlx4_priv *priv = mlx4_priv(dev);
750 struct mlx4_mr_table *mr_table = &priv->mr_table;
753 /* Nothing to do for slaves - all MR handling is forwarded
755 if (mlx4_is_slave(dev))
758 if (!is_power_of_2(dev->caps.num_mpts))
761 err = mlx4_bitmap_init(&mr_table->mpt_bitmap, dev->caps.num_mpts,
762 ~0, dev->caps.reserved_mrws, 0);
766 err = mlx4_buddy_init(&mr_table->mtt_buddy,
767 ilog2((u32)dev->caps.num_mtts /
768 (1 << log_mtts_per_seg)));
772 if (dev->caps.reserved_mtts) {
773 priv->reserved_mtts =
774 mlx4_alloc_mtt_range(dev,
775 fls(dev->caps.reserved_mtts - 1));
776 if (priv->reserved_mtts < 0) {
777 mlx4_warn(dev, "MTT table of order %u is too small\n",
778 mr_table->mtt_buddy.max_order);
780 goto err_reserve_mtts;
787 mlx4_buddy_cleanup(&mr_table->mtt_buddy);
790 mlx4_bitmap_cleanup(&mr_table->mpt_bitmap);
795 void mlx4_cleanup_mr_table(struct mlx4_dev *dev)
797 struct mlx4_priv *priv = mlx4_priv(dev);
798 struct mlx4_mr_table *mr_table = &priv->mr_table;
800 if (mlx4_is_slave(dev))
802 if (priv->reserved_mtts >= 0)
803 mlx4_free_mtt_range(dev, priv->reserved_mtts,
804 fls(dev->caps.reserved_mtts - 1));
805 mlx4_buddy_cleanup(&mr_table->mtt_buddy);
806 mlx4_bitmap_cleanup(&mr_table->mpt_bitmap);
809 static inline int mlx4_check_fmr(struct mlx4_fmr *fmr, u64 *page_list,
810 int npages, u64 iova)
814 if (npages > fmr->max_pages)
817 page_mask = (1 << fmr->page_shift) - 1;
819 /* We are getting page lists, so va must be page aligned. */
820 if (iova & page_mask)
823 /* Trust the user not to pass misaligned data in page_list */
825 for (i = 0; i < npages; ++i) {
826 if (page_list[i] & ~page_mask)
830 if (fmr->maps >= fmr->max_maps)
836 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
837 int npages, u64 iova, u32 *lkey, u32 *rkey)
842 err = mlx4_check_fmr(fmr, page_list, npages, iova);
848 key = key_to_hw_index(fmr->mr.key);
849 key += dev->caps.num_mpts;
850 *lkey = *rkey = fmr->mr.key = hw_index_to_key(key);
852 *(u8 *) fmr->mpt = MLX4_MPT_STATUS_SW;
854 /* Make sure MPT status is visible before writing MTT entries */
857 dma_sync_single_for_cpu(&dev->pdev->dev, fmr->dma_handle,
858 npages * sizeof(u64), DMA_TO_DEVICE);
860 for (i = 0; i < npages; ++i)
861 fmr->mtts[i] = cpu_to_be64(page_list[i] | MLX4_MTT_FLAG_PRESENT);
863 dma_sync_single_for_device(&dev->pdev->dev, fmr->dma_handle,
864 npages * sizeof(u64), DMA_TO_DEVICE);
866 fmr->mpt->key = cpu_to_be32(key);
867 fmr->mpt->lkey = cpu_to_be32(key);
868 fmr->mpt->length = cpu_to_be64(npages * (1ull << fmr->page_shift));
869 fmr->mpt->start = cpu_to_be64(iova);
871 /* Make MTT entries are visible before setting MPT status */
874 *(u8 *) fmr->mpt = MLX4_MPT_STATUS_HW;
876 /* Make sure MPT status is visible before consumer can use FMR */
881 EXPORT_SYMBOL_GPL(mlx4_map_phys_fmr);
883 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
884 int max_maps, u8 page_shift, struct mlx4_fmr *fmr)
886 struct mlx4_priv *priv = mlx4_priv(dev);
889 if (max_maps > dev->caps.max_fmr_maps)
892 if (page_shift < (ffs(dev->caps.page_size_cap) - 1) || page_shift >= 32)
895 /* All MTTs must fit in the same page */
896 if (max_pages * sizeof *fmr->mtts > PAGE_SIZE)
899 fmr->page_shift = page_shift;
900 fmr->max_pages = max_pages;
901 fmr->max_maps = max_maps;
904 err = mlx4_mr_alloc(dev, pd, 0, 0, access, max_pages,
905 page_shift, &fmr->mr);
909 fmr->mtts = mlx4_table_find(&priv->mr_table.mtt_table,
921 (void) mlx4_mr_free(dev, &fmr->mr);
924 EXPORT_SYMBOL_GPL(mlx4_fmr_alloc);
926 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr)
928 struct mlx4_priv *priv = mlx4_priv(dev);
931 err = mlx4_mr_enable(dev, &fmr->mr);
935 fmr->mpt = mlx4_table_find(&priv->mr_table.dmpt_table,
936 key_to_hw_index(fmr->mr.key), NULL);
942 EXPORT_SYMBOL_GPL(mlx4_fmr_enable);
944 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
945 u32 *lkey, u32 *rkey)
947 struct mlx4_cmd_mailbox *mailbox;
955 mailbox = mlx4_alloc_cmd_mailbox(dev);
956 if (IS_ERR(mailbox)) {
957 err = PTR_ERR(mailbox);
958 pr_warn("mlx4_ib: mlx4_alloc_cmd_mailbox failed (%d)\n", err);
962 err = mlx4_HW2SW_MPT(dev, NULL,
963 key_to_hw_index(fmr->mr.key) &
964 (dev->caps.num_mpts - 1));
965 mlx4_free_cmd_mailbox(dev, mailbox);
967 pr_warn("mlx4_ib: mlx4_HW2SW_MPT failed (%d)\n", err);
970 fmr->mr.enabled = MLX4_MPT_EN_SW;
972 EXPORT_SYMBOL_GPL(mlx4_fmr_unmap);
974 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr)
981 ret = mlx4_mr_free(dev, &fmr->mr);
984 fmr->mr.enabled = MLX4_MPT_DISABLED;
988 EXPORT_SYMBOL_GPL(mlx4_fmr_free);
990 int mlx4_SYNC_TPT(struct mlx4_dev *dev)
992 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_SYNC_TPT, 1000,
995 EXPORT_SYMBOL_GPL(mlx4_SYNC_TPT);