2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 #include <linux/bitops.h>
38 #include <linux/compiler.h>
39 #include <linux/list.h>
40 #include <linux/mutex.h>
41 #include <linux/netdevice.h>
42 #include <linux/if_vlan.h>
43 #include <linux/net_tstamp.h>
44 #ifdef CONFIG_MLX4_EN_DCB
45 #include <linux/dcbnl.h>
47 #include <linux/cpu_rmap.h>
49 #include <linux/mlx4/device.h>
50 #include <linux/mlx4/qp.h>
51 #include <linux/mlx4/cq.h>
52 #include <linux/mlx4/srq.h>
53 #include <linux/mlx4/doorbell.h>
54 #include <linux/mlx4/cmd.h>
58 #define DRV_NAME "mlx4_en"
59 #define DRV_VERSION "2.0"
60 #define DRV_RELDATE "Dec 2011"
62 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
69 #define MLX4_EN_PAGE_SHIFT 12
70 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
71 #define DEF_RX_RINGS 16
72 #define MAX_RX_RINGS 128
73 #define MIN_RX_RINGS 4
75 #define HEADROOM (2048 / TXBB_SIZE + 1)
76 #define STAMP_STRIDE 64
77 #define STAMP_DWORDS (STAMP_STRIDE / 4)
78 #define STAMP_SHIFT 31
79 #define STAMP_VAL 0x7fffffff
80 #define STATS_DELAY (HZ / 4)
81 #define SERVICE_TASK_DELAY (HZ / 4)
82 #define MAX_NUM_OF_FS_RULES 256
84 #define MLX4_EN_FILTER_HASH_SHIFT 4
85 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60
87 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
88 #define MAX_DESC_SIZE 512
89 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
92 * OS related constants and tunables
95 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
97 /* Use the maximum between 16384 and a single page */
98 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384)
100 #define MLX4_EN_ALLOC_PREFER_ORDER PAGE_ALLOC_COSTLY_ORDER
102 /* Receive fragment sizes; we use at most 3 fragments (for 9600 byte MTU
103 * and 4K allocations) */
105 FRAG_SZ0 = 1536 - NET_IP_ALIGN,
108 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
110 #define MLX4_EN_MAX_RX_FRAGS 4
112 /* Maximum ring sizes */
113 #define MLX4_EN_MAX_TX_SIZE 8192
114 #define MLX4_EN_MAX_RX_SIZE 8192
116 /* Minimum ring size for our page-allocation scheme to work */
117 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
118 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
120 #define MLX4_EN_SMALL_PKT_SIZE 64
121 #define MLX4_EN_MAX_TX_RING_P_UP 32
122 #define MLX4_EN_NUM_UP 8
123 #define MLX4_EN_DEF_TX_RING_SIZE 512
124 #define MLX4_EN_DEF_RX_RING_SIZE 1024
125 #define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \
128 /* Target number of packets to coalesce with interrupt moderation */
129 #define MLX4_EN_RX_COAL_TARGET 44
130 #define MLX4_EN_RX_COAL_TIME 0x10
132 #define MLX4_EN_TX_COAL_PKTS 16
133 #define MLX4_EN_TX_COAL_TIME 0x10
135 #define MLX4_EN_RX_RATE_LOW 400000
136 #define MLX4_EN_RX_COAL_TIME_LOW 0
137 #define MLX4_EN_RX_RATE_HIGH 450000
138 #define MLX4_EN_RX_COAL_TIME_HIGH 128
139 #define MLX4_EN_RX_SIZE_THRESH 1024
140 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
141 #define MLX4_EN_SAMPLE_INTERVAL 0
142 #define MLX4_EN_AVG_PKT_SMALL 256
144 #define MLX4_EN_AUTO_CONF 0xffff
146 #define MLX4_EN_DEF_RX_PAUSE 1
147 #define MLX4_EN_DEF_TX_PAUSE 1
149 /* Interval between successive polls in the Tx routine when polling is used
150 instead of interrupts (in per-core Tx rings) - should be power of 2 */
151 #define MLX4_EN_TX_POLL_MODER 16
152 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
154 #define ETH_LLC_SNAP_SIZE 8
156 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
157 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
158 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
160 #define MLX4_EN_MIN_MTU 46
161 #define ETH_BCAST 0xffffffffffffULL
163 #define MLX4_EN_LOOPBACK_RETRIES 5
164 #define MLX4_EN_LOOPBACK_TIMEOUT 100
166 #ifdef MLX4_EN_PERF_STAT
167 /* Number of samples to 'average' */
169 #define AVG_FACTOR 1024
170 #define NUM_PERF_STATS NUM_PERF_COUNTERS
172 #define INC_PERF_COUNTER(cnt) (++(cnt))
173 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
174 #define AVG_PERF_COUNTER(cnt, sample) \
175 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
176 #define GET_PERF_COUNTER(cnt) (cnt)
177 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
181 #define NUM_PERF_STATS 0
182 #define INC_PERF_COUNTER(cnt) do {} while (0)
183 #define ADD_PERF_COUNTER(cnt, add) do {} while (0)
184 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
185 #define GET_PERF_COUNTER(cnt) (0)
186 #define GET_AVG_PERF_COUNTER(cnt) (0)
187 #endif /* MLX4_EN_PERF_STAT */
202 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
203 #define XNOR(x, y) (!(x) == !(y))
206 struct mlx4_en_tx_info {
217 #define MLX4_EN_BIT_DESC_OWN 0x80000000
218 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
219 #define MLX4_EN_MEMTYPE_PAD 0x100
220 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
223 struct mlx4_en_tx_desc {
224 struct mlx4_wqe_ctrl_seg ctrl;
226 struct mlx4_wqe_data_seg data; /* at least one data segment */
227 struct mlx4_wqe_lso_seg lso;
228 struct mlx4_wqe_inline_seg inl;
232 #define MLX4_EN_USE_SRQ 0x01000000
234 #define MLX4_EN_CX3_LOW_ID 0x1000
235 #define MLX4_EN_CX3_HIGH_ID 0x1005
237 struct mlx4_en_rx_alloc {
244 struct mlx4_en_tx_ring {
245 struct mlx4_hwq_resources wqres;
246 u32 size ; /* number of TXBBs */
249 u16 cqn; /* index of port CQ associated with this ring */
256 struct mlx4_en_tx_info *tx_info;
260 struct mlx4_qp_context context;
262 enum mlx4_qp_state qp_state;
263 struct mlx4_srq dummy;
265 unsigned long packets;
266 unsigned long tx_csum;
269 struct netdev_queue *tx_queue;
270 int hwtstamp_tx_type;
273 struct mlx4_en_rx_desc {
274 /* actual number of entries depends on rx ring stride */
275 struct mlx4_wqe_data_seg data[0];
278 struct mlx4_en_rx_ring {
279 struct mlx4_hwq_resources wqres;
280 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
281 u32 size ; /* number of Rx descs*/
286 u16 cqn; /* index of port CQ associated with this ring */
294 unsigned long packets;
295 #ifdef CONFIG_NET_RX_BUSY_POLL
296 unsigned long yields;
297 unsigned long misses;
298 unsigned long cleaned;
300 unsigned long csum_ok;
301 unsigned long csum_none;
302 int hwtstamp_rx_filter;
307 struct mlx4_hwq_resources wqres;
310 struct net_device *dev;
311 struct napi_struct napi;
318 struct mlx4_cqe *buf;
319 #define MLX4_EN_OPCODE_ERROR 0x1e
321 #ifdef CONFIG_NET_RX_BUSY_POLL
323 #define MLX4_EN_CQ_STATE_IDLE 0
324 #define MLX4_EN_CQ_STATE_NAPI 1 /* NAPI owns this CQ */
325 #define MLX4_EN_CQ_STATE_POLL 2 /* poll owns this CQ */
326 #define MLX4_CQ_LOCKED (MLX4_EN_CQ_STATE_NAPI | MLX4_EN_CQ_STATE_POLL)
327 #define MLX4_EN_CQ_STATE_NAPI_YIELD 4 /* NAPI yielded this CQ */
328 #define MLX4_EN_CQ_STATE_POLL_YIELD 8 /* poll yielded this CQ */
329 #define CQ_YIELD (MLX4_EN_CQ_STATE_NAPI_YIELD | MLX4_EN_CQ_STATE_POLL_YIELD)
330 #define CQ_USER_PEND (MLX4_EN_CQ_STATE_POLL | MLX4_EN_CQ_STATE_POLL_YIELD)
331 spinlock_t poll_lock; /* protects from LLS/napi conflicts */
332 #endif /* CONFIG_NET_RX_BUSY_POLL */
335 struct mlx4_en_port_profile {
348 struct mlx4_en_profile {
355 u8 num_tx_rings_p_up;
356 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
360 struct mlx4_dev *dev;
361 struct pci_dev *pdev;
362 struct mutex state_lock;
363 struct net_device *pndev[MLX4_MAX_PORTS + 1];
366 struct mlx4_en_profile profile;
368 struct workqueue_struct *workqueue;
369 struct device *dma_device;
370 void __iomem *uar_map;
371 struct mlx4_uar priv_uar;
375 u8 mac_removed[MLX4_MAX_PORTS + 1];
376 struct cyclecounter cycles;
377 struct timecounter clock;
378 unsigned long last_overflow_check;
379 unsigned long overflow_period;
383 struct mlx4_en_rss_map {
385 struct mlx4_qp qps[MAX_RX_RINGS];
386 enum mlx4_qp_state state[MAX_RX_RINGS];
387 struct mlx4_qp indir_qp;
388 enum mlx4_qp_state indir_state;
391 struct mlx4_en_port_state {
397 struct mlx4_en_pkt_stats {
398 unsigned long broadcast;
399 unsigned long rx_prio[8];
400 unsigned long tx_prio[8];
401 #define NUM_PKT_STATS 17
404 struct mlx4_en_port_stats {
405 unsigned long tso_packets;
406 unsigned long queue_stopped;
407 unsigned long wake_queue;
408 unsigned long tx_timeout;
409 unsigned long rx_alloc_failed;
410 unsigned long rx_chksum_good;
411 unsigned long rx_chksum_none;
412 unsigned long tx_chksum_offload;
413 #define NUM_PORT_STATS 8
416 struct mlx4_en_perf_stats {
423 #define NUM_PERF_COUNTERS 6
426 enum mlx4_en_mclist_act {
432 struct mlx4_en_mc_list {
433 struct list_head list;
434 enum mlx4_en_mclist_act action;
439 struct mlx4_en_frag_info {
441 u16 frag_prefix_size;
446 #ifdef CONFIG_MLX4_EN_DCB
447 /* Minimal TC BW - setting to 0 will block traffic */
448 #define MLX4_EN_BW_MIN 1
449 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
451 #define MLX4_EN_TC_ETS 7
455 struct ethtool_flow_id {
456 struct list_head list;
457 struct ethtool_rx_flow_spec flow_spec;
462 MLX4_EN_FLAG_PROMISC = (1 << 0),
463 MLX4_EN_FLAG_MC_PROMISC = (1 << 1),
464 /* whether we need to enable hardware loopback by putting dmac
467 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2),
468 /* whether we need to drop packets that hardware loopback-ed */
469 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3),
470 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4)
473 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)
474 #define MLX4_EN_MAC_HASH_IDX 5
476 struct mlx4_en_priv {
477 struct mlx4_en_dev *mdev;
478 struct mlx4_en_port_profile *prof;
479 struct net_device *dev;
480 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
481 struct net_device_stats stats;
482 struct net_device_stats ret_stats;
483 struct mlx4_en_port_state port_state;
484 spinlock_t stats_lock;
485 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
486 /* To allow rules removal while port is going down */
487 struct list_head ethtool_list;
489 unsigned long last_moder_packets[MAX_RX_RINGS];
490 unsigned long last_moder_tx_packets;
491 unsigned long last_moder_bytes[MAX_RX_RINGS];
492 unsigned long last_moder_jiffies;
493 int last_moder_time[MAX_RX_RINGS];
503 u16 adaptive_rx_coal;
506 u32 validate_loopback;
508 struct mlx4_hwq_resources res;
516 unsigned char prev_mac[ETH_ALEN + 2];
522 struct mlx4_en_rss_map rss_map;
525 u8 num_tx_rings_p_up;
529 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
533 struct mlx4_en_tx_ring **tx_ring;
534 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS];
535 struct mlx4_en_cq **tx_cq;
536 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS];
537 struct mlx4_qp drop_qp;
538 struct work_struct rx_mode_task;
539 struct work_struct watchdog_task;
540 struct work_struct linkstate_task;
541 struct delayed_work stats_task;
542 struct delayed_work service_task;
543 struct mlx4_en_perf_stats pstats;
544 struct mlx4_en_pkt_stats pkstats;
545 struct mlx4_en_port_stats port_stats;
547 struct list_head mc_list;
548 struct list_head curr_list;
550 struct mlx4_en_stat_out_mbox hw_stats;
555 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE];
556 struct hwtstamp_config hwtstamp_config;
558 #ifdef CONFIG_MLX4_EN_DCB
560 u16 maxrate[IEEE_8021QAZ_MAX_TCS];
562 #ifdef CONFIG_RFS_ACCEL
563 spinlock_t filters_lock;
565 struct list_head filters;
566 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
572 MLX4_EN_WOL_MAGIC = (1ULL << 61),
573 MLX4_EN_WOL_ENABLED = (1ULL << 62),
576 struct mlx4_mac_entry {
577 struct hlist_node hlist;
578 unsigned char mac[ETH_ALEN + 2];
583 #ifdef CONFIG_NET_RX_BUSY_POLL
584 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq)
586 spin_lock_init(&cq->poll_lock);
587 cq->state = MLX4_EN_CQ_STATE_IDLE;
590 /* called from the device poll rutine to get ownership of a cq */
591 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq)
594 spin_lock(&cq->poll_lock);
595 if (cq->state & MLX4_CQ_LOCKED) {
596 WARN_ON(cq->state & MLX4_EN_CQ_STATE_NAPI);
597 cq->state |= MLX4_EN_CQ_STATE_NAPI_YIELD;
600 /* we don't care if someone yielded */
601 cq->state = MLX4_EN_CQ_STATE_NAPI;
602 spin_unlock(&cq->poll_lock);
606 /* returns true is someone tried to get the cq while napi had it */
607 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq)
610 spin_lock(&cq->poll_lock);
611 WARN_ON(cq->state & (MLX4_EN_CQ_STATE_POLL |
612 MLX4_EN_CQ_STATE_NAPI_YIELD));
614 if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD)
616 cq->state = MLX4_EN_CQ_STATE_IDLE;
617 spin_unlock(&cq->poll_lock);
621 /* called from mlx4_en_low_latency_poll() */
622 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq)
625 spin_lock_bh(&cq->poll_lock);
626 if ((cq->state & MLX4_CQ_LOCKED)) {
627 struct net_device *dev = cq->dev;
628 struct mlx4_en_priv *priv = netdev_priv(dev);
629 struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring];
631 cq->state |= MLX4_EN_CQ_STATE_POLL_YIELD;
635 /* preserve yield marks */
636 cq->state |= MLX4_EN_CQ_STATE_POLL;
637 spin_unlock_bh(&cq->poll_lock);
641 /* returns true if someone tried to get the cq while it was locked */
642 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq)
645 spin_lock_bh(&cq->poll_lock);
646 WARN_ON(cq->state & (MLX4_EN_CQ_STATE_NAPI));
648 if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD)
650 cq->state = MLX4_EN_CQ_STATE_IDLE;
651 spin_unlock_bh(&cq->poll_lock);
655 /* true if a socket is polling, even if it did not get the lock */
656 static inline bool mlx4_en_cq_ll_polling(struct mlx4_en_cq *cq)
658 WARN_ON(!(cq->state & MLX4_CQ_LOCKED));
659 return cq->state & CQ_USER_PEND;
662 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq)
666 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq)
671 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq)
676 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq)
681 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq)
686 static inline bool mlx4_en_cq_ll_polling(struct mlx4_en_cq *cq)
690 #endif /* CONFIG_NET_RX_BUSY_POLL */
692 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
694 void mlx4_en_update_loopback_state(struct net_device *dev,
695 netdev_features_t features);
697 void mlx4_en_destroy_netdev(struct net_device *dev);
698 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
699 struct mlx4_en_port_profile *prof);
701 int mlx4_en_start_port(struct net_device *dev);
702 void mlx4_en_stop_port(struct net_device *dev, int detach);
704 void mlx4_en_free_resources(struct mlx4_en_priv *priv);
705 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
707 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq,
708 int entries, int ring, enum cq_type mode, int node);
709 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq);
710 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
712 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
713 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
714 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
716 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
717 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
719 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
721 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
722 struct mlx4_en_tx_ring **pring,
723 int qpn, u32 size, u16 stride, int node);
724 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
725 struct mlx4_en_tx_ring **pring);
726 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
727 struct mlx4_en_tx_ring *ring,
728 int cq, int user_prio);
729 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
730 struct mlx4_en_tx_ring *ring);
732 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
733 struct mlx4_en_rx_ring **pring,
734 u32 size, u16 stride, int node);
735 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
736 struct mlx4_en_rx_ring **pring,
737 u32 size, u16 stride);
738 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
739 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
740 struct mlx4_en_rx_ring *ring);
741 int mlx4_en_process_rx_cq(struct net_device *dev,
742 struct mlx4_en_cq *cq,
744 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
745 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
746 int is_tx, int rss, int qpn, int cqn, int user_prio,
747 struct mlx4_qp_context *context);
748 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
749 int mlx4_en_map_buffer(struct mlx4_buf *buf);
750 void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
752 void mlx4_en_calc_rx_buf(struct net_device *dev);
753 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
754 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
755 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
756 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
757 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
758 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
760 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
761 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
763 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
764 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
766 #ifdef CONFIG_MLX4_EN_DCB
767 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
768 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;
771 int mlx4_en_setup_tc(struct net_device *dev, u8 up);
773 #ifdef CONFIG_RFS_ACCEL
774 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv);
777 #define MLX4_EN_NUM_SELF_TEST 5
778 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
779 u64 mlx4_en_mac_to_u64(u8 *addr);
780 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);
783 * Functions for time stamping
785 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);
786 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev,
787 struct skb_shared_hwtstamps *hwts,
789 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev);
790 int mlx4_en_timestamp_config(struct net_device *dev,
796 extern const struct ethtool_ops mlx4_en_ethtool_ops;
801 * printk / logging functions
805 int en_print(const char *level, const struct mlx4_en_priv *priv,
806 const char *format, ...);
808 #define en_dbg(mlevel, priv, format, arg...) \
810 if (NETIF_MSG_##mlevel & priv->msg_enable) \
811 en_print(KERN_DEBUG, priv, format, ##arg); \
813 #define en_warn(priv, format, arg...) \
814 en_print(KERN_WARNING, priv, format, ##arg)
815 #define en_err(priv, format, arg...) \
816 en_print(KERN_ERR, priv, format, ##arg)
817 #define en_info(priv, format, arg...) \
818 en_print(KERN_INFO, priv, format, ## arg)
820 #define mlx4_err(mdev, format, arg...) \
821 pr_err("%s %s: " format, DRV_NAME, \
822 dev_name(&mdev->pdev->dev), ##arg)
823 #define mlx4_info(mdev, format, arg...) \
824 pr_info("%s %s: " format, DRV_NAME, \
825 dev_name(&mdev->pdev->dev), ##arg)
826 #define mlx4_warn(mdev, format, arg...) \
827 pr_warning("%s %s: " format, DRV_NAME, \
828 dev_name(&mdev->pdev->dev), ##arg)