2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 #include <linux/bitops.h>
38 #include <linux/compiler.h>
39 #include <linux/list.h>
40 #include <linux/mutex.h>
41 #include <linux/netdevice.h>
42 #include <linux/if_vlan.h>
43 #include <linux/net_tstamp.h>
44 #ifdef CONFIG_MLX4_EN_DCB
45 #include <linux/dcbnl.h>
47 #include <linux/cpu_rmap.h>
48 #include <linux/ptp_clock_kernel.h>
50 #include <linux/mlx4/device.h>
51 #include <linux/mlx4/qp.h>
52 #include <linux/mlx4/cq.h>
53 #include <linux/mlx4/srq.h>
54 #include <linux/mlx4/doorbell.h>
55 #include <linux/mlx4/cmd.h>
58 #include "mlx4_stats.h"
60 #define DRV_NAME "mlx4_en"
61 #define DRV_VERSION "2.2-1"
62 #define DRV_RELDATE "Feb 2014"
64 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
71 #define MLX4_EN_PAGE_SHIFT 12
72 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
73 #define DEF_RX_RINGS 16
74 #define MAX_RX_RINGS 128
75 #define MIN_RX_RINGS 4
77 #define HEADROOM (2048 / TXBB_SIZE + 1)
78 #define STAMP_STRIDE 64
79 #define STAMP_DWORDS (STAMP_STRIDE / 4)
80 #define STAMP_SHIFT 31
81 #define STAMP_VAL 0x7fffffff
82 #define STATS_DELAY (HZ / 4)
83 #define SERVICE_TASK_DELAY (HZ / 4)
84 #define MAX_NUM_OF_FS_RULES 256
86 #define MLX4_EN_FILTER_HASH_SHIFT 4
87 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60
89 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
90 #define MAX_DESC_SIZE 512
91 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
94 * OS related constants and tunables
97 #define MLX4_EN_PRIV_FLAGS_BLUEFLAME 1
98 #define MLX4_EN_PRIV_FLAGS_PHV 2
100 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
102 /* Use the maximum between 16384 and a single page */
103 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384)
105 #define MLX4_EN_ALLOC_PREFER_ORDER min_t(int, get_order(32768), \
106 PAGE_ALLOC_COSTLY_ORDER)
108 /* Receive fragment sizes; we use at most 3 fragments (for 9600 byte MTU
109 * and 4K allocations) */
111 FRAG_SZ0 = 1536 - NET_IP_ALIGN,
114 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
116 #define MLX4_EN_MAX_RX_FRAGS 4
118 /* Maximum ring sizes */
119 #define MLX4_EN_MAX_TX_SIZE 8192
120 #define MLX4_EN_MAX_RX_SIZE 8192
122 /* Minimum ring size for our page-allocation scheme to work */
123 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
124 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
126 #define MLX4_EN_SMALL_PKT_SIZE 64
127 #define MLX4_EN_MIN_TX_RING_P_UP 1
128 #define MLX4_EN_MAX_TX_RING_P_UP 32
129 #define MLX4_EN_NUM_UP 8
130 #define MLX4_EN_DEF_TX_RING_SIZE 512
131 #define MLX4_EN_DEF_RX_RING_SIZE 1024
132 #define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \
135 #define MLX4_EN_DEFAULT_TX_WORK 256
136 #define MLX4_EN_DOORBELL_BUDGET 8
138 /* Target number of packets to coalesce with interrupt moderation */
139 #define MLX4_EN_RX_COAL_TARGET 44
140 #define MLX4_EN_RX_COAL_TIME 0x10
142 #define MLX4_EN_TX_COAL_PKTS 16
143 #define MLX4_EN_TX_COAL_TIME 0x10
145 #define MLX4_EN_RX_RATE_LOW 400000
146 #define MLX4_EN_RX_COAL_TIME_LOW 0
147 #define MLX4_EN_RX_RATE_HIGH 450000
148 #define MLX4_EN_RX_COAL_TIME_HIGH 128
149 #define MLX4_EN_RX_SIZE_THRESH 1024
150 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
151 #define MLX4_EN_SAMPLE_INTERVAL 0
152 #define MLX4_EN_AVG_PKT_SMALL 256
154 #define MLX4_EN_AUTO_CONF 0xffff
156 #define MLX4_EN_DEF_RX_PAUSE 1
157 #define MLX4_EN_DEF_TX_PAUSE 1
159 /* Interval between successive polls in the Tx routine when polling is used
160 instead of interrupts (in per-core Tx rings) - should be power of 2 */
161 #define MLX4_EN_TX_POLL_MODER 16
162 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
164 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
165 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
166 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
168 #define MLX4_EN_MIN_MTU 46
169 /* VLAN_HLEN is added twice,to support skb vlan tagged with multiple
170 * headers. (For example: ETH_P_8021Q and ETH_P_8021AD).
172 #define MLX4_EN_EFF_MTU(mtu) ((mtu) + ETH_HLEN + (2 * VLAN_HLEN))
173 #define ETH_BCAST 0xffffffffffffULL
175 #define MLX4_EN_LOOPBACK_RETRIES 5
176 #define MLX4_EN_LOOPBACK_TIMEOUT 100
178 #ifdef MLX4_EN_PERF_STAT
179 /* Number of samples to 'average' */
181 #define AVG_FACTOR 1024
183 #define INC_PERF_COUNTER(cnt) (++(cnt))
184 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
185 #define AVG_PERF_COUNTER(cnt, sample) \
186 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
187 #define GET_PERF_COUNTER(cnt) (cnt)
188 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
192 #define INC_PERF_COUNTER(cnt) do {} while (0)
193 #define ADD_PERF_COUNTER(cnt, add) do {} while (0)
194 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
195 #define GET_PERF_COUNTER(cnt) (0)
196 #define GET_AVG_PERF_COUNTER(cnt) (0)
197 #endif /* MLX4_EN_PERF_STAT */
199 /* Constants for TX flow */
201 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
211 /* keep tx types first */
214 #define MLX4_EN_NUM_TX_TYPES (TX_XDP + 1)
222 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
223 #define XNOR(x, y) (!(x) == !(y))
226 struct mlx4_en_tx_info {
240 } ____cacheline_aligned_in_smp;
243 #define MLX4_EN_BIT_DESC_OWN 0x80000000
244 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
245 #define MLX4_EN_MEMTYPE_PAD 0x100
246 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
249 struct mlx4_en_tx_desc {
250 struct mlx4_wqe_ctrl_seg ctrl;
252 struct mlx4_wqe_data_seg data; /* at least one data segment */
253 struct mlx4_wqe_lso_seg lso;
254 struct mlx4_wqe_inline_seg inl;
258 #define MLX4_EN_USE_SRQ 0x01000000
260 #define MLX4_EN_CX3_LOW_ID 0x1000
261 #define MLX4_EN_CX3_HIGH_ID 0x1005
263 struct mlx4_en_rx_alloc {
270 #define MLX4_EN_CACHE_SIZE (2 * NAPI_POLL_WEIGHT)
271 struct mlx4_en_page_cache {
273 struct mlx4_en_rx_alloc buf[MLX4_EN_CACHE_SIZE];
278 struct mlx4_en_tx_ring {
279 /* cache line used and dirtied in tx completion
280 * (mlx4_en_free_tx_buf())
284 unsigned long wake_queue;
285 struct netdev_queue *tx_queue;
286 u32 (*free_tx_desc)(struct mlx4_en_priv *priv,
287 struct mlx4_en_tx_ring *ring,
289 u64 timestamp, int napi_mode);
290 struct mlx4_en_rx_ring *recycle_ring;
292 /* cache line used and dirtied in mlx4_en_xmit() */
293 u32 prod ____cacheline_aligned_in_smp;
294 unsigned int tx_dropped;
296 unsigned long packets;
297 unsigned long tx_csum;
298 unsigned long tso_packets;
299 unsigned long xmit_more;
302 /* Following part should be mostly read */
305 u32 size; /* number of TXBBs */
310 struct mlx4_en_tx_info *tx_info;
318 /* Not used in fast path
319 * Only queue_stopped might be used if BQL is not properly working.
321 unsigned long queue_stopped;
322 struct mlx4_hwq_resources sp_wqres;
323 struct mlx4_qp sp_qp;
324 struct mlx4_qp_context sp_context;
325 cpumask_t sp_affinity_mask;
326 enum mlx4_qp_state sp_qp_state;
328 u16 sp_cqn; /* index of port CQ associated with this ring */
329 } ____cacheline_aligned_in_smp;
331 struct mlx4_en_rx_desc {
332 /* actual number of entries depends on rx ring stride */
333 struct mlx4_wqe_data_seg data[0];
336 struct mlx4_en_rx_ring {
337 struct mlx4_hwq_resources wqres;
338 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
339 u32 size ; /* number of Rx descs*/
344 u16 cqn; /* index of port CQ associated with this ring */
351 struct bpf_prog __rcu *xdp_prog;
352 struct mlx4_en_page_cache page_cache;
354 unsigned long packets;
355 unsigned long csum_ok;
356 unsigned long csum_none;
357 unsigned long csum_complete;
358 unsigned long xdp_drop;
359 unsigned long xdp_tx;
360 unsigned long xdp_tx_full;
361 unsigned long dropped;
362 int hwtstamp_rx_filter;
363 cpumask_var_t affinity_mask;
368 struct mlx4_hwq_resources wqres;
370 struct net_device *dev;
371 struct napi_struct napi;
378 struct mlx4_cqe *buf;
379 #define MLX4_EN_OPCODE_ERROR 0x1e
381 struct irq_desc *irq_desc;
384 struct mlx4_en_port_profile {
386 u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES];
390 u8 num_tx_rings_p_up;
397 struct hwtstamp_config hwtstamp_config;
400 struct mlx4_en_profile {
406 u8 num_tx_rings_p_up;
407 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
411 struct mlx4_dev *dev;
412 struct pci_dev *pdev;
413 struct mutex state_lock;
414 struct net_device *pndev[MLX4_MAX_PORTS + 1];
415 struct net_device *upper[MLX4_MAX_PORTS + 1];
418 struct mlx4_en_profile profile;
420 struct workqueue_struct *workqueue;
421 struct device *dma_device;
422 void __iomem *uar_map;
423 struct mlx4_uar priv_uar;
427 u8 mac_removed[MLX4_MAX_PORTS + 1];
429 struct cyclecounter cycles;
430 seqlock_t clock_lock;
431 struct timecounter clock;
432 unsigned long last_overflow_check;
433 struct ptp_clock *ptp_clock;
434 struct ptp_clock_info ptp_clock_info;
435 struct notifier_block nb;
439 struct mlx4_en_rss_map {
441 struct mlx4_qp qps[MAX_RX_RINGS];
442 enum mlx4_qp_state state[MAX_RX_RINGS];
443 struct mlx4_qp indir_qp;
444 enum mlx4_qp_state indir_state;
447 enum mlx4_en_port_flag {
448 MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */
449 MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */
452 struct mlx4_en_port_state {
459 enum mlx4_en_mclist_act {
465 struct mlx4_en_mc_list {
466 struct list_head list;
467 enum mlx4_en_mclist_act action;
473 struct mlx4_en_frag_info {
479 #ifdef CONFIG_MLX4_EN_DCB
480 /* Minimal TC BW - setting to 0 will block traffic */
481 #define MLX4_EN_BW_MIN 1
482 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
484 #define MLX4_EN_TC_ETS 7
493 struct mlx4_en_cee_config {
495 enum dcb_pfc_type dcb_pfc[MLX4_EN_NUM_UP];
499 struct ethtool_flow_id {
500 struct list_head list;
501 struct ethtool_rx_flow_spec flow_spec;
506 MLX4_EN_FLAG_PROMISC = (1 << 0),
507 MLX4_EN_FLAG_MC_PROMISC = (1 << 1),
508 /* whether we need to enable hardware loopback by putting dmac
511 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2),
512 /* whether we need to drop packets that hardware loopback-ed */
513 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3),
514 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4),
515 MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP = (1 << 5),
516 #ifdef CONFIG_MLX4_EN_DCB
517 MLX4_EN_FLAG_DCB_ENABLED = (1 << 6),
521 #define PORT_BEACON_MAX_LIMIT (65535)
522 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)
523 #define MLX4_EN_MAC_HASH_IDX 5
525 struct mlx4_en_stats_bitmap {
526 DECLARE_BITMAP(bitmap, NUM_ALL_STATS);
527 struct mutex mutex; /* for mutual access to stats bitmap */
530 struct mlx4_en_priv {
531 struct mlx4_en_dev *mdev;
532 struct mlx4_en_port_profile *prof;
533 struct net_device *dev;
534 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
535 struct mlx4_en_port_state port_state;
536 spinlock_t stats_lock;
537 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
538 /* To allow rules removal while port is going down */
539 struct list_head ethtool_list;
541 unsigned long last_moder_packets[MAX_RX_RINGS];
542 unsigned long last_moder_tx_packets;
543 unsigned long last_moder_bytes[MAX_RX_RINGS];
544 unsigned long last_moder_jiffies;
545 int last_moder_time[MAX_RX_RINGS];
555 u16 adaptive_rx_coal;
558 u32 validate_loopback;
560 struct mlx4_hwq_resources res;
568 unsigned char current_mac[ETH_ALEN + 2];
575 struct mlx4_en_rss_map rss_map;
578 u8 num_tx_rings_p_up;
580 u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES];
583 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
589 struct mlx4_en_tx_ring **tx_ring[MLX4_EN_NUM_TX_TYPES];
590 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS];
591 struct mlx4_en_cq **tx_cq[MLX4_EN_NUM_TX_TYPES];
592 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS];
593 struct mlx4_qp drop_qp;
594 struct work_struct rx_mode_task;
595 struct work_struct watchdog_task;
596 struct work_struct linkstate_task;
597 struct delayed_work stats_task;
598 struct delayed_work service_task;
599 struct work_struct vxlan_add_task;
600 struct work_struct vxlan_del_task;
601 struct mlx4_en_perf_stats pstats;
602 struct mlx4_en_pkt_stats pkstats;
603 struct mlx4_en_counter_stats pf_stats;
604 struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES];
605 struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES];
606 struct mlx4_en_flow_stats_rx rx_flowstats;
607 struct mlx4_en_flow_stats_tx tx_flowstats;
608 struct mlx4_en_port_stats port_stats;
609 struct mlx4_en_xdp_stats xdp_stats;
610 struct mlx4_en_stats_bitmap stats_bitmap;
611 struct list_head mc_list;
612 struct list_head curr_list;
614 struct mlx4_en_stat_out_mbox hw_stats;
618 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE];
619 struct hwtstamp_config hwtstamp_config;
622 #ifdef CONFIG_MLX4_EN_DCB
623 #define MLX4_EN_DCB_ENABLED 0x3
625 u16 maxrate[IEEE_8021QAZ_MAX_TCS];
626 enum dcbnl_cndd_states cndd_state[IEEE_8021QAZ_MAX_TCS];
627 struct mlx4_en_cee_config cee_config;
630 #ifdef CONFIG_RFS_ACCEL
631 spinlock_t filters_lock;
633 struct list_head filters;
634 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
640 u8 rss_key[MLX4_EN_RSS_KEY_SIZE];
645 MLX4_EN_WOL_MAGIC = (1ULL << 61),
646 MLX4_EN_WOL_ENABLED = (1ULL << 62),
649 struct mlx4_mac_entry {
650 struct hlist_node hlist;
651 unsigned char mac[ETH_ALEN + 2];
656 static inline struct mlx4_cqe *mlx4_en_get_cqe(void *buf, int idx, int cqe_sz)
658 return buf + idx * cqe_sz;
661 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
663 void mlx4_en_init_ptys2ethtool_map(void);
664 void mlx4_en_update_loopback_state(struct net_device *dev,
665 netdev_features_t features);
667 void mlx4_en_destroy_netdev(struct net_device *dev);
668 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
669 struct mlx4_en_port_profile *prof);
671 int mlx4_en_start_port(struct net_device *dev);
672 void mlx4_en_stop_port(struct net_device *dev, int detach);
674 void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev,
675 struct mlx4_en_stats_bitmap *stats_bitmap,
676 u8 rx_ppp, u8 rx_pause,
677 u8 tx_ppp, u8 tx_pause);
679 int mlx4_en_try_alloc_resources(struct mlx4_en_priv *priv,
680 struct mlx4_en_priv *tmp,
681 struct mlx4_en_port_profile *prof,
682 bool carry_xdp_prog);
683 void mlx4_en_safe_replace_resources(struct mlx4_en_priv *priv,
684 struct mlx4_en_priv *tmp);
686 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq,
687 int entries, int ring, enum cq_type mode, int node);
688 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq);
689 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
691 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
692 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
693 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
695 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
696 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
697 void *accel_priv, select_queue_fallback_t fallback);
698 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
699 netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring,
700 struct mlx4_en_rx_alloc *frame,
701 struct net_device *dev, unsigned int length,
702 int tx_ind, int *doorbell_pending);
703 void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring);
704 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring,
705 struct mlx4_en_rx_alloc *frame);
707 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
708 struct mlx4_en_tx_ring **pring,
709 u32 size, u16 stride,
710 int node, int queue_index);
711 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
712 struct mlx4_en_tx_ring **pring);
713 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
714 struct mlx4_en_tx_ring *ring,
715 int cq, int user_prio);
716 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
717 struct mlx4_en_tx_ring *ring);
718 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev);
719 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv);
720 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
721 struct mlx4_en_rx_ring **pring,
722 u32 size, u16 stride, int node);
723 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
724 struct mlx4_en_rx_ring **pring,
725 u32 size, u16 stride);
726 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
727 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
728 struct mlx4_en_rx_ring *ring);
729 int mlx4_en_process_rx_cq(struct net_device *dev,
730 struct mlx4_en_cq *cq,
732 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
733 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget);
734 u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
735 struct mlx4_en_tx_ring *ring,
736 int index, u8 owner, u64 timestamp,
738 u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv,
739 struct mlx4_en_tx_ring *ring,
740 int index, u8 owner, u64 timestamp,
742 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
743 int is_tx, int rss, int qpn, int cqn, int user_prio,
744 struct mlx4_qp_context *context);
745 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
746 int mlx4_en_change_mcast_lb(struct mlx4_en_priv *priv, struct mlx4_qp *qp,
748 void mlx4_en_calc_rx_buf(struct net_device *dev);
749 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
750 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
751 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
752 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
753 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
754 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
756 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
757 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
759 void mlx4_en_fold_software_stats(struct net_device *dev);
760 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
761 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
763 #ifdef CONFIG_MLX4_EN_DCB
764 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
765 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;
768 int mlx4_en_setup_tc(struct net_device *dev, u8 up);
770 #ifdef CONFIG_RFS_ACCEL
771 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv);
774 #define MLX4_EN_NUM_SELF_TEST 5
775 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
776 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);
778 #define DEV_FEATURE_CHANGED(dev, new_features, feature) \
779 ((dev->features & feature) ^ (new_features & feature))
781 int mlx4_en_reset_config(struct net_device *dev,
782 struct hwtstamp_config ts_config,
783 netdev_features_t new_features);
784 void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev,
785 struct mlx4_en_stats_bitmap *stats_bitmap,
786 u8 rx_ppp, u8 rx_pause,
787 u8 tx_ppp, u8 tx_pause);
788 int mlx4_en_netdev_event(struct notifier_block *this,
789 unsigned long event, void *ptr);
792 * Functions for time stamping
794 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);
795 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev,
796 struct skb_shared_hwtstamps *hwts,
798 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev);
799 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev);
803 extern const struct ethtool_ops mlx4_en_ethtool_ops;
808 * printk / logging functions
812 void en_print(const char *level, const struct mlx4_en_priv *priv,
813 const char *format, ...);
815 #define en_dbg(mlevel, priv, format, ...) \
817 if (NETIF_MSG_##mlevel & (priv)->msg_enable) \
818 en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__); \
820 #define en_warn(priv, format, ...) \
821 en_print(KERN_WARNING, priv, format, ##__VA_ARGS__)
822 #define en_err(priv, format, ...) \
823 en_print(KERN_ERR, priv, format, ##__VA_ARGS__)
824 #define en_info(priv, format, ...) \
825 en_print(KERN_INFO, priv, format, ##__VA_ARGS__)
827 #define mlx4_err(mdev, format, ...) \
828 pr_err(DRV_NAME " %s: " format, \
829 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
830 #define mlx4_info(mdev, format, ...) \
831 pr_info(DRV_NAME " %s: " format, \
832 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
833 #define mlx4_warn(mdev, format, ...) \
834 pr_warn(DRV_NAME " %s: " format, \
835 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)