2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/mutex.h>
41 #include <linux/radix-tree.h>
42 #include <linux/rbtree.h>
43 #include <linux/timer.h>
44 #include <linux/semaphore.h>
45 #include <linux/workqueue.h>
47 #include <linux/mlx4/device.h>
48 #include <linux/mlx4/driver.h>
49 #include <linux/mlx4/doorbell.h>
50 #include <linux/mlx4/cmd.h>
52 #define DRV_NAME "mlx4_core"
53 #define PFX DRV_NAME ": "
54 #define DRV_VERSION "1.1"
55 #define DRV_RELDATE "Dec, 2011"
57 #define MLX4_FS_UDP_UC_EN (1 << 1)
58 #define MLX4_FS_TCP_UC_EN (1 << 2)
59 #define MLX4_FS_NUM_OF_L2_ADDR 8
60 #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7
61 #define MLX4_FS_NUM_MCG (1 << 17)
65 MLX4_FS_L2_L3_L4_HASH,
70 #define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */
71 #define MLX4_RATELIMIT_DEFAULT 0xffff
73 struct mlx4_set_port_prio2tc_context {
77 struct mlx4_port_scheduler_tc_cfg_be {
80 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
84 struct mlx4_set_port_scheduler_context {
85 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
89 MLX4_HCR_BASE = 0x80680,
90 MLX4_HCR_SIZE = 0x0001c,
91 MLX4_CLR_INT_SIZE = 0x00008,
92 MLX4_SLAVE_COMM_BASE = 0x0,
93 MLX4_COMM_PAGESIZE = 0x1000
97 MLX4_MAX_MGM_ENTRY_SIZE = 0x1000,
98 MLX4_MAX_QP_PER_MGM = 4 * (MLX4_MAX_MGM_ENTRY_SIZE / 16 - 2),
99 MLX4_MTT_ENTRY_PER_SEG = 8,
103 MLX4_NUM_PDS = 1 << 15
107 MLX4_CMPT_TYPE_QP = 0,
108 MLX4_CMPT_TYPE_SRQ = 1,
109 MLX4_CMPT_TYPE_CQ = 2,
110 MLX4_CMPT_TYPE_EQ = 3,
115 MLX4_CMPT_SHIFT = 24,
116 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
120 MLX4_MR_DISABLED = 0,
125 #define MLX4_COMM_TIME 10000
131 MLX4_COMM_CMD_VHCR_EN,
132 MLX4_COMM_CMD_VHCR_POST,
133 MLX4_COMM_CMD_FLR = 254
136 /*The flag indicates that the slave should delay the RESET cmd*/
137 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
138 /*indicates how many retries will be done if we are in the middle of FLR*/
139 #define NUM_OF_RESET_RETRIES 10
140 #define SLEEP_TIME_IN_RESET (2 * 1000)
153 MLX4_NUM_OF_RESOURCE_TYPE
156 enum mlx4_alloc_mode {
158 RES_OP_RESERVE_AND_MAP,
162 enum mlx4_res_tracker_free_type {
164 RES_TR_FREE_SLAVES_ONLY,
165 RES_TR_FREE_STRUCTS_ONLY,
169 *Virtual HCR structures.
170 * mlx4_vhcr is the sw representation, in machine endianess
172 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
173 * to FW to go through communication channel.
174 * It is big endian, and has the same structure as the physical HCR
175 * used by command interface
188 struct mlx4_vhcr_cmd {
199 struct mlx4_cmd_info {
204 bool encode_slave_id;
205 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
206 struct mlx4_cmd_mailbox *inbox);
207 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
208 struct mlx4_cmd_mailbox *inbox,
209 struct mlx4_cmd_mailbox *outbox,
210 struct mlx4_cmd_info *cmd);
213 #ifdef CONFIG_MLX4_DEBUG
214 extern int mlx4_debug_level;
215 #else /* CONFIG_MLX4_DEBUG */
216 #define mlx4_debug_level (0)
217 #endif /* CONFIG_MLX4_DEBUG */
219 #define mlx4_dbg(mdev, format, arg...) \
221 if (mlx4_debug_level) \
222 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
225 #define mlx4_err(mdev, format, arg...) \
226 dev_err(&mdev->pdev->dev, format, ##arg)
227 #define mlx4_info(mdev, format, arg...) \
228 dev_info(&mdev->pdev->dev, format, ##arg)
229 #define mlx4_warn(mdev, format, arg...) \
230 dev_warn(&mdev->pdev->dev, format, ##arg)
232 extern int mlx4_log_num_mgm_entry_size;
233 extern int log_mtts_per_seg;
235 #define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
236 #define ALL_SLAVES 0xff
246 unsigned long *table;
250 unsigned long **bits;
251 unsigned int *num_free;
258 struct mlx4_icm_table {
266 struct mlx4_icm **icm;
270 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
272 struct mlx4_mpt_entry {
286 __be32 first_byte_offset;
290 * Must be packed because start is 64 bits but only aligned to 32 bits.
292 struct mlx4_eq_context {
306 __be32 mtt_base_addr_l;
308 __be32 consumer_index;
309 __be32 producer_index;
313 struct mlx4_cq_context {
317 __be32 logsize_usrpage;
325 __be32 mtt_base_addr_l;
326 __be32 last_notified_index;
327 __be32 solicit_producer_index;
328 __be32 consumer_index;
329 __be32 producer_index;
334 struct mlx4_srq_context {
335 __be32 state_logsize_srqn;
339 __be32 pg_offset_cqn;
344 __be32 mtt_base_addr_l;
346 __be16 limit_watermark;
387 } __packed port_change;
389 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
391 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
392 } __packed comm_channel_arm;
397 } __packed mac_update;
403 } __packed flr_event;
405 __be16 current_temperature;
406 __be16 warning_threshold;
415 struct mlx4_dev *dev;
416 void __iomem *doorbell;
422 struct mlx4_buf_list *page_list;
426 struct mlx4_slave_eqe {
432 struct mlx4_slave_event_eq_info {
437 struct mlx4_profile {
451 struct mlx4_icm *fw_icm;
452 struct mlx4_icm *aux_icm;
466 MLX4_MCAST_CONFIG = 0,
467 MLX4_MCAST_DISABLE = 1,
468 MLX4_MCAST_ENABLE = 2,
471 #define VLAN_FLTR_SIZE 128
473 struct mlx4_vlan_fltr {
474 __be32 entry[VLAN_FLTR_SIZE];
477 struct mlx4_mcast_entry {
478 struct list_head list;
482 struct mlx4_promisc_qp {
483 struct list_head list;
487 struct mlx4_steer_index {
488 struct list_head list;
490 struct list_head duplicates;
493 #define MLX4_EVENT_TYPES_NUM 64
495 struct mlx4_slave_state {
502 u16 mtu[MLX4_MAX_PORTS + 1];
503 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
504 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
505 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
506 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
507 /* event type to eq number lookup */
508 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
512 /*initialized via the kzalloc*/
513 u8 is_slave_going_down;
519 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
522 struct mlx4_resource_tracker {
524 /* tree for each resources */
525 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
526 /* num_of_slave's lists, one per slave */
527 struct slave_list *slave_list;
530 #define SLAVE_EVENT_EQ_SIZE 128
531 struct mlx4_slave_event_eq {
535 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
538 struct mlx4_master_qp0_state {
539 int proxy_qp0_active;
544 struct mlx4_mfunc_master_ctx {
545 struct mlx4_slave_state *slave_state;
546 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
547 int init_port_ref[MLX4_MAX_PORTS + 1];
548 u16 max_mtu[MLX4_MAX_PORTS + 1];
549 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
550 struct mlx4_resource_tracker res_tracker;
551 struct workqueue_struct *comm_wq;
552 struct work_struct comm_work;
553 struct work_struct slave_event_work;
554 struct work_struct slave_flr_event_work;
555 spinlock_t slave_state_lock;
556 __be32 comm_arm_bit_vector[4];
557 struct mlx4_eqe cmd_eqe;
558 struct mlx4_slave_event_eq slave_eq;
559 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
563 struct mlx4_comm __iomem *comm;
564 struct mlx4_vhcr_cmd *vhcr;
567 struct mlx4_mfunc_master_ctx master;
571 struct pci_pool *pool;
573 struct mutex hcr_mutex;
574 struct semaphore poll_sem;
575 struct semaphore event_sem;
576 struct semaphore slave_sem;
578 spinlock_t context_lock;
580 struct mlx4_cmd_context *context;
587 struct mlx4_uar_table {
588 struct mlx4_bitmap bitmap;
591 struct mlx4_mr_table {
592 struct mlx4_bitmap mpt_bitmap;
593 struct mlx4_buddy mtt_buddy;
596 struct mlx4_icm_table mtt_table;
597 struct mlx4_icm_table dmpt_table;
600 struct mlx4_cq_table {
601 struct mlx4_bitmap bitmap;
603 struct radix_tree_root tree;
604 struct mlx4_icm_table table;
605 struct mlx4_icm_table cmpt_table;
608 struct mlx4_eq_table {
609 struct mlx4_bitmap bitmap;
611 void __iomem *clr_int;
612 void __iomem **uar_map;
615 struct mlx4_icm_table table;
616 struct mlx4_icm_table cmpt_table;
621 struct mlx4_srq_table {
622 struct mlx4_bitmap bitmap;
624 struct radix_tree_root tree;
625 struct mlx4_icm_table table;
626 struct mlx4_icm_table cmpt_table;
629 struct mlx4_qp_table {
630 struct mlx4_bitmap bitmap;
634 struct mlx4_icm_table qp_table;
635 struct mlx4_icm_table auxc_table;
636 struct mlx4_icm_table altc_table;
637 struct mlx4_icm_table rdmarc_table;
638 struct mlx4_icm_table cmpt_table;
641 struct mlx4_mcg_table {
643 struct mlx4_bitmap bitmap;
644 struct mlx4_icm_table table;
647 struct mlx4_catas_err {
649 struct timer_list timer;
650 struct list_head list;
653 #define MLX4_MAX_MAC_NUM 128
654 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
656 struct mlx4_mac_table {
657 __be64 entries[MLX4_MAX_MAC_NUM];
658 int refs[MLX4_MAX_MAC_NUM];
664 #define MLX4_MAX_VLAN_NUM 128
665 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
667 struct mlx4_vlan_table {
668 __be32 entries[MLX4_MAX_VLAN_NUM];
669 int refs[MLX4_MAX_VLAN_NUM];
675 #define SET_PORT_GEN_ALL_VALID 0x7
676 #define SET_PORT_PROMISC_SHIFT 31
677 #define SET_PORT_MC_PROMISC_SHIFT 30
680 MCAST_DIRECT_ONLY = 0,
686 struct mlx4_set_port_general_context {
699 struct mlx4_set_port_rqp_calc_context {
717 struct mlx4_mac_entry {
722 struct mlx4_port_info {
723 struct mlx4_dev *dev;
726 struct device_attribute port_attr;
727 enum mlx4_port_type tmp_type;
728 char dev_mtu_name[16];
729 struct device_attribute port_mtu_attr;
730 struct mlx4_mac_table mac_table;
731 struct radix_tree_root mac_tree;
732 struct mlx4_vlan_table vlan_table;
737 struct mlx4_dev *dev;
738 u8 do_sense_port[MLX4_MAX_PORTS + 1];
739 u8 sense_allowed[MLX4_MAX_PORTS + 1];
740 struct delayed_work sense_poll;
743 struct mlx4_msix_ctl {
745 struct mutex pool_lock;
749 struct list_head promisc_qps[MLX4_NUM_STEERS];
750 struct list_head steer_entries[MLX4_NUM_STEERS];
756 struct list_head dev_list;
757 struct list_head ctx_list;
760 struct list_head pgdir_list;
761 struct mutex pgdir_mutex;
765 struct mlx4_mfunc mfunc;
767 struct mlx4_bitmap pd_bitmap;
768 struct mlx4_bitmap xrcd_bitmap;
769 struct mlx4_uar_table uar_table;
770 struct mlx4_mr_table mr_table;
771 struct mlx4_cq_table cq_table;
772 struct mlx4_eq_table eq_table;
773 struct mlx4_srq_table srq_table;
774 struct mlx4_qp_table qp_table;
775 struct mlx4_mcg_table mcg_table;
776 struct mlx4_bitmap counters_bitmap;
778 struct mlx4_catas_err catas_err;
780 void __iomem *clr_base;
782 struct mlx4_uar driver_uar;
784 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
785 struct mlx4_sense sense;
786 struct mutex port_mutex;
787 struct mlx4_msix_ctl msix_ctl;
788 struct mlx4_steer *steer;
789 struct list_head bf_list;
790 struct mutex bf_mutex;
791 struct io_mapping *bf_mapping;
796 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
798 return container_of(dev, struct mlx4_priv, dev);
801 #define MLX4_SENSE_RANGE (HZ * 3)
803 extern struct workqueue_struct *mlx4_wq;
805 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
806 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
807 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
808 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
809 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
810 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
811 u32 reserved_bot, u32 resetrved_top);
812 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
814 int mlx4_reset(struct mlx4_dev *dev);
816 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
817 void mlx4_free_eq_table(struct mlx4_dev *dev);
819 int mlx4_init_pd_table(struct mlx4_dev *dev);
820 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
821 int mlx4_init_uar_table(struct mlx4_dev *dev);
822 int mlx4_init_mr_table(struct mlx4_dev *dev);
823 int mlx4_init_eq_table(struct mlx4_dev *dev);
824 int mlx4_init_cq_table(struct mlx4_dev *dev);
825 int mlx4_init_qp_table(struct mlx4_dev *dev);
826 int mlx4_init_srq_table(struct mlx4_dev *dev);
827 int mlx4_init_mcg_table(struct mlx4_dev *dev);
829 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
830 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
831 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
832 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
833 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
834 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
835 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
836 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
837 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
838 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
839 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
840 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
841 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
842 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
843 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
844 int __mlx4_mr_reserve(struct mlx4_dev *dev);
845 void __mlx4_mr_release(struct mlx4_dev *dev, u32 index);
846 int __mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index);
847 void __mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index);
848 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
849 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
851 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
852 struct mlx4_vhcr *vhcr,
853 struct mlx4_cmd_mailbox *inbox,
854 struct mlx4_cmd_mailbox *outbox,
855 struct mlx4_cmd_info *cmd);
856 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
857 struct mlx4_vhcr *vhcr,
858 struct mlx4_cmd_mailbox *inbox,
859 struct mlx4_cmd_mailbox *outbox,
860 struct mlx4_cmd_info *cmd);
861 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
862 struct mlx4_vhcr *vhcr,
863 struct mlx4_cmd_mailbox *inbox,
864 struct mlx4_cmd_mailbox *outbox,
865 struct mlx4_cmd_info *cmd);
866 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
867 struct mlx4_vhcr *vhcr,
868 struct mlx4_cmd_mailbox *inbox,
869 struct mlx4_cmd_mailbox *outbox,
870 struct mlx4_cmd_info *cmd);
871 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
872 struct mlx4_vhcr *vhcr,
873 struct mlx4_cmd_mailbox *inbox,
874 struct mlx4_cmd_mailbox *outbox,
875 struct mlx4_cmd_info *cmd);
876 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
877 struct mlx4_vhcr *vhcr,
878 struct mlx4_cmd_mailbox *inbox,
879 struct mlx4_cmd_mailbox *outbox,
880 struct mlx4_cmd_info *cmd);
881 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
882 struct mlx4_vhcr *vhcr,
883 struct mlx4_cmd_mailbox *inbox,
884 struct mlx4_cmd_mailbox *outbox,
885 struct mlx4_cmd_info *cmd);
886 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
888 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
889 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
890 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
891 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
892 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
893 int start_index, int npages, u64 *page_list);
894 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
895 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
896 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
897 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
899 void mlx4_start_catas_poll(struct mlx4_dev *dev);
900 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
901 void mlx4_catas_init(void);
902 int mlx4_restart_one(struct pci_dev *pdev);
903 int mlx4_register_device(struct mlx4_dev *dev);
904 void mlx4_unregister_device(struct mlx4_dev *dev);
905 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, int port);
908 struct mlx4_init_hca_param;
910 u64 mlx4_make_profile(struct mlx4_dev *dev,
911 struct mlx4_profile *request,
912 struct mlx4_dev_cap *dev_cap,
913 struct mlx4_init_hca_param *init_hca);
914 void mlx4_master_comm_channel(struct work_struct *work);
915 void mlx4_gen_slave_eqe(struct work_struct *work);
916 void mlx4_master_handle_slave_flr(struct work_struct *work);
918 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
919 struct mlx4_vhcr *vhcr,
920 struct mlx4_cmd_mailbox *inbox,
921 struct mlx4_cmd_mailbox *outbox,
922 struct mlx4_cmd_info *cmd);
923 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
924 struct mlx4_vhcr *vhcr,
925 struct mlx4_cmd_mailbox *inbox,
926 struct mlx4_cmd_mailbox *outbox,
927 struct mlx4_cmd_info *cmd);
928 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
929 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
930 struct mlx4_cmd_mailbox *outbox,
931 struct mlx4_cmd_info *cmd);
932 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
933 struct mlx4_vhcr *vhcr,
934 struct mlx4_cmd_mailbox *inbox,
935 struct mlx4_cmd_mailbox *outbox,
936 struct mlx4_cmd_info *cmd);
937 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
938 struct mlx4_vhcr *vhcr,
939 struct mlx4_cmd_mailbox *inbox,
940 struct mlx4_cmd_mailbox *outbox,
941 struct mlx4_cmd_info *cmd);
942 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
943 struct mlx4_vhcr *vhcr,
944 struct mlx4_cmd_mailbox *inbox,
945 struct mlx4_cmd_mailbox *outbox,
946 struct mlx4_cmd_info *cmd);
947 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
948 struct mlx4_vhcr *vhcr,
949 struct mlx4_cmd_mailbox *inbox,
950 struct mlx4_cmd_mailbox *outbox,
951 struct mlx4_cmd_info *cmd);
952 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
953 struct mlx4_vhcr *vhcr,
954 struct mlx4_cmd_mailbox *inbox,
955 struct mlx4_cmd_mailbox *outbox,
956 struct mlx4_cmd_info *cmd);
957 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
958 struct mlx4_vhcr *vhcr,
959 struct mlx4_cmd_mailbox *inbox,
960 struct mlx4_cmd_mailbox *outbox,
961 struct mlx4_cmd_info *cmd);
962 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
963 struct mlx4_vhcr *vhcr,
964 struct mlx4_cmd_mailbox *inbox,
965 struct mlx4_cmd_mailbox *outbox,
966 struct mlx4_cmd_info *cmd);
967 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
968 struct mlx4_vhcr *vhcr,
969 struct mlx4_cmd_mailbox *inbox,
970 struct mlx4_cmd_mailbox *outbox,
971 struct mlx4_cmd_info *cmd);
972 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
973 struct mlx4_vhcr *vhcr,
974 struct mlx4_cmd_mailbox *inbox,
975 struct mlx4_cmd_mailbox *outbox,
976 struct mlx4_cmd_info *cmd);
977 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
978 struct mlx4_vhcr *vhcr,
979 struct mlx4_cmd_mailbox *inbox,
980 struct mlx4_cmd_mailbox *outbox,
981 struct mlx4_cmd_info *cmd);
982 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
983 struct mlx4_vhcr *vhcr,
984 struct mlx4_cmd_mailbox *inbox,
985 struct mlx4_cmd_mailbox *outbox,
986 struct mlx4_cmd_info *cmd);
987 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
988 struct mlx4_vhcr *vhcr,
989 struct mlx4_cmd_mailbox *inbox,
990 struct mlx4_cmd_mailbox *outbox,
991 struct mlx4_cmd_info *cmd);
992 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
993 struct mlx4_vhcr *vhcr,
994 struct mlx4_cmd_mailbox *inbox,
995 struct mlx4_cmd_mailbox *outbox,
996 struct mlx4_cmd_info *cmd);
997 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
998 struct mlx4_vhcr *vhcr,
999 struct mlx4_cmd_mailbox *inbox,
1000 struct mlx4_cmd_mailbox *outbox,
1001 struct mlx4_cmd_info *cmd);
1002 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1003 struct mlx4_vhcr *vhcr,
1004 struct mlx4_cmd_mailbox *inbox,
1005 struct mlx4_cmd_mailbox *outbox,
1006 struct mlx4_cmd_info *cmd);
1008 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
1010 int mlx4_cmd_init(struct mlx4_dev *dev);
1011 void mlx4_cmd_cleanup(struct mlx4_dev *dev);
1012 int mlx4_multi_func_init(struct mlx4_dev *dev);
1013 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
1014 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1015 int mlx4_cmd_use_events(struct mlx4_dev *dev);
1016 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1018 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1019 unsigned long timeout);
1021 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1022 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1024 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1026 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1028 void mlx4_handle_catas_err(struct mlx4_dev *dev);
1030 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1031 enum mlx4_port_type *type);
1032 void mlx4_do_sense_ports(struct mlx4_dev *dev,
1033 enum mlx4_port_type *stype,
1034 enum mlx4_port_type *defaults);
1035 void mlx4_start_sense(struct mlx4_dev *dev);
1036 void mlx4_stop_sense(struct mlx4_dev *dev);
1037 void mlx4_sense_init(struct mlx4_dev *dev);
1038 int mlx4_check_port_params(struct mlx4_dev *dev,
1039 enum mlx4_port_type *port_type);
1040 int mlx4_change_port_types(struct mlx4_dev *dev,
1041 enum mlx4_port_type *port_types);
1043 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1044 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1046 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port);
1047 /* resource tracker functions*/
1048 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1049 enum mlx4_resource resource_type,
1050 u64 resource_id, int *slave);
1051 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1052 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1054 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1055 enum mlx4_res_tracker_free_type type);
1057 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1058 struct mlx4_vhcr *vhcr,
1059 struct mlx4_cmd_mailbox *inbox,
1060 struct mlx4_cmd_mailbox *outbox,
1061 struct mlx4_cmd_info *cmd);
1062 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1063 struct mlx4_vhcr *vhcr,
1064 struct mlx4_cmd_mailbox *inbox,
1065 struct mlx4_cmd_mailbox *outbox,
1066 struct mlx4_cmd_info *cmd);
1067 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1068 struct mlx4_vhcr *vhcr,
1069 struct mlx4_cmd_mailbox *inbox,
1070 struct mlx4_cmd_mailbox *outbox,
1071 struct mlx4_cmd_info *cmd);
1072 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1073 struct mlx4_vhcr *vhcr,
1074 struct mlx4_cmd_mailbox *inbox,
1075 struct mlx4_cmd_mailbox *outbox,
1076 struct mlx4_cmd_info *cmd);
1077 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1078 struct mlx4_vhcr *vhcr,
1079 struct mlx4_cmd_mailbox *inbox,
1080 struct mlx4_cmd_mailbox *outbox,
1081 struct mlx4_cmd_info *cmd);
1082 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1083 struct mlx4_vhcr *vhcr,
1084 struct mlx4_cmd_mailbox *inbox,
1085 struct mlx4_cmd_mailbox *outbox,
1086 struct mlx4_cmd_info *cmd);
1087 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1090 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1091 struct mlx4_vhcr *vhcr,
1092 struct mlx4_cmd_mailbox *inbox,
1093 struct mlx4_cmd_mailbox *outbox,
1094 struct mlx4_cmd_info *cmd);
1096 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1097 struct mlx4_vhcr *vhcr,
1098 struct mlx4_cmd_mailbox *inbox,
1099 struct mlx4_cmd_mailbox *outbox,
1100 struct mlx4_cmd_info *cmd);
1101 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1102 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1103 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1104 int block_mcast_loopback, enum mlx4_protocol prot,
1105 enum mlx4_steer_type steer);
1106 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1107 struct mlx4_vhcr *vhcr,
1108 struct mlx4_cmd_mailbox *inbox,
1109 struct mlx4_cmd_mailbox *outbox,
1110 struct mlx4_cmd_info *cmd);
1111 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1112 struct mlx4_vhcr *vhcr,
1113 struct mlx4_cmd_mailbox *inbox,
1114 struct mlx4_cmd_mailbox *outbox,
1115 struct mlx4_cmd_info *cmd);
1116 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1117 int port, void *buf);
1118 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1119 struct mlx4_cmd_mailbox *outbox);
1120 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1121 struct mlx4_vhcr *vhcr,
1122 struct mlx4_cmd_mailbox *inbox,
1123 struct mlx4_cmd_mailbox *outbox,
1124 struct mlx4_cmd_info *cmd);
1125 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1126 struct mlx4_vhcr *vhcr,
1127 struct mlx4_cmd_mailbox *inbox,
1128 struct mlx4_cmd_mailbox *outbox,
1129 struct mlx4_cmd_info *cmd);
1130 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1131 struct mlx4_vhcr *vhcr,
1132 struct mlx4_cmd_mailbox *inbox,
1133 struct mlx4_cmd_mailbox *outbox,
1134 struct mlx4_cmd_info *cmd);
1135 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1136 struct mlx4_vhcr *vhcr,
1137 struct mlx4_cmd_mailbox *inbox,
1138 struct mlx4_cmd_mailbox *outbox,
1139 struct mlx4_cmd_info *cmd);
1140 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1141 struct mlx4_vhcr *vhcr,
1142 struct mlx4_cmd_mailbox *inbox,
1143 struct mlx4_cmd_mailbox *outbox,
1144 struct mlx4_cmd_info *cmd);
1146 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1147 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1149 static inline void set_param_l(u64 *arg, u32 val)
1151 *((u32 *)arg) = val;
1154 static inline void set_param_h(u64 *arg, u32 val)
1156 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1159 static inline u32 get_param_l(u64 *arg)
1161 return (u32) (*arg & 0xffffffff);
1164 static inline u32 get_param_h(u64 *arg)
1166 return (u32)(*arg >> 32);
1169 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1171 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1174 #define NOT_MASKED_PD_BITS 17