2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/mutex.h>
41 #include <linux/radix-tree.h>
42 #include <linux/rbtree.h>
43 #include <linux/timer.h>
44 #include <linux/semaphore.h>
45 #include <linux/workqueue.h>
46 #include <linux/interrupt.h>
47 #include <linux/spinlock.h>
49 #include <linux/mlx4/device.h>
50 #include <linux/mlx4/driver.h>
51 #include <linux/mlx4/doorbell.h>
52 #include <linux/mlx4/cmd.h>
54 #define DRV_NAME "mlx4_core"
55 #define PFX DRV_NAME ": "
56 #define DRV_VERSION "2.2-1"
57 #define DRV_RELDATE "Feb, 2014"
59 #define MLX4_FS_UDP_UC_EN (1 << 1)
60 #define MLX4_FS_TCP_UC_EN (1 << 2)
61 #define MLX4_FS_NUM_OF_L2_ADDR 8
62 #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7
63 #define MLX4_FS_NUM_MCG (1 << 17)
65 #define INIT_HCA_TPT_MW_ENABLE (1 << 7)
67 struct mlx4_set_port_prio2tc_context {
71 struct mlx4_port_scheduler_tc_cfg_be {
74 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
78 struct mlx4_set_port_scheduler_context {
79 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
83 MLX4_HCR_BASE = 0x80680,
84 MLX4_HCR_SIZE = 0x0001c,
85 MLX4_CLR_INT_SIZE = 0x00008,
86 MLX4_SLAVE_COMM_BASE = 0x0,
87 MLX4_COMM_PAGESIZE = 0x1000,
88 MLX4_CLOCK_SIZE = 0x00008
92 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10,
93 MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7,
94 MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12,
95 MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2),
96 MLX4_MTT_ENTRY_PER_SEG = 8,
100 MLX4_NUM_PDS = 1 << 15
104 MLX4_CMPT_TYPE_QP = 0,
105 MLX4_CMPT_TYPE_SRQ = 1,
106 MLX4_CMPT_TYPE_CQ = 2,
107 MLX4_CMPT_TYPE_EQ = 3,
112 MLX4_CMPT_SHIFT = 24,
113 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
116 enum mlx4_mpt_state {
117 MLX4_MPT_DISABLED = 0,
122 #define MLX4_COMM_TIME 10000
128 MLX4_COMM_CMD_VHCR_EN,
129 MLX4_COMM_CMD_VHCR_POST,
130 MLX4_COMM_CMD_FLR = 254
134 MLX4_VF_SMI_DISABLED,
138 /*The flag indicates that the slave should delay the RESET cmd*/
139 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
140 /*indicates how many retries will be done if we are in the middle of FLR*/
141 #define NUM_OF_RESET_RETRIES 10
142 #define SLEEP_TIME_IN_RESET (2 * 1000)
155 MLX4_NUM_OF_RESOURCE_TYPE
158 enum mlx4_alloc_mode {
160 RES_OP_RESERVE_AND_MAP,
164 enum mlx4_res_tracker_free_type {
166 RES_TR_FREE_SLAVES_ONLY,
167 RES_TR_FREE_STRUCTS_ONLY,
171 *Virtual HCR structures.
172 * mlx4_vhcr is the sw representation, in machine endianess
174 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
175 * to FW to go through communication channel.
176 * It is big endian, and has the same structure as the physical HCR
177 * used by command interface
190 struct mlx4_vhcr_cmd {
201 struct mlx4_cmd_info {
206 bool encode_slave_id;
207 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
208 struct mlx4_cmd_mailbox *inbox);
209 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
210 struct mlx4_cmd_mailbox *inbox,
211 struct mlx4_cmd_mailbox *outbox,
212 struct mlx4_cmd_info *cmd);
215 #ifdef CONFIG_MLX4_DEBUG
216 extern int mlx4_debug_level;
217 #else /* CONFIG_MLX4_DEBUG */
218 #define mlx4_debug_level (0)
219 #endif /* CONFIG_MLX4_DEBUG */
221 #define mlx4_dbg(mdev, format, ...) \
223 if (mlx4_debug_level) \
224 dev_printk(KERN_DEBUG, &(mdev)->pdev->dev, format, \
228 #define mlx4_err(mdev, format, ...) \
229 dev_err(&(mdev)->pdev->dev, format, ##__VA_ARGS__)
230 #define mlx4_info(mdev, format, ...) \
231 dev_info(&(mdev)->pdev->dev, format, ##__VA_ARGS__)
232 #define mlx4_warn(mdev, format, ...) \
233 dev_warn(&(mdev)->pdev->dev, format, ##__VA_ARGS__)
235 extern int mlx4_log_num_mgm_entry_size;
236 extern int log_mtts_per_seg;
238 #define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
239 #define ALL_SLAVES 0xff
250 unsigned long *table;
254 unsigned long **bits;
255 unsigned int *num_free;
262 struct mlx4_icm_table {
270 struct mlx4_icm **icm;
273 #define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28)
274 #define MLX4_MPT_FLAG_FREE (0x3UL << 28)
275 #define MLX4_MPT_FLAG_MIO (1 << 17)
276 #define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15)
277 #define MLX4_MPT_FLAG_PHYSICAL (1 << 9)
278 #define MLX4_MPT_FLAG_REGION (1 << 8)
280 #define MLX4_MPT_PD_MASK (0x1FFFFUL)
281 #define MLX4_MPT_PD_VF_MASK (0xFE0000UL)
282 #define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27)
283 #define MLX4_MPT_PD_FLAG_RAE (1 << 28)
284 #define MLX4_MPT_PD_FLAG_EN_INV (3 << 24)
286 #define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7)
288 #define MLX4_MPT_STATUS_SW 0xF0
289 #define MLX4_MPT_STATUS_HW 0x00
291 #define MLX4_CQE_SIZE_MASK_STRIDE 0x3
292 #define MLX4_EQE_SIZE_MASK_STRIDE 0x30
295 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
297 struct mlx4_mpt_entry {
311 __be32 first_byte_offset;
315 * Must be packed because start is 64 bits but only aligned to 32 bits.
317 struct mlx4_eq_context {
331 __be32 mtt_base_addr_l;
333 __be32 consumer_index;
334 __be32 producer_index;
338 struct mlx4_cq_context {
342 __be32 logsize_usrpage;
350 __be32 mtt_base_addr_l;
351 __be32 last_notified_index;
352 __be32 solicit_producer_index;
353 __be32 consumer_index;
354 __be32 producer_index;
359 struct mlx4_srq_context {
360 __be32 state_logsize_srqn;
364 __be32 pg_offset_cqn;
369 __be32 mtt_base_addr_l;
371 __be16 limit_watermark;
379 struct mlx4_eq_tasklet {
380 struct list_head list;
381 struct list_head process_list;
382 struct tasklet_struct task;
383 /* lock on completion tasklet list */
388 struct mlx4_dev *dev;
389 void __iomem *doorbell;
395 struct mlx4_buf_list *page_list;
397 struct mlx4_eq_tasklet tasklet_ctx;
400 struct mlx4_slave_eqe {
406 struct mlx4_slave_event_eq_info {
411 struct mlx4_profile {
426 struct mlx4_icm *fw_icm;
427 struct mlx4_icm *aux_icm;
442 MLX4_MCAST_CONFIG = 0,
443 MLX4_MCAST_DISABLE = 1,
444 MLX4_MCAST_ENABLE = 2,
447 #define VLAN_FLTR_SIZE 128
449 struct mlx4_vlan_fltr {
450 __be32 entry[VLAN_FLTR_SIZE];
453 struct mlx4_mcast_entry {
454 struct list_head list;
458 struct mlx4_promisc_qp {
459 struct list_head list;
463 struct mlx4_steer_index {
464 struct list_head list;
466 struct list_head duplicates;
469 #define MLX4_EVENT_TYPES_NUM 64
471 struct mlx4_slave_state {
479 u16 mtu[MLX4_MAX_PORTS + 1];
480 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
481 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
482 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
483 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
484 /* event type to eq number lookup */
485 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
489 /*initialized via the kzalloc*/
490 u8 is_slave_going_down;
492 enum slave_port_state port_state[MLX4_MAX_PORTS + 1];
495 #define MLX4_VGT 4095
498 struct mlx4_vport_state {
507 struct mlx4_vf_admin_state {
508 struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1];
509 u8 enable_smi[MLX4_MAX_PORTS + 1];
512 struct mlx4_vport_oper_state {
513 struct mlx4_vport_state state;
518 struct mlx4_vf_oper_state {
519 struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1];
520 u8 smi_enabled[MLX4_MAX_PORTS + 1];
525 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
528 struct resource_allocator {
529 spinlock_t alloc_lock; /* protect quotas */
532 int res_port_rsvd[MLX4_MAX_PORTS];
536 int res_port_free[MLX4_MAX_PORTS];
543 struct mlx4_resource_tracker {
545 /* tree for each resources */
546 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
547 /* num_of_slave's lists, one per slave */
548 struct slave_list *slave_list;
549 struct resource_allocator res_alloc[MLX4_NUM_OF_RESOURCE_TYPE];
552 #define SLAVE_EVENT_EQ_SIZE 128
553 struct mlx4_slave_event_eq {
557 spinlock_t event_lock;
558 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
561 struct mlx4_master_qp0_state {
562 int proxy_qp0_active;
567 struct mlx4_mfunc_master_ctx {
568 struct mlx4_slave_state *slave_state;
569 struct mlx4_vf_admin_state *vf_admin;
570 struct mlx4_vf_oper_state *vf_oper;
571 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
572 int init_port_ref[MLX4_MAX_PORTS + 1];
573 u16 max_mtu[MLX4_MAX_PORTS + 1];
574 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
575 struct mlx4_resource_tracker res_tracker;
576 struct workqueue_struct *comm_wq;
577 struct work_struct comm_work;
578 struct work_struct slave_event_work;
579 struct work_struct slave_flr_event_work;
580 spinlock_t slave_state_lock;
581 __be32 comm_arm_bit_vector[4];
582 struct mlx4_eqe cmd_eqe;
583 struct mlx4_slave_event_eq slave_eq;
584 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
588 struct mlx4_comm __iomem *comm;
589 struct mlx4_vhcr_cmd *vhcr;
592 struct mlx4_mfunc_master_ctx master;
595 #define MGM_QPN_MASK 0x00FFFFFF
596 #define MGM_BLCK_LB_BIT 30
599 __be32 next_gid_index;
600 __be32 members_count;
603 __be32 qp[MLX4_MAX_QP_PER_MGM];
607 struct pci_pool *pool;
609 struct mutex hcr_mutex;
610 struct mutex slave_cmd_mutex;
611 struct semaphore poll_sem;
612 struct semaphore event_sem;
614 spinlock_t context_lock;
616 struct mlx4_cmd_context *context;
625 MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0,
626 MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1,
627 MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE = 1 << 2,
629 struct mlx4_vf_immed_vlan_work {
630 struct work_struct work;
631 struct mlx4_priv *priv;
643 struct mlx4_uar_table {
644 struct mlx4_bitmap bitmap;
647 struct mlx4_mr_table {
648 struct mlx4_bitmap mpt_bitmap;
649 struct mlx4_buddy mtt_buddy;
652 struct mlx4_icm_table mtt_table;
653 struct mlx4_icm_table dmpt_table;
656 struct mlx4_cq_table {
657 struct mlx4_bitmap bitmap;
659 struct radix_tree_root tree;
660 struct mlx4_icm_table table;
661 struct mlx4_icm_table cmpt_table;
664 struct mlx4_eq_table {
665 struct mlx4_bitmap bitmap;
667 void __iomem *clr_int;
668 void __iomem **uar_map;
671 struct mlx4_icm_table table;
672 struct mlx4_icm_table cmpt_table;
677 struct mlx4_srq_table {
678 struct mlx4_bitmap bitmap;
680 struct radix_tree_root tree;
681 struct mlx4_icm_table table;
682 struct mlx4_icm_table cmpt_table;
685 enum mlx4_qp_table_zones {
686 MLX4_QP_TABLE_ZONE_GENERAL,
687 MLX4_QP_TABLE_ZONE_RSS,
688 MLX4_QP_TABLE_ZONE_RAW_ETH,
689 MLX4_QP_TABLE_ZONE_NUM
692 #define MLX4_A0_STEERING_TABLE_SIZE 256
694 struct mlx4_qp_table {
695 struct mlx4_bitmap *bitmap_gen;
696 struct mlx4_zone_allocator *zones;
697 u32 zones_uids[MLX4_QP_TABLE_ZONE_NUM];
701 struct mlx4_icm_table qp_table;
702 struct mlx4_icm_table auxc_table;
703 struct mlx4_icm_table altc_table;
704 struct mlx4_icm_table rdmarc_table;
705 struct mlx4_icm_table cmpt_table;
708 struct mlx4_mcg_table {
710 struct mlx4_bitmap bitmap;
711 struct mlx4_icm_table table;
714 struct mlx4_catas_err {
716 struct timer_list timer;
717 struct list_head list;
720 #define MLX4_MAX_MAC_NUM 128
721 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
723 struct mlx4_mac_table {
724 __be64 entries[MLX4_MAX_MAC_NUM];
725 int refs[MLX4_MAX_MAC_NUM];
731 #define MLX4_ROCE_GID_ENTRY_SIZE 16
733 struct mlx4_roce_gid_entry {
734 u8 raw[MLX4_ROCE_GID_ENTRY_SIZE];
737 struct mlx4_roce_gid_table {
738 struct mlx4_roce_gid_entry roce_gids[MLX4_ROCE_MAX_GIDS];
742 #define MLX4_MAX_VLAN_NUM 128
743 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
745 struct mlx4_vlan_table {
746 __be32 entries[MLX4_MAX_VLAN_NUM];
747 int refs[MLX4_MAX_VLAN_NUM];
753 #define SET_PORT_GEN_ALL_VALID 0x7
754 #define SET_PORT_PROMISC_SHIFT 31
755 #define SET_PORT_MC_PROMISC_SHIFT 30
758 MCAST_DIRECT_ONLY = 0,
764 struct mlx4_set_port_general_context {
777 struct mlx4_set_port_rqp_calc_context {
795 struct mlx4_port_info {
796 struct mlx4_dev *dev;
799 struct device_attribute port_attr;
800 enum mlx4_port_type tmp_type;
801 char dev_mtu_name[16];
802 struct device_attribute port_mtu_attr;
803 struct mlx4_mac_table mac_table;
804 struct mlx4_vlan_table vlan_table;
805 struct mlx4_roce_gid_table gid_table;
810 struct mlx4_dev *dev;
811 u8 do_sense_port[MLX4_MAX_PORTS + 1];
812 u8 sense_allowed[MLX4_MAX_PORTS + 1];
813 struct delayed_work sense_poll;
816 struct mlx4_msix_ctl {
818 struct mutex pool_lock;
822 struct list_head promisc_qps[MLX4_NUM_STEERS];
823 struct list_head steer_entries[MLX4_NUM_STEERS];
827 MLX4_PCI_DEV_IS_VF = 1 << 0,
828 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1,
839 struct list_head dev_list;
840 struct list_head ctx_list;
846 struct list_head pgdir_list;
847 struct mutex pgdir_mutex;
851 struct mlx4_mfunc mfunc;
853 struct mlx4_bitmap pd_bitmap;
854 struct mlx4_bitmap xrcd_bitmap;
855 struct mlx4_uar_table uar_table;
856 struct mlx4_mr_table mr_table;
857 struct mlx4_cq_table cq_table;
858 struct mlx4_eq_table eq_table;
859 struct mlx4_srq_table srq_table;
860 struct mlx4_qp_table qp_table;
861 struct mlx4_mcg_table mcg_table;
862 struct mlx4_bitmap counters_bitmap;
864 struct mlx4_catas_err catas_err;
866 void __iomem *clr_base;
868 struct mlx4_uar driver_uar;
870 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
871 struct mlx4_sense sense;
872 struct mutex port_mutex;
873 struct mlx4_msix_ctl msix_ctl;
874 struct mlx4_steer *steer;
875 struct list_head bf_list;
876 struct mutex bf_mutex;
877 struct io_mapping *bf_mapping;
878 void __iomem *clock_mapping;
881 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
882 __be64 slave_node_guids[MLX4_MFUNC_MAX];
884 atomic_t opreq_count;
885 struct work_struct opreq_task;
888 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
890 return container_of(dev, struct mlx4_priv, dev);
893 #define MLX4_SENSE_RANGE (HZ * 3)
895 extern struct workqueue_struct *mlx4_wq;
897 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
898 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj, int use_rr);
899 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt,
900 int align, u32 skip_mask);
901 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt,
903 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
904 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
905 u32 reserved_bot, u32 resetrved_top);
906 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
908 int mlx4_reset(struct mlx4_dev *dev);
910 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
911 void mlx4_free_eq_table(struct mlx4_dev *dev);
913 int mlx4_init_pd_table(struct mlx4_dev *dev);
914 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
915 int mlx4_init_uar_table(struct mlx4_dev *dev);
916 int mlx4_init_mr_table(struct mlx4_dev *dev);
917 int mlx4_init_eq_table(struct mlx4_dev *dev);
918 int mlx4_init_cq_table(struct mlx4_dev *dev);
919 int mlx4_init_qp_table(struct mlx4_dev *dev);
920 int mlx4_init_srq_table(struct mlx4_dev *dev);
921 int mlx4_init_mcg_table(struct mlx4_dev *dev);
923 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
924 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
925 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
926 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
927 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
928 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
929 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
930 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
931 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
932 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn, gfp_t gfp);
933 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
934 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
935 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
936 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
937 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
938 int __mlx4_mpt_reserve(struct mlx4_dev *dev);
939 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index);
940 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index, gfp_t gfp);
941 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index);
942 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
943 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
945 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
946 struct mlx4_vhcr *vhcr,
947 struct mlx4_cmd_mailbox *inbox,
948 struct mlx4_cmd_mailbox *outbox,
949 struct mlx4_cmd_info *cmd);
950 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
951 struct mlx4_vhcr *vhcr,
952 struct mlx4_cmd_mailbox *inbox,
953 struct mlx4_cmd_mailbox *outbox,
954 struct mlx4_cmd_info *cmd);
955 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
956 struct mlx4_vhcr *vhcr,
957 struct mlx4_cmd_mailbox *inbox,
958 struct mlx4_cmd_mailbox *outbox,
959 struct mlx4_cmd_info *cmd);
960 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
961 struct mlx4_vhcr *vhcr,
962 struct mlx4_cmd_mailbox *inbox,
963 struct mlx4_cmd_mailbox *outbox,
964 struct mlx4_cmd_info *cmd);
965 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
966 struct mlx4_vhcr *vhcr,
967 struct mlx4_cmd_mailbox *inbox,
968 struct mlx4_cmd_mailbox *outbox,
969 struct mlx4_cmd_info *cmd);
970 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
971 struct mlx4_vhcr *vhcr,
972 struct mlx4_cmd_mailbox *inbox,
973 struct mlx4_cmd_mailbox *outbox,
974 struct mlx4_cmd_info *cmd);
975 int mlx4_CONFIG_DEV_wrapper(struct mlx4_dev *dev, int slave,
976 struct mlx4_vhcr *vhcr,
977 struct mlx4_cmd_mailbox *inbox,
978 struct mlx4_cmd_mailbox *outbox,
979 struct mlx4_cmd_info *cmd);
980 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
981 struct mlx4_vhcr *vhcr,
982 struct mlx4_cmd_mailbox *inbox,
983 struct mlx4_cmd_mailbox *outbox,
984 struct mlx4_cmd_info *cmd);
985 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
986 int *base, u8 flags);
987 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
988 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
989 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
990 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
991 int start_index, int npages, u64 *page_list);
992 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
993 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
994 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
995 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
997 void mlx4_start_catas_poll(struct mlx4_dev *dev);
998 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
999 void mlx4_catas_init(void);
1000 int mlx4_restart_one(struct pci_dev *pdev);
1001 int mlx4_register_device(struct mlx4_dev *dev);
1002 void mlx4_unregister_device(struct mlx4_dev *dev);
1003 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
1004 unsigned long param);
1006 struct mlx4_dev_cap;
1007 struct mlx4_init_hca_param;
1009 u64 mlx4_make_profile(struct mlx4_dev *dev,
1010 struct mlx4_profile *request,
1011 struct mlx4_dev_cap *dev_cap,
1012 struct mlx4_init_hca_param *init_hca);
1013 void mlx4_master_comm_channel(struct work_struct *work);
1014 void mlx4_gen_slave_eqe(struct work_struct *work);
1015 void mlx4_master_handle_slave_flr(struct work_struct *work);
1017 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
1018 struct mlx4_vhcr *vhcr,
1019 struct mlx4_cmd_mailbox *inbox,
1020 struct mlx4_cmd_mailbox *outbox,
1021 struct mlx4_cmd_info *cmd);
1022 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
1023 struct mlx4_vhcr *vhcr,
1024 struct mlx4_cmd_mailbox *inbox,
1025 struct mlx4_cmd_mailbox *outbox,
1026 struct mlx4_cmd_info *cmd);
1027 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
1028 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
1029 struct mlx4_cmd_mailbox *outbox,
1030 struct mlx4_cmd_info *cmd);
1031 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
1032 struct mlx4_vhcr *vhcr,
1033 struct mlx4_cmd_mailbox *inbox,
1034 struct mlx4_cmd_mailbox *outbox,
1035 struct mlx4_cmd_info *cmd);
1036 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
1037 struct mlx4_vhcr *vhcr,
1038 struct mlx4_cmd_mailbox *inbox,
1039 struct mlx4_cmd_mailbox *outbox,
1040 struct mlx4_cmd_info *cmd);
1041 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
1042 struct mlx4_vhcr *vhcr,
1043 struct mlx4_cmd_mailbox *inbox,
1044 struct mlx4_cmd_mailbox *outbox,
1045 struct mlx4_cmd_info *cmd);
1046 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1047 struct mlx4_vhcr *vhcr,
1048 struct mlx4_cmd_mailbox *inbox,
1049 struct mlx4_cmd_mailbox *outbox,
1050 struct mlx4_cmd_info *cmd);
1051 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1052 struct mlx4_vhcr *vhcr,
1053 struct mlx4_cmd_mailbox *inbox,
1054 struct mlx4_cmd_mailbox *outbox,
1055 struct mlx4_cmd_info *cmd);
1056 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1057 struct mlx4_vhcr *vhcr,
1058 struct mlx4_cmd_mailbox *inbox,
1059 struct mlx4_cmd_mailbox *outbox,
1060 struct mlx4_cmd_info *cmd);
1061 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1062 struct mlx4_vhcr *vhcr,
1063 struct mlx4_cmd_mailbox *inbox,
1064 struct mlx4_cmd_mailbox *outbox,
1065 struct mlx4_cmd_info *cmd);
1066 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1067 struct mlx4_vhcr *vhcr,
1068 struct mlx4_cmd_mailbox *inbox,
1069 struct mlx4_cmd_mailbox *outbox,
1070 struct mlx4_cmd_info *cmd);
1071 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1072 struct mlx4_vhcr *vhcr,
1073 struct mlx4_cmd_mailbox *inbox,
1074 struct mlx4_cmd_mailbox *outbox,
1075 struct mlx4_cmd_info *cmd);
1076 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1077 struct mlx4_vhcr *vhcr,
1078 struct mlx4_cmd_mailbox *inbox,
1079 struct mlx4_cmd_mailbox *outbox,
1080 struct mlx4_cmd_info *cmd);
1081 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1082 struct mlx4_vhcr *vhcr,
1083 struct mlx4_cmd_mailbox *inbox,
1084 struct mlx4_cmd_mailbox *outbox,
1085 struct mlx4_cmd_info *cmd);
1086 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
1087 struct mlx4_vhcr *vhcr,
1088 struct mlx4_cmd_mailbox *inbox,
1089 struct mlx4_cmd_mailbox *outbox,
1090 struct mlx4_cmd_info *cmd);
1091 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1092 struct mlx4_vhcr *vhcr,
1093 struct mlx4_cmd_mailbox *inbox,
1094 struct mlx4_cmd_mailbox *outbox,
1095 struct mlx4_cmd_info *cmd);
1096 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1097 struct mlx4_vhcr *vhcr,
1098 struct mlx4_cmd_mailbox *inbox,
1099 struct mlx4_cmd_mailbox *outbox,
1100 struct mlx4_cmd_info *cmd);
1101 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
1102 struct mlx4_vhcr *vhcr,
1103 struct mlx4_cmd_mailbox *inbox,
1104 struct mlx4_cmd_mailbox *outbox,
1105 struct mlx4_cmd_info *cmd);
1106 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1107 struct mlx4_vhcr *vhcr,
1108 struct mlx4_cmd_mailbox *inbox,
1109 struct mlx4_cmd_mailbox *outbox,
1110 struct mlx4_cmd_info *cmd);
1111 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1112 struct mlx4_vhcr *vhcr,
1113 struct mlx4_cmd_mailbox *inbox,
1114 struct mlx4_cmd_mailbox *outbox,
1115 struct mlx4_cmd_info *cmd);
1116 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1117 struct mlx4_vhcr *vhcr,
1118 struct mlx4_cmd_mailbox *inbox,
1119 struct mlx4_cmd_mailbox *outbox,
1120 struct mlx4_cmd_info *cmd);
1121 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave,
1122 struct mlx4_vhcr *vhcr,
1123 struct mlx4_cmd_mailbox *inbox,
1124 struct mlx4_cmd_mailbox *outbox,
1125 struct mlx4_cmd_info *cmd);
1126 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1127 struct mlx4_vhcr *vhcr,
1128 struct mlx4_cmd_mailbox *inbox,
1129 struct mlx4_cmd_mailbox *outbox,
1130 struct mlx4_cmd_info *cmd);
1131 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1132 struct mlx4_vhcr *vhcr,
1133 struct mlx4_cmd_mailbox *inbox,
1134 struct mlx4_cmd_mailbox *outbox,
1135 struct mlx4_cmd_info *cmd);
1136 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1137 struct mlx4_vhcr *vhcr,
1138 struct mlx4_cmd_mailbox *inbox,
1139 struct mlx4_cmd_mailbox *outbox,
1140 struct mlx4_cmd_info *cmd);
1141 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1142 struct mlx4_vhcr *vhcr,
1143 struct mlx4_cmd_mailbox *inbox,
1144 struct mlx4_cmd_mailbox *outbox,
1145 struct mlx4_cmd_info *cmd);
1146 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave,
1147 struct mlx4_vhcr *vhcr,
1148 struct mlx4_cmd_mailbox *inbox,
1149 struct mlx4_cmd_mailbox *outbox,
1150 struct mlx4_cmd_info *cmd);
1152 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
1155 MLX4_CMD_CLEANUP_STRUCT = 1UL << 0,
1156 MLX4_CMD_CLEANUP_POOL = 1UL << 1,
1157 MLX4_CMD_CLEANUP_HCR = 1UL << 2,
1158 MLX4_CMD_CLEANUP_VHCR = 1UL << 3,
1159 MLX4_CMD_CLEANUP_ALL = (MLX4_CMD_CLEANUP_VHCR << 1) - 1
1162 int mlx4_cmd_init(struct mlx4_dev *dev);
1163 void mlx4_cmd_cleanup(struct mlx4_dev *dev, int cleanup_mask);
1164 int mlx4_multi_func_init(struct mlx4_dev *dev);
1165 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
1166 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1167 int mlx4_cmd_use_events(struct mlx4_dev *dev);
1168 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1170 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1171 unsigned long timeout);
1173 void mlx4_cq_tasklet_cb(unsigned long data);
1174 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1175 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1177 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1179 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1181 void mlx4_handle_catas_err(struct mlx4_dev *dev);
1183 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1184 enum mlx4_port_type *type);
1185 void mlx4_do_sense_ports(struct mlx4_dev *dev,
1186 enum mlx4_port_type *stype,
1187 enum mlx4_port_type *defaults);
1188 void mlx4_start_sense(struct mlx4_dev *dev);
1189 void mlx4_stop_sense(struct mlx4_dev *dev);
1190 void mlx4_sense_init(struct mlx4_dev *dev);
1191 int mlx4_check_port_params(struct mlx4_dev *dev,
1192 enum mlx4_port_type *port_type);
1193 int mlx4_change_port_types(struct mlx4_dev *dev,
1194 enum mlx4_port_type *port_types);
1196 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1197 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1198 void mlx4_init_roce_gid_table(struct mlx4_dev *dev,
1199 struct mlx4_roce_gid_table *table);
1200 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1201 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1203 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz);
1204 /* resource tracker functions*/
1205 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1206 enum mlx4_resource resource_type,
1207 u64 resource_id, int *slave);
1208 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1209 void mlx4_reset_roce_gids(struct mlx4_dev *dev, int slave);
1210 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1212 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1213 enum mlx4_res_tracker_free_type type);
1215 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1216 struct mlx4_vhcr *vhcr,
1217 struct mlx4_cmd_mailbox *inbox,
1218 struct mlx4_cmd_mailbox *outbox,
1219 struct mlx4_cmd_info *cmd);
1220 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1221 struct mlx4_vhcr *vhcr,
1222 struct mlx4_cmd_mailbox *inbox,
1223 struct mlx4_cmd_mailbox *outbox,
1224 struct mlx4_cmd_info *cmd);
1225 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1226 struct mlx4_vhcr *vhcr,
1227 struct mlx4_cmd_mailbox *inbox,
1228 struct mlx4_cmd_mailbox *outbox,
1229 struct mlx4_cmd_info *cmd);
1230 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1231 struct mlx4_vhcr *vhcr,
1232 struct mlx4_cmd_mailbox *inbox,
1233 struct mlx4_cmd_mailbox *outbox,
1234 struct mlx4_cmd_info *cmd);
1235 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1236 struct mlx4_vhcr *vhcr,
1237 struct mlx4_cmd_mailbox *inbox,
1238 struct mlx4_cmd_mailbox *outbox,
1239 struct mlx4_cmd_info *cmd);
1240 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1241 struct mlx4_vhcr *vhcr,
1242 struct mlx4_cmd_mailbox *inbox,
1243 struct mlx4_cmd_mailbox *outbox,
1244 struct mlx4_cmd_info *cmd);
1245 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1247 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1248 int *gid_tbl_len, int *pkey_tbl_len);
1250 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1251 struct mlx4_vhcr *vhcr,
1252 struct mlx4_cmd_mailbox *inbox,
1253 struct mlx4_cmd_mailbox *outbox,
1254 struct mlx4_cmd_info *cmd);
1256 int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave,
1257 struct mlx4_vhcr *vhcr,
1258 struct mlx4_cmd_mailbox *inbox,
1259 struct mlx4_cmd_mailbox *outbox,
1260 struct mlx4_cmd_info *cmd);
1262 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1263 struct mlx4_vhcr *vhcr,
1264 struct mlx4_cmd_mailbox *inbox,
1265 struct mlx4_cmd_mailbox *outbox,
1266 struct mlx4_cmd_info *cmd);
1267 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1268 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1269 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1270 int block_mcast_loopback, enum mlx4_protocol prot,
1271 enum mlx4_steer_type steer);
1272 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1273 u8 gid[16], u8 port,
1274 int block_mcast_loopback,
1275 enum mlx4_protocol prot, u64 *reg_id);
1276 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1277 struct mlx4_vhcr *vhcr,
1278 struct mlx4_cmd_mailbox *inbox,
1279 struct mlx4_cmd_mailbox *outbox,
1280 struct mlx4_cmd_info *cmd);
1281 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1282 struct mlx4_vhcr *vhcr,
1283 struct mlx4_cmd_mailbox *inbox,
1284 struct mlx4_cmd_mailbox *outbox,
1285 struct mlx4_cmd_info *cmd);
1286 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1287 int port, void *buf);
1288 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1289 struct mlx4_cmd_mailbox *outbox);
1290 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1291 struct mlx4_vhcr *vhcr,
1292 struct mlx4_cmd_mailbox *inbox,
1293 struct mlx4_cmd_mailbox *outbox,
1294 struct mlx4_cmd_info *cmd);
1295 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1296 struct mlx4_vhcr *vhcr,
1297 struct mlx4_cmd_mailbox *inbox,
1298 struct mlx4_cmd_mailbox *outbox,
1299 struct mlx4_cmd_info *cmd);
1300 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1301 struct mlx4_vhcr *vhcr,
1302 struct mlx4_cmd_mailbox *inbox,
1303 struct mlx4_cmd_mailbox *outbox,
1304 struct mlx4_cmd_info *cmd);
1305 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1306 struct mlx4_vhcr *vhcr,
1307 struct mlx4_cmd_mailbox *inbox,
1308 struct mlx4_cmd_mailbox *outbox,
1309 struct mlx4_cmd_info *cmd);
1310 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1311 struct mlx4_vhcr *vhcr,
1312 struct mlx4_cmd_mailbox *inbox,
1313 struct mlx4_cmd_mailbox *outbox,
1314 struct mlx4_cmd_info *cmd);
1315 int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave,
1316 struct mlx4_vhcr *vhcr,
1317 struct mlx4_cmd_mailbox *inbox,
1318 struct mlx4_cmd_mailbox *outbox,
1319 struct mlx4_cmd_info *cmd);
1321 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1322 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1324 static inline void set_param_l(u64 *arg, u32 val)
1326 *arg = (*arg & 0xffffffff00000000ULL) | (u64) val;
1329 static inline void set_param_h(u64 *arg, u32 val)
1331 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1334 static inline u32 get_param_l(u64 *arg)
1336 return (u32) (*arg & 0xffffffff);
1339 static inline u32 get_param_h(u64 *arg)
1341 return (u32)(*arg >> 32);
1344 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1346 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1349 #define NOT_MASKED_PD_BITS 17
1351 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work);
1353 void mlx4_init_quotas(struct mlx4_dev *dev);
1355 int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave, int port);
1356 /* Returns the VF index of slave */
1357 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave);
1358 int mlx4_config_mad_demux(struct mlx4_dev *dev);
1360 enum mlx4_zone_flags {
1361 MLX4_ZONE_ALLOW_ALLOC_FROM_LOWER_PRIO = 1UL << 0,
1362 MLX4_ZONE_ALLOW_ALLOC_FROM_EQ_PRIO = 1UL << 1,
1363 MLX4_ZONE_FALLBACK_TO_HIGHER_PRIO = 1UL << 2,
1364 MLX4_ZONE_USE_RR = 1UL << 3,
1367 enum mlx4_zone_alloc_flags {
1368 /* No two objects could overlap between zones. UID
1369 * could be left unused. If this flag is given and
1370 * two overlapped zones are used, an object will be free'd
1371 * from the smallest possible matching zone.
1373 MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP = 1UL << 0,
1376 struct mlx4_zone_allocator;
1378 /* Create a new zone allocator */
1379 struct mlx4_zone_allocator *mlx4_zone_allocator_create(enum mlx4_zone_alloc_flags flags);
1381 /* Attach a mlx4_bitmap <bitmap> of priority <priority> to the zone allocator
1382 * <zone_alloc>. Allocating an object from this zone adds an offset <offset>.
1383 * Similarly, when searching for an object to free, this offset it taken into
1384 * account. The use_rr mlx4_ib parameter for allocating objects from this <bitmap>
1385 * is given through the MLX4_ZONE_USE_RR flag in <flags>.
1386 * When an allocation fails, <zone_alloc> tries to allocate from other zones
1387 * according to the policy set by <flags>. <puid> is the unique identifier
1388 * received to this zone.
1390 int mlx4_zone_add_one(struct mlx4_zone_allocator *zone_alloc,
1391 struct mlx4_bitmap *bitmap,
1397 /* Remove bitmap indicated by <uid> from <zone_alloc> */
1398 int mlx4_zone_remove_one(struct mlx4_zone_allocator *zone_alloc, u32 uid);
1400 /* Delete the zone allocator <zone_alloc. This function doesn't destroy
1401 * the attached bitmaps.
1403 void mlx4_zone_allocator_destroy(struct mlx4_zone_allocator *zone_alloc);
1405 /* Allocate <count> objects with align <align> and skip_mask <skip_mask>
1406 * from the mlx4_bitmap whose uid is <uid>. The bitmap which we actually
1407 * allocated from is returned in <puid>. If the allocation fails, a negative
1408 * number is returned. Otherwise, the offset of the first object is returned.
1410 u32 mlx4_zone_alloc_entries(struct mlx4_zone_allocator *zones, u32 uid, int count,
1411 int align, u32 skip_mask, u32 *puid);
1413 /* Free <count> objects, start from <obj> of the uid <uid> from zone_allocator
1416 u32 mlx4_zone_free_entries(struct mlx4_zone_allocator *zones,
1417 u32 uid, u32 obj, u32 count);
1419 /* If <zones> was allocated with MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP, instead of
1420 * specifying the uid when freeing an object, zone allocator could figure it by
1421 * itself. Other parameters are similar to mlx4_zone_free.
1423 u32 mlx4_zone_free_entries_unique(struct mlx4_zone_allocator *zones, u32 obj, u32 count);
1425 /* Returns a pointer to mlx4_bitmap that was attached to <zones> with <uid> */
1426 struct mlx4_bitmap *mlx4_zone_get_bitmap(struct mlx4_zone_allocator *zones, u32 uid);