2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/mutex.h>
41 #include <linux/radix-tree.h>
42 #include <linux/timer.h>
43 #include <linux/semaphore.h>
44 #include <linux/workqueue.h>
46 #include <linux/mlx4/device.h>
47 #include <linux/mlx4/driver.h>
48 #include <linux/mlx4/doorbell.h>
49 #include <linux/mlx4/cmd.h>
51 #define DRV_NAME "mlx4_core"
52 #define DRV_VERSION "1.0"
53 #define DRV_RELDATE "July 14, 2011"
56 MLX4_HCR_BASE = 0x80680,
57 MLX4_HCR_SIZE = 0x0001c,
58 MLX4_CLR_INT_SIZE = 0x00008,
59 MLX4_SLAVE_COMM_BASE = 0x0,
60 MLX4_COMM_PAGESIZE = 0x1000
64 MLX4_MAX_MGM_ENTRY_SIZE = 0x1000,
65 MLX4_MAX_QP_PER_MGM = 4 * (MLX4_MAX_MGM_ENTRY_SIZE / 16 - 2),
66 MLX4_MTT_ENTRY_PER_SEG = 8,
70 MLX4_NUM_PDS = 1 << 15
74 MLX4_CMPT_TYPE_QP = 0,
75 MLX4_CMPT_TYPE_SRQ = 1,
76 MLX4_CMPT_TYPE_CQ = 2,
77 MLX4_CMPT_TYPE_EQ = 3,
83 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
92 #define MLX4_COMM_TIME 10000
98 MLX4_COMM_CMD_VHCR_EN,
99 MLX4_COMM_CMD_VHCR_POST,
100 MLX4_COMM_CMD_FLR = 254
103 /*The flag indicates that the slave should delay the RESET cmd*/
104 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
105 /*indicates how many retries will be done if we are in the middle of FLR*/
106 #define NUM_OF_RESET_RETRIES 10
107 #define SLEEP_TIME_IN_RESET (2 * 1000)
119 MLX4_NUM_OF_RESOURCE_TYPE
122 enum mlx4_alloc_mode {
124 RES_OP_RESERVE_AND_MAP,
130 *Virtual HCR structures.
131 * mlx4_vhcr is the sw representation, in machine endianess
133 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
134 * to FW to go through communication channel.
135 * It is big endian, and has the same structure as the physical HCR
136 * used by command interface
149 struct mlx4_vhcr_cmd {
160 struct mlx4_cmd_info {
165 bool encode_slave_id;
166 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
167 struct mlx4_cmd_mailbox *inbox);
168 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
169 struct mlx4_cmd_mailbox *inbox,
170 struct mlx4_cmd_mailbox *outbox,
171 struct mlx4_cmd_info *cmd);
174 #ifdef CONFIG_MLX4_DEBUG
175 extern int mlx4_debug_level;
176 #else /* CONFIG_MLX4_DEBUG */
177 #define mlx4_debug_level (0)
178 #endif /* CONFIG_MLX4_DEBUG */
180 #define mlx4_dbg(mdev, format, arg...) \
182 if (mlx4_debug_level) \
183 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
186 #define mlx4_err(mdev, format, arg...) \
187 dev_err(&mdev->pdev->dev, format, ##arg)
188 #define mlx4_info(mdev, format, arg...) \
189 dev_info(&mdev->pdev->dev, format, ##arg)
190 #define mlx4_warn(mdev, format, arg...) \
191 dev_warn(&mdev->pdev->dev, format, ##arg)
193 extern int mlx4_log_num_mgm_entry_size;
195 #define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
196 #define ALL_SLAVES 0xff
206 unsigned long *table;
210 unsigned long **bits;
211 unsigned int *num_free;
218 struct mlx4_icm_table {
226 struct mlx4_icm **icm;
230 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
232 struct mlx4_mpt_entry {
246 __be32 first_byte_offset;
250 * Must be packed because start is 64 bits but only aligned to 32 bits.
252 struct mlx4_eq_context {
266 __be32 mtt_base_addr_l;
268 __be32 consumer_index;
269 __be32 producer_index;
273 struct mlx4_cq_context {
277 __be32 logsize_usrpage;
285 __be32 mtt_base_addr_l;
286 __be32 last_notified_index;
287 __be32 solicit_producer_index;
288 __be32 consumer_index;
289 __be32 producer_index;
294 struct mlx4_srq_context {
295 __be32 state_logsize_srqn;
299 __be32 pg_offset_cqn;
304 __be32 mtt_base_addr_l;
306 __be16 limit_watermark;
347 } __packed port_change;
349 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
351 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
352 } __packed comm_channel_arm;
357 } __packed mac_update;
363 } __packed flr_event;
371 struct mlx4_dev *dev;
372 void __iomem *doorbell;
378 struct mlx4_buf_list *page_list;
382 struct mlx4_slave_eqe {
388 struct mlx4_slave_event_eq_info {
394 struct mlx4_profile {
408 struct mlx4_icm *fw_icm;
409 struct mlx4_icm *aux_icm;
423 MLX4_MCAST_CONFIG = 0,
424 MLX4_MCAST_DISABLE = 1,
425 MLX4_MCAST_ENABLE = 2,
428 #define VLAN_FLTR_SIZE 128
430 struct mlx4_vlan_fltr {
431 __be32 entry[VLAN_FLTR_SIZE];
434 struct mlx4_mcast_entry {
435 struct list_head list;
439 struct mlx4_promisc_qp {
440 struct list_head list;
444 struct mlx4_steer_index {
445 struct list_head list;
447 struct list_head duplicates;
450 struct mlx4_slave_state {
457 u16 mtu[MLX4_MAX_PORTS + 1];
458 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
459 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
460 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
461 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
462 struct mlx4_slave_event_eq_info event_eq;
466 /*initialized via the kzalloc*/
467 u8 is_slave_going_down;
473 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
476 struct mlx4_resource_tracker {
478 /* tree for each resources */
479 struct radix_tree_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
480 /* num_of_slave's lists, one per slave */
481 struct slave_list *slave_list;
484 #define SLAVE_EVENT_EQ_SIZE 128
485 struct mlx4_slave_event_eq {
489 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
492 struct mlx4_master_qp0_state {
493 int proxy_qp0_active;
498 struct mlx4_mfunc_master_ctx {
499 struct mlx4_slave_state *slave_state;
500 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
501 int init_port_ref[MLX4_MAX_PORTS + 1];
502 u16 max_mtu[MLX4_MAX_PORTS + 1];
503 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
504 struct mlx4_resource_tracker res_tracker;
505 struct workqueue_struct *comm_wq;
506 struct work_struct comm_work;
507 struct work_struct slave_event_work;
508 struct work_struct slave_flr_event_work;
509 spinlock_t slave_state_lock;
510 __be32 comm_arm_bit_vector[4];
511 struct mlx4_eqe cmd_eqe;
512 struct mlx4_slave_event_eq slave_eq;
513 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
517 struct mlx4_comm __iomem *comm;
518 struct mlx4_vhcr_cmd *vhcr;
521 struct mlx4_mfunc_master_ctx master;
525 struct pci_pool *pool;
527 struct mutex hcr_mutex;
528 struct semaphore poll_sem;
529 struct semaphore event_sem;
530 struct semaphore slave_sem;
532 spinlock_t context_lock;
534 struct mlx4_cmd_context *context;
541 struct mlx4_uar_table {
542 struct mlx4_bitmap bitmap;
545 struct mlx4_mr_table {
546 struct mlx4_bitmap mpt_bitmap;
547 struct mlx4_buddy mtt_buddy;
550 struct mlx4_icm_table mtt_table;
551 struct mlx4_icm_table dmpt_table;
554 struct mlx4_cq_table {
555 struct mlx4_bitmap bitmap;
557 struct radix_tree_root tree;
558 struct mlx4_icm_table table;
559 struct mlx4_icm_table cmpt_table;
562 struct mlx4_eq_table {
563 struct mlx4_bitmap bitmap;
565 void __iomem *clr_int;
566 void __iomem **uar_map;
569 struct mlx4_icm_table table;
570 struct mlx4_icm_table cmpt_table;
575 struct mlx4_srq_table {
576 struct mlx4_bitmap bitmap;
578 struct radix_tree_root tree;
579 struct mlx4_icm_table table;
580 struct mlx4_icm_table cmpt_table;
583 struct mlx4_qp_table {
584 struct mlx4_bitmap bitmap;
588 struct mlx4_icm_table qp_table;
589 struct mlx4_icm_table auxc_table;
590 struct mlx4_icm_table altc_table;
591 struct mlx4_icm_table rdmarc_table;
592 struct mlx4_icm_table cmpt_table;
595 struct mlx4_mcg_table {
597 struct mlx4_bitmap bitmap;
598 struct mlx4_icm_table table;
601 struct mlx4_catas_err {
603 struct timer_list timer;
604 struct list_head list;
607 #define MLX4_MAX_MAC_NUM 128
608 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
610 struct mlx4_mac_table {
611 __be64 entries[MLX4_MAX_MAC_NUM];
612 int refs[MLX4_MAX_MAC_NUM];
618 #define MLX4_MAX_VLAN_NUM 128
619 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
621 struct mlx4_vlan_table {
622 __be32 entries[MLX4_MAX_VLAN_NUM];
623 int refs[MLX4_MAX_VLAN_NUM];
629 #define SET_PORT_GEN_ALL_VALID 0x7
630 #define SET_PORT_PROMISC_SHIFT 31
631 #define SET_PORT_MC_PROMISC_SHIFT 30
634 MCAST_DIRECT_ONLY = 0,
640 struct mlx4_set_port_general_context {
653 struct mlx4_set_port_rqp_calc_context {
671 struct mlx4_mac_entry {
675 struct mlx4_port_info {
676 struct mlx4_dev *dev;
679 struct device_attribute port_attr;
680 enum mlx4_port_type tmp_type;
681 struct mlx4_mac_table mac_table;
682 struct radix_tree_root mac_tree;
683 struct mlx4_vlan_table vlan_table;
688 struct mlx4_dev *dev;
689 u8 do_sense_port[MLX4_MAX_PORTS + 1];
690 u8 sense_allowed[MLX4_MAX_PORTS + 1];
691 struct delayed_work sense_poll;
694 struct mlx4_msix_ctl {
696 spinlock_t pool_lock;
700 struct list_head promisc_qps[MLX4_NUM_STEERS];
701 struct list_head steer_entries[MLX4_NUM_STEERS];
702 struct list_head high_prios;
708 struct list_head dev_list;
709 struct list_head ctx_list;
712 struct list_head pgdir_list;
713 struct mutex pgdir_mutex;
717 struct mlx4_mfunc mfunc;
719 struct mlx4_bitmap pd_bitmap;
720 struct mlx4_bitmap xrcd_bitmap;
721 struct mlx4_uar_table uar_table;
722 struct mlx4_mr_table mr_table;
723 struct mlx4_cq_table cq_table;
724 struct mlx4_eq_table eq_table;
725 struct mlx4_srq_table srq_table;
726 struct mlx4_qp_table qp_table;
727 struct mlx4_mcg_table mcg_table;
728 struct mlx4_bitmap counters_bitmap;
730 struct mlx4_catas_err catas_err;
732 void __iomem *clr_base;
734 struct mlx4_uar driver_uar;
736 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
737 struct mlx4_sense sense;
738 struct mutex port_mutex;
739 struct mlx4_msix_ctl msix_ctl;
740 struct mlx4_steer *steer;
741 struct list_head bf_list;
742 struct mutex bf_mutex;
743 struct io_mapping *bf_mapping;
747 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
749 return container_of(dev, struct mlx4_priv, dev);
752 #define MLX4_SENSE_RANGE (HZ * 3)
754 extern struct workqueue_struct *mlx4_wq;
756 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
757 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
758 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
759 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
760 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
761 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
762 u32 reserved_bot, u32 resetrved_top);
763 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
765 int mlx4_reset(struct mlx4_dev *dev);
767 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
768 void mlx4_free_eq_table(struct mlx4_dev *dev);
770 int mlx4_init_pd_table(struct mlx4_dev *dev);
771 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
772 int mlx4_init_uar_table(struct mlx4_dev *dev);
773 int mlx4_init_mr_table(struct mlx4_dev *dev);
774 int mlx4_init_eq_table(struct mlx4_dev *dev);
775 int mlx4_init_cq_table(struct mlx4_dev *dev);
776 int mlx4_init_qp_table(struct mlx4_dev *dev);
777 int mlx4_init_srq_table(struct mlx4_dev *dev);
778 int mlx4_init_mcg_table(struct mlx4_dev *dev);
780 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
781 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
782 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
783 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
784 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
785 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
786 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
787 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
788 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
789 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
790 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
791 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
792 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
793 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
794 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
795 int __mlx4_mr_reserve(struct mlx4_dev *dev);
796 void __mlx4_mr_release(struct mlx4_dev *dev, u32 index);
797 int __mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index);
798 void __mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index);
799 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
800 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
802 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
803 struct mlx4_vhcr *vhcr,
804 struct mlx4_cmd_mailbox *inbox,
805 struct mlx4_cmd_mailbox *outbox,
806 struct mlx4_cmd_info *cmd);
807 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
808 struct mlx4_vhcr *vhcr,
809 struct mlx4_cmd_mailbox *inbox,
810 struct mlx4_cmd_mailbox *outbox,
811 struct mlx4_cmd_info *cmd);
812 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
813 struct mlx4_vhcr *vhcr,
814 struct mlx4_cmd_mailbox *inbox,
815 struct mlx4_cmd_mailbox *outbox,
816 struct mlx4_cmd_info *cmd);
817 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
818 struct mlx4_vhcr *vhcr,
819 struct mlx4_cmd_mailbox *inbox,
820 struct mlx4_cmd_mailbox *outbox,
821 struct mlx4_cmd_info *cmd);
822 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
823 struct mlx4_vhcr *vhcr,
824 struct mlx4_cmd_mailbox *inbox,
825 struct mlx4_cmd_mailbox *outbox,
826 struct mlx4_cmd_info *cmd);
827 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
828 struct mlx4_vhcr *vhcr,
829 struct mlx4_cmd_mailbox *inbox,
830 struct mlx4_cmd_mailbox *outbox,
831 struct mlx4_cmd_info *cmd);
832 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
833 struct mlx4_vhcr *vhcr,
834 struct mlx4_cmd_mailbox *inbox,
835 struct mlx4_cmd_mailbox *outbox,
836 struct mlx4_cmd_info *cmd);
837 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
839 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
840 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
841 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
842 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
843 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
844 int start_index, int npages, u64 *page_list);
846 void mlx4_start_catas_poll(struct mlx4_dev *dev);
847 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
848 void mlx4_catas_init(void);
849 int mlx4_restart_one(struct pci_dev *pdev);
850 int mlx4_register_device(struct mlx4_dev *dev);
851 void mlx4_unregister_device(struct mlx4_dev *dev);
852 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, int port);
855 struct mlx4_init_hca_param;
857 u64 mlx4_make_profile(struct mlx4_dev *dev,
858 struct mlx4_profile *request,
859 struct mlx4_dev_cap *dev_cap,
860 struct mlx4_init_hca_param *init_hca);
861 void mlx4_master_comm_channel(struct work_struct *work);
862 void mlx4_gen_slave_eqe(struct work_struct *work);
863 void mlx4_master_handle_slave_flr(struct work_struct *work);
865 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
866 struct mlx4_vhcr *vhcr,
867 struct mlx4_cmd_mailbox *inbox,
868 struct mlx4_cmd_mailbox *outbox,
869 struct mlx4_cmd_info *cmd);
870 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
871 struct mlx4_vhcr *vhcr,
872 struct mlx4_cmd_mailbox *inbox,
873 struct mlx4_cmd_mailbox *outbox,
874 struct mlx4_cmd_info *cmd);
875 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
876 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
877 struct mlx4_cmd_mailbox *outbox,
878 struct mlx4_cmd_info *cmd);
879 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
880 struct mlx4_vhcr *vhcr,
881 struct mlx4_cmd_mailbox *inbox,
882 struct mlx4_cmd_mailbox *outbox,
883 struct mlx4_cmd_info *cmd);
884 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
885 struct mlx4_vhcr *vhcr,
886 struct mlx4_cmd_mailbox *inbox,
887 struct mlx4_cmd_mailbox *outbox,
888 struct mlx4_cmd_info *cmd);
889 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
890 struct mlx4_vhcr *vhcr,
891 struct mlx4_cmd_mailbox *inbox,
892 struct mlx4_cmd_mailbox *outbox,
893 struct mlx4_cmd_info *cmd);
894 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
895 struct mlx4_vhcr *vhcr,
896 struct mlx4_cmd_mailbox *inbox,
897 struct mlx4_cmd_mailbox *outbox,
898 struct mlx4_cmd_info *cmd);
899 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
900 struct mlx4_vhcr *vhcr,
901 struct mlx4_cmd_mailbox *inbox,
902 struct mlx4_cmd_mailbox *outbox,
903 struct mlx4_cmd_info *cmd);
904 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
905 struct mlx4_vhcr *vhcr,
906 struct mlx4_cmd_mailbox *inbox,
907 struct mlx4_cmd_mailbox *outbox,
908 struct mlx4_cmd_info *cmd);
909 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
910 struct mlx4_vhcr *vhcr,
911 struct mlx4_cmd_mailbox *inbox,
912 struct mlx4_cmd_mailbox *outbox,
913 struct mlx4_cmd_info *cmd);
914 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
915 struct mlx4_vhcr *vhcr,
916 struct mlx4_cmd_mailbox *inbox,
917 struct mlx4_cmd_mailbox *outbox,
918 struct mlx4_cmd_info *cmd);
919 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
920 struct mlx4_vhcr *vhcr,
921 struct mlx4_cmd_mailbox *inbox,
922 struct mlx4_cmd_mailbox *outbox,
923 struct mlx4_cmd_info *cmd);
924 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
925 struct mlx4_vhcr *vhcr,
926 struct mlx4_cmd_mailbox *inbox,
927 struct mlx4_cmd_mailbox *outbox,
928 struct mlx4_cmd_info *cmd);
929 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
930 struct mlx4_vhcr *vhcr,
931 struct mlx4_cmd_mailbox *inbox,
932 struct mlx4_cmd_mailbox *outbox,
933 struct mlx4_cmd_info *cmd);
934 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
935 struct mlx4_vhcr *vhcr,
936 struct mlx4_cmd_mailbox *inbox,
937 struct mlx4_cmd_mailbox *outbox,
938 struct mlx4_cmd_info *cmd);
939 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
940 struct mlx4_vhcr *vhcr,
941 struct mlx4_cmd_mailbox *inbox,
942 struct mlx4_cmd_mailbox *outbox,
943 struct mlx4_cmd_info *cmd);
944 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
945 struct mlx4_vhcr *vhcr,
946 struct mlx4_cmd_mailbox *inbox,
947 struct mlx4_cmd_mailbox *outbox,
948 struct mlx4_cmd_info *cmd);
949 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
950 struct mlx4_vhcr *vhcr,
951 struct mlx4_cmd_mailbox *inbox,
952 struct mlx4_cmd_mailbox *outbox,
953 struct mlx4_cmd_info *cmd);
955 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
957 int mlx4_cmd_init(struct mlx4_dev *dev);
958 void mlx4_cmd_cleanup(struct mlx4_dev *dev);
959 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
960 int mlx4_cmd_use_events(struct mlx4_dev *dev);
961 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
963 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
964 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
966 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
968 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
970 void mlx4_handle_catas_err(struct mlx4_dev *dev);
972 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
973 enum mlx4_port_type *type);
974 void mlx4_do_sense_ports(struct mlx4_dev *dev,
975 enum mlx4_port_type *stype,
976 enum mlx4_port_type *defaults);
977 void mlx4_start_sense(struct mlx4_dev *dev);
978 void mlx4_stop_sense(struct mlx4_dev *dev);
979 void mlx4_sense_init(struct mlx4_dev *dev);
980 int mlx4_check_port_params(struct mlx4_dev *dev,
981 enum mlx4_port_type *port_type);
982 int mlx4_change_port_types(struct mlx4_dev *dev,
983 enum mlx4_port_type *port_types);
985 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
986 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
988 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port);
989 /* resource tracker functions*/
990 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
991 enum mlx4_resource resource_type,
992 int resource_id, int *slave);
993 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
994 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
996 void mlx4_free_resource_tracker(struct mlx4_dev *dev);
998 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
999 struct mlx4_vhcr *vhcr,
1000 struct mlx4_cmd_mailbox *inbox,
1001 struct mlx4_cmd_mailbox *outbox,
1002 struct mlx4_cmd_info *cmd);
1003 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1004 struct mlx4_vhcr *vhcr,
1005 struct mlx4_cmd_mailbox *inbox,
1006 struct mlx4_cmd_mailbox *outbox,
1007 struct mlx4_cmd_info *cmd);
1008 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1009 struct mlx4_vhcr *vhcr,
1010 struct mlx4_cmd_mailbox *inbox,
1011 struct mlx4_cmd_mailbox *outbox,
1012 struct mlx4_cmd_info *cmd);
1013 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1014 struct mlx4_vhcr *vhcr,
1015 struct mlx4_cmd_mailbox *inbox,
1016 struct mlx4_cmd_mailbox *outbox,
1017 struct mlx4_cmd_info *cmd);
1018 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1019 int mlx4_check_ext_port_caps(struct mlx4_dev *dev, u8 port);
1022 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1023 struct mlx4_vhcr *vhcr,
1024 struct mlx4_cmd_mailbox *inbox,
1025 struct mlx4_cmd_mailbox *outbox,
1026 struct mlx4_cmd_info *cmd);
1028 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1029 struct mlx4_vhcr *vhcr,
1030 struct mlx4_cmd_mailbox *inbox,
1031 struct mlx4_cmd_mailbox *outbox,
1032 struct mlx4_cmd_info *cmd);
1033 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1034 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1035 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1036 int block_mcast_loopback, enum mlx4_protocol prot,
1037 enum mlx4_steer_type steer);
1038 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1039 struct mlx4_vhcr *vhcr,
1040 struct mlx4_cmd_mailbox *inbox,
1041 struct mlx4_cmd_mailbox *outbox,
1042 struct mlx4_cmd_info *cmd);
1043 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1044 struct mlx4_vhcr *vhcr,
1045 struct mlx4_cmd_mailbox *inbox,
1046 struct mlx4_cmd_mailbox *outbox,
1047 struct mlx4_cmd_info *cmd);
1048 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1049 int port, void *buf);
1050 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1051 struct mlx4_cmd_mailbox *outbox);
1052 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1053 struct mlx4_vhcr *vhcr,
1054 struct mlx4_cmd_mailbox *inbox,
1055 struct mlx4_cmd_mailbox *outbox,
1056 struct mlx4_cmd_info *cmd);
1057 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1058 struct mlx4_vhcr *vhcr,
1059 struct mlx4_cmd_mailbox *inbox,
1060 struct mlx4_cmd_mailbox *outbox,
1061 struct mlx4_cmd_info *cmd);
1062 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1063 struct mlx4_vhcr *vhcr,
1064 struct mlx4_cmd_mailbox *inbox,
1065 struct mlx4_cmd_mailbox *outbox,
1066 struct mlx4_cmd_info *cmd);
1068 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1069 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1071 static inline void set_param_l(u64 *arg, u32 val)
1073 *((u32 *)arg) = val;
1076 static inline void set_param_h(u64 *arg, u32 val)
1078 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1081 static inline u32 get_param_l(u64 *arg)
1083 return (u32) (*arg & 0xffffffff);
1086 static inline u32 get_param_h(u64 *arg)
1088 return (u32)(*arg >> 32);
1091 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1093 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1096 #define NOT_MASKED_PD_BITS 17