2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/mutex.h>
41 #include <linux/radix-tree.h>
42 #include <linux/rbtree.h>
43 #include <linux/timer.h>
44 #include <linux/semaphore.h>
45 #include <linux/workqueue.h>
46 #include <linux/interrupt.h>
47 #include <linux/spinlock.h>
49 #include <linux/mlx4/device.h>
50 #include <linux/mlx4/driver.h>
51 #include <linux/mlx4/doorbell.h>
52 #include <linux/mlx4/cmd.h>
54 #define DRV_NAME "mlx4_core"
55 #define PFX DRV_NAME ": "
56 #define DRV_VERSION "2.2-1"
57 #define DRV_RELDATE "Feb, 2014"
59 #define MLX4_FS_UDP_UC_EN (1 << 1)
60 #define MLX4_FS_TCP_UC_EN (1 << 2)
61 #define MLX4_FS_NUM_OF_L2_ADDR 8
62 #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7
63 #define MLX4_FS_NUM_MCG (1 << 17)
65 #define INIT_HCA_TPT_MW_ENABLE (1 << 7)
67 struct mlx4_set_port_prio2tc_context {
71 struct mlx4_port_scheduler_tc_cfg_be {
74 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
78 struct mlx4_set_port_scheduler_context {
79 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
83 MLX4_HCR_BASE = 0x80680,
84 MLX4_HCR_SIZE = 0x0001c,
85 MLX4_CLR_INT_SIZE = 0x00008,
86 MLX4_SLAVE_COMM_BASE = 0x0,
87 MLX4_COMM_PAGESIZE = 0x1000,
88 MLX4_CLOCK_SIZE = 0x00008
92 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10,
93 MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7,
94 MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12,
95 MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2),
96 MLX4_MTT_ENTRY_PER_SEG = 8,
100 MLX4_NUM_PDS = 1 << 15
104 MLX4_CMPT_TYPE_QP = 0,
105 MLX4_CMPT_TYPE_SRQ = 1,
106 MLX4_CMPT_TYPE_CQ = 2,
107 MLX4_CMPT_TYPE_EQ = 3,
112 MLX4_CMPT_SHIFT = 24,
113 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
116 enum mlx4_mpt_state {
117 MLX4_MPT_DISABLED = 0,
122 #define MLX4_COMM_TIME 10000
128 MLX4_COMM_CMD_VHCR_EN,
129 MLX4_COMM_CMD_VHCR_POST,
130 MLX4_COMM_CMD_FLR = 254
134 MLX4_VF_SMI_DISABLED,
138 /*The flag indicates that the slave should delay the RESET cmd*/
139 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
140 /*indicates how many retries will be done if we are in the middle of FLR*/
141 #define NUM_OF_RESET_RETRIES 10
142 #define SLEEP_TIME_IN_RESET (2 * 1000)
155 MLX4_NUM_OF_RESOURCE_TYPE
158 enum mlx4_alloc_mode {
160 RES_OP_RESERVE_AND_MAP,
164 enum mlx4_res_tracker_free_type {
166 RES_TR_FREE_SLAVES_ONLY,
167 RES_TR_FREE_STRUCTS_ONLY,
171 *Virtual HCR structures.
172 * mlx4_vhcr is the sw representation, in machine endianess
174 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
175 * to FW to go through communication channel.
176 * It is big endian, and has the same structure as the physical HCR
177 * used by command interface
190 struct mlx4_vhcr_cmd {
201 struct mlx4_cmd_info {
206 bool encode_slave_id;
207 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
208 struct mlx4_cmd_mailbox *inbox);
209 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
210 struct mlx4_cmd_mailbox *inbox,
211 struct mlx4_cmd_mailbox *outbox,
212 struct mlx4_cmd_info *cmd);
215 #ifdef CONFIG_MLX4_DEBUG
216 extern int mlx4_debug_level;
217 #else /* CONFIG_MLX4_DEBUG */
218 #define mlx4_debug_level (0)
219 #endif /* CONFIG_MLX4_DEBUG */
221 #define mlx4_dbg(mdev, format, ...) \
223 if (mlx4_debug_level) \
224 dev_printk(KERN_DEBUG, &(mdev)->pdev->dev, format, \
228 #define mlx4_err(mdev, format, ...) \
229 dev_err(&(mdev)->pdev->dev, format, ##__VA_ARGS__)
230 #define mlx4_info(mdev, format, ...) \
231 dev_info(&(mdev)->pdev->dev, format, ##__VA_ARGS__)
232 #define mlx4_warn(mdev, format, ...) \
233 dev_warn(&(mdev)->pdev->dev, format, ##__VA_ARGS__)
235 extern int mlx4_log_num_mgm_entry_size;
236 extern int log_mtts_per_seg;
238 #define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
239 #define ALL_SLAVES 0xff
249 unsigned long *table;
253 unsigned long **bits;
254 unsigned int *num_free;
261 struct mlx4_icm_table {
269 struct mlx4_icm **icm;
272 #define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28)
273 #define MLX4_MPT_FLAG_FREE (0x3UL << 28)
274 #define MLX4_MPT_FLAG_MIO (1 << 17)
275 #define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15)
276 #define MLX4_MPT_FLAG_PHYSICAL (1 << 9)
277 #define MLX4_MPT_FLAG_REGION (1 << 8)
279 #define MLX4_MPT_PD_MASK (0x1FFFFUL)
280 #define MLX4_MPT_PD_VF_MASK (0xFE0000UL)
281 #define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27)
282 #define MLX4_MPT_PD_FLAG_RAE (1 << 28)
283 #define MLX4_MPT_PD_FLAG_EN_INV (3 << 24)
285 #define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7)
287 #define MLX4_MPT_STATUS_SW 0xF0
288 #define MLX4_MPT_STATUS_HW 0x00
290 #define MLX4_CQE_SIZE_MASK_STRIDE 0x3
291 #define MLX4_EQE_SIZE_MASK_STRIDE 0x30
294 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
296 struct mlx4_mpt_entry {
310 __be32 first_byte_offset;
314 * Must be packed because start is 64 bits but only aligned to 32 bits.
316 struct mlx4_eq_context {
330 __be32 mtt_base_addr_l;
332 __be32 consumer_index;
333 __be32 producer_index;
337 struct mlx4_cq_context {
341 __be32 logsize_usrpage;
349 __be32 mtt_base_addr_l;
350 __be32 last_notified_index;
351 __be32 solicit_producer_index;
352 __be32 consumer_index;
353 __be32 producer_index;
358 struct mlx4_srq_context {
359 __be32 state_logsize_srqn;
363 __be32 pg_offset_cqn;
368 __be32 mtt_base_addr_l;
370 __be16 limit_watermark;
378 struct mlx4_eq_tasklet {
379 struct list_head list;
380 struct list_head process_list;
381 struct tasklet_struct task;
382 /* lock on completion tasklet list */
387 struct mlx4_dev *dev;
388 void __iomem *doorbell;
394 struct mlx4_buf_list *page_list;
396 struct mlx4_eq_tasklet tasklet_ctx;
399 struct mlx4_slave_eqe {
405 struct mlx4_slave_event_eq_info {
410 struct mlx4_profile {
425 struct mlx4_icm *fw_icm;
426 struct mlx4_icm *aux_icm;
441 MLX4_MCAST_CONFIG = 0,
442 MLX4_MCAST_DISABLE = 1,
443 MLX4_MCAST_ENABLE = 2,
446 #define VLAN_FLTR_SIZE 128
448 struct mlx4_vlan_fltr {
449 __be32 entry[VLAN_FLTR_SIZE];
452 struct mlx4_mcast_entry {
453 struct list_head list;
457 struct mlx4_promisc_qp {
458 struct list_head list;
462 struct mlx4_steer_index {
463 struct list_head list;
465 struct list_head duplicates;
468 #define MLX4_EVENT_TYPES_NUM 64
470 struct mlx4_slave_state {
478 u16 mtu[MLX4_MAX_PORTS + 1];
479 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
480 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
481 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
482 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
483 /* event type to eq number lookup */
484 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
488 /*initialized via the kzalloc*/
489 u8 is_slave_going_down;
491 enum slave_port_state port_state[MLX4_MAX_PORTS + 1];
494 #define MLX4_VGT 4095
497 struct mlx4_vport_state {
506 struct mlx4_vf_admin_state {
507 struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1];
508 u8 enable_smi[MLX4_MAX_PORTS + 1];
511 struct mlx4_vport_oper_state {
512 struct mlx4_vport_state state;
517 struct mlx4_vf_oper_state {
518 struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1];
519 u8 smi_enabled[MLX4_MAX_PORTS + 1];
524 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
527 struct resource_allocator {
528 spinlock_t alloc_lock; /* protect quotas */
531 int res_port_rsvd[MLX4_MAX_PORTS];
535 int res_port_free[MLX4_MAX_PORTS];
542 struct mlx4_resource_tracker {
544 /* tree for each resources */
545 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
546 /* num_of_slave's lists, one per slave */
547 struct slave_list *slave_list;
548 struct resource_allocator res_alloc[MLX4_NUM_OF_RESOURCE_TYPE];
551 #define SLAVE_EVENT_EQ_SIZE 128
552 struct mlx4_slave_event_eq {
556 spinlock_t event_lock;
557 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
560 struct mlx4_master_qp0_state {
561 int proxy_qp0_active;
566 struct mlx4_mfunc_master_ctx {
567 struct mlx4_slave_state *slave_state;
568 struct mlx4_vf_admin_state *vf_admin;
569 struct mlx4_vf_oper_state *vf_oper;
570 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
571 int init_port_ref[MLX4_MAX_PORTS + 1];
572 u16 max_mtu[MLX4_MAX_PORTS + 1];
573 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
574 struct mlx4_resource_tracker res_tracker;
575 struct workqueue_struct *comm_wq;
576 struct work_struct comm_work;
577 struct work_struct slave_event_work;
578 struct work_struct slave_flr_event_work;
579 spinlock_t slave_state_lock;
580 __be32 comm_arm_bit_vector[4];
581 struct mlx4_eqe cmd_eqe;
582 struct mlx4_slave_event_eq slave_eq;
583 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
587 struct mlx4_comm __iomem *comm;
588 struct mlx4_vhcr_cmd *vhcr;
591 struct mlx4_mfunc_master_ctx master;
594 #define MGM_QPN_MASK 0x00FFFFFF
595 #define MGM_BLCK_LB_BIT 30
598 __be32 next_gid_index;
599 __be32 members_count;
602 __be32 qp[MLX4_MAX_QP_PER_MGM];
606 struct pci_pool *pool;
608 struct mutex hcr_mutex;
609 struct mutex slave_cmd_mutex;
610 struct semaphore poll_sem;
611 struct semaphore event_sem;
613 spinlock_t context_lock;
615 struct mlx4_cmd_context *context;
624 MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0,
625 MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1,
626 MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE = 1 << 2,
628 struct mlx4_vf_immed_vlan_work {
629 struct work_struct work;
630 struct mlx4_priv *priv;
642 struct mlx4_uar_table {
643 struct mlx4_bitmap bitmap;
646 struct mlx4_mr_table {
647 struct mlx4_bitmap mpt_bitmap;
648 struct mlx4_buddy mtt_buddy;
651 struct mlx4_icm_table mtt_table;
652 struct mlx4_icm_table dmpt_table;
655 struct mlx4_cq_table {
656 struct mlx4_bitmap bitmap;
658 struct radix_tree_root tree;
659 struct mlx4_icm_table table;
660 struct mlx4_icm_table cmpt_table;
663 struct mlx4_eq_table {
664 struct mlx4_bitmap bitmap;
666 void __iomem *clr_int;
667 void __iomem **uar_map;
670 struct mlx4_icm_table table;
671 struct mlx4_icm_table cmpt_table;
676 struct mlx4_srq_table {
677 struct mlx4_bitmap bitmap;
679 struct radix_tree_root tree;
680 struct mlx4_icm_table table;
681 struct mlx4_icm_table cmpt_table;
684 struct mlx4_qp_table {
685 struct mlx4_bitmap bitmap;
689 struct mlx4_icm_table qp_table;
690 struct mlx4_icm_table auxc_table;
691 struct mlx4_icm_table altc_table;
692 struct mlx4_icm_table rdmarc_table;
693 struct mlx4_icm_table cmpt_table;
696 struct mlx4_mcg_table {
698 struct mlx4_bitmap bitmap;
699 struct mlx4_icm_table table;
702 struct mlx4_catas_err {
704 struct timer_list timer;
705 struct list_head list;
708 #define MLX4_MAX_MAC_NUM 128
709 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
711 struct mlx4_mac_table {
712 __be64 entries[MLX4_MAX_MAC_NUM];
713 int refs[MLX4_MAX_MAC_NUM];
719 #define MLX4_ROCE_GID_ENTRY_SIZE 16
721 struct mlx4_roce_gid_entry {
722 u8 raw[MLX4_ROCE_GID_ENTRY_SIZE];
725 struct mlx4_roce_gid_table {
726 struct mlx4_roce_gid_entry roce_gids[MLX4_ROCE_MAX_GIDS];
730 #define MLX4_MAX_VLAN_NUM 128
731 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
733 struct mlx4_vlan_table {
734 __be32 entries[MLX4_MAX_VLAN_NUM];
735 int refs[MLX4_MAX_VLAN_NUM];
741 #define SET_PORT_GEN_ALL_VALID 0x7
742 #define SET_PORT_PROMISC_SHIFT 31
743 #define SET_PORT_MC_PROMISC_SHIFT 30
746 MCAST_DIRECT_ONLY = 0,
752 struct mlx4_set_port_general_context {
765 struct mlx4_set_port_rqp_calc_context {
783 struct mlx4_port_info {
784 struct mlx4_dev *dev;
787 struct device_attribute port_attr;
788 enum mlx4_port_type tmp_type;
789 char dev_mtu_name[16];
790 struct device_attribute port_mtu_attr;
791 struct mlx4_mac_table mac_table;
792 struct mlx4_vlan_table vlan_table;
793 struct mlx4_roce_gid_table gid_table;
798 struct mlx4_dev *dev;
799 u8 do_sense_port[MLX4_MAX_PORTS + 1];
800 u8 sense_allowed[MLX4_MAX_PORTS + 1];
801 struct delayed_work sense_poll;
804 struct mlx4_msix_ctl {
806 struct mutex pool_lock;
810 struct list_head promisc_qps[MLX4_NUM_STEERS];
811 struct list_head steer_entries[MLX4_NUM_STEERS];
815 MLX4_PCI_DEV_IS_VF = 1 << 0,
816 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1,
827 struct list_head dev_list;
828 struct list_head ctx_list;
834 struct list_head pgdir_list;
835 struct mutex pgdir_mutex;
839 struct mlx4_mfunc mfunc;
841 struct mlx4_bitmap pd_bitmap;
842 struct mlx4_bitmap xrcd_bitmap;
843 struct mlx4_uar_table uar_table;
844 struct mlx4_mr_table mr_table;
845 struct mlx4_cq_table cq_table;
846 struct mlx4_eq_table eq_table;
847 struct mlx4_srq_table srq_table;
848 struct mlx4_qp_table qp_table;
849 struct mlx4_mcg_table mcg_table;
850 struct mlx4_bitmap counters_bitmap;
852 struct mlx4_catas_err catas_err;
854 void __iomem *clr_base;
856 struct mlx4_uar driver_uar;
858 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
859 struct mlx4_sense sense;
860 struct mutex port_mutex;
861 struct mlx4_msix_ctl msix_ctl;
862 struct mlx4_steer *steer;
863 struct list_head bf_list;
864 struct mutex bf_mutex;
865 struct io_mapping *bf_mapping;
866 void __iomem *clock_mapping;
869 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
870 __be64 slave_node_guids[MLX4_MFUNC_MAX];
872 atomic_t opreq_count;
873 struct work_struct opreq_task;
876 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
878 return container_of(dev, struct mlx4_priv, dev);
881 #define MLX4_SENSE_RANGE (HZ * 3)
883 extern struct workqueue_struct *mlx4_wq;
885 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
886 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj, int use_rr);
887 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt,
888 int align, u32 skip_mask);
889 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt,
891 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
892 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
893 u32 reserved_bot, u32 resetrved_top);
894 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
896 int mlx4_reset(struct mlx4_dev *dev);
898 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
899 void mlx4_free_eq_table(struct mlx4_dev *dev);
901 int mlx4_init_pd_table(struct mlx4_dev *dev);
902 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
903 int mlx4_init_uar_table(struct mlx4_dev *dev);
904 int mlx4_init_mr_table(struct mlx4_dev *dev);
905 int mlx4_init_eq_table(struct mlx4_dev *dev);
906 int mlx4_init_cq_table(struct mlx4_dev *dev);
907 int mlx4_init_qp_table(struct mlx4_dev *dev);
908 int mlx4_init_srq_table(struct mlx4_dev *dev);
909 int mlx4_init_mcg_table(struct mlx4_dev *dev);
911 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
912 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
913 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
914 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
915 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
916 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
917 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
918 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
919 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
920 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn, gfp_t gfp);
921 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
922 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
923 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
924 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
925 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
926 int __mlx4_mpt_reserve(struct mlx4_dev *dev);
927 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index);
928 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index, gfp_t gfp);
929 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index);
930 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
931 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
933 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
934 struct mlx4_vhcr *vhcr,
935 struct mlx4_cmd_mailbox *inbox,
936 struct mlx4_cmd_mailbox *outbox,
937 struct mlx4_cmd_info *cmd);
938 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
939 struct mlx4_vhcr *vhcr,
940 struct mlx4_cmd_mailbox *inbox,
941 struct mlx4_cmd_mailbox *outbox,
942 struct mlx4_cmd_info *cmd);
943 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
944 struct mlx4_vhcr *vhcr,
945 struct mlx4_cmd_mailbox *inbox,
946 struct mlx4_cmd_mailbox *outbox,
947 struct mlx4_cmd_info *cmd);
948 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
949 struct mlx4_vhcr *vhcr,
950 struct mlx4_cmd_mailbox *inbox,
951 struct mlx4_cmd_mailbox *outbox,
952 struct mlx4_cmd_info *cmd);
953 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
954 struct mlx4_vhcr *vhcr,
955 struct mlx4_cmd_mailbox *inbox,
956 struct mlx4_cmd_mailbox *outbox,
957 struct mlx4_cmd_info *cmd);
958 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
959 struct mlx4_vhcr *vhcr,
960 struct mlx4_cmd_mailbox *inbox,
961 struct mlx4_cmd_mailbox *outbox,
962 struct mlx4_cmd_info *cmd);
963 int mlx4_CONFIG_DEV_wrapper(struct mlx4_dev *dev, int slave,
964 struct mlx4_vhcr *vhcr,
965 struct mlx4_cmd_mailbox *inbox,
966 struct mlx4_cmd_mailbox *outbox,
967 struct mlx4_cmd_info *cmd);
968 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
969 struct mlx4_vhcr *vhcr,
970 struct mlx4_cmd_mailbox *inbox,
971 struct mlx4_cmd_mailbox *outbox,
972 struct mlx4_cmd_info *cmd);
973 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
974 int *base, u8 flags);
975 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
976 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
977 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
978 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
979 int start_index, int npages, u64 *page_list);
980 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
981 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
982 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
983 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
985 void mlx4_start_catas_poll(struct mlx4_dev *dev);
986 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
987 void mlx4_catas_init(void);
988 int mlx4_restart_one(struct pci_dev *pdev);
989 int mlx4_register_device(struct mlx4_dev *dev);
990 void mlx4_unregister_device(struct mlx4_dev *dev);
991 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
992 unsigned long param);
995 struct mlx4_init_hca_param;
997 u64 mlx4_make_profile(struct mlx4_dev *dev,
998 struct mlx4_profile *request,
999 struct mlx4_dev_cap *dev_cap,
1000 struct mlx4_init_hca_param *init_hca);
1001 void mlx4_master_comm_channel(struct work_struct *work);
1002 void mlx4_gen_slave_eqe(struct work_struct *work);
1003 void mlx4_master_handle_slave_flr(struct work_struct *work);
1005 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
1006 struct mlx4_vhcr *vhcr,
1007 struct mlx4_cmd_mailbox *inbox,
1008 struct mlx4_cmd_mailbox *outbox,
1009 struct mlx4_cmd_info *cmd);
1010 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
1011 struct mlx4_vhcr *vhcr,
1012 struct mlx4_cmd_mailbox *inbox,
1013 struct mlx4_cmd_mailbox *outbox,
1014 struct mlx4_cmd_info *cmd);
1015 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
1016 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
1017 struct mlx4_cmd_mailbox *outbox,
1018 struct mlx4_cmd_info *cmd);
1019 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
1020 struct mlx4_vhcr *vhcr,
1021 struct mlx4_cmd_mailbox *inbox,
1022 struct mlx4_cmd_mailbox *outbox,
1023 struct mlx4_cmd_info *cmd);
1024 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
1025 struct mlx4_vhcr *vhcr,
1026 struct mlx4_cmd_mailbox *inbox,
1027 struct mlx4_cmd_mailbox *outbox,
1028 struct mlx4_cmd_info *cmd);
1029 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
1030 struct mlx4_vhcr *vhcr,
1031 struct mlx4_cmd_mailbox *inbox,
1032 struct mlx4_cmd_mailbox *outbox,
1033 struct mlx4_cmd_info *cmd);
1034 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1035 struct mlx4_vhcr *vhcr,
1036 struct mlx4_cmd_mailbox *inbox,
1037 struct mlx4_cmd_mailbox *outbox,
1038 struct mlx4_cmd_info *cmd);
1039 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1040 struct mlx4_vhcr *vhcr,
1041 struct mlx4_cmd_mailbox *inbox,
1042 struct mlx4_cmd_mailbox *outbox,
1043 struct mlx4_cmd_info *cmd);
1044 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1045 struct mlx4_vhcr *vhcr,
1046 struct mlx4_cmd_mailbox *inbox,
1047 struct mlx4_cmd_mailbox *outbox,
1048 struct mlx4_cmd_info *cmd);
1049 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1050 struct mlx4_vhcr *vhcr,
1051 struct mlx4_cmd_mailbox *inbox,
1052 struct mlx4_cmd_mailbox *outbox,
1053 struct mlx4_cmd_info *cmd);
1054 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1055 struct mlx4_vhcr *vhcr,
1056 struct mlx4_cmd_mailbox *inbox,
1057 struct mlx4_cmd_mailbox *outbox,
1058 struct mlx4_cmd_info *cmd);
1059 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1060 struct mlx4_vhcr *vhcr,
1061 struct mlx4_cmd_mailbox *inbox,
1062 struct mlx4_cmd_mailbox *outbox,
1063 struct mlx4_cmd_info *cmd);
1064 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1065 struct mlx4_vhcr *vhcr,
1066 struct mlx4_cmd_mailbox *inbox,
1067 struct mlx4_cmd_mailbox *outbox,
1068 struct mlx4_cmd_info *cmd);
1069 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1070 struct mlx4_vhcr *vhcr,
1071 struct mlx4_cmd_mailbox *inbox,
1072 struct mlx4_cmd_mailbox *outbox,
1073 struct mlx4_cmd_info *cmd);
1074 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
1075 struct mlx4_vhcr *vhcr,
1076 struct mlx4_cmd_mailbox *inbox,
1077 struct mlx4_cmd_mailbox *outbox,
1078 struct mlx4_cmd_info *cmd);
1079 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1080 struct mlx4_vhcr *vhcr,
1081 struct mlx4_cmd_mailbox *inbox,
1082 struct mlx4_cmd_mailbox *outbox,
1083 struct mlx4_cmd_info *cmd);
1084 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1085 struct mlx4_vhcr *vhcr,
1086 struct mlx4_cmd_mailbox *inbox,
1087 struct mlx4_cmd_mailbox *outbox,
1088 struct mlx4_cmd_info *cmd);
1089 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
1090 struct mlx4_vhcr *vhcr,
1091 struct mlx4_cmd_mailbox *inbox,
1092 struct mlx4_cmd_mailbox *outbox,
1093 struct mlx4_cmd_info *cmd);
1094 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1095 struct mlx4_vhcr *vhcr,
1096 struct mlx4_cmd_mailbox *inbox,
1097 struct mlx4_cmd_mailbox *outbox,
1098 struct mlx4_cmd_info *cmd);
1099 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1100 struct mlx4_vhcr *vhcr,
1101 struct mlx4_cmd_mailbox *inbox,
1102 struct mlx4_cmd_mailbox *outbox,
1103 struct mlx4_cmd_info *cmd);
1104 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1105 struct mlx4_vhcr *vhcr,
1106 struct mlx4_cmd_mailbox *inbox,
1107 struct mlx4_cmd_mailbox *outbox,
1108 struct mlx4_cmd_info *cmd);
1109 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave,
1110 struct mlx4_vhcr *vhcr,
1111 struct mlx4_cmd_mailbox *inbox,
1112 struct mlx4_cmd_mailbox *outbox,
1113 struct mlx4_cmd_info *cmd);
1114 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1115 struct mlx4_vhcr *vhcr,
1116 struct mlx4_cmd_mailbox *inbox,
1117 struct mlx4_cmd_mailbox *outbox,
1118 struct mlx4_cmd_info *cmd);
1119 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1120 struct mlx4_vhcr *vhcr,
1121 struct mlx4_cmd_mailbox *inbox,
1122 struct mlx4_cmd_mailbox *outbox,
1123 struct mlx4_cmd_info *cmd);
1124 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1125 struct mlx4_vhcr *vhcr,
1126 struct mlx4_cmd_mailbox *inbox,
1127 struct mlx4_cmd_mailbox *outbox,
1128 struct mlx4_cmd_info *cmd);
1129 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1130 struct mlx4_vhcr *vhcr,
1131 struct mlx4_cmd_mailbox *inbox,
1132 struct mlx4_cmd_mailbox *outbox,
1133 struct mlx4_cmd_info *cmd);
1134 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave,
1135 struct mlx4_vhcr *vhcr,
1136 struct mlx4_cmd_mailbox *inbox,
1137 struct mlx4_cmd_mailbox *outbox,
1138 struct mlx4_cmd_info *cmd);
1140 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
1143 MLX4_CMD_CLEANUP_STRUCT = 1UL << 0,
1144 MLX4_CMD_CLEANUP_POOL = 1UL << 1,
1145 MLX4_CMD_CLEANUP_HCR = 1UL << 2,
1146 MLX4_CMD_CLEANUP_VHCR = 1UL << 3,
1147 MLX4_CMD_CLEANUP_ALL = (MLX4_CMD_CLEANUP_VHCR << 1) - 1
1150 int mlx4_cmd_init(struct mlx4_dev *dev);
1151 void mlx4_cmd_cleanup(struct mlx4_dev *dev, int cleanup_mask);
1152 int mlx4_multi_func_init(struct mlx4_dev *dev);
1153 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
1154 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1155 int mlx4_cmd_use_events(struct mlx4_dev *dev);
1156 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1158 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1159 unsigned long timeout);
1161 void mlx4_cq_tasklet_cb(unsigned long data);
1162 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1163 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1165 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1167 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1169 void mlx4_handle_catas_err(struct mlx4_dev *dev);
1171 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1172 enum mlx4_port_type *type);
1173 void mlx4_do_sense_ports(struct mlx4_dev *dev,
1174 enum mlx4_port_type *stype,
1175 enum mlx4_port_type *defaults);
1176 void mlx4_start_sense(struct mlx4_dev *dev);
1177 void mlx4_stop_sense(struct mlx4_dev *dev);
1178 void mlx4_sense_init(struct mlx4_dev *dev);
1179 int mlx4_check_port_params(struct mlx4_dev *dev,
1180 enum mlx4_port_type *port_type);
1181 int mlx4_change_port_types(struct mlx4_dev *dev,
1182 enum mlx4_port_type *port_types);
1184 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1185 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1186 void mlx4_init_roce_gid_table(struct mlx4_dev *dev,
1187 struct mlx4_roce_gid_table *table);
1188 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1189 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1191 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz);
1192 /* resource tracker functions*/
1193 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1194 enum mlx4_resource resource_type,
1195 u64 resource_id, int *slave);
1196 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1197 void mlx4_reset_roce_gids(struct mlx4_dev *dev, int slave);
1198 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1200 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1201 enum mlx4_res_tracker_free_type type);
1203 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1204 struct mlx4_vhcr *vhcr,
1205 struct mlx4_cmd_mailbox *inbox,
1206 struct mlx4_cmd_mailbox *outbox,
1207 struct mlx4_cmd_info *cmd);
1208 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1209 struct mlx4_vhcr *vhcr,
1210 struct mlx4_cmd_mailbox *inbox,
1211 struct mlx4_cmd_mailbox *outbox,
1212 struct mlx4_cmd_info *cmd);
1213 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1214 struct mlx4_vhcr *vhcr,
1215 struct mlx4_cmd_mailbox *inbox,
1216 struct mlx4_cmd_mailbox *outbox,
1217 struct mlx4_cmd_info *cmd);
1218 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1219 struct mlx4_vhcr *vhcr,
1220 struct mlx4_cmd_mailbox *inbox,
1221 struct mlx4_cmd_mailbox *outbox,
1222 struct mlx4_cmd_info *cmd);
1223 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1224 struct mlx4_vhcr *vhcr,
1225 struct mlx4_cmd_mailbox *inbox,
1226 struct mlx4_cmd_mailbox *outbox,
1227 struct mlx4_cmd_info *cmd);
1228 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1229 struct mlx4_vhcr *vhcr,
1230 struct mlx4_cmd_mailbox *inbox,
1231 struct mlx4_cmd_mailbox *outbox,
1232 struct mlx4_cmd_info *cmd);
1233 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1235 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1236 int *gid_tbl_len, int *pkey_tbl_len);
1238 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1239 struct mlx4_vhcr *vhcr,
1240 struct mlx4_cmd_mailbox *inbox,
1241 struct mlx4_cmd_mailbox *outbox,
1242 struct mlx4_cmd_info *cmd);
1244 int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave,
1245 struct mlx4_vhcr *vhcr,
1246 struct mlx4_cmd_mailbox *inbox,
1247 struct mlx4_cmd_mailbox *outbox,
1248 struct mlx4_cmd_info *cmd);
1250 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1251 struct mlx4_vhcr *vhcr,
1252 struct mlx4_cmd_mailbox *inbox,
1253 struct mlx4_cmd_mailbox *outbox,
1254 struct mlx4_cmd_info *cmd);
1255 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1256 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1257 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1258 int block_mcast_loopback, enum mlx4_protocol prot,
1259 enum mlx4_steer_type steer);
1260 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1261 u8 gid[16], u8 port,
1262 int block_mcast_loopback,
1263 enum mlx4_protocol prot, u64 *reg_id);
1264 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1265 struct mlx4_vhcr *vhcr,
1266 struct mlx4_cmd_mailbox *inbox,
1267 struct mlx4_cmd_mailbox *outbox,
1268 struct mlx4_cmd_info *cmd);
1269 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1270 struct mlx4_vhcr *vhcr,
1271 struct mlx4_cmd_mailbox *inbox,
1272 struct mlx4_cmd_mailbox *outbox,
1273 struct mlx4_cmd_info *cmd);
1274 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1275 int port, void *buf);
1276 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1277 struct mlx4_cmd_mailbox *outbox);
1278 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1279 struct mlx4_vhcr *vhcr,
1280 struct mlx4_cmd_mailbox *inbox,
1281 struct mlx4_cmd_mailbox *outbox,
1282 struct mlx4_cmd_info *cmd);
1283 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1284 struct mlx4_vhcr *vhcr,
1285 struct mlx4_cmd_mailbox *inbox,
1286 struct mlx4_cmd_mailbox *outbox,
1287 struct mlx4_cmd_info *cmd);
1288 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1289 struct mlx4_vhcr *vhcr,
1290 struct mlx4_cmd_mailbox *inbox,
1291 struct mlx4_cmd_mailbox *outbox,
1292 struct mlx4_cmd_info *cmd);
1293 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1294 struct mlx4_vhcr *vhcr,
1295 struct mlx4_cmd_mailbox *inbox,
1296 struct mlx4_cmd_mailbox *outbox,
1297 struct mlx4_cmd_info *cmd);
1298 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1299 struct mlx4_vhcr *vhcr,
1300 struct mlx4_cmd_mailbox *inbox,
1301 struct mlx4_cmd_mailbox *outbox,
1302 struct mlx4_cmd_info *cmd);
1303 int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave,
1304 struct mlx4_vhcr *vhcr,
1305 struct mlx4_cmd_mailbox *inbox,
1306 struct mlx4_cmd_mailbox *outbox,
1307 struct mlx4_cmd_info *cmd);
1309 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1310 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1312 static inline void set_param_l(u64 *arg, u32 val)
1314 *arg = (*arg & 0xffffffff00000000ULL) | (u64) val;
1317 static inline void set_param_h(u64 *arg, u32 val)
1319 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1322 static inline u32 get_param_l(u64 *arg)
1324 return (u32) (*arg & 0xffffffff);
1327 static inline u32 get_param_h(u64 *arg)
1329 return (u32)(*arg >> 32);
1332 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1334 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1337 #define NOT_MASKED_PD_BITS 17
1339 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work);
1341 void mlx4_init_quotas(struct mlx4_dev *dev);
1343 int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave, int port);
1344 /* Returns the VF index of slave */
1345 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave);
1346 int mlx4_config_mad_demux(struct mlx4_dev *dev);