2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/mutex.h>
41 #include <linux/radix-tree.h>
42 #include <linux/rbtree.h>
43 #include <linux/timer.h>
44 #include <linux/semaphore.h>
45 #include <linux/workqueue.h>
47 #include <linux/mlx4/device.h>
48 #include <linux/mlx4/driver.h>
49 #include <linux/mlx4/doorbell.h>
50 #include <linux/mlx4/cmd.h>
52 #define DRV_NAME "mlx4_core"
53 #define PFX DRV_NAME ": "
54 #define DRV_VERSION "2.2-1"
55 #define DRV_RELDATE "Feb, 2014"
57 #define MLX4_FS_UDP_UC_EN (1 << 1)
58 #define MLX4_FS_TCP_UC_EN (1 << 2)
59 #define MLX4_FS_NUM_OF_L2_ADDR 8
60 #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7
61 #define MLX4_FS_NUM_MCG (1 << 17)
63 #define INIT_HCA_TPT_MW_ENABLE (1 << 7)
67 #define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */
68 #define MLX4_RATELIMIT_DEFAULT 0xffff
70 struct mlx4_set_port_prio2tc_context {
74 struct mlx4_port_scheduler_tc_cfg_be {
77 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
81 struct mlx4_set_port_scheduler_context {
82 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
86 MLX4_HCR_BASE = 0x80680,
87 MLX4_HCR_SIZE = 0x0001c,
88 MLX4_CLR_INT_SIZE = 0x00008,
89 MLX4_SLAVE_COMM_BASE = 0x0,
90 MLX4_COMM_PAGESIZE = 0x1000,
91 MLX4_CLOCK_SIZE = 0x00008
95 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10,
96 MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7,
97 MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12,
98 MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2),
99 MLX4_MTT_ENTRY_PER_SEG = 8,
103 MLX4_NUM_PDS = 1 << 15
107 MLX4_CMPT_TYPE_QP = 0,
108 MLX4_CMPT_TYPE_SRQ = 1,
109 MLX4_CMPT_TYPE_CQ = 2,
110 MLX4_CMPT_TYPE_EQ = 3,
115 MLX4_CMPT_SHIFT = 24,
116 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
119 enum mlx4_mpt_state {
120 MLX4_MPT_DISABLED = 0,
125 #define MLX4_COMM_TIME 10000
131 MLX4_COMM_CMD_VHCR_EN,
132 MLX4_COMM_CMD_VHCR_POST,
133 MLX4_COMM_CMD_FLR = 254
137 MLX4_VF_SMI_DISABLED,
141 /*The flag indicates that the slave should delay the RESET cmd*/
142 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
143 /*indicates how many retries will be done if we are in the middle of FLR*/
144 #define NUM_OF_RESET_RETRIES 10
145 #define SLEEP_TIME_IN_RESET (2 * 1000)
158 MLX4_NUM_OF_RESOURCE_TYPE
161 enum mlx4_alloc_mode {
163 RES_OP_RESERVE_AND_MAP,
167 enum mlx4_res_tracker_free_type {
169 RES_TR_FREE_SLAVES_ONLY,
170 RES_TR_FREE_STRUCTS_ONLY,
174 *Virtual HCR structures.
175 * mlx4_vhcr is the sw representation, in machine endianess
177 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
178 * to FW to go through communication channel.
179 * It is big endian, and has the same structure as the physical HCR
180 * used by command interface
193 struct mlx4_vhcr_cmd {
204 struct mlx4_cmd_info {
209 bool encode_slave_id;
210 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
211 struct mlx4_cmd_mailbox *inbox);
212 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
213 struct mlx4_cmd_mailbox *inbox,
214 struct mlx4_cmd_mailbox *outbox,
215 struct mlx4_cmd_info *cmd);
218 #ifdef CONFIG_MLX4_DEBUG
219 extern int mlx4_debug_level;
220 #else /* CONFIG_MLX4_DEBUG */
221 #define mlx4_debug_level (0)
222 #endif /* CONFIG_MLX4_DEBUG */
224 #define mlx4_dbg(mdev, format, ...) \
226 if (mlx4_debug_level) \
227 dev_printk(KERN_DEBUG, &(mdev)->pdev->dev, format, \
231 #define mlx4_err(mdev, format, ...) \
232 dev_err(&(mdev)->pdev->dev, format, ##__VA_ARGS__)
233 #define mlx4_info(mdev, format, ...) \
234 dev_info(&(mdev)->pdev->dev, format, ##__VA_ARGS__)
235 #define mlx4_warn(mdev, format, ...) \
236 dev_warn(&(mdev)->pdev->dev, format, ##__VA_ARGS__)
238 extern int mlx4_log_num_mgm_entry_size;
239 extern int log_mtts_per_seg;
241 #define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
242 #define ALL_SLAVES 0xff
252 unsigned long *table;
256 unsigned long **bits;
257 unsigned int *num_free;
264 struct mlx4_icm_table {
272 struct mlx4_icm **icm;
275 #define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28)
276 #define MLX4_MPT_FLAG_FREE (0x3UL << 28)
277 #define MLX4_MPT_FLAG_MIO (1 << 17)
278 #define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15)
279 #define MLX4_MPT_FLAG_PHYSICAL (1 << 9)
280 #define MLX4_MPT_FLAG_REGION (1 << 8)
282 #define MLX4_MPT_PD_MASK (0x1FFFFUL)
283 #define MLX4_MPT_PD_VF_MASK (0xFE0000UL)
284 #define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27)
285 #define MLX4_MPT_PD_FLAG_RAE (1 << 28)
286 #define MLX4_MPT_PD_FLAG_EN_INV (3 << 24)
288 #define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7)
290 #define MLX4_MPT_STATUS_SW 0xF0
291 #define MLX4_MPT_STATUS_HW 0x00
294 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
296 struct mlx4_mpt_entry {
310 __be32 first_byte_offset;
314 * Must be packed because start is 64 bits but only aligned to 32 bits.
316 struct mlx4_eq_context {
330 __be32 mtt_base_addr_l;
332 __be32 consumer_index;
333 __be32 producer_index;
337 struct mlx4_cq_context {
341 __be32 logsize_usrpage;
349 __be32 mtt_base_addr_l;
350 __be32 last_notified_index;
351 __be32 solicit_producer_index;
352 __be32 consumer_index;
353 __be32 producer_index;
358 struct mlx4_srq_context {
359 __be32 state_logsize_srqn;
363 __be32 pg_offset_cqn;
368 __be32 mtt_base_addr_l;
370 __be16 limit_watermark;
379 struct mlx4_dev *dev;
380 void __iomem *doorbell;
386 struct mlx4_buf_list *page_list;
390 struct mlx4_slave_eqe {
396 struct mlx4_slave_event_eq_info {
401 struct mlx4_profile {
416 struct mlx4_icm *fw_icm;
417 struct mlx4_icm *aux_icm;
432 MLX4_MCAST_CONFIG = 0,
433 MLX4_MCAST_DISABLE = 1,
434 MLX4_MCAST_ENABLE = 2,
437 #define VLAN_FLTR_SIZE 128
439 struct mlx4_vlan_fltr {
440 __be32 entry[VLAN_FLTR_SIZE];
443 struct mlx4_mcast_entry {
444 struct list_head list;
448 struct mlx4_promisc_qp {
449 struct list_head list;
453 struct mlx4_steer_index {
454 struct list_head list;
456 struct list_head duplicates;
459 #define MLX4_EVENT_TYPES_NUM 64
461 struct mlx4_slave_state {
469 u16 mtu[MLX4_MAX_PORTS + 1];
470 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
471 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
472 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
473 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
474 /* event type to eq number lookup */
475 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
479 /*initialized via the kzalloc*/
480 u8 is_slave_going_down;
482 enum slave_port_state port_state[MLX4_MAX_PORTS + 1];
485 #define MLX4_VGT 4095
488 struct mlx4_vport_state {
497 struct mlx4_vf_admin_state {
498 struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1];
499 u8 enable_smi[MLX4_MAX_PORTS + 1];
502 struct mlx4_vport_oper_state {
503 struct mlx4_vport_state state;
508 struct mlx4_vf_oper_state {
509 struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1];
510 u8 smi_enabled[MLX4_MAX_PORTS + 1];
515 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
518 struct resource_allocator {
519 spinlock_t alloc_lock; /* protect quotas */
522 int res_port_rsvd[MLX4_MAX_PORTS];
526 int res_port_free[MLX4_MAX_PORTS];
533 struct mlx4_resource_tracker {
535 /* tree for each resources */
536 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
537 /* num_of_slave's lists, one per slave */
538 struct slave_list *slave_list;
539 struct resource_allocator res_alloc[MLX4_NUM_OF_RESOURCE_TYPE];
542 #define SLAVE_EVENT_EQ_SIZE 128
543 struct mlx4_slave_event_eq {
547 spinlock_t event_lock;
548 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
551 struct mlx4_master_qp0_state {
552 int proxy_qp0_active;
557 struct mlx4_mfunc_master_ctx {
558 struct mlx4_slave_state *slave_state;
559 struct mlx4_vf_admin_state *vf_admin;
560 struct mlx4_vf_oper_state *vf_oper;
561 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
562 int init_port_ref[MLX4_MAX_PORTS + 1];
563 u16 max_mtu[MLX4_MAX_PORTS + 1];
564 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
565 struct mlx4_resource_tracker res_tracker;
566 struct workqueue_struct *comm_wq;
567 struct work_struct comm_work;
568 struct work_struct slave_event_work;
569 struct work_struct slave_flr_event_work;
570 spinlock_t slave_state_lock;
571 __be32 comm_arm_bit_vector[4];
572 struct mlx4_eqe cmd_eqe;
573 struct mlx4_slave_event_eq slave_eq;
574 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
578 struct mlx4_comm __iomem *comm;
579 struct mlx4_vhcr_cmd *vhcr;
582 struct mlx4_mfunc_master_ctx master;
585 #define MGM_QPN_MASK 0x00FFFFFF
586 #define MGM_BLCK_LB_BIT 30
589 __be32 next_gid_index;
590 __be32 members_count;
593 __be32 qp[MLX4_MAX_QP_PER_MGM];
597 struct pci_pool *pool;
599 struct mutex hcr_mutex;
600 struct mutex slave_cmd_mutex;
601 struct semaphore poll_sem;
602 struct semaphore event_sem;
604 spinlock_t context_lock;
606 struct mlx4_cmd_context *context;
614 MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0,
615 MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1,
616 MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE = 1 << 2,
618 struct mlx4_vf_immed_vlan_work {
619 struct work_struct work;
620 struct mlx4_priv *priv;
632 struct mlx4_uar_table {
633 struct mlx4_bitmap bitmap;
636 struct mlx4_mr_table {
637 struct mlx4_bitmap mpt_bitmap;
638 struct mlx4_buddy mtt_buddy;
641 struct mlx4_icm_table mtt_table;
642 struct mlx4_icm_table dmpt_table;
645 struct mlx4_cq_table {
646 struct mlx4_bitmap bitmap;
648 struct radix_tree_root tree;
649 struct mlx4_icm_table table;
650 struct mlx4_icm_table cmpt_table;
653 struct mlx4_eq_table {
654 struct mlx4_bitmap bitmap;
656 void __iomem *clr_int;
657 void __iomem **uar_map;
660 struct mlx4_icm_table table;
661 struct mlx4_icm_table cmpt_table;
666 struct mlx4_srq_table {
667 struct mlx4_bitmap bitmap;
669 struct radix_tree_root tree;
670 struct mlx4_icm_table table;
671 struct mlx4_icm_table cmpt_table;
674 struct mlx4_qp_table {
675 struct mlx4_bitmap bitmap;
679 struct mlx4_icm_table qp_table;
680 struct mlx4_icm_table auxc_table;
681 struct mlx4_icm_table altc_table;
682 struct mlx4_icm_table rdmarc_table;
683 struct mlx4_icm_table cmpt_table;
686 struct mlx4_mcg_table {
688 struct mlx4_bitmap bitmap;
689 struct mlx4_icm_table table;
692 struct mlx4_catas_err {
694 struct timer_list timer;
695 struct list_head list;
698 #define MLX4_MAX_MAC_NUM 128
699 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
701 struct mlx4_mac_table {
702 __be64 entries[MLX4_MAX_MAC_NUM];
703 int refs[MLX4_MAX_MAC_NUM];
709 #define MLX4_ROCE_GID_ENTRY_SIZE 16
711 struct mlx4_roce_gid_entry {
712 u8 raw[MLX4_ROCE_GID_ENTRY_SIZE];
715 struct mlx4_roce_gid_table {
716 struct mlx4_roce_gid_entry roce_gids[MLX4_ROCE_MAX_GIDS];
720 #define MLX4_MAX_VLAN_NUM 128
721 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
723 struct mlx4_vlan_table {
724 __be32 entries[MLX4_MAX_VLAN_NUM];
725 int refs[MLX4_MAX_VLAN_NUM];
731 #define SET_PORT_GEN_ALL_VALID 0x7
732 #define SET_PORT_PROMISC_SHIFT 31
733 #define SET_PORT_MC_PROMISC_SHIFT 30
736 MCAST_DIRECT_ONLY = 0,
742 struct mlx4_set_port_general_context {
755 struct mlx4_set_port_rqp_calc_context {
773 struct mlx4_port_info {
774 struct mlx4_dev *dev;
777 struct device_attribute port_attr;
778 enum mlx4_port_type tmp_type;
779 char dev_mtu_name[16];
780 struct device_attribute port_mtu_attr;
781 struct mlx4_mac_table mac_table;
782 struct mlx4_vlan_table vlan_table;
783 struct mlx4_roce_gid_table gid_table;
788 struct mlx4_dev *dev;
789 u8 do_sense_port[MLX4_MAX_PORTS + 1];
790 u8 sense_allowed[MLX4_MAX_PORTS + 1];
791 struct delayed_work sense_poll;
794 struct mlx4_msix_ctl {
796 struct mutex pool_lock;
800 struct list_head promisc_qps[MLX4_NUM_STEERS];
801 struct list_head steer_entries[MLX4_NUM_STEERS];
805 MLX4_PCI_DEV_IS_VF = 1 << 0,
806 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1,
817 struct list_head dev_list;
818 struct list_head ctx_list;
824 struct list_head pgdir_list;
825 struct mutex pgdir_mutex;
829 struct mlx4_mfunc mfunc;
831 struct mlx4_bitmap pd_bitmap;
832 struct mlx4_bitmap xrcd_bitmap;
833 struct mlx4_uar_table uar_table;
834 struct mlx4_mr_table mr_table;
835 struct mlx4_cq_table cq_table;
836 struct mlx4_eq_table eq_table;
837 struct mlx4_srq_table srq_table;
838 struct mlx4_qp_table qp_table;
839 struct mlx4_mcg_table mcg_table;
840 struct mlx4_bitmap counters_bitmap;
842 struct mlx4_catas_err catas_err;
844 void __iomem *clr_base;
846 struct mlx4_uar driver_uar;
848 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
849 struct mlx4_sense sense;
850 struct mutex port_mutex;
851 struct mlx4_msix_ctl msix_ctl;
852 struct mlx4_steer *steer;
853 struct list_head bf_list;
854 struct mutex bf_mutex;
855 struct io_mapping *bf_mapping;
856 void __iomem *clock_mapping;
859 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
860 __be64 slave_node_guids[MLX4_MFUNC_MAX];
862 atomic_t opreq_count;
863 struct work_struct opreq_task;
866 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
868 return container_of(dev, struct mlx4_priv, dev);
871 #define MLX4_SENSE_RANGE (HZ * 3)
873 extern struct workqueue_struct *mlx4_wq;
875 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
876 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj, int use_rr);
877 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
878 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt,
880 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
881 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
882 u32 reserved_bot, u32 resetrved_top);
883 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
885 int mlx4_reset(struct mlx4_dev *dev);
887 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
888 void mlx4_free_eq_table(struct mlx4_dev *dev);
890 int mlx4_init_pd_table(struct mlx4_dev *dev);
891 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
892 int mlx4_init_uar_table(struct mlx4_dev *dev);
893 int mlx4_init_mr_table(struct mlx4_dev *dev);
894 int mlx4_init_eq_table(struct mlx4_dev *dev);
895 int mlx4_init_cq_table(struct mlx4_dev *dev);
896 int mlx4_init_qp_table(struct mlx4_dev *dev);
897 int mlx4_init_srq_table(struct mlx4_dev *dev);
898 int mlx4_init_mcg_table(struct mlx4_dev *dev);
900 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
901 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
902 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
903 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
904 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
905 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
906 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
907 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
908 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
909 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn, gfp_t gfp);
910 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
911 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
912 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
913 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
914 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
915 int __mlx4_mpt_reserve(struct mlx4_dev *dev);
916 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index);
917 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index, gfp_t gfp);
918 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index);
919 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
920 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
922 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
923 struct mlx4_vhcr *vhcr,
924 struct mlx4_cmd_mailbox *inbox,
925 struct mlx4_cmd_mailbox *outbox,
926 struct mlx4_cmd_info *cmd);
927 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
928 struct mlx4_vhcr *vhcr,
929 struct mlx4_cmd_mailbox *inbox,
930 struct mlx4_cmd_mailbox *outbox,
931 struct mlx4_cmd_info *cmd);
932 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
933 struct mlx4_vhcr *vhcr,
934 struct mlx4_cmd_mailbox *inbox,
935 struct mlx4_cmd_mailbox *outbox,
936 struct mlx4_cmd_info *cmd);
937 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
938 struct mlx4_vhcr *vhcr,
939 struct mlx4_cmd_mailbox *inbox,
940 struct mlx4_cmd_mailbox *outbox,
941 struct mlx4_cmd_info *cmd);
942 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
943 struct mlx4_vhcr *vhcr,
944 struct mlx4_cmd_mailbox *inbox,
945 struct mlx4_cmd_mailbox *outbox,
946 struct mlx4_cmd_info *cmd);
947 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
948 struct mlx4_vhcr *vhcr,
949 struct mlx4_cmd_mailbox *inbox,
950 struct mlx4_cmd_mailbox *outbox,
951 struct mlx4_cmd_info *cmd);
952 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
953 struct mlx4_vhcr *vhcr,
954 struct mlx4_cmd_mailbox *inbox,
955 struct mlx4_cmd_mailbox *outbox,
956 struct mlx4_cmd_info *cmd);
957 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
959 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
960 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
961 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
962 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
963 int start_index, int npages, u64 *page_list);
964 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
965 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
966 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
967 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
969 void mlx4_start_catas_poll(struct mlx4_dev *dev);
970 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
971 void mlx4_catas_init(void);
972 int mlx4_restart_one(struct pci_dev *pdev);
973 int mlx4_register_device(struct mlx4_dev *dev);
974 void mlx4_unregister_device(struct mlx4_dev *dev);
975 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
976 unsigned long param);
979 struct mlx4_init_hca_param;
981 u64 mlx4_make_profile(struct mlx4_dev *dev,
982 struct mlx4_profile *request,
983 struct mlx4_dev_cap *dev_cap,
984 struct mlx4_init_hca_param *init_hca);
985 void mlx4_master_comm_channel(struct work_struct *work);
986 void mlx4_gen_slave_eqe(struct work_struct *work);
987 void mlx4_master_handle_slave_flr(struct work_struct *work);
989 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
990 struct mlx4_vhcr *vhcr,
991 struct mlx4_cmd_mailbox *inbox,
992 struct mlx4_cmd_mailbox *outbox,
993 struct mlx4_cmd_info *cmd);
994 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
995 struct mlx4_vhcr *vhcr,
996 struct mlx4_cmd_mailbox *inbox,
997 struct mlx4_cmd_mailbox *outbox,
998 struct mlx4_cmd_info *cmd);
999 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
1000 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
1001 struct mlx4_cmd_mailbox *outbox,
1002 struct mlx4_cmd_info *cmd);
1003 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
1004 struct mlx4_vhcr *vhcr,
1005 struct mlx4_cmd_mailbox *inbox,
1006 struct mlx4_cmd_mailbox *outbox,
1007 struct mlx4_cmd_info *cmd);
1008 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
1009 struct mlx4_vhcr *vhcr,
1010 struct mlx4_cmd_mailbox *inbox,
1011 struct mlx4_cmd_mailbox *outbox,
1012 struct mlx4_cmd_info *cmd);
1013 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
1014 struct mlx4_vhcr *vhcr,
1015 struct mlx4_cmd_mailbox *inbox,
1016 struct mlx4_cmd_mailbox *outbox,
1017 struct mlx4_cmd_info *cmd);
1018 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1019 struct mlx4_vhcr *vhcr,
1020 struct mlx4_cmd_mailbox *inbox,
1021 struct mlx4_cmd_mailbox *outbox,
1022 struct mlx4_cmd_info *cmd);
1023 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1024 struct mlx4_vhcr *vhcr,
1025 struct mlx4_cmd_mailbox *inbox,
1026 struct mlx4_cmd_mailbox *outbox,
1027 struct mlx4_cmd_info *cmd);
1028 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1029 struct mlx4_vhcr *vhcr,
1030 struct mlx4_cmd_mailbox *inbox,
1031 struct mlx4_cmd_mailbox *outbox,
1032 struct mlx4_cmd_info *cmd);
1033 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1034 struct mlx4_vhcr *vhcr,
1035 struct mlx4_cmd_mailbox *inbox,
1036 struct mlx4_cmd_mailbox *outbox,
1037 struct mlx4_cmd_info *cmd);
1038 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1039 struct mlx4_vhcr *vhcr,
1040 struct mlx4_cmd_mailbox *inbox,
1041 struct mlx4_cmd_mailbox *outbox,
1042 struct mlx4_cmd_info *cmd);
1043 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1044 struct mlx4_vhcr *vhcr,
1045 struct mlx4_cmd_mailbox *inbox,
1046 struct mlx4_cmd_mailbox *outbox,
1047 struct mlx4_cmd_info *cmd);
1048 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1049 struct mlx4_vhcr *vhcr,
1050 struct mlx4_cmd_mailbox *inbox,
1051 struct mlx4_cmd_mailbox *outbox,
1052 struct mlx4_cmd_info *cmd);
1053 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1054 struct mlx4_vhcr *vhcr,
1055 struct mlx4_cmd_mailbox *inbox,
1056 struct mlx4_cmd_mailbox *outbox,
1057 struct mlx4_cmd_info *cmd);
1058 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
1059 struct mlx4_vhcr *vhcr,
1060 struct mlx4_cmd_mailbox *inbox,
1061 struct mlx4_cmd_mailbox *outbox,
1062 struct mlx4_cmd_info *cmd);
1063 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1064 struct mlx4_vhcr *vhcr,
1065 struct mlx4_cmd_mailbox *inbox,
1066 struct mlx4_cmd_mailbox *outbox,
1067 struct mlx4_cmd_info *cmd);
1068 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1069 struct mlx4_vhcr *vhcr,
1070 struct mlx4_cmd_mailbox *inbox,
1071 struct mlx4_cmd_mailbox *outbox,
1072 struct mlx4_cmd_info *cmd);
1073 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
1074 struct mlx4_vhcr *vhcr,
1075 struct mlx4_cmd_mailbox *inbox,
1076 struct mlx4_cmd_mailbox *outbox,
1077 struct mlx4_cmd_info *cmd);
1078 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1079 struct mlx4_vhcr *vhcr,
1080 struct mlx4_cmd_mailbox *inbox,
1081 struct mlx4_cmd_mailbox *outbox,
1082 struct mlx4_cmd_info *cmd);
1083 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1084 struct mlx4_vhcr *vhcr,
1085 struct mlx4_cmd_mailbox *inbox,
1086 struct mlx4_cmd_mailbox *outbox,
1087 struct mlx4_cmd_info *cmd);
1088 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1089 struct mlx4_vhcr *vhcr,
1090 struct mlx4_cmd_mailbox *inbox,
1091 struct mlx4_cmd_mailbox *outbox,
1092 struct mlx4_cmd_info *cmd);
1093 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave,
1094 struct mlx4_vhcr *vhcr,
1095 struct mlx4_cmd_mailbox *inbox,
1096 struct mlx4_cmd_mailbox *outbox,
1097 struct mlx4_cmd_info *cmd);
1098 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1099 struct mlx4_vhcr *vhcr,
1100 struct mlx4_cmd_mailbox *inbox,
1101 struct mlx4_cmd_mailbox *outbox,
1102 struct mlx4_cmd_info *cmd);
1103 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1104 struct mlx4_vhcr *vhcr,
1105 struct mlx4_cmd_mailbox *inbox,
1106 struct mlx4_cmd_mailbox *outbox,
1107 struct mlx4_cmd_info *cmd);
1108 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1109 struct mlx4_vhcr *vhcr,
1110 struct mlx4_cmd_mailbox *inbox,
1111 struct mlx4_cmd_mailbox *outbox,
1112 struct mlx4_cmd_info *cmd);
1113 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1114 struct mlx4_vhcr *vhcr,
1115 struct mlx4_cmd_mailbox *inbox,
1116 struct mlx4_cmd_mailbox *outbox,
1117 struct mlx4_cmd_info *cmd);
1118 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave,
1119 struct mlx4_vhcr *vhcr,
1120 struct mlx4_cmd_mailbox *inbox,
1121 struct mlx4_cmd_mailbox *outbox,
1122 struct mlx4_cmd_info *cmd);
1124 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
1126 int mlx4_cmd_init(struct mlx4_dev *dev);
1127 void mlx4_cmd_cleanup(struct mlx4_dev *dev);
1128 int mlx4_multi_func_init(struct mlx4_dev *dev);
1129 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
1130 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1131 int mlx4_cmd_use_events(struct mlx4_dev *dev);
1132 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1134 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1135 unsigned long timeout);
1137 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1138 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1140 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1142 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1144 void mlx4_handle_catas_err(struct mlx4_dev *dev);
1146 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1147 enum mlx4_port_type *type);
1148 void mlx4_do_sense_ports(struct mlx4_dev *dev,
1149 enum mlx4_port_type *stype,
1150 enum mlx4_port_type *defaults);
1151 void mlx4_start_sense(struct mlx4_dev *dev);
1152 void mlx4_stop_sense(struct mlx4_dev *dev);
1153 void mlx4_sense_init(struct mlx4_dev *dev);
1154 int mlx4_check_port_params(struct mlx4_dev *dev,
1155 enum mlx4_port_type *port_type);
1156 int mlx4_change_port_types(struct mlx4_dev *dev,
1157 enum mlx4_port_type *port_types);
1159 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1160 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1161 void mlx4_init_roce_gid_table(struct mlx4_dev *dev,
1162 struct mlx4_roce_gid_table *table);
1163 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1164 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1166 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz);
1167 /* resource tracker functions*/
1168 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1169 enum mlx4_resource resource_type,
1170 u64 resource_id, int *slave);
1171 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1172 void mlx4_reset_roce_gids(struct mlx4_dev *dev, int slave);
1173 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1175 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1176 enum mlx4_res_tracker_free_type type);
1178 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1179 struct mlx4_vhcr *vhcr,
1180 struct mlx4_cmd_mailbox *inbox,
1181 struct mlx4_cmd_mailbox *outbox,
1182 struct mlx4_cmd_info *cmd);
1183 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1184 struct mlx4_vhcr *vhcr,
1185 struct mlx4_cmd_mailbox *inbox,
1186 struct mlx4_cmd_mailbox *outbox,
1187 struct mlx4_cmd_info *cmd);
1188 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1189 struct mlx4_vhcr *vhcr,
1190 struct mlx4_cmd_mailbox *inbox,
1191 struct mlx4_cmd_mailbox *outbox,
1192 struct mlx4_cmd_info *cmd);
1193 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1194 struct mlx4_vhcr *vhcr,
1195 struct mlx4_cmd_mailbox *inbox,
1196 struct mlx4_cmd_mailbox *outbox,
1197 struct mlx4_cmd_info *cmd);
1198 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1199 struct mlx4_vhcr *vhcr,
1200 struct mlx4_cmd_mailbox *inbox,
1201 struct mlx4_cmd_mailbox *outbox,
1202 struct mlx4_cmd_info *cmd);
1203 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1204 struct mlx4_vhcr *vhcr,
1205 struct mlx4_cmd_mailbox *inbox,
1206 struct mlx4_cmd_mailbox *outbox,
1207 struct mlx4_cmd_info *cmd);
1208 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1210 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1211 int *gid_tbl_len, int *pkey_tbl_len);
1213 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1214 struct mlx4_vhcr *vhcr,
1215 struct mlx4_cmd_mailbox *inbox,
1216 struct mlx4_cmd_mailbox *outbox,
1217 struct mlx4_cmd_info *cmd);
1219 int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave,
1220 struct mlx4_vhcr *vhcr,
1221 struct mlx4_cmd_mailbox *inbox,
1222 struct mlx4_cmd_mailbox *outbox,
1223 struct mlx4_cmd_info *cmd);
1225 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1226 struct mlx4_vhcr *vhcr,
1227 struct mlx4_cmd_mailbox *inbox,
1228 struct mlx4_cmd_mailbox *outbox,
1229 struct mlx4_cmd_info *cmd);
1230 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1231 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1232 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1233 int block_mcast_loopback, enum mlx4_protocol prot,
1234 enum mlx4_steer_type steer);
1235 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1236 u8 gid[16], u8 port,
1237 int block_mcast_loopback,
1238 enum mlx4_protocol prot, u64 *reg_id);
1239 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1240 struct mlx4_vhcr *vhcr,
1241 struct mlx4_cmd_mailbox *inbox,
1242 struct mlx4_cmd_mailbox *outbox,
1243 struct mlx4_cmd_info *cmd);
1244 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1245 struct mlx4_vhcr *vhcr,
1246 struct mlx4_cmd_mailbox *inbox,
1247 struct mlx4_cmd_mailbox *outbox,
1248 struct mlx4_cmd_info *cmd);
1249 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1250 int port, void *buf);
1251 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1252 struct mlx4_cmd_mailbox *outbox);
1253 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1254 struct mlx4_vhcr *vhcr,
1255 struct mlx4_cmd_mailbox *inbox,
1256 struct mlx4_cmd_mailbox *outbox,
1257 struct mlx4_cmd_info *cmd);
1258 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1259 struct mlx4_vhcr *vhcr,
1260 struct mlx4_cmd_mailbox *inbox,
1261 struct mlx4_cmd_mailbox *outbox,
1262 struct mlx4_cmd_info *cmd);
1263 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1264 struct mlx4_vhcr *vhcr,
1265 struct mlx4_cmd_mailbox *inbox,
1266 struct mlx4_cmd_mailbox *outbox,
1267 struct mlx4_cmd_info *cmd);
1268 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1269 struct mlx4_vhcr *vhcr,
1270 struct mlx4_cmd_mailbox *inbox,
1271 struct mlx4_cmd_mailbox *outbox,
1272 struct mlx4_cmd_info *cmd);
1273 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1274 struct mlx4_vhcr *vhcr,
1275 struct mlx4_cmd_mailbox *inbox,
1276 struct mlx4_cmd_mailbox *outbox,
1277 struct mlx4_cmd_info *cmd);
1279 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1280 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1282 static inline void set_param_l(u64 *arg, u32 val)
1284 *arg = (*arg & 0xffffffff00000000ULL) | (u64) val;
1287 static inline void set_param_h(u64 *arg, u32 val)
1289 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1292 static inline u32 get_param_l(u64 *arg)
1294 return (u32) (*arg & 0xffffffff);
1297 static inline u32 get_param_h(u64 *arg)
1299 return (u32)(*arg >> 32);
1302 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1304 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1307 #define NOT_MASKED_PD_BITS 17
1309 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work);
1311 void mlx4_init_quotas(struct mlx4_dev *dev);
1313 int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave, int port);
1314 /* Returns the VF index of slave */
1315 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave);
1316 int mlx4_config_mad_demux(struct mlx4_dev *dev);