2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/mutex.h>
41 #include <linux/radix-tree.h>
42 #include <linux/rbtree.h>
43 #include <linux/timer.h>
44 #include <linux/semaphore.h>
45 #include <linux/workqueue.h>
46 #include <linux/interrupt.h>
47 #include <linux/spinlock.h>
49 #include <linux/mlx4/device.h>
50 #include <linux/mlx4/driver.h>
51 #include <linux/mlx4/doorbell.h>
52 #include <linux/mlx4/cmd.h>
54 #define DRV_NAME "mlx4_core"
55 #define PFX DRV_NAME ": "
56 #define DRV_VERSION "2.2-1"
57 #define DRV_RELDATE "Feb, 2014"
59 #define MLX4_FS_UDP_UC_EN (1 << 1)
60 #define MLX4_FS_TCP_UC_EN (1 << 2)
61 #define MLX4_FS_NUM_OF_L2_ADDR 8
62 #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7
63 #define MLX4_FS_NUM_MCG (1 << 17)
65 #define INIT_HCA_TPT_MW_ENABLE (1 << 7)
67 struct mlx4_set_port_prio2tc_context {
71 struct mlx4_port_scheduler_tc_cfg_be {
74 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
78 struct mlx4_set_port_scheduler_context {
79 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
83 MLX4_HCR_BASE = 0x80680,
84 MLX4_HCR_SIZE = 0x0001c,
85 MLX4_CLR_INT_SIZE = 0x00008,
86 MLX4_SLAVE_COMM_BASE = 0x0,
87 MLX4_COMM_PAGESIZE = 0x1000,
88 MLX4_CLOCK_SIZE = 0x00008,
89 MLX4_COMM_CHAN_CAPS = 0x8,
90 MLX4_COMM_CHAN_FLAGS = 0xc
94 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10,
95 MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7,
96 MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12,
97 MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2),
98 MLX4_MTT_ENTRY_PER_SEG = 8,
102 MLX4_NUM_PDS = 1 << 15
106 MLX4_CMPT_TYPE_QP = 0,
107 MLX4_CMPT_TYPE_SRQ = 1,
108 MLX4_CMPT_TYPE_CQ = 2,
109 MLX4_CMPT_TYPE_EQ = 3,
114 MLX4_CMPT_SHIFT = 24,
115 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
118 enum mlx4_mpt_state {
119 MLX4_MPT_DISABLED = 0,
124 #define MLX4_COMM_TIME 10000
125 #define MLX4_COMM_OFFLINE_TIME_OUT 30000
132 MLX4_COMM_CMD_VHCR_EN,
133 MLX4_COMM_CMD_VHCR_POST,
134 MLX4_COMM_CMD_FLR = 254
138 MLX4_VF_SMI_DISABLED,
142 /*The flag indicates that the slave should delay the RESET cmd*/
143 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
144 /*indicates how many retries will be done if we are in the middle of FLR*/
145 #define NUM_OF_RESET_RETRIES 10
146 #define SLEEP_TIME_IN_RESET (2 * 1000)
159 MLX4_NUM_OF_RESOURCE_TYPE
162 enum mlx4_alloc_mode {
164 RES_OP_RESERVE_AND_MAP,
168 enum mlx4_res_tracker_free_type {
170 RES_TR_FREE_SLAVES_ONLY,
171 RES_TR_FREE_STRUCTS_ONLY,
175 *Virtual HCR structures.
176 * mlx4_vhcr is the sw representation, in machine endianess
178 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
179 * to FW to go through communication channel.
180 * It is big endian, and has the same structure as the physical HCR
181 * used by command interface
194 struct mlx4_vhcr_cmd {
205 struct mlx4_cmd_info {
210 bool encode_slave_id;
211 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
212 struct mlx4_cmd_mailbox *inbox);
213 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
214 struct mlx4_cmd_mailbox *inbox,
215 struct mlx4_cmd_mailbox *outbox,
216 struct mlx4_cmd_info *cmd);
219 #ifdef CONFIG_MLX4_DEBUG
220 extern int mlx4_debug_level;
221 #else /* CONFIG_MLX4_DEBUG */
222 #define mlx4_debug_level (0)
223 #endif /* CONFIG_MLX4_DEBUG */
225 #define mlx4_dbg(mdev, format, ...) \
227 if (mlx4_debug_level) \
228 dev_printk(KERN_DEBUG, \
229 &(mdev)->persist->pdev->dev, format, \
233 #define mlx4_err(mdev, format, ...) \
234 dev_err(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__)
235 #define mlx4_info(mdev, format, ...) \
236 dev_info(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__)
237 #define mlx4_warn(mdev, format, ...) \
238 dev_warn(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__)
240 extern int mlx4_log_num_mgm_entry_size;
241 extern int log_mtts_per_seg;
242 extern int mlx4_internal_err_reset;
244 #define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
245 #define ALL_SLAVES 0xff
256 unsigned long *table;
260 unsigned long **bits;
261 unsigned int *num_free;
268 struct mlx4_icm_table {
276 struct mlx4_icm **icm;
279 #define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28)
280 #define MLX4_MPT_FLAG_FREE (0x3UL << 28)
281 #define MLX4_MPT_FLAG_MIO (1 << 17)
282 #define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15)
283 #define MLX4_MPT_FLAG_PHYSICAL (1 << 9)
284 #define MLX4_MPT_FLAG_REGION (1 << 8)
286 #define MLX4_MPT_PD_MASK (0x1FFFFUL)
287 #define MLX4_MPT_PD_VF_MASK (0xFE0000UL)
288 #define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27)
289 #define MLX4_MPT_PD_FLAG_RAE (1 << 28)
290 #define MLX4_MPT_PD_FLAG_EN_INV (3 << 24)
292 #define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7)
294 #define MLX4_MPT_STATUS_SW 0xF0
295 #define MLX4_MPT_STATUS_HW 0x00
297 #define MLX4_CQE_SIZE_MASK_STRIDE 0x3
298 #define MLX4_EQE_SIZE_MASK_STRIDE 0x30
301 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
303 struct mlx4_mpt_entry {
317 __be32 first_byte_offset;
321 * Must be packed because start is 64 bits but only aligned to 32 bits.
323 struct mlx4_eq_context {
337 __be32 mtt_base_addr_l;
339 __be32 consumer_index;
340 __be32 producer_index;
344 struct mlx4_cq_context {
348 __be32 logsize_usrpage;
356 __be32 mtt_base_addr_l;
357 __be32 last_notified_index;
358 __be32 solicit_producer_index;
359 __be32 consumer_index;
360 __be32 producer_index;
365 struct mlx4_srq_context {
366 __be32 state_logsize_srqn;
370 __be32 pg_offset_cqn;
375 __be32 mtt_base_addr_l;
377 __be16 limit_watermark;
385 struct mlx4_eq_tasklet {
386 struct list_head list;
387 struct list_head process_list;
388 struct tasklet_struct task;
389 /* lock on completion tasklet list */
394 struct mlx4_dev *dev;
395 void __iomem *doorbell;
401 struct mlx4_buf_list *page_list;
403 struct mlx4_eq_tasklet tasklet_ctx;
406 struct mlx4_slave_eqe {
412 struct mlx4_slave_event_eq_info {
417 struct mlx4_profile {
432 struct mlx4_icm *fw_icm;
433 struct mlx4_icm *aux_icm;
448 MLX4_MCAST_CONFIG = 0,
449 MLX4_MCAST_DISABLE = 1,
450 MLX4_MCAST_ENABLE = 2,
453 #define VLAN_FLTR_SIZE 128
455 struct mlx4_vlan_fltr {
456 __be32 entry[VLAN_FLTR_SIZE];
459 struct mlx4_mcast_entry {
460 struct list_head list;
464 struct mlx4_promisc_qp {
465 struct list_head list;
469 struct mlx4_steer_index {
470 struct list_head list;
472 struct list_head duplicates;
475 #define MLX4_EVENT_TYPES_NUM 64
477 struct mlx4_slave_state {
485 u16 mtu[MLX4_MAX_PORTS + 1];
486 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
487 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
488 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
489 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
490 /* event type to eq number lookup */
491 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
495 /*initialized via the kzalloc*/
496 u8 is_slave_going_down;
498 enum slave_port_state port_state[MLX4_MAX_PORTS + 1];
501 #define MLX4_VGT 4095
504 struct mlx4_vport_state {
513 struct mlx4_vf_admin_state {
514 struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1];
515 u8 enable_smi[MLX4_MAX_PORTS + 1];
518 struct mlx4_vport_oper_state {
519 struct mlx4_vport_state state;
524 struct mlx4_vf_oper_state {
525 struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1];
526 u8 smi_enabled[MLX4_MAX_PORTS + 1];
531 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
534 struct resource_allocator {
535 spinlock_t alloc_lock; /* protect quotas */
538 int res_port_rsvd[MLX4_MAX_PORTS];
542 int res_port_free[MLX4_MAX_PORTS];
549 struct mlx4_resource_tracker {
551 /* tree for each resources */
552 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
553 /* num_of_slave's lists, one per slave */
554 struct slave_list *slave_list;
555 struct resource_allocator res_alloc[MLX4_NUM_OF_RESOURCE_TYPE];
558 #define SLAVE_EVENT_EQ_SIZE 128
559 struct mlx4_slave_event_eq {
563 spinlock_t event_lock;
564 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
567 struct mlx4_master_qp0_state {
568 int proxy_qp0_active;
573 struct mlx4_mfunc_master_ctx {
574 struct mlx4_slave_state *slave_state;
575 struct mlx4_vf_admin_state *vf_admin;
576 struct mlx4_vf_oper_state *vf_oper;
577 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
578 int init_port_ref[MLX4_MAX_PORTS + 1];
579 u16 max_mtu[MLX4_MAX_PORTS + 1];
580 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
581 struct mlx4_resource_tracker res_tracker;
582 struct workqueue_struct *comm_wq;
583 struct work_struct comm_work;
584 struct work_struct slave_event_work;
585 struct work_struct slave_flr_event_work;
586 spinlock_t slave_state_lock;
587 __be32 comm_arm_bit_vector[4];
588 struct mlx4_eqe cmd_eqe;
589 struct mlx4_slave_event_eq slave_eq;
590 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
594 struct mlx4_comm __iomem *comm;
595 struct mlx4_vhcr_cmd *vhcr;
598 struct mlx4_mfunc_master_ctx master;
601 #define MGM_QPN_MASK 0x00FFFFFF
602 #define MGM_BLCK_LB_BIT 30
605 __be32 next_gid_index;
606 __be32 members_count;
609 __be32 qp[MLX4_MAX_QP_PER_MGM];
613 struct pci_pool *pool;
615 struct mutex slave_cmd_mutex;
616 struct semaphore poll_sem;
617 struct semaphore event_sem;
619 spinlock_t context_lock;
621 struct mlx4_cmd_context *context;
630 MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0,
631 MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1,
632 MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE = 1 << 2,
634 struct mlx4_vf_immed_vlan_work {
635 struct work_struct work;
636 struct mlx4_priv *priv;
648 struct mlx4_uar_table {
649 struct mlx4_bitmap bitmap;
652 struct mlx4_mr_table {
653 struct mlx4_bitmap mpt_bitmap;
654 struct mlx4_buddy mtt_buddy;
657 struct mlx4_icm_table mtt_table;
658 struct mlx4_icm_table dmpt_table;
661 struct mlx4_cq_table {
662 struct mlx4_bitmap bitmap;
664 struct radix_tree_root tree;
665 struct mlx4_icm_table table;
666 struct mlx4_icm_table cmpt_table;
669 struct mlx4_eq_table {
670 struct mlx4_bitmap bitmap;
672 void __iomem *clr_int;
673 void __iomem **uar_map;
676 struct mlx4_icm_table table;
677 struct mlx4_icm_table cmpt_table;
682 struct mlx4_srq_table {
683 struct mlx4_bitmap bitmap;
685 struct radix_tree_root tree;
686 struct mlx4_icm_table table;
687 struct mlx4_icm_table cmpt_table;
690 enum mlx4_qp_table_zones {
691 MLX4_QP_TABLE_ZONE_GENERAL,
692 MLX4_QP_TABLE_ZONE_RSS,
693 MLX4_QP_TABLE_ZONE_RAW_ETH,
694 MLX4_QP_TABLE_ZONE_NUM
697 struct mlx4_qp_table {
698 struct mlx4_bitmap *bitmap_gen;
699 struct mlx4_zone_allocator *zones;
700 u32 zones_uids[MLX4_QP_TABLE_ZONE_NUM];
704 struct mlx4_icm_table qp_table;
705 struct mlx4_icm_table auxc_table;
706 struct mlx4_icm_table altc_table;
707 struct mlx4_icm_table rdmarc_table;
708 struct mlx4_icm_table cmpt_table;
711 struct mlx4_mcg_table {
713 struct mlx4_bitmap bitmap;
714 struct mlx4_icm_table table;
717 struct mlx4_catas_err {
719 struct timer_list timer;
720 struct list_head list;
723 #define MLX4_MAX_MAC_NUM 128
724 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
726 struct mlx4_mac_table {
727 __be64 entries[MLX4_MAX_MAC_NUM];
728 int refs[MLX4_MAX_MAC_NUM];
734 #define MLX4_ROCE_GID_ENTRY_SIZE 16
736 struct mlx4_roce_gid_entry {
737 u8 raw[MLX4_ROCE_GID_ENTRY_SIZE];
740 struct mlx4_roce_gid_table {
741 struct mlx4_roce_gid_entry roce_gids[MLX4_ROCE_MAX_GIDS];
745 #define MLX4_MAX_VLAN_NUM 128
746 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
748 struct mlx4_vlan_table {
749 __be32 entries[MLX4_MAX_VLAN_NUM];
750 int refs[MLX4_MAX_VLAN_NUM];
756 #define SET_PORT_GEN_ALL_VALID 0x7
757 #define SET_PORT_PROMISC_SHIFT 31
758 #define SET_PORT_MC_PROMISC_SHIFT 30
761 MCAST_DIRECT_ONLY = 0,
767 struct mlx4_set_port_general_context {
780 struct mlx4_set_port_rqp_calc_context {
798 struct mlx4_port_info {
799 struct mlx4_dev *dev;
802 struct device_attribute port_attr;
803 enum mlx4_port_type tmp_type;
804 char dev_mtu_name[16];
805 struct device_attribute port_mtu_attr;
806 struct mlx4_mac_table mac_table;
807 struct mlx4_vlan_table vlan_table;
808 struct mlx4_roce_gid_table gid_table;
813 struct mlx4_dev *dev;
814 u8 do_sense_port[MLX4_MAX_PORTS + 1];
815 u8 sense_allowed[MLX4_MAX_PORTS + 1];
816 struct delayed_work sense_poll;
819 struct mlx4_msix_ctl {
821 struct mutex pool_lock;
825 struct list_head promisc_qps[MLX4_NUM_STEERS];
826 struct list_head steer_entries[MLX4_NUM_STEERS];
830 MLX4_PCI_DEV_IS_VF = 1 << 0,
831 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1,
842 struct list_head dev_list;
843 struct list_head ctx_list;
849 struct list_head pgdir_list;
850 struct mutex pgdir_mutex;
854 struct mlx4_mfunc mfunc;
856 struct mlx4_bitmap pd_bitmap;
857 struct mlx4_bitmap xrcd_bitmap;
858 struct mlx4_uar_table uar_table;
859 struct mlx4_mr_table mr_table;
860 struct mlx4_cq_table cq_table;
861 struct mlx4_eq_table eq_table;
862 struct mlx4_srq_table srq_table;
863 struct mlx4_qp_table qp_table;
864 struct mlx4_mcg_table mcg_table;
865 struct mlx4_bitmap counters_bitmap;
867 struct mlx4_catas_err catas_err;
869 void __iomem *clr_base;
871 struct mlx4_uar driver_uar;
873 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
874 struct mlx4_sense sense;
875 struct mutex port_mutex;
876 struct mlx4_msix_ctl msix_ctl;
877 struct mlx4_steer *steer;
878 struct list_head bf_list;
879 struct mutex bf_mutex;
880 struct io_mapping *bf_mapping;
881 void __iomem *clock_mapping;
884 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
885 __be64 slave_node_guids[MLX4_MFUNC_MAX];
887 atomic_t opreq_count;
888 struct work_struct opreq_task;
891 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
893 return container_of(dev, struct mlx4_priv, dev);
896 #define MLX4_SENSE_RANGE (HZ * 3)
898 extern struct workqueue_struct *mlx4_wq;
900 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
901 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj, int use_rr);
902 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt,
903 int align, u32 skip_mask);
904 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt,
906 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
907 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
908 u32 reserved_bot, u32 resetrved_top);
909 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
911 int mlx4_reset(struct mlx4_dev *dev);
913 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
914 void mlx4_free_eq_table(struct mlx4_dev *dev);
916 int mlx4_init_pd_table(struct mlx4_dev *dev);
917 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
918 int mlx4_init_uar_table(struct mlx4_dev *dev);
919 int mlx4_init_mr_table(struct mlx4_dev *dev);
920 int mlx4_init_eq_table(struct mlx4_dev *dev);
921 int mlx4_init_cq_table(struct mlx4_dev *dev);
922 int mlx4_init_qp_table(struct mlx4_dev *dev);
923 int mlx4_init_srq_table(struct mlx4_dev *dev);
924 int mlx4_init_mcg_table(struct mlx4_dev *dev);
926 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
927 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
928 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
929 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
930 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
931 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
932 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
933 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
934 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
935 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn, gfp_t gfp);
936 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
937 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
938 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
939 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
940 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
941 int __mlx4_mpt_reserve(struct mlx4_dev *dev);
942 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index);
943 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index, gfp_t gfp);
944 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index);
945 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
946 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
948 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
949 struct mlx4_vhcr *vhcr,
950 struct mlx4_cmd_mailbox *inbox,
951 struct mlx4_cmd_mailbox *outbox,
952 struct mlx4_cmd_info *cmd);
953 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
954 struct mlx4_vhcr *vhcr,
955 struct mlx4_cmd_mailbox *inbox,
956 struct mlx4_cmd_mailbox *outbox,
957 struct mlx4_cmd_info *cmd);
958 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
959 struct mlx4_vhcr *vhcr,
960 struct mlx4_cmd_mailbox *inbox,
961 struct mlx4_cmd_mailbox *outbox,
962 struct mlx4_cmd_info *cmd);
963 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
964 struct mlx4_vhcr *vhcr,
965 struct mlx4_cmd_mailbox *inbox,
966 struct mlx4_cmd_mailbox *outbox,
967 struct mlx4_cmd_info *cmd);
968 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
969 struct mlx4_vhcr *vhcr,
970 struct mlx4_cmd_mailbox *inbox,
971 struct mlx4_cmd_mailbox *outbox,
972 struct mlx4_cmd_info *cmd);
973 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
974 struct mlx4_vhcr *vhcr,
975 struct mlx4_cmd_mailbox *inbox,
976 struct mlx4_cmd_mailbox *outbox,
977 struct mlx4_cmd_info *cmd);
978 int mlx4_CONFIG_DEV_wrapper(struct mlx4_dev *dev, int slave,
979 struct mlx4_vhcr *vhcr,
980 struct mlx4_cmd_mailbox *inbox,
981 struct mlx4_cmd_mailbox *outbox,
982 struct mlx4_cmd_info *cmd);
983 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
984 struct mlx4_vhcr *vhcr,
985 struct mlx4_cmd_mailbox *inbox,
986 struct mlx4_cmd_mailbox *outbox,
987 struct mlx4_cmd_info *cmd);
988 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
989 int *base, u8 flags);
990 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
991 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
992 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
993 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
994 int start_index, int npages, u64 *page_list);
995 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
996 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
997 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
998 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
1000 void mlx4_start_catas_poll(struct mlx4_dev *dev);
1001 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
1002 int mlx4_catas_init(struct mlx4_dev *dev);
1003 void mlx4_catas_end(struct mlx4_dev *dev);
1004 int mlx4_restart_one(struct pci_dev *pdev);
1005 int mlx4_register_device(struct mlx4_dev *dev);
1006 void mlx4_unregister_device(struct mlx4_dev *dev);
1007 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
1008 unsigned long param);
1010 struct mlx4_dev_cap;
1011 struct mlx4_init_hca_param;
1013 u64 mlx4_make_profile(struct mlx4_dev *dev,
1014 struct mlx4_profile *request,
1015 struct mlx4_dev_cap *dev_cap,
1016 struct mlx4_init_hca_param *init_hca);
1017 void mlx4_master_comm_channel(struct work_struct *work);
1018 void mlx4_gen_slave_eqe(struct work_struct *work);
1019 void mlx4_master_handle_slave_flr(struct work_struct *work);
1021 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
1022 struct mlx4_vhcr *vhcr,
1023 struct mlx4_cmd_mailbox *inbox,
1024 struct mlx4_cmd_mailbox *outbox,
1025 struct mlx4_cmd_info *cmd);
1026 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
1027 struct mlx4_vhcr *vhcr,
1028 struct mlx4_cmd_mailbox *inbox,
1029 struct mlx4_cmd_mailbox *outbox,
1030 struct mlx4_cmd_info *cmd);
1031 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
1032 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
1033 struct mlx4_cmd_mailbox *outbox,
1034 struct mlx4_cmd_info *cmd);
1035 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
1036 struct mlx4_vhcr *vhcr,
1037 struct mlx4_cmd_mailbox *inbox,
1038 struct mlx4_cmd_mailbox *outbox,
1039 struct mlx4_cmd_info *cmd);
1040 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
1041 struct mlx4_vhcr *vhcr,
1042 struct mlx4_cmd_mailbox *inbox,
1043 struct mlx4_cmd_mailbox *outbox,
1044 struct mlx4_cmd_info *cmd);
1045 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
1046 struct mlx4_vhcr *vhcr,
1047 struct mlx4_cmd_mailbox *inbox,
1048 struct mlx4_cmd_mailbox *outbox,
1049 struct mlx4_cmd_info *cmd);
1050 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1051 struct mlx4_vhcr *vhcr,
1052 struct mlx4_cmd_mailbox *inbox,
1053 struct mlx4_cmd_mailbox *outbox,
1054 struct mlx4_cmd_info *cmd);
1055 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1056 struct mlx4_vhcr *vhcr,
1057 struct mlx4_cmd_mailbox *inbox,
1058 struct mlx4_cmd_mailbox *outbox,
1059 struct mlx4_cmd_info *cmd);
1060 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1061 struct mlx4_vhcr *vhcr,
1062 struct mlx4_cmd_mailbox *inbox,
1063 struct mlx4_cmd_mailbox *outbox,
1064 struct mlx4_cmd_info *cmd);
1065 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1066 struct mlx4_vhcr *vhcr,
1067 struct mlx4_cmd_mailbox *inbox,
1068 struct mlx4_cmd_mailbox *outbox,
1069 struct mlx4_cmd_info *cmd);
1070 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1071 struct mlx4_vhcr *vhcr,
1072 struct mlx4_cmd_mailbox *inbox,
1073 struct mlx4_cmd_mailbox *outbox,
1074 struct mlx4_cmd_info *cmd);
1075 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1076 struct mlx4_vhcr *vhcr,
1077 struct mlx4_cmd_mailbox *inbox,
1078 struct mlx4_cmd_mailbox *outbox,
1079 struct mlx4_cmd_info *cmd);
1080 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1081 struct mlx4_vhcr *vhcr,
1082 struct mlx4_cmd_mailbox *inbox,
1083 struct mlx4_cmd_mailbox *outbox,
1084 struct mlx4_cmd_info *cmd);
1085 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1086 struct mlx4_vhcr *vhcr,
1087 struct mlx4_cmd_mailbox *inbox,
1088 struct mlx4_cmd_mailbox *outbox,
1089 struct mlx4_cmd_info *cmd);
1090 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
1091 struct mlx4_vhcr *vhcr,
1092 struct mlx4_cmd_mailbox *inbox,
1093 struct mlx4_cmd_mailbox *outbox,
1094 struct mlx4_cmd_info *cmd);
1095 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1096 struct mlx4_vhcr *vhcr,
1097 struct mlx4_cmd_mailbox *inbox,
1098 struct mlx4_cmd_mailbox *outbox,
1099 struct mlx4_cmd_info *cmd);
1100 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1101 struct mlx4_vhcr *vhcr,
1102 struct mlx4_cmd_mailbox *inbox,
1103 struct mlx4_cmd_mailbox *outbox,
1104 struct mlx4_cmd_info *cmd);
1105 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
1106 struct mlx4_vhcr *vhcr,
1107 struct mlx4_cmd_mailbox *inbox,
1108 struct mlx4_cmd_mailbox *outbox,
1109 struct mlx4_cmd_info *cmd);
1110 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1111 struct mlx4_vhcr *vhcr,
1112 struct mlx4_cmd_mailbox *inbox,
1113 struct mlx4_cmd_mailbox *outbox,
1114 struct mlx4_cmd_info *cmd);
1115 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1116 struct mlx4_vhcr *vhcr,
1117 struct mlx4_cmd_mailbox *inbox,
1118 struct mlx4_cmd_mailbox *outbox,
1119 struct mlx4_cmd_info *cmd);
1120 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1121 struct mlx4_vhcr *vhcr,
1122 struct mlx4_cmd_mailbox *inbox,
1123 struct mlx4_cmd_mailbox *outbox,
1124 struct mlx4_cmd_info *cmd);
1125 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave,
1126 struct mlx4_vhcr *vhcr,
1127 struct mlx4_cmd_mailbox *inbox,
1128 struct mlx4_cmd_mailbox *outbox,
1129 struct mlx4_cmd_info *cmd);
1130 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1131 struct mlx4_vhcr *vhcr,
1132 struct mlx4_cmd_mailbox *inbox,
1133 struct mlx4_cmd_mailbox *outbox,
1134 struct mlx4_cmd_info *cmd);
1135 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1136 struct mlx4_vhcr *vhcr,
1137 struct mlx4_cmd_mailbox *inbox,
1138 struct mlx4_cmd_mailbox *outbox,
1139 struct mlx4_cmd_info *cmd);
1140 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1141 struct mlx4_vhcr *vhcr,
1142 struct mlx4_cmd_mailbox *inbox,
1143 struct mlx4_cmd_mailbox *outbox,
1144 struct mlx4_cmd_info *cmd);
1145 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1146 struct mlx4_vhcr *vhcr,
1147 struct mlx4_cmd_mailbox *inbox,
1148 struct mlx4_cmd_mailbox *outbox,
1149 struct mlx4_cmd_info *cmd);
1150 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave,
1151 struct mlx4_vhcr *vhcr,
1152 struct mlx4_cmd_mailbox *inbox,
1153 struct mlx4_cmd_mailbox *outbox,
1154 struct mlx4_cmd_info *cmd);
1156 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
1159 MLX4_CMD_CLEANUP_STRUCT = 1UL << 0,
1160 MLX4_CMD_CLEANUP_POOL = 1UL << 1,
1161 MLX4_CMD_CLEANUP_HCR = 1UL << 2,
1162 MLX4_CMD_CLEANUP_VHCR = 1UL << 3,
1163 MLX4_CMD_CLEANUP_ALL = (MLX4_CMD_CLEANUP_VHCR << 1) - 1
1166 int mlx4_cmd_init(struct mlx4_dev *dev);
1167 void mlx4_cmd_cleanup(struct mlx4_dev *dev, int cleanup_mask);
1168 int mlx4_multi_func_init(struct mlx4_dev *dev);
1169 int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev);
1170 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
1171 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1172 int mlx4_cmd_use_events(struct mlx4_dev *dev);
1173 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1175 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1176 unsigned long timeout);
1178 void mlx4_cq_tasklet_cb(unsigned long data);
1179 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1180 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1182 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1184 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1186 void mlx4_enter_error_state(struct mlx4_dev_persistent *persist);
1188 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1189 enum mlx4_port_type *type);
1190 void mlx4_do_sense_ports(struct mlx4_dev *dev,
1191 enum mlx4_port_type *stype,
1192 enum mlx4_port_type *defaults);
1193 void mlx4_start_sense(struct mlx4_dev *dev);
1194 void mlx4_stop_sense(struct mlx4_dev *dev);
1195 void mlx4_sense_init(struct mlx4_dev *dev);
1196 int mlx4_check_port_params(struct mlx4_dev *dev,
1197 enum mlx4_port_type *port_type);
1198 int mlx4_change_port_types(struct mlx4_dev *dev,
1199 enum mlx4_port_type *port_types);
1201 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1202 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1203 void mlx4_init_roce_gid_table(struct mlx4_dev *dev,
1204 struct mlx4_roce_gid_table *table);
1205 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1206 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1208 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz);
1209 /* resource tracker functions*/
1210 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1211 enum mlx4_resource resource_type,
1212 u64 resource_id, int *slave);
1213 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1214 void mlx4_reset_roce_gids(struct mlx4_dev *dev, int slave);
1215 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1217 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1218 enum mlx4_res_tracker_free_type type);
1220 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1221 struct mlx4_vhcr *vhcr,
1222 struct mlx4_cmd_mailbox *inbox,
1223 struct mlx4_cmd_mailbox *outbox,
1224 struct mlx4_cmd_info *cmd);
1225 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1226 struct mlx4_vhcr *vhcr,
1227 struct mlx4_cmd_mailbox *inbox,
1228 struct mlx4_cmd_mailbox *outbox,
1229 struct mlx4_cmd_info *cmd);
1230 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1231 struct mlx4_vhcr *vhcr,
1232 struct mlx4_cmd_mailbox *inbox,
1233 struct mlx4_cmd_mailbox *outbox,
1234 struct mlx4_cmd_info *cmd);
1235 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1236 struct mlx4_vhcr *vhcr,
1237 struct mlx4_cmd_mailbox *inbox,
1238 struct mlx4_cmd_mailbox *outbox,
1239 struct mlx4_cmd_info *cmd);
1240 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1241 struct mlx4_vhcr *vhcr,
1242 struct mlx4_cmd_mailbox *inbox,
1243 struct mlx4_cmd_mailbox *outbox,
1244 struct mlx4_cmd_info *cmd);
1245 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1246 struct mlx4_vhcr *vhcr,
1247 struct mlx4_cmd_mailbox *inbox,
1248 struct mlx4_cmd_mailbox *outbox,
1249 struct mlx4_cmd_info *cmd);
1250 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1252 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1253 int *gid_tbl_len, int *pkey_tbl_len);
1255 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1256 struct mlx4_vhcr *vhcr,
1257 struct mlx4_cmd_mailbox *inbox,
1258 struct mlx4_cmd_mailbox *outbox,
1259 struct mlx4_cmd_info *cmd);
1261 int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave,
1262 struct mlx4_vhcr *vhcr,
1263 struct mlx4_cmd_mailbox *inbox,
1264 struct mlx4_cmd_mailbox *outbox,
1265 struct mlx4_cmd_info *cmd);
1267 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1268 struct mlx4_vhcr *vhcr,
1269 struct mlx4_cmd_mailbox *inbox,
1270 struct mlx4_cmd_mailbox *outbox,
1271 struct mlx4_cmd_info *cmd);
1272 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1273 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1274 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1275 int block_mcast_loopback, enum mlx4_protocol prot,
1276 enum mlx4_steer_type steer);
1277 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1278 u8 gid[16], u8 port,
1279 int block_mcast_loopback,
1280 enum mlx4_protocol prot, u64 *reg_id);
1281 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1282 struct mlx4_vhcr *vhcr,
1283 struct mlx4_cmd_mailbox *inbox,
1284 struct mlx4_cmd_mailbox *outbox,
1285 struct mlx4_cmd_info *cmd);
1286 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1287 struct mlx4_vhcr *vhcr,
1288 struct mlx4_cmd_mailbox *inbox,
1289 struct mlx4_cmd_mailbox *outbox,
1290 struct mlx4_cmd_info *cmd);
1291 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1292 int port, void *buf);
1293 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1294 struct mlx4_cmd_mailbox *outbox);
1295 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1296 struct mlx4_vhcr *vhcr,
1297 struct mlx4_cmd_mailbox *inbox,
1298 struct mlx4_cmd_mailbox *outbox,
1299 struct mlx4_cmd_info *cmd);
1300 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1301 struct mlx4_vhcr *vhcr,
1302 struct mlx4_cmd_mailbox *inbox,
1303 struct mlx4_cmd_mailbox *outbox,
1304 struct mlx4_cmd_info *cmd);
1305 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1306 struct mlx4_vhcr *vhcr,
1307 struct mlx4_cmd_mailbox *inbox,
1308 struct mlx4_cmd_mailbox *outbox,
1309 struct mlx4_cmd_info *cmd);
1310 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1311 struct mlx4_vhcr *vhcr,
1312 struct mlx4_cmd_mailbox *inbox,
1313 struct mlx4_cmd_mailbox *outbox,
1314 struct mlx4_cmd_info *cmd);
1315 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1316 struct mlx4_vhcr *vhcr,
1317 struct mlx4_cmd_mailbox *inbox,
1318 struct mlx4_cmd_mailbox *outbox,
1319 struct mlx4_cmd_info *cmd);
1320 int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave,
1321 struct mlx4_vhcr *vhcr,
1322 struct mlx4_cmd_mailbox *inbox,
1323 struct mlx4_cmd_mailbox *outbox,
1324 struct mlx4_cmd_info *cmd);
1326 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1327 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1329 static inline void set_param_l(u64 *arg, u32 val)
1331 *arg = (*arg & 0xffffffff00000000ULL) | (u64) val;
1334 static inline void set_param_h(u64 *arg, u32 val)
1336 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1339 static inline u32 get_param_l(u64 *arg)
1341 return (u32) (*arg & 0xffffffff);
1344 static inline u32 get_param_h(u64 *arg)
1346 return (u32)(*arg >> 32);
1349 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1351 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1354 #define NOT_MASKED_PD_BITS 17
1356 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work);
1358 void mlx4_init_quotas(struct mlx4_dev *dev);
1360 int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave, int port);
1361 /* Returns the VF index of slave */
1362 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave);
1363 int mlx4_config_mad_demux(struct mlx4_dev *dev);
1365 enum mlx4_zone_flags {
1366 MLX4_ZONE_ALLOW_ALLOC_FROM_LOWER_PRIO = 1UL << 0,
1367 MLX4_ZONE_ALLOW_ALLOC_FROM_EQ_PRIO = 1UL << 1,
1368 MLX4_ZONE_FALLBACK_TO_HIGHER_PRIO = 1UL << 2,
1369 MLX4_ZONE_USE_RR = 1UL << 3,
1372 enum mlx4_zone_alloc_flags {
1373 /* No two objects could overlap between zones. UID
1374 * could be left unused. If this flag is given and
1375 * two overlapped zones are used, an object will be free'd
1376 * from the smallest possible matching zone.
1378 MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP = 1UL << 0,
1381 struct mlx4_zone_allocator;
1383 /* Create a new zone allocator */
1384 struct mlx4_zone_allocator *mlx4_zone_allocator_create(enum mlx4_zone_alloc_flags flags);
1386 /* Attach a mlx4_bitmap <bitmap> of priority <priority> to the zone allocator
1387 * <zone_alloc>. Allocating an object from this zone adds an offset <offset>.
1388 * Similarly, when searching for an object to free, this offset it taken into
1389 * account. The use_rr mlx4_ib parameter for allocating objects from this <bitmap>
1390 * is given through the MLX4_ZONE_USE_RR flag in <flags>.
1391 * When an allocation fails, <zone_alloc> tries to allocate from other zones
1392 * according to the policy set by <flags>. <puid> is the unique identifier
1393 * received to this zone.
1395 int mlx4_zone_add_one(struct mlx4_zone_allocator *zone_alloc,
1396 struct mlx4_bitmap *bitmap,
1402 /* Remove bitmap indicated by <uid> from <zone_alloc> */
1403 int mlx4_zone_remove_one(struct mlx4_zone_allocator *zone_alloc, u32 uid);
1405 /* Delete the zone allocator <zone_alloc. This function doesn't destroy
1406 * the attached bitmaps.
1408 void mlx4_zone_allocator_destroy(struct mlx4_zone_allocator *zone_alloc);
1410 /* Allocate <count> objects with align <align> and skip_mask <skip_mask>
1411 * from the mlx4_bitmap whose uid is <uid>. The bitmap which we actually
1412 * allocated from is returned in <puid>. If the allocation fails, a negative
1413 * number is returned. Otherwise, the offset of the first object is returned.
1415 u32 mlx4_zone_alloc_entries(struct mlx4_zone_allocator *zones, u32 uid, int count,
1416 int align, u32 skip_mask, u32 *puid);
1418 /* Free <count> objects, start from <obj> of the uid <uid> from zone_allocator
1421 u32 mlx4_zone_free_entries(struct mlx4_zone_allocator *zones,
1422 u32 uid, u32 obj, u32 count);
1424 /* If <zones> was allocated with MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP, instead of
1425 * specifying the uid when freeing an object, zone allocator could figure it by
1426 * itself. Other parameters are similar to mlx4_zone_free.
1428 u32 mlx4_zone_free_entries_unique(struct mlx4_zone_allocator *zones, u32 obj, u32 count);
1430 /* Returns a pointer to mlx4_bitmap that was attached to <zones> with <uid> */
1431 struct mlx4_bitmap *mlx4_zone_get_bitmap(struct mlx4_zone_allocator *zones, u32 uid);