drivers/net/ethernet/mellanox/mlx4/main.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  */
  35
  36 #include <linux/module.h>
  37 #include <linux/init.h>
  38 #include <linux/errno.h>
  39 #include <linux/pci.h>
  40 #include <linux/dma-mapping.h>
  41 #include <linux/slab.h>
  42 #include <linux/io-mapping.h>
  43 #include <linux/delay.h>
  44 #include <linux/kmod.h>
  45
  46 #include <linux/mlx4/device.h>
  47 #include <linux/mlx4/doorbell.h>
  48
  49 #include "mlx4.h"
  50 #include "fw.h"
  51 #include "icm.h"
  52
  53 MODULE_AUTHOR("Roland Dreier");
  54 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
  55 MODULE_LICENSE("Dual BSD/GPL");
  56 MODULE_VERSION(DRV_VERSION);
  57
  58 struct workqueue_struct *mlx4_wq;
  59
  60 #ifdef CONFIG_MLX4_DEBUG
  61
  62 int mlx4_debug_level = 0;
  63 module_param_named(debug_level, mlx4_debug_level, int, 0644);
  64 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
  65
  66 #endif /* CONFIG_MLX4_DEBUG */
  67
  68 #ifdef CONFIG_PCI_MSI
  69
  70 static int msi_x = 1;
  71 module_param(msi_x, int, 0444);
  72 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  73
  74 #else /* CONFIG_PCI_MSI */
  75
  76 #define msi_x (0)
  77
  78 #endif /* CONFIG_PCI_MSI */
  79
  80 static int num_vfs;
  81 module_param(num_vfs, int, 0444);
  82 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0");
  83
  84 static int probe_vf;
  85 module_param(probe_vf, int, 0644);
  86 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)");
  87
  88 int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
  89 module_param_named(log_num_mgm_entry_size,
  90                         mlx4_log_num_mgm_entry_size, int, 0444);
  91 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
  92                                          " of qp per mcg, for example:"
  93                                          " 10 gives 248.range: 7 <="
  94                                          " log_num_mgm_entry_size <= 12."
  95                                          " To activate device managed"
  96                                          " flow steering when available, set to -1");
  97
  98 static bool enable_64b_cqe_eqe = true;
  99 module_param(enable_64b_cqe_eqe, bool, 0444);
 100 MODULE_PARM_DESC(enable_64b_cqe_eqe,
 101                  "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
 102
 103 #define HCA_GLOBAL_CAP_MASK            0
 104
 105 #define PF_CONTEXT_BEHAVIOUR_MASK       MLX4_FUNC_CAP_64B_EQE_CQE
 106
 107 static char mlx4_version[] =
 108         DRV_NAME ": Mellanox ConnectX core driver v"
 109         DRV_VERSION " (" DRV_RELDATE ")\n";
 110
 111 static struct mlx4_profile default_profile = {
 112         .num_qp         = 1 << 18,
 113         .num_srq        = 1 << 16,
 114         .rdmarc_per_qp  = 1 << 4,
 115         .num_cq         = 1 << 16,
 116         .num_mcg        = 1 << 13,
 117         .num_mpt        = 1 << 19,
 118         .num_mtt        = 1 << 20, /* It is really num mtt segements */
 119 };
 120
 121 static int log_num_mac = 7;
 122 module_param_named(log_num_mac, log_num_mac, int, 0444);
 123 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
 124
 125 static int log_num_vlan;
 126 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
 127 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
 128 /* Log2 max number of VLANs per ETH port (0-7) */
 129 #define MLX4_LOG_NUM_VLANS 7
 130
 131 static bool use_prio;
 132 module_param_named(use_prio, use_prio, bool, 0444);
 133 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
 134                   "(0/1, default 0)");
 135
 136 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
 137 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
 138 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
 139
 140 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
 141 static int arr_argc = 2;
 142 module_param_array(port_type_array, int, &arr_argc, 0444);
 143 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
 144                                 "1 for IB, 2 for Ethernet");
 145
 146 struct mlx4_port_config {
 147         struct list_head list;
 148         enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
 149         struct pci_dev *pdev;
 150 };
 151
 152 int mlx4_check_port_params(struct mlx4_dev *dev,
 153                            enum mlx4_port_type *port_type)
 154 {
 155         int i;
 156
 157         for (i = 0; i < dev->caps.num_ports - 1; i++) {
 158                 if (port_type[i] != port_type[i + 1]) {
 159                         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
 160                                 mlx4_err(dev, "Only same port types supported "
 161                                          "on this HCA, aborting.\n");
 162                                 return -EINVAL;
 163                         }
 164                 }
 165         }
 166
 167         for (i = 0; i < dev->caps.num_ports; i++) {
 168                 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
 169                         mlx4_err(dev, "Requested port type for port %d is not "
 170                                       "supported on this HCA\n", i + 1);
 171                         return -EINVAL;
 172                 }
 173         }
 174         return 0;
 175 }
 176
 177 static void mlx4_set_port_mask(struct mlx4_dev *dev)
 178 {
 179         int i;
 180
 181         for (i = 1; i <= dev->caps.num_ports; ++i)
 182                 dev->caps.port_mask[i] = dev->caps.port_type[i];
 183 }
 184
 185 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
 186 {
 187         int err;
 188         int i;
 189
 190         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
 191         if (err) {
 192                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
 193                 return err;
 194         }
 195
 196         if (dev_cap->min_page_sz > PAGE_SIZE) {
 197                 mlx4_err(dev, "HCA minimum page size of %d bigger than "
 198                          "kernel PAGE_SIZE of %ld, aborting.\n",
 199                          dev_cap->min_page_sz, PAGE_SIZE);
 200                 return -ENODEV;
 201         }
 202         if (dev_cap->num_ports > MLX4_MAX_PORTS) {
 203                 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
 204                          "aborting.\n",
 205                          dev_cap->num_ports, MLX4_MAX_PORTS);
 206                 return -ENODEV;
 207         }
 208
 209         if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
 210                 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
 211                          "PCI resource 2 size of 0x%llx, aborting.\n",
 212                          dev_cap->uar_size,
 213                          (unsigned long long) pci_resource_len(dev->pdev, 2));
 214                 return -ENODEV;
 215         }
 216
 217         dev->caps.num_ports          = dev_cap->num_ports;
 218         dev->phys_caps.num_phys_eqs  = MLX4_MAX_EQ_NUM;
 219         for (i = 1; i <= dev->caps.num_ports; ++i) {
 220                 dev->caps.vl_cap[i]         = dev_cap->max_vl[i];
 221                 dev->caps.ib_mtu_cap[i]     = dev_cap->ib_mtu[i];
 222                 dev->phys_caps.gid_phys_table_len[i]  = dev_cap->max_gids[i];
 223                 dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i];
 224                 /* set gid and pkey table operating lengths by default
 225                  * to non-sriov values */
 226                 dev->caps.gid_table_len[i]  = dev_cap->max_gids[i];
 227                 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
 228                 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
 229                 dev->caps.eth_mtu_cap[i]    = dev_cap->eth_mtu[i];
 230                 dev->caps.def_mac[i]        = dev_cap->def_mac[i];
 231                 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
 232                 dev->caps.suggested_type[i] = dev_cap->suggested_type[i];
 233                 dev->caps.default_sense[i] = dev_cap->default_sense[i];
 234                 dev->caps.trans_type[i]     = dev_cap->trans_type[i];
 235                 dev->caps.vendor_oui[i]     = dev_cap->vendor_oui[i];
 236                 dev->caps.wavelength[i]     = dev_cap->wavelength[i];
 237                 dev->caps.trans_code[i]     = dev_cap->trans_code[i];
 238         }
 239
 240         dev->caps.uar_page_size      = PAGE_SIZE;
 241         dev->caps.num_uars           = dev_cap->uar_size / PAGE_SIZE;
 242         dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
 243         dev->caps.bf_reg_size        = dev_cap->bf_reg_size;
 244         dev->caps.bf_regs_per_page   = dev_cap->bf_regs_per_page;
 245         dev->caps.max_sq_sg          = dev_cap->max_sq_sg;
 246         dev->caps.max_rq_sg          = dev_cap->max_rq_sg;
 247         dev->caps.max_wqes           = dev_cap->max_qp_sz;
 248         dev->caps.max_qp_init_rdma   = dev_cap->max_requester_per_qp;
 249         dev->caps.max_srq_wqes       = dev_cap->max_srq_sz;
 250         dev->caps.max_srq_sge        = dev_cap->max_rq_sg - 1;
 251         dev->caps.reserved_srqs      = dev_cap->reserved_srqs;
 252         dev->caps.max_sq_desc_sz     = dev_cap->max_sq_desc_sz;
 253         dev->caps.max_rq_desc_sz     = dev_cap->max_rq_desc_sz;
 254         /*
 255          * Subtract 1 from the limit because we need to allocate a
 256          * spare CQE so the HCA HW can tell the difference between an
 257          * empty CQ and a full CQ.
 258          */
 259         dev->caps.max_cqes           = dev_cap->max_cq_sz - 1;
 260         dev->caps.reserved_cqs       = dev_cap->reserved_cqs;
 261         dev->caps.reserved_eqs       = dev_cap->reserved_eqs;
 262         dev->caps.reserved_mtts      = dev_cap->reserved_mtts;
 263         dev->caps.reserved_mrws      = dev_cap->reserved_mrws;
 264
 265         /* The first 128 UARs are used for EQ doorbells */
 266         dev->caps.reserved_uars      = max_t(int, 128, dev_cap->reserved_uars);
 267         dev->caps.reserved_pds       = dev_cap->reserved_pds;
 268         dev->caps.reserved_xrcds     = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
 269                                         dev_cap->reserved_xrcds : 0;
 270         dev->caps.max_xrcds          = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
 271                                         dev_cap->max_xrcds : 0;
 272         dev->caps.mtt_entry_sz       = dev_cap->mtt_entry_sz;
 273
 274         dev->caps.max_msg_sz         = dev_cap->max_msg_sz;
 275         dev->caps.page_size_cap      = ~(u32) (dev_cap->min_page_sz - 1);
 276         dev->caps.flags              = dev_cap->flags;
 277         dev->caps.flags2             = dev_cap->flags2;
 278         dev->caps.bmme_flags         = dev_cap->bmme_flags;
 279         dev->caps.reserved_lkey      = dev_cap->reserved_lkey;
 280         dev->caps.stat_rate_support  = dev_cap->stat_rate_support;
 281         dev->caps.max_gso_sz         = dev_cap->max_gso_sz;
 282         dev->caps.max_rss_tbl_sz     = dev_cap->max_rss_tbl_sz;
 283
 284         /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
 285         if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
 286                 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
 287         /* Don't do sense port on multifunction devices (for now at least) */
 288         if (mlx4_is_mfunc(dev))
 289                 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
 290
 291         dev->caps.log_num_macs  = log_num_mac;
 292         dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
 293         dev->caps.log_num_prios = use_prio ? 3 : 0;
 294
 295         for (i = 1; i <= dev->caps.num_ports; ++i) {
 296                 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
 297                 if (dev->caps.supported_type[i]) {
 298                         /* if only ETH is supported - assign ETH */
 299                         if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
 300                                 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
 301                         /* if only IB is supported, assign IB */
 302                         else if (dev->caps.supported_type[i] ==
 303                                  MLX4_PORT_TYPE_IB)
 304                                 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
 305                         else {
 306                                 /* if IB and ETH are supported, we set the port
 307                                  * type according to user selection of port type;
 308                                  * if user selected none, take the FW hint */
 309                                 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
 310                                         dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
 311                                                 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
 312                                 else
 313                                         dev->caps.port_type[i] = port_type_array[i - 1];
 314                         }
 315                 }
 316                 /*
 317                  * Link sensing is allowed on the port if 3 conditions are true:
 318                  * 1. Both protocols are supported on the port.
 319                  * 2. Different types are supported on the port
 320                  * 3. FW declared that it supports link sensing
 321                  */
 322                 mlx4_priv(dev)->sense.sense_allowed[i] =
 323                         ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
 324                          (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
 325                          (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
 326
 327                 /*
 328                  * If "default_sense" bit is set, we move the port to "AUTO" mode
 329                  * and perform sense_port FW command to try and set the correct
 330                  * port type from beginning
 331                  */
 332                 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
 333                         enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
 334                         dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
 335                         mlx4_SENSE_PORT(dev, i, &sensed_port);
 336                         if (sensed_port != MLX4_PORT_TYPE_NONE)
 337                                 dev->caps.port_type[i] = sensed_port;
 338                 } else {
 339                         dev->caps.possible_type[i] = dev->caps.port_type[i];
 340                 }
 341
 342                 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
 343                         dev->caps.log_num_macs = dev_cap->log_max_macs[i];
 344                         mlx4_warn(dev, "Requested number of MACs is too much "
 345                                   "for port %d, reducing to %d.\n",
 346                                   i, 1 << dev->caps.log_num_macs);
 347                 }
 348                 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
 349                         dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
 350                         mlx4_warn(dev, "Requested number of VLANs is too much "
 351                                   "for port %d, reducing to %d.\n",
 352                                   i, 1 << dev->caps.log_num_vlans);
 353                 }
 354         }
 355
 356         dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
 357
 358         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
 359         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
 360                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
 361                 (1 << dev->caps.log_num_macs) *
 362                 (1 << dev->caps.log_num_vlans) *
 363                 (1 << dev->caps.log_num_prios) *
 364                 dev->caps.num_ports;
 365         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
 366
 367         dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
 368                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
 369                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
 370                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
 371
 372         dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
 373
 374         if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
 375                 if (dev_cap->flags &
 376                     (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
 377                         mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
 378                         dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
 379                         dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
 380                 }
 381         }
 382
 383         if ((dev->caps.flags &
 384             (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
 385             mlx4_is_master(dev))
 386                 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
 387
 388         return 0;
 389 }
 390
 391 static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,
 392                                        enum pci_bus_speed *speed,
 393                                        enum pcie_link_width *width)
 394 {
 395         u32 lnkcap1, lnkcap2;
 396         int err1, err2;
 397
 398 #define  PCIE_MLW_CAP_SHIFT 4   /* start of MLW mask in link capabilities */
 399
 400         *speed = PCI_SPEED_UNKNOWN;
 401         *width = PCIE_LNK_WIDTH_UNKNOWN;
 402
 403         err1 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP, &lnkcap1);
 404         err2 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP2, &lnkcap2);
 405         if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
 406                 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
 407                         *speed = PCIE_SPEED_8_0GT;
 408                 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
 409                         *speed = PCIE_SPEED_5_0GT;
 410                 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
 411                         *speed = PCIE_SPEED_2_5GT;
 412         }
 413         if (!err1) {
 414                 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
 415                 if (!lnkcap2) { /* pre-r3.0 */
 416                         if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
 417                                 *speed = PCIE_SPEED_5_0GT;
 418                         else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
 419                                 *speed = PCIE_SPEED_2_5GT;
 420                 }
 421         }
 422
 423         if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {
 424                 return err1 ? err1 :
 425                         err2 ? err2 : -EINVAL;
 426         }
 427         return 0;
 428 }
 429
 430 static void mlx4_check_pcie_caps(struct mlx4_dev *dev)
 431 {
 432         enum pcie_link_width width, width_cap;
 433         enum pci_bus_speed speed, speed_cap;
 434         int err;
 435
 436 #define PCIE_SPEED_STR(speed) \
 437         (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
 438          speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
 439          speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
 440          "Unknown")
 441
 442         err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);
 443         if (err) {
 444                 mlx4_warn(dev,
 445                           "Unable to determine PCIe device BW capabilities\n");
 446                 return;
 447         }
 448
 449         err = pcie_get_minimum_link(dev->pdev, &speed, &width);
 450         if (err || speed == PCI_SPEED_UNKNOWN ||
 451             width == PCIE_LNK_WIDTH_UNKNOWN) {
 452                 mlx4_warn(dev,
 453                           "Unable to determine PCI device chain minimum BW\n");
 454                 return;
 455         }
 456
 457         if (width != width_cap || speed != speed_cap)
 458                 mlx4_warn(dev,
 459                           "PCIe BW is different than device's capability\n");
 460
 461         mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",
 462                   PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
 463         mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",
 464                   width, width_cap);
 465         return;
 466 }
 467
 468 /*The function checks if there are live vf, return the num of them*/
 469 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
 470 {
 471         struct mlx4_priv *priv = mlx4_priv(dev);
 472         struct mlx4_slave_state *s_state;
 473         int i;
 474         int ret = 0;
 475
 476         for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
 477                 s_state = &priv->mfunc.master.slave_state[i];
 478                 if (s_state->active && s_state->last_cmd !=
 479                     MLX4_COMM_CMD_RESET) {
 480                         mlx4_warn(dev, "%s: slave: %d is still active\n",
 481                                   __func__, i);
 482                         ret++;
 483                 }
 484         }
 485         return ret;
 486 }
 487
 488 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
 489 {
 490         u32 qk = MLX4_RESERVED_QKEY_BASE;
 491
 492         if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
 493             qpn < dev->phys_caps.base_proxy_sqpn)
 494                 return -EINVAL;
 495
 496         if (qpn >= dev->phys_caps.base_tunnel_sqpn)
 497                 /* tunnel qp */
 498                 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
 499         else
 500                 qk += qpn - dev->phys_caps.base_proxy_sqpn;
 501         *qkey = qk;
 502         return 0;
 503 }
 504 EXPORT_SYMBOL(mlx4_get_parav_qkey);
 505
 506 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
 507 {
 508         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 509
 510         if (!mlx4_is_master(dev))
 511                 return;
 512
 513         priv->virt2phys_pkey[slave][port - 1][i] = val;
 514 }
 515 EXPORT_SYMBOL(mlx4_sync_pkey_table);
 516
 517 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
 518 {
 519         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 520
 521         if (!mlx4_is_master(dev))
 522                 return;
 523
 524         priv->slave_node_guids[slave] = guid;
 525 }
 526 EXPORT_SYMBOL(mlx4_put_slave_node_guid);
 527
 528 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
 529 {
 530         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 531
 532         if (!mlx4_is_master(dev))
 533                 return 0;
 534
 535         return priv->slave_node_guids[slave];
 536 }
 537 EXPORT_SYMBOL(mlx4_get_slave_node_guid);
 538
 539 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
 540 {
 541         struct mlx4_priv *priv = mlx4_priv(dev);
 542         struct mlx4_slave_state *s_slave;
 543
 544         if (!mlx4_is_master(dev))
 545                 return 0;
 546
 547         s_slave = &priv->mfunc.master.slave_state[slave];
 548         return !!s_slave->active;
 549 }
 550 EXPORT_SYMBOL(mlx4_is_slave_active);
 551
 552 static void slave_adjust_steering_mode(struct mlx4_dev *dev,
 553                                        struct mlx4_dev_cap *dev_cap,
 554                                        struct mlx4_init_hca_param *hca_param)
 555 {
 556         dev->caps.steering_mode = hca_param->steering_mode;
 557         if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
 558                 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
 559                 dev->caps.fs_log_max_ucast_qp_range_size =
 560                         dev_cap->fs_log_max_ucast_qp_range_size;
 561         } else
 562                 dev->caps.num_qp_per_mgm =
 563                         4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
 564
 565         mlx4_dbg(dev, "Steering mode is: %s\n",
 566                  mlx4_steering_mode_str(dev->caps.steering_mode));
 567 }
 568
 569 static int mlx4_slave_cap(struct mlx4_dev *dev)
 570 {
 571         int                        err;
 572         u32                        page_size;
 573         struct mlx4_dev_cap        dev_cap;
 574         struct mlx4_func_cap       func_cap;
 575         struct mlx4_init_hca_param hca_param;
 576         int                        i;
 577
 578         memset(&hca_param, 0, sizeof(hca_param));
 579         err = mlx4_QUERY_HCA(dev, &hca_param);
 580         if (err) {
 581                 mlx4_err(dev, "QUERY_HCA command failed, aborting.\n");
 582                 return err;
 583         }
 584
 585         /*fail if the hca has an unknown capability */
 586         if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) !=
 587             HCA_GLOBAL_CAP_MASK) {
 588                 mlx4_err(dev, "Unknown hca global capabilities\n");
 589                 return -ENOSYS;
 590         }
 591
 592         mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
 593
 594         dev->caps.hca_core_clock = hca_param.hca_core_clock;
 595
 596         memset(&dev_cap, 0, sizeof(dev_cap));
 597         dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
 598         err = mlx4_dev_cap(dev, &dev_cap);
 599         if (err) {
 600                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
 601                 return err;
 602         }
 603
 604         err = mlx4_QUERY_FW(dev);
 605         if (err)
 606                 mlx4_err(dev, "QUERY_FW command failed: could not get FW version.\n");
 607
 608         page_size = ~dev->caps.page_size_cap + 1;
 609         mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
 610         if (page_size > PAGE_SIZE) {
 611                 mlx4_err(dev, "HCA minimum page size of %d bigger than "
 612                          "kernel PAGE_SIZE of %ld, aborting.\n",
 613                          page_size, PAGE_SIZE);
 614                 return -ENODEV;
 615         }
 616
 617         /* slave gets uar page size from QUERY_HCA fw command */
 618         dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
 619
 620         /* TODO: relax this assumption */
 621         if (dev->caps.uar_page_size != PAGE_SIZE) {
 622                 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
 623                          dev->caps.uar_page_size, PAGE_SIZE);
 624                 return -ENODEV;
 625         }
 626
 627         memset(&func_cap, 0, sizeof(func_cap));
 628         err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
 629         if (err) {
 630                 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d).\n",
 631                           err);
 632                 return err;
 633         }
 634
 635         if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
 636             PF_CONTEXT_BEHAVIOUR_MASK) {
 637                 mlx4_err(dev, "Unknown pf context behaviour\n");
 638                 return -ENOSYS;
 639         }
 640
 641         dev->caps.num_ports             = func_cap.num_ports;
 642         dev->quotas.qp                  = func_cap.qp_quota;
 643         dev->quotas.srq                 = func_cap.srq_quota;
 644         dev->quotas.cq                  = func_cap.cq_quota;
 645         dev->quotas.mpt                 = func_cap.mpt_quota;
 646         dev->quotas.mtt                 = func_cap.mtt_quota;
 647         dev->caps.num_qps               = 1 << hca_param.log_num_qps;
 648         dev->caps.num_srqs              = 1 << hca_param.log_num_srqs;
 649         dev->caps.num_cqs               = 1 << hca_param.log_num_cqs;
 650         dev->caps.num_mpts              = 1 << hca_param.log_mpt_sz;
 651         dev->caps.num_eqs               = func_cap.max_eq;
 652         dev->caps.reserved_eqs          = func_cap.reserved_eq;
 653         dev->caps.num_pds               = MLX4_NUM_PDS;
 654         dev->caps.num_mgms              = 0;
 655         dev->caps.num_amgms             = 0;
 656
 657         if (dev->caps.num_ports > MLX4_MAX_PORTS) {
 658                 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
 659                          "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS);
 660                 return -ENODEV;
 661         }
 662
 663         dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 664         dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 665         dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 666         dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 667
 668         if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
 669             !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy) {
 670                 err = -ENOMEM;
 671                 goto err_mem;
 672         }
 673
 674         for (i = 1; i <= dev->caps.num_ports; ++i) {
 675                 err = mlx4_QUERY_FUNC_CAP(dev, (u32) i, &func_cap);
 676                 if (err) {
 677                         mlx4_err(dev, "QUERY_FUNC_CAP port command failed for"
 678                                  " port %d, aborting (%d).\n", i, err);
 679                         goto err_mem;
 680                 }
 681                 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
 682                 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
 683                 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
 684                 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
 685                 dev->caps.port_mask[i] = dev->caps.port_type[i];
 686                 dev->caps.phys_port_id[i] = func_cap.phys_port_id;
 687                 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i,
 688                                                     &dev->caps.gid_table_len[i],
 689                                                     &dev->caps.pkey_table_len[i]))
 690                         goto err_mem;
 691         }
 692
 693         if (dev->caps.uar_page_size * (dev->caps.num_uars -
 694                                        dev->caps.reserved_uars) >
 695                                        pci_resource_len(dev->pdev, 2)) {
 696                 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than "
 697                          "PCI resource 2 size of 0x%llx, aborting.\n",
 698                          dev->caps.uar_page_size * dev->caps.num_uars,
 699                          (unsigned long long) pci_resource_len(dev->pdev, 2));
 700                 goto err_mem;
 701         }
 702
 703         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
 704                 dev->caps.eqe_size   = 64;
 705                 dev->caps.eqe_factor = 1;
 706         } else {
 707                 dev->caps.eqe_size   = 32;
 708                 dev->caps.eqe_factor = 0;
 709         }
 710
 711         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
 712                 dev->caps.cqe_size   = 64;
 713                 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE;
 714         } else {
 715                 dev->caps.cqe_size   = 32;
 716         }
 717
 718         dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
 719         mlx4_warn(dev, "Timestamping is not supported in slave mode.\n");
 720
 721         slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
 722
 723         return 0;
 724
 725 err_mem:
 726         kfree(dev->caps.qp0_tunnel);
 727         kfree(dev->caps.qp0_proxy);
 728         kfree(dev->caps.qp1_tunnel);
 729         kfree(dev->caps.qp1_proxy);
 730         dev->caps.qp0_tunnel = dev->caps.qp0_proxy =
 731                 dev->caps.qp1_tunnel = dev->caps.qp1_proxy = NULL;
 732
 733         return err;
 734 }
 735
 736 static void mlx4_request_modules(struct mlx4_dev *dev)
 737 {
 738         int port;
 739         int has_ib_port = false;
 740         int has_eth_port = false;
 741 #define EN_DRV_NAME     "mlx4_en"
 742 #define IB_DRV_NAME     "mlx4_ib"
 743
 744         for (port = 1; port <= dev->caps.num_ports; port++) {
 745                 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
 746                         has_ib_port = true;
 747                 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
 748                         has_eth_port = true;
 749         }
 750
 751         if (has_ib_port)
 752                 request_module_nowait(IB_DRV_NAME);
 753         if (has_eth_port)
 754                 request_module_nowait(EN_DRV_NAME);
 755 }
 756
 757 /*
 758  * Change the port configuration of the device.
 759  * Every user of this function must hold the port mutex.
 760  */
 761 int mlx4_change_port_types(struct mlx4_dev *dev,
 762                            enum mlx4_port_type *port_types)
 763 {
 764         int err = 0;
 765         int change = 0;
 766         int port;
 767
 768         for (port = 0; port <  dev->caps.num_ports; port++) {
 769                 /* Change the port type only if the new type is different
 770                  * from the current, and not set to Auto */
 771                 if (port_types[port] != dev->caps.port_type[port + 1])
 772                         change = 1;
 773         }
 774         if (change) {
 775                 mlx4_unregister_device(dev);
 776                 for (port = 1; port <= dev->caps.num_ports; port++) {
 777                         mlx4_CLOSE_PORT(dev, port);
 778                         dev->caps.port_type[port] = port_types[port - 1];
 779                         err = mlx4_SET_PORT(dev, port, -1);
 780                         if (err) {
 781                                 mlx4_err(dev, "Failed to set port %d, "
 782                                               "aborting\n", port);
 783                                 goto out;
 784                         }
 785                 }
 786                 mlx4_set_port_mask(dev);
 787                 err = mlx4_register_device(dev);
 788                 if (err) {
 789                         mlx4_err(dev, "Failed to register device\n");
 790                         goto out;
 791                 }
 792                 mlx4_request_modules(dev);
 793         }
 794
 795 out:
 796         return err;
 797 }
 798
 799 static ssize_t show_port_type(struct device *dev,
 800                               struct device_attribute *attr,
 801                               char *buf)
 802 {
 803         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
 804                                                    port_attr);
 805         struct mlx4_dev *mdev = info->dev;
 806         char type[8];
 807
 808         sprintf(type, "%s",
 809                 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
 810                 "ib" : "eth");
 811         if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
 812                 sprintf(buf, "auto (%s)\n", type);
 813         else
 814                 sprintf(buf, "%s\n", type);
 815
 816         return strlen(buf);
 817 }
 818
 819 static ssize_t set_port_type(struct device *dev,
 820                              struct device_attribute *attr,
 821                              const char *buf, size_t count)
 822 {
 823         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
 824                                                    port_attr);
 825         struct mlx4_dev *mdev = info->dev;
 826         struct mlx4_priv *priv = mlx4_priv(mdev);
 827         enum mlx4_port_type types[MLX4_MAX_PORTS];
 828         enum mlx4_port_type new_types[MLX4_MAX_PORTS];
 829         int i;
 830         int err = 0;
 831
 832         if (!strcmp(buf, "ib\n"))
 833                 info->tmp_type = MLX4_PORT_TYPE_IB;
 834         else if (!strcmp(buf, "eth\n"))
 835                 info->tmp_type = MLX4_PORT_TYPE_ETH;
 836         else if (!strcmp(buf, "auto\n"))
 837                 info->tmp_type = MLX4_PORT_TYPE_AUTO;
 838         else {
 839                 mlx4_err(mdev, "%s is not supported port type\n", buf);
 840                 return -EINVAL;
 841         }
 842
 843         mlx4_stop_sense(mdev);
 844         mutex_lock(&priv->port_mutex);
 845         /* Possible type is always the one that was delivered */
 846         mdev->caps.possible_type[info->port] = info->tmp_type;
 847
 848         for (i = 0; i < mdev->caps.num_ports; i++) {
 849                 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
 850                                         mdev->caps.possible_type[i+1];
 851                 if (types[i] == MLX4_PORT_TYPE_AUTO)
 852                         types[i] = mdev->caps.port_type[i+1];
 853         }
 854
 855         if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
 856             !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
 857                 for (i = 1; i <= mdev->caps.num_ports; i++) {
 858                         if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
 859                                 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
 860                                 err = -EINVAL;
 861                         }
 862                 }
 863         }
 864         if (err) {
 865                 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
 866                                "Set only 'eth' or 'ib' for both ports "
 867                                "(should be the same)\n");
 868                 goto out;
 869         }
 870
 871         mlx4_do_sense_ports(mdev, new_types, types);
 872
 873         err = mlx4_check_port_params(mdev, new_types);
 874         if (err)
 875                 goto out;
 876
 877         /* We are about to apply the changes after the configuration
 878          * was verified, no need to remember the temporary types
 879          * any more */
 880         for (i = 0; i < mdev->caps.num_ports; i++)
 881                 priv->port[i + 1].tmp_type = 0;
 882
 883         err = mlx4_change_port_types(mdev, new_types);
 884
 885 out:
 886         mlx4_start_sense(mdev);
 887         mutex_unlock(&priv->port_mutex);
 888         return err ? err : count;
 889 }
 890
 891 enum ibta_mtu {
 892         IB_MTU_256  = 1,
 893         IB_MTU_512  = 2,
 894         IB_MTU_1024 = 3,
 895         IB_MTU_2048 = 4,
 896         IB_MTU_4096 = 5
 897 };
 898
 899 static inline int int_to_ibta_mtu(int mtu)
 900 {
 901         switch (mtu) {
 902         case 256:  return IB_MTU_256;
 903         case 512:  return IB_MTU_512;
 904         case 1024: return IB_MTU_1024;
 905         case 2048: return IB_MTU_2048;
 906         case 4096: return IB_MTU_4096;
 907         default: return -1;
 908         }
 909 }
 910
 911 static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
 912 {
 913         switch (mtu) {
 914         case IB_MTU_256:  return  256;
 915         case IB_MTU_512:  return  512;
 916         case IB_MTU_1024: return 1024;
 917         case IB_MTU_2048: return 2048;
 918         case IB_MTU_4096: return 4096;
 919         default: return -1;
 920         }
 921 }
 922
 923 static ssize_t show_port_ib_mtu(struct device *dev,
 924                              struct device_attribute *attr,
 925                              char *buf)
 926 {
 927         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
 928                                                    port_mtu_attr);
 929         struct mlx4_dev *mdev = info->dev;
 930
 931         if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
 932                 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
 933
 934         sprintf(buf, "%d\n",
 935                         ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
 936         return strlen(buf);
 937 }
 938
 939 static ssize_t set_port_ib_mtu(struct device *dev,
 940                              struct device_attribute *attr,
 941                              const char *buf, size_t count)
 942 {
 943         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
 944                                                    port_mtu_attr);
 945         struct mlx4_dev *mdev = info->dev;
 946         struct mlx4_priv *priv = mlx4_priv(mdev);
 947         int err, port, mtu, ibta_mtu = -1;
 948
 949         if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
 950                 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
 951                 return -EINVAL;
 952         }
 953
 954         err = kstrtoint(buf, 0, &mtu);
 955         if (!err)
 956                 ibta_mtu = int_to_ibta_mtu(mtu);
 957
 958         if (err || ibta_mtu < 0) {
 959                 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
 960                 return -EINVAL;
 961         }
 962
 963         mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
 964
 965         mlx4_stop_sense(mdev);
 966         mutex_lock(&priv->port_mutex);
 967         mlx4_unregister_device(mdev);
 968         for (port = 1; port <= mdev->caps.num_ports; port++) {
 969                 mlx4_CLOSE_PORT(mdev, port);
 970                 err = mlx4_SET_PORT(mdev, port, -1);
 971                 if (err) {
 972                         mlx4_err(mdev, "Failed to set port %d, "
 973                                       "aborting\n", port);
 974                         goto err_set_port;
 975                 }
 976         }
 977         err = mlx4_register_device(mdev);
 978 err_set_port:
 979         mutex_unlock(&priv->port_mutex);
 980         mlx4_start_sense(mdev);
 981         return err ? err : count;
 982 }
 983
 984 static int mlx4_load_fw(struct mlx4_dev *dev)
 985 {
 986         struct mlx4_priv *priv = mlx4_priv(dev);
 987         int err;
 988
 989         priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
 990                                          GFP_HIGHUSER | __GFP_NOWARN, 0);
 991         if (!priv->fw.fw_icm) {
 992                 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
 993                 return -ENOMEM;
 994         }
 995
 996         err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
 997         if (err) {
 998                 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
 999                 goto err_free;
1000         }
1001
1002         err = mlx4_RUN_FW(dev);
1003         if (err) {
1004                 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
1005                 goto err_unmap_fa;
1006         }
1007
1008         return 0;
1009
1010 err_unmap_fa:
1011         mlx4_UNMAP_FA(dev);
1012
1013 err_free:
1014         mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1015         return err;
1016 }
1017
1018 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1019                                 int cmpt_entry_sz)
1020 {
1021         struct mlx4_priv *priv = mlx4_priv(dev);
1022         int err;
1023         int num_eqs;
1024
1025         err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1026                                   cmpt_base +
1027                                   ((u64) (MLX4_CMPT_TYPE_QP *
1028                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1029                                   cmpt_entry_sz, dev->caps.num_qps,
1030                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1031                                   0, 0);
1032         if (err)
1033                 goto err;
1034
1035         err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1036                                   cmpt_base +
1037                                   ((u64) (MLX4_CMPT_TYPE_SRQ *
1038                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1039                                   cmpt_entry_sz, dev->caps.num_srqs,
1040                                   dev->caps.reserved_srqs, 0, 0);
1041         if (err)
1042                 goto err_qp;
1043
1044         err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1045                                   cmpt_base +
1046                                   ((u64) (MLX4_CMPT_TYPE_CQ *
1047                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1048                                   cmpt_entry_sz, dev->caps.num_cqs,
1049                                   dev->caps.reserved_cqs, 0, 0);
1050         if (err)
1051                 goto err_srq;
1052
1053         num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
1054                   dev->caps.num_eqs;
1055         err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1056                                   cmpt_base +
1057                                   ((u64) (MLX4_CMPT_TYPE_EQ *
1058                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1059                                   cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
1060         if (err)
1061                 goto err_cq;
1062
1063         return 0;
1064
1065 err_cq:
1066         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1067
1068 err_srq:
1069         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1070
1071 err_qp:
1072         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1073
1074 err:
1075         return err;
1076 }
1077
1078 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1079                          struct mlx4_init_hca_param *init_hca, u64 icm_size)
1080 {
1081         struct mlx4_priv *priv = mlx4_priv(dev);
1082         u64 aux_pages;
1083         int num_eqs;
1084         int err;
1085
1086         err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1087         if (err) {
1088                 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
1089                 return err;
1090         }
1091
1092         mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
1093                  (unsigned long long) icm_size >> 10,
1094                  (unsigned long long) aux_pages << 2);
1095
1096         priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
1097                                           GFP_HIGHUSER | __GFP_NOWARN, 0);
1098         if (!priv->fw.aux_icm) {
1099                 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
1100                 return -ENOMEM;
1101         }
1102
1103         err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1104         if (err) {
1105                 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
1106                 goto err_free_aux;
1107         }
1108
1109         err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1110         if (err) {
1111                 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
1112                 goto err_unmap_aux;
1113         }
1114
1115
1116         num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
1117                    dev->caps.num_eqs;
1118         err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1119                                   init_hca->eqc_base, dev_cap->eqc_entry_sz,
1120                                   num_eqs, num_eqs, 0, 0);
1121         if (err) {
1122                 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
1123                 goto err_unmap_cmpt;
1124         }
1125
1126         /*
1127          * Reserved MTT entries must be aligned up to a cacheline
1128          * boundary, since the FW will write to them, while the driver
1129          * writes to all other MTT entries. (The variable
1130          * dev->caps.mtt_entry_sz below is really the MTT segment
1131          * size, not the raw entry size)
1132          */
1133         dev->caps.reserved_mtts =
1134                 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1135                       dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1136
1137         err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1138                                   init_hca->mtt_base,
1139                                   dev->caps.mtt_entry_sz,
1140                                   dev->caps.num_mtts,
1141                                   dev->caps.reserved_mtts, 1, 0);
1142         if (err) {
1143                 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
1144                 goto err_unmap_eq;
1145         }
1146
1147         err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1148                                   init_hca->dmpt_base,
1149                                   dev_cap->dmpt_entry_sz,
1150                                   dev->caps.num_mpts,
1151                                   dev->caps.reserved_mrws, 1, 1);
1152         if (err) {
1153                 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
1154                 goto err_unmap_mtt;
1155         }
1156
1157         err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1158                                   init_hca->qpc_base,
1159                                   dev_cap->qpc_entry_sz,
1160                                   dev->caps.num_qps,
1161                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1162                                   0, 0);
1163         if (err) {
1164                 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
1165                 goto err_unmap_dmpt;
1166         }
1167
1168         err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1169                                   init_hca->auxc_base,
1170                                   dev_cap->aux_entry_sz,
1171                                   dev->caps.num_qps,
1172                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1173                                   0, 0);
1174         if (err) {
1175                 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
1176                 goto err_unmap_qp;
1177         }
1178
1179         err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1180                                   init_hca->altc_base,
1181                                   dev_cap->altc_entry_sz,
1182                                   dev->caps.num_qps,
1183                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1184                                   0, 0);
1185         if (err) {
1186                 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
1187                 goto err_unmap_auxc;
1188         }
1189
1190         err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1191                                   init_hca->rdmarc_base,
1192                                   dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1193                                   dev->caps.num_qps,
1194                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1195                                   0, 0);
1196         if (err) {
1197                 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1198                 goto err_unmap_altc;
1199         }
1200
1201         err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1202                                   init_hca->cqc_base,
1203                                   dev_cap->cqc_entry_sz,
1204                                   dev->caps.num_cqs,
1205                                   dev->caps.reserved_cqs, 0, 0);
1206         if (err) {
1207                 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
1208                 goto err_unmap_rdmarc;
1209         }
1210
1211         err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1212                                   init_hca->srqc_base,
1213                                   dev_cap->srq_entry_sz,
1214                                   dev->caps.num_srqs,
1215                                   dev->caps.reserved_srqs, 0, 0);
1216         if (err) {
1217                 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
1218                 goto err_unmap_cq;
1219         }
1220
1221         /*
1222          * For flow steering device managed mode it is required to use
1223          * mlx4_init_icm_table. For B0 steering mode it's not strictly
1224          * required, but for simplicity just map the whole multicast
1225          * group table now.  The table isn't very big and it's a lot
1226          * easier than trying to track ref counts.
1227          */
1228         err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
1229                                   init_hca->mc_base,
1230                                   mlx4_get_mgm_entry_size(dev),
1231                                   dev->caps.num_mgms + dev->caps.num_amgms,
1232                                   dev->caps.num_mgms + dev->caps.num_amgms,
1233                                   0, 0);
1234         if (err) {
1235                 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
1236                 goto err_unmap_srq;
1237         }
1238
1239         return 0;
1240
1241 err_unmap_srq:
1242         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1243
1244 err_unmap_cq:
1245         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1246
1247 err_unmap_rdmarc:
1248         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1249
1250 err_unmap_altc:
1251         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1252
1253 err_unmap_auxc:
1254         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1255
1256 err_unmap_qp:
1257         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1258
1259 err_unmap_dmpt:
1260         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1261
1262 err_unmap_mtt:
1263         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1264
1265 err_unmap_eq:
1266         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1267
1268 err_unmap_cmpt:
1269         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1270         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1271         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1272         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1273
1274 err_unmap_aux:
1275         mlx4_UNMAP_ICM_AUX(dev);
1276
1277 err_free_aux:
1278         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1279
1280         return err;
1281 }
1282
1283 static void mlx4_free_icms(struct mlx4_dev *dev)
1284 {
1285         struct mlx4_priv *priv = mlx4_priv(dev);
1286
1287         mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1288         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1289         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1290         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1291         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1292         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1293         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1294         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1295         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1296         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1297         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1298         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1299         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1300         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1301
1302         mlx4_UNMAP_ICM_AUX(dev);
1303         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1304 }
1305
1306 static void mlx4_slave_exit(struct mlx4_dev *dev)
1307 {
1308         struct mlx4_priv *priv = mlx4_priv(dev);
1309
1310         mutex_lock(&priv->cmd.slave_cmd_mutex);
1311         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
1312                 mlx4_warn(dev, "Failed to close slave function.\n");
1313         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1314 }
1315
1316 static int map_bf_area(struct mlx4_dev *dev)
1317 {
1318         struct mlx4_priv *priv = mlx4_priv(dev);
1319         resource_size_t bf_start;
1320         resource_size_t bf_len;
1321         int err = 0;
1322
1323         if (!dev->caps.bf_reg_size)
1324                 return -ENXIO;
1325
1326         bf_start = pci_resource_start(dev->pdev, 2) +
1327                         (dev->caps.num_uars << PAGE_SHIFT);
1328         bf_len = pci_resource_len(dev->pdev, 2) -
1329                         (dev->caps.num_uars << PAGE_SHIFT);
1330         priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1331         if (!priv->bf_mapping)
1332                 err = -ENOMEM;
1333
1334         return err;
1335 }
1336
1337 static void unmap_bf_area(struct mlx4_dev *dev)
1338 {
1339         if (mlx4_priv(dev)->bf_mapping)
1340                 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1341 }
1342
1343 cycle_t mlx4_read_clock(struct mlx4_dev *dev)
1344 {
1345         u32 clockhi, clocklo, clockhi1;
1346         cycle_t cycles;
1347         int i;
1348         struct mlx4_priv *priv = mlx4_priv(dev);
1349
1350         for (i = 0; i < 10; i++) {
1351                 clockhi = swab32(readl(priv->clock_mapping));
1352                 clocklo = swab32(readl(priv->clock_mapping + 4));
1353                 clockhi1 = swab32(readl(priv->clock_mapping));
1354                 if (clockhi == clockhi1)
1355                         break;
1356         }
1357
1358         cycles = (u64) clockhi << 32 | (u64) clocklo;
1359
1360         return cycles;
1361 }
1362 EXPORT_SYMBOL_GPL(mlx4_read_clock);
1363
1364
1365 static int map_internal_clock(struct mlx4_dev *dev)
1366 {
1367         struct mlx4_priv *priv = mlx4_priv(dev);
1368
1369         priv->clock_mapping =
1370                 ioremap(pci_resource_start(dev->pdev, priv->fw.clock_bar) +
1371                         priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1372
1373         if (!priv->clock_mapping)
1374                 return -ENOMEM;
1375
1376         return 0;
1377 }
1378
1379 static void unmap_internal_clock(struct mlx4_dev *dev)
1380 {
1381         struct mlx4_priv *priv = mlx4_priv(dev);
1382
1383         if (priv->clock_mapping)
1384                 iounmap(priv->clock_mapping);
1385 }
1386
1387 static void mlx4_close_hca(struct mlx4_dev *dev)
1388 {
1389         unmap_internal_clock(dev);
1390         unmap_bf_area(dev);
1391         if (mlx4_is_slave(dev))
1392                 mlx4_slave_exit(dev);
1393         else {
1394                 mlx4_CLOSE_HCA(dev, 0);
1395                 mlx4_free_icms(dev);
1396                 mlx4_UNMAP_FA(dev);
1397                 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1398         }
1399 }
1400
1401 static int mlx4_init_slave(struct mlx4_dev *dev)
1402 {
1403         struct mlx4_priv *priv = mlx4_priv(dev);
1404         u64 dma = (u64) priv->mfunc.vhcr_dma;
1405         int ret_from_reset = 0;
1406         u32 slave_read;
1407         u32 cmd_channel_ver;
1408
1409         mutex_lock(&priv->cmd.slave_cmd_mutex);
1410         priv->cmd.max_cmds = 1;
1411         mlx4_warn(dev, "Sending reset\n");
1412         ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1413                                        MLX4_COMM_TIME);
1414         /* if we are in the middle of flr the slave will try
1415          * NUM_OF_RESET_RETRIES times before leaving.*/
1416         if (ret_from_reset) {
1417                 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1418                         mlx4_warn(dev, "slave is currently in the "
1419                                   "middle of FLR. Deferring probe.\n");
1420                         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1421                         return -EPROBE_DEFER;
1422                 } else
1423                         goto err;
1424         }
1425
1426         /* check the driver version - the slave I/F revision
1427          * must match the master's */
1428         slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1429         cmd_channel_ver = mlx4_comm_get_version();
1430
1431         if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1432                 MLX4_COMM_GET_IF_REV(slave_read)) {
1433                 mlx4_err(dev, "slave driver version is not supported"
1434                          " by the master\n");
1435                 goto err;
1436         }
1437
1438         mlx4_warn(dev, "Sending vhcr0\n");
1439         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1440                                                     MLX4_COMM_TIME))
1441                 goto err;
1442         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1443                                                     MLX4_COMM_TIME))
1444                 goto err;
1445         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1446                                                     MLX4_COMM_TIME))
1447                 goto err;
1448         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1449                 goto err;
1450
1451         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1452         return 0;
1453
1454 err:
1455         mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
1456         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1457         return -EIO;
1458 }
1459
1460 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1461 {
1462         int i;
1463
1464         for (i = 1; i <= dev->caps.num_ports; i++) {
1465                 dev->caps.gid_table_len[i] = 1;
1466                 dev->caps.pkey_table_len[i] =
1467                         dev->phys_caps.pkey_phys_table_len[i] - 1;
1468         }
1469 }
1470
1471 static int choose_log_fs_mgm_entry_size(int qp_per_entry)
1472 {
1473         int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
1474
1475         for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
1476               i++) {
1477                 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
1478                         break;
1479         }
1480
1481         return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
1482 }
1483
1484 static void choose_steering_mode(struct mlx4_dev *dev,
1485                                  struct mlx4_dev_cap *dev_cap)
1486 {
1487         if (mlx4_log_num_mgm_entry_size == -1 &&
1488             dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
1489             (!mlx4_is_mfunc(dev) ||
1490              (dev_cap->fs_max_num_qp_per_entry >= (num_vfs + 1))) &&
1491             choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
1492                 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
1493                 dev->oper_log_mgm_entry_size =
1494                         choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
1495                 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1496                 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
1497                 dev->caps.fs_log_max_ucast_qp_range_size =
1498                         dev_cap->fs_log_max_ucast_qp_range_size;
1499         } else {
1500                 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
1501                     dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1502                         dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
1503                 else {
1504                         dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
1505
1506                         if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
1507                             dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1508                                 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags "
1509                                           "set to use B0 steering. Falling back to A0 steering mode.\n");
1510                 }
1511                 dev->oper_log_mgm_entry_size =
1512                         mlx4_log_num_mgm_entry_size > 0 ?
1513                         mlx4_log_num_mgm_entry_size :
1514                         MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
1515                 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
1516         }
1517         mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, "
1518                  "modparam log_num_mgm_entry_size = %d\n",
1519                  mlx4_steering_mode_str(dev->caps.steering_mode),
1520                  dev->oper_log_mgm_entry_size,
1521                  mlx4_log_num_mgm_entry_size);
1522 }
1523
1524 static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
1525                                        struct mlx4_dev_cap *dev_cap)
1526 {
1527         if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
1528             dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS)
1529                 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
1530         else
1531                 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
1532
1533         mlx4_dbg(dev, "Tunneling offload mode is: %s\n",  (dev->caps.tunnel_offload_mode
1534                  == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
1535 }
1536
1537 static int mlx4_init_hca(struct mlx4_dev *dev)
1538 {
1539         struct mlx4_priv          *priv = mlx4_priv(dev);
1540         struct mlx4_adapter        adapter;
1541         struct mlx4_dev_cap        dev_cap;
1542         struct mlx4_mod_stat_cfg   mlx4_cfg;
1543         struct mlx4_profile        profile;
1544         struct mlx4_init_hca_param init_hca;
1545         u64 icm_size;
1546         int err;
1547
1548         if (!mlx4_is_slave(dev)) {
1549                 err = mlx4_QUERY_FW(dev);
1550                 if (err) {
1551                         if (err == -EACCES)
1552                                 mlx4_info(dev, "non-primary physical function, skipping.\n");
1553                         else
1554                                 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
1555                         return err;
1556                 }
1557
1558                 err = mlx4_load_fw(dev);
1559                 if (err) {
1560                         mlx4_err(dev, "Failed to start FW, aborting.\n");
1561                         return err;
1562                 }
1563
1564                 mlx4_cfg.log_pg_sz_m = 1;
1565                 mlx4_cfg.log_pg_sz = 0;
1566                 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1567                 if (err)
1568                         mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
1569
1570                 err = mlx4_dev_cap(dev, &dev_cap);
1571                 if (err) {
1572                         mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
1573                         goto err_stop_fw;
1574                 }
1575
1576                 choose_steering_mode(dev, &dev_cap);
1577                 choose_tunnel_offload_mode(dev, &dev_cap);
1578
1579                 err = mlx4_get_phys_port_id(dev);
1580                 if (err)
1581                         mlx4_err(dev, "Fail to get physical port id\n");
1582
1583                 if (mlx4_is_master(dev))
1584                         mlx4_parav_master_pf_caps(dev);
1585
1586                 profile = default_profile;
1587                 if (dev->caps.steering_mode ==
1588                     MLX4_STEERING_MODE_DEVICE_MANAGED)
1589                         profile.num_mcg = MLX4_FS_NUM_MCG;
1590
1591                 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
1592                                              &init_hca);
1593                 if ((long long) icm_size < 0) {
1594                         err = icm_size;
1595                         goto err_stop_fw;
1596                 }
1597
1598                 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
1599
1600                 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
1601                 init_hca.uar_page_sz = PAGE_SHIFT - 12;
1602                 init_hca.mw_enabled = 0;
1603                 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
1604                     dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
1605                         init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
1606
1607                 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
1608                 if (err)
1609                         goto err_stop_fw;
1610
1611                 err = mlx4_INIT_HCA(dev, &init_hca);
1612                 if (err) {
1613                         mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
1614                         goto err_free_icm;
1615                 }
1616                 /*
1617                  * If TS is supported by FW
1618                  * read HCA frequency by QUERY_HCA command
1619                  */
1620                 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1621                         memset(&init_hca, 0, sizeof(init_hca));
1622                         err = mlx4_QUERY_HCA(dev, &init_hca);
1623                         if (err) {
1624                                 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp.\n");
1625                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1626                         } else {
1627                                 dev->caps.hca_core_clock =
1628                                         init_hca.hca_core_clock;
1629                         }
1630
1631                         /* In case we got HCA frequency 0 - disable timestamping
1632                          * to avoid dividing by zero
1633                          */
1634                         if (!dev->caps.hca_core_clock) {
1635                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1636                                 mlx4_err(dev,
1637                                          "HCA frequency is 0. Timestamping is not supported.");
1638                         } else if (map_internal_clock(dev)) {
1639                                 /*
1640                                  * Map internal clock,
1641                                  * in case of failure disable timestamping
1642                                  */
1643                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1644                                 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported.\n");
1645                         }
1646                 }
1647         } else {
1648                 err = mlx4_init_slave(dev);
1649                 if (err) {
1650                         if (err != -EPROBE_DEFER)
1651                                 mlx4_err(dev, "Failed to initialize slave\n");
1652                         return err;
1653                 }
1654
1655                 err = mlx4_slave_cap(dev);
1656                 if (err) {
1657                         mlx4_err(dev, "Failed to obtain slave caps\n");
1658                         goto err_close;
1659                 }
1660         }
1661
1662         if (map_bf_area(dev))
1663                 mlx4_dbg(dev, "Failed to map blue flame area\n");
1664
1665         /*Only the master set the ports, all the rest got it from it.*/
1666         if (!mlx4_is_slave(dev))
1667                 mlx4_set_port_mask(dev);
1668
1669         err = mlx4_QUERY_ADAPTER(dev, &adapter);
1670         if (err) {
1671                 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
1672                 goto unmap_bf;
1673         }
1674
1675         priv->eq_table.inta_pin = adapter.inta_pin;
1676         memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
1677
1678         return 0;
1679
1680 unmap_bf:
1681         unmap_internal_clock(dev);
1682         unmap_bf_area(dev);
1683
1684 err_close:
1685         if (mlx4_is_slave(dev))
1686                 mlx4_slave_exit(dev);
1687         else
1688                 mlx4_CLOSE_HCA(dev, 0);
1689
1690 err_free_icm:
1691         if (!mlx4_is_slave(dev))
1692                 mlx4_free_icms(dev);
1693
1694 err_stop_fw:
1695         if (!mlx4_is_slave(dev)) {
1696                 mlx4_UNMAP_FA(dev);
1697                 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1698         }
1699         return err;
1700 }
1701
1702 static int mlx4_init_counters_table(struct mlx4_dev *dev)
1703 {
1704         struct mlx4_priv *priv = mlx4_priv(dev);
1705         int nent;
1706
1707         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1708                 return -ENOENT;
1709
1710         nent = dev->caps.max_counters;
1711         return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
1712 }
1713
1714 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
1715 {
1716         mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
1717 }
1718
1719 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1720 {
1721         struct mlx4_priv *priv = mlx4_priv(dev);
1722
1723         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1724                 return -ENOENT;
1725
1726         *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
1727         if (*idx == -1)
1728                 return -ENOMEM;
1729
1730         return 0;
1731 }
1732
1733 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1734 {
1735         u64 out_param;
1736         int err;
1737
1738         if (mlx4_is_mfunc(dev)) {
1739                 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
1740                                    RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
1741                                    MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1742                 if (!err)
1743                         *idx = get_param_l(&out_param);
1744
1745                 return err;
1746         }
1747         return __mlx4_counter_alloc(dev, idx);
1748 }
1749 EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
1750
1751 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1752 {
1753         mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
1754         return;
1755 }
1756
1757 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1758 {
1759         u64 in_param = 0;
1760
1761         if (mlx4_is_mfunc(dev)) {
1762                 set_param_l(&in_param, idx);
1763                 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
1764                          MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
1765                          MLX4_CMD_WRAPPED);
1766                 return;
1767         }
1768         __mlx4_counter_free(dev, idx);
1769 }
1770 EXPORT_SYMBOL_GPL(mlx4_counter_free);
1771
1772 static int mlx4_setup_hca(struct mlx4_dev *dev)
1773 {
1774         struct mlx4_priv *priv = mlx4_priv(dev);
1775         int err;
1776         int port;
1777         __be32 ib_port_default_caps;
1778
1779         err = mlx4_init_uar_table(dev);
1780         if (err) {
1781                 mlx4_err(dev, "Failed to initialize "
1782                          "user access region table, aborting.\n");
1783                 return err;
1784         }
1785
1786         err = mlx4_uar_alloc(dev, &priv->driver_uar);
1787         if (err) {
1788                 mlx4_err(dev, "Failed to allocate driver access region, "
1789                          "aborting.\n");
1790                 goto err_uar_table_free;
1791         }
1792
1793         priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
1794         if (!priv->kar) {
1795                 mlx4_err(dev, "Couldn't map kernel access region, "
1796                          "aborting.\n");
1797                 err = -ENOMEM;
1798                 goto err_uar_free;
1799         }
1800
1801         err = mlx4_init_pd_table(dev);
1802         if (err) {
1803                 mlx4_err(dev, "Failed to initialize "
1804                          "protection domain table, aborting.\n");
1805                 goto err_kar_unmap;
1806         }
1807
1808         err = mlx4_init_xrcd_table(dev);
1809         if (err) {
1810                 mlx4_err(dev, "Failed to initialize "
1811                          "reliable connection domain table, aborting.\n");
1812                 goto err_pd_table_free;
1813         }
1814
1815         err = mlx4_init_mr_table(dev);
1816         if (err) {
1817                 mlx4_err(dev, "Failed to initialize "
1818                          "memory region table, aborting.\n");
1819                 goto err_xrcd_table_free;
1820         }
1821
1822         if (!mlx4_is_slave(dev)) {
1823                 err = mlx4_init_mcg_table(dev);
1824                 if (err) {
1825                         mlx4_err(dev, "Failed to initialize multicast group table, aborting.\n");
1826                         goto err_mr_table_free;
1827                 }
1828         }
1829
1830         err = mlx4_init_eq_table(dev);
1831         if (err) {
1832                 mlx4_err(dev, "Failed to initialize "
1833                          "event queue table, aborting.\n");
1834                 goto err_mcg_table_free;
1835         }
1836
1837         err = mlx4_cmd_use_events(dev);
1838         if (err) {
1839                 mlx4_err(dev, "Failed to switch to event-driven "
1840                          "firmware commands, aborting.\n");
1841                 goto err_eq_table_free;
1842         }
1843
1844         err = mlx4_NOP(dev);
1845         if (err) {
1846                 if (dev->flags & MLX4_FLAG_MSI_X) {
1847                         mlx4_warn(dev, "NOP command failed to generate MSI-X "
1848                                   "interrupt IRQ %d).\n",
1849                                   priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1850                         mlx4_warn(dev, "Trying again without MSI-X.\n");
1851                 } else {
1852                         mlx4_err(dev, "NOP command failed to generate interrupt "
1853                                  "(IRQ %d), aborting.\n",
1854                                  priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1855                         mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
1856                 }
1857
1858                 goto err_cmd_poll;
1859         }
1860
1861         mlx4_dbg(dev, "NOP command IRQ test passed\n");
1862
1863         err = mlx4_init_cq_table(dev);
1864         if (err) {
1865                 mlx4_err(dev, "Failed to initialize "
1866                          "completion queue table, aborting.\n");
1867                 goto err_cmd_poll;
1868         }
1869
1870         err = mlx4_init_srq_table(dev);
1871         if (err) {
1872                 mlx4_err(dev, "Failed to initialize "
1873                          "shared receive queue table, aborting.\n");
1874                 goto err_cq_table_free;
1875         }
1876
1877         err = mlx4_init_qp_table(dev);
1878         if (err) {
1879                 mlx4_err(dev, "Failed to initialize "
1880                          "queue pair table, aborting.\n");
1881                 goto err_srq_table_free;
1882         }
1883
1884         err = mlx4_init_counters_table(dev);
1885         if (err && err != -ENOENT) {
1886                 mlx4_err(dev, "Failed to initialize counters table, aborting.\n");
1887                 goto err_qp_table_free;
1888         }
1889
1890         if (!mlx4_is_slave(dev)) {
1891                 for (port = 1; port <= dev->caps.num_ports; port++) {
1892                         ib_port_default_caps = 0;
1893                         err = mlx4_get_port_ib_caps(dev, port,
1894                                                     &ib_port_default_caps);
1895                         if (err)
1896                                 mlx4_warn(dev, "failed to get port %d default "
1897                                           "ib capabilities (%d). Continuing "
1898                                           "with caps = 0\n", port, err);
1899                         dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
1900
1901                         /* initialize per-slave default ib port capabilities */
1902                         if (mlx4_is_master(dev)) {
1903                                 int i;
1904                                 for (i = 0; i < dev->num_slaves; i++) {
1905                                         if (i == mlx4_master_func_num(dev))
1906                                                 continue;
1907                                         priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
1908                                                         ib_port_default_caps;
1909                                 }
1910                         }
1911
1912                         if (mlx4_is_mfunc(dev))
1913                                 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
1914                         else
1915                                 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
1916
1917                         err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
1918                                             dev->caps.pkey_table_len[port] : -1);
1919                         if (err) {
1920                                 mlx4_err(dev, "Failed to set port %d, aborting\n",
1921                                         port);
1922                                 goto err_counters_table_free;
1923                         }
1924                 }
1925         }
1926
1927         return 0;
1928
1929 err_counters_table_free:
1930         mlx4_cleanup_counters_table(dev);
1931
1932 err_qp_table_free:
1933         mlx4_cleanup_qp_table(dev);
1934
1935 err_srq_table_free:
1936         mlx4_cleanup_srq_table(dev);
1937
1938 err_cq_table_free:
1939         mlx4_cleanup_cq_table(dev);
1940
1941 err_cmd_poll:
1942         mlx4_cmd_use_polling(dev);
1943
1944 err_eq_table_free:
1945         mlx4_cleanup_eq_table(dev);
1946
1947 err_mcg_table_free:
1948         if (!mlx4_is_slave(dev))
1949                 mlx4_cleanup_mcg_table(dev);
1950
1951 err_mr_table_free:
1952         mlx4_cleanup_mr_table(dev);
1953
1954 err_xrcd_table_free:
1955         mlx4_cleanup_xrcd_table(dev);
1956
1957 err_pd_table_free:
1958         mlx4_cleanup_pd_table(dev);
1959
1960 err_kar_unmap:
1961         iounmap(priv->kar);
1962
1963 err_uar_free:
1964         mlx4_uar_free(dev, &priv->driver_uar);
1965
1966 err_uar_table_free:
1967         mlx4_cleanup_uar_table(dev);
1968         return err;
1969 }
1970
1971 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
1972 {
1973         struct mlx4_priv *priv = mlx4_priv(dev);
1974         struct msix_entry *entries;
1975         int nreq = min_t(int, dev->caps.num_ports *
1976                          min_t(int, num_online_cpus() + 1,
1977                                MAX_MSIX_P_PORT) + MSIX_LEGACY_SZ, MAX_MSIX);
1978         int i;
1979
1980         if (msi_x) {
1981                 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
1982                              nreq);
1983
1984                 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
1985                 if (!entries)
1986                         goto no_msi;
1987
1988                 for (i = 0; i < nreq; ++i)
1989                         entries[i].entry = i;
1990
1991                 nreq = pci_enable_msix_range(dev->pdev, entries, 2, nreq);
1992
1993                 if (nreq < 0) {
1994                         kfree(entries);
1995                         goto no_msi;
1996                 } else if (nreq < MSIX_LEGACY_SZ +
1997                                   dev->caps.num_ports * MIN_MSIX_P_PORT) {
1998                         /*Working in legacy mode , all EQ's shared*/
1999                         dev->caps.comp_pool           = 0;
2000                         dev->caps.num_comp_vectors = nreq - 1;
2001                 } else {
2002                         dev->caps.comp_pool           = nreq - MSIX_LEGACY_SZ;
2003                         dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
2004                 }
2005                 for (i = 0; i < nreq; ++i)
2006                         priv->eq_table.eq[i].irq = entries[i].vector;
2007
2008                 dev->flags |= MLX4_FLAG_MSI_X;
2009
2010                 kfree(entries);
2011                 return;
2012         }
2013
2014 no_msi:
2015         dev->caps.num_comp_vectors = 1;
2016         dev->caps.comp_pool        = 0;
2017
2018         for (i = 0; i < 2; ++i)
2019                 priv->eq_table.eq[i].irq = dev->pdev->irq;
2020 }
2021
2022 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2023 {
2024         struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
2025         int err = 0;
2026
2027         info->dev = dev;
2028         info->port = port;
2029         if (!mlx4_is_slave(dev)) {
2030                 mlx4_init_mac_table(dev, &info->mac_table);
2031                 mlx4_init_vlan_table(dev, &info->vlan_table);
2032                 info->base_qpn = mlx4_get_base_qpn(dev, port);
2033         }
2034
2035         sprintf(info->dev_name, "mlx4_port%d", port);
2036         info->port_attr.attr.name = info->dev_name;
2037         if (mlx4_is_mfunc(dev))
2038                 info->port_attr.attr.mode = S_IRUGO;
2039         else {
2040                 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
2041                 info->port_attr.store     = set_port_type;
2042         }
2043         info->port_attr.show      = show_port_type;
2044         sysfs_attr_init(&info->port_attr.attr);
2045
2046         err = device_create_file(&dev->pdev->dev, &info->port_attr);
2047         if (err) {
2048                 mlx4_err(dev, "Failed to create file for port %d\n", port);
2049                 info->port = -1;
2050         }
2051
2052         sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
2053         info->port_mtu_attr.attr.name = info->dev_mtu_name;
2054         if (mlx4_is_mfunc(dev))
2055                 info->port_mtu_attr.attr.mode = S_IRUGO;
2056         else {
2057                 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
2058                 info->port_mtu_attr.store     = set_port_ib_mtu;
2059         }
2060         info->port_mtu_attr.show      = show_port_ib_mtu;
2061         sysfs_attr_init(&info->port_mtu_attr.attr);
2062
2063         err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr);
2064         if (err) {
2065                 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
2066                 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
2067                 info->port = -1;
2068         }
2069
2070         return err;
2071 }
2072
2073 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
2074 {
2075         if (info->port < 0)
2076                 return;
2077
2078         device_remove_file(&info->dev->pdev->dev, &info->port_attr);
2079         device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr);
2080 }
2081
2082 static int mlx4_init_steering(struct mlx4_dev *dev)
2083 {
2084         struct mlx4_priv *priv = mlx4_priv(dev);
2085         int num_entries = dev->caps.num_ports;
2086         int i, j;
2087
2088         priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
2089         if (!priv->steer)
2090                 return -ENOMEM;
2091
2092         for (i = 0; i < num_entries; i++)
2093                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2094                         INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
2095                         INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
2096                 }
2097         return 0;
2098 }
2099
2100 static void mlx4_clear_steering(struct mlx4_dev *dev)
2101 {
2102         struct mlx4_priv *priv = mlx4_priv(dev);
2103         struct mlx4_steer_index *entry, *tmp_entry;
2104         struct mlx4_promisc_qp *pqp, *tmp_pqp;
2105         int num_entries = dev->caps.num_ports;
2106         int i, j;
2107
2108         for (i = 0; i < num_entries; i++) {
2109                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2110                         list_for_each_entry_safe(pqp, tmp_pqp,
2111                                                  &priv->steer[i].promisc_qps[j],
2112                                                  list) {
2113                                 list_del(&pqp->list);
2114                                 kfree(pqp);
2115                         }
2116                         list_for_each_entry_safe(entry, tmp_entry,
2117                                                  &priv->steer[i].steer_entries[j],
2118                                                  list) {
2119                                 list_del(&entry->list);
2120                                 list_for_each_entry_safe(pqp, tmp_pqp,
2121                                                          &entry->duplicates,
2122                                                          list) {
2123                                         list_del(&pqp->list);
2124                                         kfree(pqp);
2125                                 }
2126                                 kfree(entry);
2127                         }
2128                 }
2129         }
2130         kfree(priv->steer);
2131 }
2132
2133 static int extended_func_num(struct pci_dev *pdev)
2134 {
2135         return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
2136 }
2137
2138 #define MLX4_OWNER_BASE 0x8069c
2139 #define MLX4_OWNER_SIZE 4
2140
2141 static int mlx4_get_ownership(struct mlx4_dev *dev)
2142 {
2143         void __iomem *owner;
2144         u32 ret;
2145
2146         if (pci_channel_offline(dev->pdev))
2147                 return -EIO;
2148
2149         owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2150                         MLX4_OWNER_SIZE);
2151         if (!owner) {
2152                 mlx4_err(dev, "Failed to obtain ownership bit\n");
2153                 return -ENOMEM;
2154         }
2155
2156         ret = readl(owner);
2157         iounmap(owner);
2158         return (int) !!ret;
2159 }
2160
2161 static void mlx4_free_ownership(struct mlx4_dev *dev)
2162 {
2163         void __iomem *owner;
2164
2165         if (pci_channel_offline(dev->pdev))
2166                 return;
2167
2168         owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2169                         MLX4_OWNER_SIZE);
2170         if (!owner) {
2171                 mlx4_err(dev, "Failed to obtain ownership bit\n");
2172                 return;
2173         }
2174         writel(0, owner);
2175         msleep(1000);
2176         iounmap(owner);
2177 }
2178
2179 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data)
2180 {
2181         struct mlx4_priv *priv;
2182         struct mlx4_dev *dev;
2183         int err;
2184         int port;
2185
2186         pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
2187
2188         err = pci_enable_device(pdev);
2189         if (err) {
2190                 dev_err(&pdev->dev, "Cannot enable PCI device, "
2191                         "aborting.\n");
2192                 return err;
2193         }
2194
2195         /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
2196          * per port, we must limit the number of VFs to 63 (since their are
2197          * 128 MACs)
2198          */
2199         if (num_vfs >= MLX4_MAX_NUM_VF) {
2200                 dev_err(&pdev->dev,
2201                         "Requested more VF's (%d) than allowed (%d)\n",
2202                         num_vfs, MLX4_MAX_NUM_VF - 1);
2203                 return -EINVAL;
2204         }
2205
2206         if (num_vfs < 0) {
2207                 pr_err("num_vfs module parameter cannot be negative\n");
2208                 return -EINVAL;
2209         }
2210         /*
2211          * Check for BARs.
2212          */
2213         if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
2214             !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2215                 dev_err(&pdev->dev, "Missing DCS, aborting."
2216                         "(driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
2217                         pci_dev_data, pci_resource_flags(pdev, 0));
2218                 err = -ENODEV;
2219                 goto err_disable_pdev;
2220         }
2221         if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
2222                 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
2223                 err = -ENODEV;
2224                 goto err_disable_pdev;
2225         }
2226
2227         err = pci_request_regions(pdev, DRV_NAME);
2228         if (err) {
2229                 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
2230                 goto err_disable_pdev;
2231         }
2232
2233         pci_set_master(pdev);
2234
2235         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
2236         if (err) {
2237                 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
2238                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2239                 if (err) {
2240                         dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
2241                         goto err_release_regions;
2242                 }
2243         }
2244         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
2245         if (err) {
2246                 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
2247                          "consistent PCI DMA mask.\n");
2248                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2249                 if (err) {
2250                         dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
2251                                 "aborting.\n");
2252                         goto err_release_regions;
2253                 }
2254         }
2255
2256         /* Allow large DMA segments, up to the firmware limit of 1 GB */
2257         dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
2258
2259         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
2260         if (!priv) {
2261                 err = -ENOMEM;
2262                 goto err_release_regions;
2263         }
2264
2265         dev       = &priv->dev;
2266         dev->pdev = pdev;
2267         INIT_LIST_HEAD(&priv->ctx_list);
2268         spin_lock_init(&priv->ctx_lock);
2269
2270         mutex_init(&priv->port_mutex);
2271
2272         INIT_LIST_HEAD(&priv->pgdir_list);
2273         mutex_init(&priv->pgdir_mutex);
2274
2275         INIT_LIST_HEAD(&priv->bf_list);
2276         mutex_init(&priv->bf_mutex);
2277
2278         dev->rev_id = pdev->revision;
2279         dev->numa_node = dev_to_node(&pdev->dev);
2280         /* Detect if this device is a virtual function */
2281         if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
2282                 /* When acting as pf, we normally skip vfs unless explicitly
2283                  * requested to probe them. */
2284                 if (num_vfs && extended_func_num(pdev) > probe_vf) {
2285                         mlx4_warn(dev, "Skipping virtual function:%d\n",
2286                                                 extended_func_num(pdev));
2287                         err = -ENODEV;
2288                         goto err_free_dev;
2289                 }
2290                 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
2291                 dev->flags |= MLX4_FLAG_SLAVE;
2292         } else {
2293                 /* We reset the device and enable SRIOV only for physical
2294                  * devices.  Try to claim ownership on the device;
2295                  * if already taken, skip -- do not allow multiple PFs */
2296                 err = mlx4_get_ownership(dev);
2297                 if (err) {
2298                         if (err < 0)
2299                                 goto err_free_dev;
2300                         else {
2301                                 mlx4_warn(dev, "Multiple PFs not yet supported."
2302                                           " Skipping PF.\n");
2303                                 err = -EINVAL;
2304                                 goto err_free_dev;
2305                         }
2306                 }
2307
2308                 if (num_vfs) {
2309                         mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", num_vfs);
2310                         err = pci_enable_sriov(pdev, num_vfs);
2311                         if (err) {
2312                                 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d).\n",
2313                                          err);
2314                                 err = 0;
2315                         } else {
2316                                 mlx4_warn(dev, "Running in master mode\n");
2317                                 dev->flags |= MLX4_FLAG_SRIOV |
2318                                               MLX4_FLAG_MASTER;
2319                                 dev->num_vfs = num_vfs;
2320                         }
2321                 }
2322
2323                 atomic_set(&priv->opreq_count, 0);
2324                 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
2325
2326                 /*
2327                  * Now reset the HCA before we touch the PCI capabilities or
2328                  * attempt a firmware command, since a boot ROM may have left
2329                  * the HCA in an undefined state.
2330                  */
2331                 err = mlx4_reset(dev);
2332                 if (err) {
2333                         mlx4_err(dev, "Failed to reset HCA, aborting.\n");
2334                         goto err_rel_own;
2335                 }
2336         }
2337
2338 slave_start:
2339         err = mlx4_cmd_init(dev);
2340         if (err) {
2341                 mlx4_err(dev, "Failed to init command interface, aborting.\n");
2342                 goto err_sriov;
2343         }
2344
2345         /* In slave functions, the communication channel must be initialized
2346          * before posting commands. Also, init num_slaves before calling
2347          * mlx4_init_hca */
2348         if (mlx4_is_mfunc(dev)) {
2349                 if (mlx4_is_master(dev))
2350                         dev->num_slaves = MLX4_MAX_NUM_SLAVES;
2351                 else {
2352                         dev->num_slaves = 0;
2353                         err = mlx4_multi_func_init(dev);
2354                         if (err) {
2355                                 mlx4_err(dev, "Failed to init slave mfunc"
2356                                          " interface, aborting.\n");
2357                                 goto err_cmd;
2358                         }
2359                 }
2360         }
2361
2362         err = mlx4_init_hca(dev);
2363         if (err) {
2364                 if (err == -EACCES) {
2365                         /* Not primary Physical function
2366                          * Running in slave mode */
2367                         mlx4_cmd_cleanup(dev);
2368                         dev->flags |= MLX4_FLAG_SLAVE;
2369                         dev->flags &= ~MLX4_FLAG_MASTER;
2370                         goto slave_start;
2371                 } else
2372                         goto err_mfunc;
2373         }
2374
2375         /* check if the device is functioning at its maximum possible speed.
2376          * No return code for this call, just warn the user in case of PCI
2377          * express device capabilities are under-satisfied by the bus.
2378          */
2379         mlx4_check_pcie_caps(dev);
2380
2381         /* In master functions, the communication channel must be initialized
2382          * after obtaining its address from fw */
2383         if (mlx4_is_master(dev)) {
2384                 err = mlx4_multi_func_init(dev);
2385                 if (err) {
2386                         mlx4_err(dev, "Failed to init master mfunc"
2387                                  "interface, aborting.\n");
2388                         goto err_close;
2389                 }
2390         }
2391
2392         err = mlx4_alloc_eq_table(dev);
2393         if (err)
2394                 goto err_master_mfunc;
2395
2396         priv->msix_ctl.pool_bm = 0;
2397         mutex_init(&priv->msix_ctl.pool_lock);
2398
2399         mlx4_enable_msi_x(dev);
2400         if ((mlx4_is_mfunc(dev)) &&
2401             !(dev->flags & MLX4_FLAG_MSI_X)) {
2402                 err = -ENOSYS;
2403                 mlx4_err(dev, "INTx is not supported in multi-function mode."
2404                          " aborting.\n");
2405                 goto err_free_eq;
2406         }
2407
2408         if (!mlx4_is_slave(dev)) {
2409                 err = mlx4_init_steering(dev);
2410                 if (err)
2411                         goto err_free_eq;
2412         }
2413
2414         err = mlx4_setup_hca(dev);
2415         if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
2416             !mlx4_is_mfunc(dev)) {
2417                 dev->flags &= ~MLX4_FLAG_MSI_X;
2418                 dev->caps.num_comp_vectors = 1;
2419                 dev->caps.comp_pool        = 0;
2420                 pci_disable_msix(pdev);
2421                 err = mlx4_setup_hca(dev);
2422         }
2423
2424         if (err)
2425                 goto err_steer;
2426
2427         mlx4_init_quotas(dev);
2428
2429         for (port = 1; port <= dev->caps.num_ports; port++) {
2430                 err = mlx4_init_port_info(dev, port);
2431                 if (err)
2432                         goto err_port;
2433         }
2434
2435         err = mlx4_register_device(dev);
2436         if (err)
2437                 goto err_port;
2438
2439         mlx4_request_modules(dev);
2440
2441         mlx4_sense_init(dev);
2442         mlx4_start_sense(dev);
2443
2444         priv->pci_dev_data = pci_dev_data;
2445         pci_set_drvdata(pdev, dev);
2446
2447         return 0;
2448
2449 err_port:
2450         for (--port; port >= 1; --port)
2451                 mlx4_cleanup_port_info(&priv->port[port]);
2452
2453         mlx4_cleanup_counters_table(dev);
2454         mlx4_cleanup_qp_table(dev);
2455         mlx4_cleanup_srq_table(dev);
2456         mlx4_cleanup_cq_table(dev);
2457         mlx4_cmd_use_polling(dev);
2458         mlx4_cleanup_eq_table(dev);
2459         mlx4_cleanup_mcg_table(dev);
2460         mlx4_cleanup_mr_table(dev);
2461         mlx4_cleanup_xrcd_table(dev);
2462         mlx4_cleanup_pd_table(dev);
2463         mlx4_cleanup_uar_table(dev);
2464
2465 err_steer:
2466         if (!mlx4_is_slave(dev))
2467                 mlx4_clear_steering(dev);
2468
2469 err_free_eq:
2470         mlx4_free_eq_table(dev);
2471
2472 err_master_mfunc:
2473         if (mlx4_is_master(dev))
2474                 mlx4_multi_func_cleanup(dev);
2475
2476 err_close:
2477         if (dev->flags & MLX4_FLAG_MSI_X)
2478                 pci_disable_msix(pdev);
2479
2480         mlx4_close_hca(dev);
2481
2482 err_mfunc:
2483         if (mlx4_is_slave(dev))
2484                 mlx4_multi_func_cleanup(dev);
2485
2486 err_cmd:
2487         mlx4_cmd_cleanup(dev);
2488
2489 err_sriov:
2490         if (dev->flags & MLX4_FLAG_SRIOV)
2491                 pci_disable_sriov(pdev);
2492
2493 err_rel_own:
2494         if (!mlx4_is_slave(dev))
2495                 mlx4_free_ownership(dev);
2496
2497 err_free_dev:
2498         kfree(priv);
2499
2500 err_release_regions:
2501         pci_release_regions(pdev);
2502
2503 err_disable_pdev:
2504         pci_disable_device(pdev);
2505         pci_set_drvdata(pdev, NULL);
2506         return err;
2507 }
2508
2509 static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
2510 {
2511         printk_once(KERN_INFO "%s", mlx4_version);
2512
2513         return __mlx4_init_one(pdev, id->driver_data);
2514 }
2515
2516 static void mlx4_remove_one(struct pci_dev *pdev)
2517 {
2518         struct mlx4_dev  *dev  = pci_get_drvdata(pdev);
2519         struct mlx4_priv *priv = mlx4_priv(dev);
2520         int p;
2521
2522         if (dev) {
2523                 /* in SRIOV it is not allowed to unload the pf's
2524                  * driver while there are alive vf's */
2525                 if (mlx4_is_master(dev)) {
2526                         if (mlx4_how_many_lives_vf(dev))
2527                                 printk(KERN_ERR "Removing PF when there are assigned VF's !!!\n");
2528                 }
2529                 mlx4_stop_sense(dev);
2530                 mlx4_unregister_device(dev);
2531
2532                 for (p = 1; p <= dev->caps.num_ports; p++) {
2533                         mlx4_cleanup_port_info(&priv->port[p]);
2534                         mlx4_CLOSE_PORT(dev, p);
2535                 }
2536
2537                 if (mlx4_is_master(dev))
2538                         mlx4_free_resource_tracker(dev,
2539                                                    RES_TR_FREE_SLAVES_ONLY);
2540
2541                 mlx4_cleanup_counters_table(dev);
2542                 mlx4_cleanup_qp_table(dev);
2543                 mlx4_cleanup_srq_table(dev);
2544                 mlx4_cleanup_cq_table(dev);
2545                 mlx4_cmd_use_polling(dev);
2546                 mlx4_cleanup_eq_table(dev);
2547                 mlx4_cleanup_mcg_table(dev);
2548                 mlx4_cleanup_mr_table(dev);
2549                 mlx4_cleanup_xrcd_table(dev);
2550                 mlx4_cleanup_pd_table(dev);
2551
2552                 if (mlx4_is_master(dev))
2553                         mlx4_free_resource_tracker(dev,
2554                                                    RES_TR_FREE_STRUCTS_ONLY);
2555
2556                 iounmap(priv->kar);
2557                 mlx4_uar_free(dev, &priv->driver_uar);
2558                 mlx4_cleanup_uar_table(dev);
2559                 if (!mlx4_is_slave(dev))
2560                         mlx4_clear_steering(dev);
2561                 mlx4_free_eq_table(dev);
2562                 if (mlx4_is_master(dev))
2563                         mlx4_multi_func_cleanup(dev);
2564                 mlx4_close_hca(dev);
2565                 if (mlx4_is_slave(dev))
2566                         mlx4_multi_func_cleanup(dev);
2567                 mlx4_cmd_cleanup(dev);
2568
2569                 if (dev->flags & MLX4_FLAG_MSI_X)
2570                         pci_disable_msix(pdev);
2571                 if (dev->flags & MLX4_FLAG_SRIOV) {
2572                         mlx4_warn(dev, "Disabling SR-IOV\n");
2573                         pci_disable_sriov(pdev);
2574                 }
2575
2576                 if (!mlx4_is_slave(dev))
2577                         mlx4_free_ownership(dev);
2578
2579                 kfree(dev->caps.qp0_tunnel);
2580                 kfree(dev->caps.qp0_proxy);
2581                 kfree(dev->caps.qp1_tunnel);
2582                 kfree(dev->caps.qp1_proxy);
2583
2584                 kfree(priv);
2585                 pci_release_regions(pdev);
2586                 pci_disable_device(pdev);
2587                 pci_set_drvdata(pdev, NULL);
2588         }
2589 }
2590
2591 int mlx4_restart_one(struct pci_dev *pdev)
2592 {
2593         struct mlx4_dev  *dev  = pci_get_drvdata(pdev);
2594         struct mlx4_priv *priv = mlx4_priv(dev);
2595         int               pci_dev_data;
2596
2597         pci_dev_data = priv->pci_dev_data;
2598         mlx4_remove_one(pdev);
2599         return __mlx4_init_one(pdev, pci_dev_data);
2600 }
2601
2602 static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
2603         /* MT25408 "Hermon" SDR */
2604         { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2605         /* MT25408 "Hermon" DDR */
2606         { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2607         /* MT25408 "Hermon" QDR */
2608         { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2609         /* MT25408 "Hermon" DDR PCIe gen2 */
2610         { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2611         /* MT25408 "Hermon" QDR PCIe gen2 */
2612         { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2613         /* MT25408 "Hermon" EN 10GigE */
2614         { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2615         /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
2616         { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2617         /* MT25458 ConnectX EN 10GBASE-T 10GigE */
2618         { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2619         /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
2620         { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2621         /* MT26468 ConnectX EN 10GigE PCIe gen2*/
2622         { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2623         /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
2624         { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2625         /* MT26478 ConnectX2 40GigE PCIe gen2 */
2626         { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2627         /* MT25400 Family [ConnectX-2 Virtual Function] */
2628         { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
2629         /* MT27500 Family [ConnectX-3] */
2630         { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
2631         /* MT27500 Family [ConnectX-3 Virtual Function] */
2632         { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
2633         { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
2634         { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
2635         { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
2636         { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
2637         { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
2638         { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
2639         { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
2640         { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
2641         { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
2642         { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
2643         { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
2644         { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
2645         { 0, }
2646 };
2647
2648 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
2649
2650 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
2651                                               pci_channel_state_t state)
2652 {
2653         mlx4_remove_one(pdev);
2654
2655         return state == pci_channel_io_perm_failure ?
2656                 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
2657 }
2658
2659 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
2660 {
2661         int ret = __mlx4_init_one(pdev, 0);
2662
2663         return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
2664 }
2665
2666 static const struct pci_error_handlers mlx4_err_handler = {
2667         .error_detected = mlx4_pci_err_detected,
2668         .slot_reset     = mlx4_pci_slot_reset,
2669 };
2670
2671 static struct pci_driver mlx4_driver = {
2672         .name           = DRV_NAME,
2673         .id_table       = mlx4_pci_table,
2674         .probe          = mlx4_init_one,
2675         .remove         = mlx4_remove_one,
2676         .err_handler    = &mlx4_err_handler,
2677 };
2678
2679 static int __init mlx4_verify_params(void)
2680 {
2681         if ((log_num_mac < 0) || (log_num_mac > 7)) {
2682                 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
2683                 return -1;
2684         }
2685
2686         if (log_num_vlan != 0)
2687                 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
2688                            MLX4_LOG_NUM_VLANS);
2689
2690         if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
2691                 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
2692                 return -1;
2693         }
2694
2695         /* Check if module param for ports type has legal combination */
2696         if (port_type_array[0] == false && port_type_array[1] == true) {
2697                 printk(KERN_WARNING "Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
2698                 port_type_array[0] = true;
2699         }
2700
2701         if (mlx4_log_num_mgm_entry_size != -1 &&
2702             (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
2703              mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE)) {
2704                 pr_warning("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not "
2705                            "in legal range (-1 or %d..%d)\n",
2706                            mlx4_log_num_mgm_entry_size,
2707                            MLX4_MIN_MGM_LOG_ENTRY_SIZE,
2708                            MLX4_MAX_MGM_LOG_ENTRY_SIZE);
2709                 return -1;
2710         }
2711
2712         return 0;
2713 }
2714
2715 static int __init mlx4_init(void)
2716 {
2717         int ret;
2718
2719         if (mlx4_verify_params())
2720                 return -EINVAL;
2721
2722         mlx4_catas_init();
2723
2724         mlx4_wq = create_singlethread_workqueue("mlx4");
2725         if (!mlx4_wq)
2726                 return -ENOMEM;
2727
2728         ret = pci_register_driver(&mlx4_driver);
2729         if (ret < 0)
2730                 destroy_workqueue(mlx4_wq);
2731         return ret < 0 ? ret : 0;
2732 }
2733
2734 static void __exit mlx4_cleanup(void)
2735 {
2736         pci_unregister_driver(&mlx4_driver);
2737         destroy_workqueue(mlx4_wq);
2738 }
2739
2740 module_init(mlx4_init);
2741 module_exit(mlx4_cleanup);