2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/errno.h>
39 #include <linux/pci.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/slab.h>
42 #include <linux/io-mapping.h>
43 #include <linux/delay.h>
44 #include <linux/kmod.h>
46 #include <linux/mlx4/device.h>
47 #include <linux/mlx4/doorbell.h>
53 MODULE_AUTHOR("Roland Dreier");
54 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
55 MODULE_LICENSE("Dual BSD/GPL");
56 MODULE_VERSION(DRV_VERSION);
58 struct workqueue_struct *mlx4_wq;
60 #ifdef CONFIG_MLX4_DEBUG
62 int mlx4_debug_level = 0;
63 module_param_named(debug_level, mlx4_debug_level, int, 0644);
64 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
66 #endif /* CONFIG_MLX4_DEBUG */
71 module_param(msi_x, int, 0444);
72 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
74 #else /* CONFIG_PCI_MSI */
78 #endif /* CONFIG_PCI_MSI */
80 static uint8_t num_vfs[3] = {0, 0, 0};
81 static int num_vfs_argc = 3;
82 module_param_array(num_vfs, byte , &num_vfs_argc, 0444);
83 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n"
84 "num_vfs=port1,port2,port1+2");
86 static uint8_t probe_vf[3] = {0, 0, 0};
87 static int probe_vfs_argc = 3;
88 module_param_array(probe_vf, byte, &probe_vfs_argc, 0444);
89 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n"
90 "probe_vf=port1,port2,port1+2");
92 int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
93 module_param_named(log_num_mgm_entry_size,
94 mlx4_log_num_mgm_entry_size, int, 0444);
95 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
96 " of qp per mcg, for example:"
97 " 10 gives 248.range: 7 <="
98 " log_num_mgm_entry_size <= 12."
99 " To activate device managed"
100 " flow steering when available, set to -1");
102 static bool enable_64b_cqe_eqe = true;
103 module_param(enable_64b_cqe_eqe, bool, 0444);
104 MODULE_PARM_DESC(enable_64b_cqe_eqe,
105 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
107 #define HCA_GLOBAL_CAP_MASK 0
109 #define PF_CONTEXT_BEHAVIOUR_MASK MLX4_FUNC_CAP_64B_EQE_CQE
111 static char mlx4_version[] =
112 DRV_NAME ": Mellanox ConnectX core driver v"
113 DRV_VERSION " (" DRV_RELDATE ")\n";
115 static struct mlx4_profile default_profile = {
118 .rdmarc_per_qp = 1 << 4,
122 .num_mtt = 1 << 20, /* It is really num mtt segements */
125 static int log_num_mac = 7;
126 module_param_named(log_num_mac, log_num_mac, int, 0444);
127 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
129 static int log_num_vlan;
130 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
131 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
132 /* Log2 max number of VLANs per ETH port (0-7) */
133 #define MLX4_LOG_NUM_VLANS 7
135 static bool use_prio;
136 module_param_named(use_prio, use_prio, bool, 0444);
137 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
140 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
141 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
142 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
144 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
145 static int arr_argc = 2;
146 module_param_array(port_type_array, int, &arr_argc, 0444);
147 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
148 "1 for IB, 2 for Ethernet");
150 struct mlx4_port_config {
151 struct list_head list;
152 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
153 struct pci_dev *pdev;
156 static atomic_t pf_loading = ATOMIC_INIT(0);
158 int mlx4_check_port_params(struct mlx4_dev *dev,
159 enum mlx4_port_type *port_type)
163 for (i = 0; i < dev->caps.num_ports - 1; i++) {
164 if (port_type[i] != port_type[i + 1]) {
165 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
166 mlx4_err(dev, "Only same port types supported "
167 "on this HCA, aborting.\n");
173 for (i = 0; i < dev->caps.num_ports; i++) {
174 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
175 mlx4_err(dev, "Requested port type for port %d is not "
176 "supported on this HCA\n", i + 1);
183 static void mlx4_set_port_mask(struct mlx4_dev *dev)
187 for (i = 1; i <= dev->caps.num_ports; ++i)
188 dev->caps.port_mask[i] = dev->caps.port_type[i];
191 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
196 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
198 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
202 if (dev_cap->min_page_sz > PAGE_SIZE) {
203 mlx4_err(dev, "HCA minimum page size of %d bigger than "
204 "kernel PAGE_SIZE of %ld, aborting.\n",
205 dev_cap->min_page_sz, PAGE_SIZE);
208 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
209 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
211 dev_cap->num_ports, MLX4_MAX_PORTS);
215 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
216 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
217 "PCI resource 2 size of 0x%llx, aborting.\n",
219 (unsigned long long) pci_resource_len(dev->pdev, 2));
223 dev->caps.num_ports = dev_cap->num_ports;
224 dev->phys_caps.num_phys_eqs = MLX4_MAX_EQ_NUM;
225 for (i = 1; i <= dev->caps.num_ports; ++i) {
226 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
227 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
228 dev->phys_caps.gid_phys_table_len[i] = dev_cap->max_gids[i];
229 dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i];
230 /* set gid and pkey table operating lengths by default
231 * to non-sriov values */
232 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
233 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
234 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
235 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
236 dev->caps.def_mac[i] = dev_cap->def_mac[i];
237 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
238 dev->caps.suggested_type[i] = dev_cap->suggested_type[i];
239 dev->caps.default_sense[i] = dev_cap->default_sense[i];
240 dev->caps.trans_type[i] = dev_cap->trans_type[i];
241 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i];
242 dev->caps.wavelength[i] = dev_cap->wavelength[i];
243 dev->caps.trans_code[i] = dev_cap->trans_code[i];
246 dev->caps.uar_page_size = PAGE_SIZE;
247 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
248 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
249 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
250 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
251 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
252 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
253 dev->caps.max_wqes = dev_cap->max_qp_sz;
254 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
255 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
256 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
257 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
258 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
259 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
261 * Subtract 1 from the limit because we need to allocate a
262 * spare CQE so the HCA HW can tell the difference between an
263 * empty CQ and a full CQ.
265 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
266 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
267 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
268 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
269 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
271 /* The first 128 UARs are used for EQ doorbells */
272 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars);
273 dev->caps.reserved_pds = dev_cap->reserved_pds;
274 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
275 dev_cap->reserved_xrcds : 0;
276 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
277 dev_cap->max_xrcds : 0;
278 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
280 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
281 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
282 dev->caps.flags = dev_cap->flags;
283 dev->caps.flags2 = dev_cap->flags2;
284 dev->caps.bmme_flags = dev_cap->bmme_flags;
285 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
286 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
287 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
288 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
290 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
291 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
292 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
293 /* Don't do sense port on multifunction devices (for now at least) */
294 if (mlx4_is_mfunc(dev))
295 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
297 dev->caps.log_num_macs = log_num_mac;
298 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
299 dev->caps.log_num_prios = use_prio ? 3 : 0;
301 for (i = 1; i <= dev->caps.num_ports; ++i) {
302 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
303 if (dev->caps.supported_type[i]) {
304 /* if only ETH is supported - assign ETH */
305 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
306 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
307 /* if only IB is supported, assign IB */
308 else if (dev->caps.supported_type[i] ==
310 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
312 /* if IB and ETH are supported, we set the port
313 * type according to user selection of port type;
314 * if user selected none, take the FW hint */
315 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
316 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
317 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
319 dev->caps.port_type[i] = port_type_array[i - 1];
323 * Link sensing is allowed on the port if 3 conditions are true:
324 * 1. Both protocols are supported on the port.
325 * 2. Different types are supported on the port
326 * 3. FW declared that it supports link sensing
328 mlx4_priv(dev)->sense.sense_allowed[i] =
329 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
330 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
331 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
334 * If "default_sense" bit is set, we move the port to "AUTO" mode
335 * and perform sense_port FW command to try and set the correct
336 * port type from beginning
338 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
339 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
340 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
341 mlx4_SENSE_PORT(dev, i, &sensed_port);
342 if (sensed_port != MLX4_PORT_TYPE_NONE)
343 dev->caps.port_type[i] = sensed_port;
345 dev->caps.possible_type[i] = dev->caps.port_type[i];
348 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
349 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
350 mlx4_warn(dev, "Requested number of MACs is too much "
351 "for port %d, reducing to %d.\n",
352 i, 1 << dev->caps.log_num_macs);
354 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
355 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
356 mlx4_warn(dev, "Requested number of VLANs is too much "
357 "for port %d, reducing to %d.\n",
358 i, 1 << dev->caps.log_num_vlans);
362 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
364 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
365 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
366 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
367 (1 << dev->caps.log_num_macs) *
368 (1 << dev->caps.log_num_vlans) *
369 (1 << dev->caps.log_num_prios) *
371 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
373 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
374 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
375 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
376 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
378 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
380 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
382 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
383 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
384 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
385 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
389 if ((dev->caps.flags &
390 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
392 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
397 static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,
398 enum pci_bus_speed *speed,
399 enum pcie_link_width *width)
401 u32 lnkcap1, lnkcap2;
404 #define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */
406 *speed = PCI_SPEED_UNKNOWN;
407 *width = PCIE_LNK_WIDTH_UNKNOWN;
409 err1 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP, &lnkcap1);
410 err2 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP2, &lnkcap2);
411 if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
412 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
413 *speed = PCIE_SPEED_8_0GT;
414 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
415 *speed = PCIE_SPEED_5_0GT;
416 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
417 *speed = PCIE_SPEED_2_5GT;
420 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
421 if (!lnkcap2) { /* pre-r3.0 */
422 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
423 *speed = PCIE_SPEED_5_0GT;
424 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
425 *speed = PCIE_SPEED_2_5GT;
429 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {
431 err2 ? err2 : -EINVAL;
436 static void mlx4_check_pcie_caps(struct mlx4_dev *dev)
438 enum pcie_link_width width, width_cap;
439 enum pci_bus_speed speed, speed_cap;
442 #define PCIE_SPEED_STR(speed) \
443 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
444 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
445 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
448 err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);
451 "Unable to determine PCIe device BW capabilities\n");
455 err = pcie_get_minimum_link(dev->pdev, &speed, &width);
456 if (err || speed == PCI_SPEED_UNKNOWN ||
457 width == PCIE_LNK_WIDTH_UNKNOWN) {
459 "Unable to determine PCI device chain minimum BW\n");
463 if (width != width_cap || speed != speed_cap)
465 "PCIe BW is different than device's capability\n");
467 mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",
468 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
469 mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",
474 /*The function checks if there are live vf, return the num of them*/
475 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
477 struct mlx4_priv *priv = mlx4_priv(dev);
478 struct mlx4_slave_state *s_state;
482 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
483 s_state = &priv->mfunc.master.slave_state[i];
484 if (s_state->active && s_state->last_cmd !=
485 MLX4_COMM_CMD_RESET) {
486 mlx4_warn(dev, "%s: slave: %d is still active\n",
494 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
496 u32 qk = MLX4_RESERVED_QKEY_BASE;
498 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
499 qpn < dev->phys_caps.base_proxy_sqpn)
502 if (qpn >= dev->phys_caps.base_tunnel_sqpn)
504 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
506 qk += qpn - dev->phys_caps.base_proxy_sqpn;
510 EXPORT_SYMBOL(mlx4_get_parav_qkey);
512 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
514 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
516 if (!mlx4_is_master(dev))
519 priv->virt2phys_pkey[slave][port - 1][i] = val;
521 EXPORT_SYMBOL(mlx4_sync_pkey_table);
523 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
525 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
527 if (!mlx4_is_master(dev))
530 priv->slave_node_guids[slave] = guid;
532 EXPORT_SYMBOL(mlx4_put_slave_node_guid);
534 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
536 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
538 if (!mlx4_is_master(dev))
541 return priv->slave_node_guids[slave];
543 EXPORT_SYMBOL(mlx4_get_slave_node_guid);
545 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
547 struct mlx4_priv *priv = mlx4_priv(dev);
548 struct mlx4_slave_state *s_slave;
550 if (!mlx4_is_master(dev))
553 s_slave = &priv->mfunc.master.slave_state[slave];
554 return !!s_slave->active;
556 EXPORT_SYMBOL(mlx4_is_slave_active);
558 static void slave_adjust_steering_mode(struct mlx4_dev *dev,
559 struct mlx4_dev_cap *dev_cap,
560 struct mlx4_init_hca_param *hca_param)
562 dev->caps.steering_mode = hca_param->steering_mode;
563 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
564 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
565 dev->caps.fs_log_max_ucast_qp_range_size =
566 dev_cap->fs_log_max_ucast_qp_range_size;
568 dev->caps.num_qp_per_mgm =
569 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
571 mlx4_dbg(dev, "Steering mode is: %s\n",
572 mlx4_steering_mode_str(dev->caps.steering_mode));
575 static int mlx4_slave_cap(struct mlx4_dev *dev)
579 struct mlx4_dev_cap dev_cap;
580 struct mlx4_func_cap func_cap;
581 struct mlx4_init_hca_param hca_param;
584 memset(&hca_param, 0, sizeof(hca_param));
585 err = mlx4_QUERY_HCA(dev, &hca_param);
587 mlx4_err(dev, "QUERY_HCA command failed, aborting.\n");
591 /*fail if the hca has an unknown capability */
592 if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) !=
593 HCA_GLOBAL_CAP_MASK) {
594 mlx4_err(dev, "Unknown hca global capabilities\n");
598 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
600 dev->caps.hca_core_clock = hca_param.hca_core_clock;
602 memset(&dev_cap, 0, sizeof(dev_cap));
603 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
604 err = mlx4_dev_cap(dev, &dev_cap);
606 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
610 err = mlx4_QUERY_FW(dev);
612 mlx4_err(dev, "QUERY_FW command failed: could not get FW version.\n");
614 page_size = ~dev->caps.page_size_cap + 1;
615 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
616 if (page_size > PAGE_SIZE) {
617 mlx4_err(dev, "HCA minimum page size of %d bigger than "
618 "kernel PAGE_SIZE of %ld, aborting.\n",
619 page_size, PAGE_SIZE);
623 /* slave gets uar page size from QUERY_HCA fw command */
624 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
626 /* TODO: relax this assumption */
627 if (dev->caps.uar_page_size != PAGE_SIZE) {
628 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
629 dev->caps.uar_page_size, PAGE_SIZE);
633 memset(&func_cap, 0, sizeof(func_cap));
634 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
636 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d).\n",
641 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
642 PF_CONTEXT_BEHAVIOUR_MASK) {
643 mlx4_err(dev, "Unknown pf context behaviour\n");
647 dev->caps.num_ports = func_cap.num_ports;
648 dev->quotas.qp = func_cap.qp_quota;
649 dev->quotas.srq = func_cap.srq_quota;
650 dev->quotas.cq = func_cap.cq_quota;
651 dev->quotas.mpt = func_cap.mpt_quota;
652 dev->quotas.mtt = func_cap.mtt_quota;
653 dev->caps.num_qps = 1 << hca_param.log_num_qps;
654 dev->caps.num_srqs = 1 << hca_param.log_num_srqs;
655 dev->caps.num_cqs = 1 << hca_param.log_num_cqs;
656 dev->caps.num_mpts = 1 << hca_param.log_mpt_sz;
657 dev->caps.num_eqs = func_cap.max_eq;
658 dev->caps.reserved_eqs = func_cap.reserved_eq;
659 dev->caps.num_pds = MLX4_NUM_PDS;
660 dev->caps.num_mgms = 0;
661 dev->caps.num_amgms = 0;
663 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
664 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
665 "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS);
669 dev->caps.qp0_qkey = kcalloc(dev->caps.num_ports, sizeof(u32), GFP_KERNEL);
670 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
671 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
672 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
673 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
675 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
676 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy ||
677 !dev->caps.qp0_qkey) {
682 for (i = 1; i <= dev->caps.num_ports; ++i) {
683 err = mlx4_QUERY_FUNC_CAP(dev, (u32) i, &func_cap);
685 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for"
686 " port %d, aborting (%d).\n", i, err);
689 dev->caps.qp0_qkey[i - 1] = func_cap.qp0_qkey;
690 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
691 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
692 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
693 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
694 dev->caps.port_mask[i] = dev->caps.port_type[i];
695 dev->caps.phys_port_id[i] = func_cap.phys_port_id;
696 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i,
697 &dev->caps.gid_table_len[i],
698 &dev->caps.pkey_table_len[i]))
702 if (dev->caps.uar_page_size * (dev->caps.num_uars -
703 dev->caps.reserved_uars) >
704 pci_resource_len(dev->pdev, 2)) {
705 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than "
706 "PCI resource 2 size of 0x%llx, aborting.\n",
707 dev->caps.uar_page_size * dev->caps.num_uars,
708 (unsigned long long) pci_resource_len(dev->pdev, 2));
712 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
713 dev->caps.eqe_size = 64;
714 dev->caps.eqe_factor = 1;
716 dev->caps.eqe_size = 32;
717 dev->caps.eqe_factor = 0;
720 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
721 dev->caps.cqe_size = 64;
722 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE;
724 dev->caps.cqe_size = 32;
727 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
728 mlx4_warn(dev, "Timestamping is not supported in slave mode.\n");
730 slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
735 kfree(dev->caps.qp0_qkey);
736 kfree(dev->caps.qp0_tunnel);
737 kfree(dev->caps.qp0_proxy);
738 kfree(dev->caps.qp1_tunnel);
739 kfree(dev->caps.qp1_proxy);
740 dev->caps.qp0_qkey = NULL;
741 dev->caps.qp0_tunnel = NULL;
742 dev->caps.qp0_proxy = NULL;
743 dev->caps.qp1_tunnel = NULL;
744 dev->caps.qp1_proxy = NULL;
749 static void mlx4_request_modules(struct mlx4_dev *dev)
752 int has_ib_port = false;
753 int has_eth_port = false;
754 #define EN_DRV_NAME "mlx4_en"
755 #define IB_DRV_NAME "mlx4_ib"
757 for (port = 1; port <= dev->caps.num_ports; port++) {
758 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
760 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
765 request_module_nowait(EN_DRV_NAME);
766 if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
767 request_module_nowait(IB_DRV_NAME);
771 * Change the port configuration of the device.
772 * Every user of this function must hold the port mutex.
774 int mlx4_change_port_types(struct mlx4_dev *dev,
775 enum mlx4_port_type *port_types)
781 for (port = 0; port < dev->caps.num_ports; port++) {
782 /* Change the port type only if the new type is different
783 * from the current, and not set to Auto */
784 if (port_types[port] != dev->caps.port_type[port + 1])
788 mlx4_unregister_device(dev);
789 for (port = 1; port <= dev->caps.num_ports; port++) {
790 mlx4_CLOSE_PORT(dev, port);
791 dev->caps.port_type[port] = port_types[port - 1];
792 err = mlx4_SET_PORT(dev, port, -1);
794 mlx4_err(dev, "Failed to set port %d, "
799 mlx4_set_port_mask(dev);
800 err = mlx4_register_device(dev);
802 mlx4_err(dev, "Failed to register device\n");
805 mlx4_request_modules(dev);
812 static ssize_t show_port_type(struct device *dev,
813 struct device_attribute *attr,
816 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
818 struct mlx4_dev *mdev = info->dev;
822 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
824 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
825 sprintf(buf, "auto (%s)\n", type);
827 sprintf(buf, "%s\n", type);
832 static ssize_t set_port_type(struct device *dev,
833 struct device_attribute *attr,
834 const char *buf, size_t count)
836 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
838 struct mlx4_dev *mdev = info->dev;
839 struct mlx4_priv *priv = mlx4_priv(mdev);
840 enum mlx4_port_type types[MLX4_MAX_PORTS];
841 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
845 if (!strcmp(buf, "ib\n"))
846 info->tmp_type = MLX4_PORT_TYPE_IB;
847 else if (!strcmp(buf, "eth\n"))
848 info->tmp_type = MLX4_PORT_TYPE_ETH;
849 else if (!strcmp(buf, "auto\n"))
850 info->tmp_type = MLX4_PORT_TYPE_AUTO;
852 mlx4_err(mdev, "%s is not supported port type\n", buf);
856 mlx4_stop_sense(mdev);
857 mutex_lock(&priv->port_mutex);
858 /* Possible type is always the one that was delivered */
859 mdev->caps.possible_type[info->port] = info->tmp_type;
861 for (i = 0; i < mdev->caps.num_ports; i++) {
862 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
863 mdev->caps.possible_type[i+1];
864 if (types[i] == MLX4_PORT_TYPE_AUTO)
865 types[i] = mdev->caps.port_type[i+1];
868 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
869 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
870 for (i = 1; i <= mdev->caps.num_ports; i++) {
871 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
872 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
878 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
879 "Set only 'eth' or 'ib' for both ports "
880 "(should be the same)\n");
884 mlx4_do_sense_ports(mdev, new_types, types);
886 err = mlx4_check_port_params(mdev, new_types);
890 /* We are about to apply the changes after the configuration
891 * was verified, no need to remember the temporary types
893 for (i = 0; i < mdev->caps.num_ports; i++)
894 priv->port[i + 1].tmp_type = 0;
896 err = mlx4_change_port_types(mdev, new_types);
899 mlx4_start_sense(mdev);
900 mutex_unlock(&priv->port_mutex);
901 return err ? err : count;
912 static inline int int_to_ibta_mtu(int mtu)
915 case 256: return IB_MTU_256;
916 case 512: return IB_MTU_512;
917 case 1024: return IB_MTU_1024;
918 case 2048: return IB_MTU_2048;
919 case 4096: return IB_MTU_4096;
924 static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
927 case IB_MTU_256: return 256;
928 case IB_MTU_512: return 512;
929 case IB_MTU_1024: return 1024;
930 case IB_MTU_2048: return 2048;
931 case IB_MTU_4096: return 4096;
936 static ssize_t show_port_ib_mtu(struct device *dev,
937 struct device_attribute *attr,
940 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
942 struct mlx4_dev *mdev = info->dev;
944 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
945 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
948 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
952 static ssize_t set_port_ib_mtu(struct device *dev,
953 struct device_attribute *attr,
954 const char *buf, size_t count)
956 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
958 struct mlx4_dev *mdev = info->dev;
959 struct mlx4_priv *priv = mlx4_priv(mdev);
960 int err, port, mtu, ibta_mtu = -1;
962 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
963 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
967 err = kstrtoint(buf, 0, &mtu);
969 ibta_mtu = int_to_ibta_mtu(mtu);
971 if (err || ibta_mtu < 0) {
972 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
976 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
978 mlx4_stop_sense(mdev);
979 mutex_lock(&priv->port_mutex);
980 mlx4_unregister_device(mdev);
981 for (port = 1; port <= mdev->caps.num_ports; port++) {
982 mlx4_CLOSE_PORT(mdev, port);
983 err = mlx4_SET_PORT(mdev, port, -1);
985 mlx4_err(mdev, "Failed to set port %d, "
990 err = mlx4_register_device(mdev);
992 mutex_unlock(&priv->port_mutex);
993 mlx4_start_sense(mdev);
994 return err ? err : count;
997 static int mlx4_load_fw(struct mlx4_dev *dev)
999 struct mlx4_priv *priv = mlx4_priv(dev);
1002 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
1003 GFP_HIGHUSER | __GFP_NOWARN, 0);
1004 if (!priv->fw.fw_icm) {
1005 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
1009 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1011 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
1015 err = mlx4_RUN_FW(dev);
1017 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
1027 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1031 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1034 struct mlx4_priv *priv = mlx4_priv(dev);
1038 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1040 ((u64) (MLX4_CMPT_TYPE_QP *
1041 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1042 cmpt_entry_sz, dev->caps.num_qps,
1043 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1048 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1050 ((u64) (MLX4_CMPT_TYPE_SRQ *
1051 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1052 cmpt_entry_sz, dev->caps.num_srqs,
1053 dev->caps.reserved_srqs, 0, 0);
1057 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1059 ((u64) (MLX4_CMPT_TYPE_CQ *
1060 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1061 cmpt_entry_sz, dev->caps.num_cqs,
1062 dev->caps.reserved_cqs, 0, 0);
1066 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
1068 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1070 ((u64) (MLX4_CMPT_TYPE_EQ *
1071 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1072 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
1079 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1082 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1085 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1091 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1092 struct mlx4_init_hca_param *init_hca, u64 icm_size)
1094 struct mlx4_priv *priv = mlx4_priv(dev);
1099 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1101 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
1105 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
1106 (unsigned long long) icm_size >> 10,
1107 (unsigned long long) aux_pages << 2);
1109 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
1110 GFP_HIGHUSER | __GFP_NOWARN, 0);
1111 if (!priv->fw.aux_icm) {
1112 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
1116 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1118 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
1122 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1124 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
1129 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
1131 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1132 init_hca->eqc_base, dev_cap->eqc_entry_sz,
1133 num_eqs, num_eqs, 0, 0);
1135 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
1136 goto err_unmap_cmpt;
1140 * Reserved MTT entries must be aligned up to a cacheline
1141 * boundary, since the FW will write to them, while the driver
1142 * writes to all other MTT entries. (The variable
1143 * dev->caps.mtt_entry_sz below is really the MTT segment
1144 * size, not the raw entry size)
1146 dev->caps.reserved_mtts =
1147 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1148 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1150 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1152 dev->caps.mtt_entry_sz,
1154 dev->caps.reserved_mtts, 1, 0);
1156 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
1160 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1161 init_hca->dmpt_base,
1162 dev_cap->dmpt_entry_sz,
1164 dev->caps.reserved_mrws, 1, 1);
1166 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
1170 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1172 dev_cap->qpc_entry_sz,
1174 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1177 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
1178 goto err_unmap_dmpt;
1181 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1182 init_hca->auxc_base,
1183 dev_cap->aux_entry_sz,
1185 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1188 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
1192 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1193 init_hca->altc_base,
1194 dev_cap->altc_entry_sz,
1196 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1199 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
1200 goto err_unmap_auxc;
1203 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1204 init_hca->rdmarc_base,
1205 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1207 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1210 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1211 goto err_unmap_altc;
1214 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1216 dev_cap->cqc_entry_sz,
1218 dev->caps.reserved_cqs, 0, 0);
1220 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
1221 goto err_unmap_rdmarc;
1224 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1225 init_hca->srqc_base,
1226 dev_cap->srq_entry_sz,
1228 dev->caps.reserved_srqs, 0, 0);
1230 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
1235 * For flow steering device managed mode it is required to use
1236 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1237 * required, but for simplicity just map the whole multicast
1238 * group table now. The table isn't very big and it's a lot
1239 * easier than trying to track ref counts.
1241 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
1243 mlx4_get_mgm_entry_size(dev),
1244 dev->caps.num_mgms + dev->caps.num_amgms,
1245 dev->caps.num_mgms + dev->caps.num_amgms,
1248 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
1255 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1258 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1261 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1264 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1267 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1270 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1273 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1276 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1279 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1282 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1283 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1284 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1285 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1288 mlx4_UNMAP_ICM_AUX(dev);
1291 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1296 static void mlx4_free_icms(struct mlx4_dev *dev)
1298 struct mlx4_priv *priv = mlx4_priv(dev);
1300 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1301 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1302 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1303 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1304 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1305 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1306 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1307 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1308 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1309 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1310 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1311 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1312 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1313 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1315 mlx4_UNMAP_ICM_AUX(dev);
1316 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1319 static void mlx4_slave_exit(struct mlx4_dev *dev)
1321 struct mlx4_priv *priv = mlx4_priv(dev);
1323 mutex_lock(&priv->cmd.slave_cmd_mutex);
1324 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
1325 mlx4_warn(dev, "Failed to close slave function.\n");
1326 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1329 static int map_bf_area(struct mlx4_dev *dev)
1331 struct mlx4_priv *priv = mlx4_priv(dev);
1332 resource_size_t bf_start;
1333 resource_size_t bf_len;
1336 if (!dev->caps.bf_reg_size)
1339 bf_start = pci_resource_start(dev->pdev, 2) +
1340 (dev->caps.num_uars << PAGE_SHIFT);
1341 bf_len = pci_resource_len(dev->pdev, 2) -
1342 (dev->caps.num_uars << PAGE_SHIFT);
1343 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1344 if (!priv->bf_mapping)
1350 static void unmap_bf_area(struct mlx4_dev *dev)
1352 if (mlx4_priv(dev)->bf_mapping)
1353 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1356 cycle_t mlx4_read_clock(struct mlx4_dev *dev)
1358 u32 clockhi, clocklo, clockhi1;
1361 struct mlx4_priv *priv = mlx4_priv(dev);
1363 for (i = 0; i < 10; i++) {
1364 clockhi = swab32(readl(priv->clock_mapping));
1365 clocklo = swab32(readl(priv->clock_mapping + 4));
1366 clockhi1 = swab32(readl(priv->clock_mapping));
1367 if (clockhi == clockhi1)
1371 cycles = (u64) clockhi << 32 | (u64) clocklo;
1375 EXPORT_SYMBOL_GPL(mlx4_read_clock);
1378 static int map_internal_clock(struct mlx4_dev *dev)
1380 struct mlx4_priv *priv = mlx4_priv(dev);
1382 priv->clock_mapping =
1383 ioremap(pci_resource_start(dev->pdev, priv->fw.clock_bar) +
1384 priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1386 if (!priv->clock_mapping)
1392 static void unmap_internal_clock(struct mlx4_dev *dev)
1394 struct mlx4_priv *priv = mlx4_priv(dev);
1396 if (priv->clock_mapping)
1397 iounmap(priv->clock_mapping);
1400 static void mlx4_close_hca(struct mlx4_dev *dev)
1402 unmap_internal_clock(dev);
1404 if (mlx4_is_slave(dev))
1405 mlx4_slave_exit(dev);
1407 mlx4_CLOSE_HCA(dev, 0);
1408 mlx4_free_icms(dev);
1410 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1414 static int mlx4_init_slave(struct mlx4_dev *dev)
1416 struct mlx4_priv *priv = mlx4_priv(dev);
1417 u64 dma = (u64) priv->mfunc.vhcr_dma;
1418 int ret_from_reset = 0;
1420 u32 cmd_channel_ver;
1422 if (atomic_read(&pf_loading)) {
1423 mlx4_warn(dev, "PF is not ready. Deferring probe\n");
1424 return -EPROBE_DEFER;
1427 mutex_lock(&priv->cmd.slave_cmd_mutex);
1428 priv->cmd.max_cmds = 1;
1429 mlx4_warn(dev, "Sending reset\n");
1430 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1432 /* if we are in the middle of flr the slave will try
1433 * NUM_OF_RESET_RETRIES times before leaving.*/
1434 if (ret_from_reset) {
1435 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1436 mlx4_warn(dev, "slave is currently in the "
1437 "middle of FLR. Deferring probe.\n");
1438 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1439 return -EPROBE_DEFER;
1444 /* check the driver version - the slave I/F revision
1445 * must match the master's */
1446 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1447 cmd_channel_ver = mlx4_comm_get_version();
1449 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1450 MLX4_COMM_GET_IF_REV(slave_read)) {
1451 mlx4_err(dev, "slave driver version is not supported"
1452 " by the master\n");
1456 mlx4_warn(dev, "Sending vhcr0\n");
1457 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1460 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1463 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1466 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1469 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1473 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
1474 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1478 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1482 for (i = 1; i <= dev->caps.num_ports; i++) {
1483 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
1484 dev->caps.gid_table_len[i] =
1485 mlx4_get_slave_num_gids(dev, 0, i);
1487 dev->caps.gid_table_len[i] = 1;
1488 dev->caps.pkey_table_len[i] =
1489 dev->phys_caps.pkey_phys_table_len[i] - 1;
1493 static int choose_log_fs_mgm_entry_size(int qp_per_entry)
1495 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
1497 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
1499 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
1503 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
1506 static void choose_steering_mode(struct mlx4_dev *dev,
1507 struct mlx4_dev_cap *dev_cap)
1509 if (mlx4_log_num_mgm_entry_size == -1 &&
1510 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
1511 (!mlx4_is_mfunc(dev) ||
1512 (dev_cap->fs_max_num_qp_per_entry >= (dev->num_vfs + 1))) &&
1513 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
1514 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
1515 dev->oper_log_mgm_entry_size =
1516 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
1517 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1518 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
1519 dev->caps.fs_log_max_ucast_qp_range_size =
1520 dev_cap->fs_log_max_ucast_qp_range_size;
1522 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
1523 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1524 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
1526 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
1528 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
1529 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1530 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags "
1531 "set to use B0 steering. Falling back to A0 steering mode.\n");
1533 dev->oper_log_mgm_entry_size =
1534 mlx4_log_num_mgm_entry_size > 0 ?
1535 mlx4_log_num_mgm_entry_size :
1536 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
1537 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
1539 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, "
1540 "modparam log_num_mgm_entry_size = %d\n",
1541 mlx4_steering_mode_str(dev->caps.steering_mode),
1542 dev->oper_log_mgm_entry_size,
1543 mlx4_log_num_mgm_entry_size);
1546 static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
1547 struct mlx4_dev_cap *dev_cap)
1549 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
1550 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS)
1551 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
1553 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
1555 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode
1556 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
1559 static int mlx4_init_hca(struct mlx4_dev *dev)
1561 struct mlx4_priv *priv = mlx4_priv(dev);
1562 struct mlx4_adapter adapter;
1563 struct mlx4_dev_cap dev_cap;
1564 struct mlx4_mod_stat_cfg mlx4_cfg;
1565 struct mlx4_profile profile;
1566 struct mlx4_init_hca_param init_hca;
1570 if (!mlx4_is_slave(dev)) {
1571 err = mlx4_QUERY_FW(dev);
1574 mlx4_info(dev, "non-primary physical function, skipping.\n");
1576 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
1580 err = mlx4_load_fw(dev);
1582 mlx4_err(dev, "Failed to start FW, aborting.\n");
1586 mlx4_cfg.log_pg_sz_m = 1;
1587 mlx4_cfg.log_pg_sz = 0;
1588 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1590 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
1592 err = mlx4_dev_cap(dev, &dev_cap);
1594 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
1598 choose_steering_mode(dev, &dev_cap);
1599 choose_tunnel_offload_mode(dev, &dev_cap);
1601 err = mlx4_get_phys_port_id(dev);
1603 mlx4_err(dev, "Fail to get physical port id\n");
1605 if (mlx4_is_master(dev))
1606 mlx4_parav_master_pf_caps(dev);
1608 profile = default_profile;
1609 if (dev->caps.steering_mode ==
1610 MLX4_STEERING_MODE_DEVICE_MANAGED)
1611 profile.num_mcg = MLX4_FS_NUM_MCG;
1613 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
1615 if ((long long) icm_size < 0) {
1620 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
1622 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
1623 init_hca.uar_page_sz = PAGE_SHIFT - 12;
1624 init_hca.mw_enabled = 0;
1625 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
1626 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
1627 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
1629 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
1633 err = mlx4_INIT_HCA(dev, &init_hca);
1635 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
1639 * If TS is supported by FW
1640 * read HCA frequency by QUERY_HCA command
1642 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1643 memset(&init_hca, 0, sizeof(init_hca));
1644 err = mlx4_QUERY_HCA(dev, &init_hca);
1646 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp.\n");
1647 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1649 dev->caps.hca_core_clock =
1650 init_hca.hca_core_clock;
1653 /* In case we got HCA frequency 0 - disable timestamping
1654 * to avoid dividing by zero
1656 if (!dev->caps.hca_core_clock) {
1657 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1659 "HCA frequency is 0. Timestamping is not supported.");
1660 } else if (map_internal_clock(dev)) {
1662 * Map internal clock,
1663 * in case of failure disable timestamping
1665 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1666 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported.\n");
1670 err = mlx4_init_slave(dev);
1672 if (err != -EPROBE_DEFER)
1673 mlx4_err(dev, "Failed to initialize slave\n");
1677 err = mlx4_slave_cap(dev);
1679 mlx4_err(dev, "Failed to obtain slave caps\n");
1684 if (map_bf_area(dev))
1685 mlx4_dbg(dev, "Failed to map blue flame area\n");
1687 /*Only the master set the ports, all the rest got it from it.*/
1688 if (!mlx4_is_slave(dev))
1689 mlx4_set_port_mask(dev);
1691 err = mlx4_QUERY_ADAPTER(dev, &adapter);
1693 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
1697 priv->eq_table.inta_pin = adapter.inta_pin;
1698 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
1703 unmap_internal_clock(dev);
1706 if (mlx4_is_slave(dev)) {
1707 kfree(dev->caps.qp0_qkey);
1708 kfree(dev->caps.qp0_tunnel);
1709 kfree(dev->caps.qp0_proxy);
1710 kfree(dev->caps.qp1_tunnel);
1711 kfree(dev->caps.qp1_proxy);
1715 if (mlx4_is_slave(dev))
1716 mlx4_slave_exit(dev);
1718 mlx4_CLOSE_HCA(dev, 0);
1721 if (!mlx4_is_slave(dev))
1722 mlx4_free_icms(dev);
1725 if (!mlx4_is_slave(dev)) {
1727 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1732 static int mlx4_init_counters_table(struct mlx4_dev *dev)
1734 struct mlx4_priv *priv = mlx4_priv(dev);
1737 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1740 nent = dev->caps.max_counters;
1741 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
1744 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
1746 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
1749 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1751 struct mlx4_priv *priv = mlx4_priv(dev);
1753 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1756 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
1763 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1768 if (mlx4_is_mfunc(dev)) {
1769 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
1770 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
1771 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1773 *idx = get_param_l(&out_param);
1777 return __mlx4_counter_alloc(dev, idx);
1779 EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
1781 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1783 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
1787 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1791 if (mlx4_is_mfunc(dev)) {
1792 set_param_l(&in_param, idx);
1793 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
1794 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
1798 __mlx4_counter_free(dev, idx);
1800 EXPORT_SYMBOL_GPL(mlx4_counter_free);
1802 static int mlx4_setup_hca(struct mlx4_dev *dev)
1804 struct mlx4_priv *priv = mlx4_priv(dev);
1807 __be32 ib_port_default_caps;
1809 err = mlx4_init_uar_table(dev);
1811 mlx4_err(dev, "Failed to initialize "
1812 "user access region table, aborting.\n");
1816 err = mlx4_uar_alloc(dev, &priv->driver_uar);
1818 mlx4_err(dev, "Failed to allocate driver access region, "
1820 goto err_uar_table_free;
1823 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
1825 mlx4_err(dev, "Couldn't map kernel access region, "
1831 err = mlx4_init_pd_table(dev);
1833 mlx4_err(dev, "Failed to initialize "
1834 "protection domain table, aborting.\n");
1838 err = mlx4_init_xrcd_table(dev);
1840 mlx4_err(dev, "Failed to initialize "
1841 "reliable connection domain table, aborting.\n");
1842 goto err_pd_table_free;
1845 err = mlx4_init_mr_table(dev);
1847 mlx4_err(dev, "Failed to initialize "
1848 "memory region table, aborting.\n");
1849 goto err_xrcd_table_free;
1852 if (!mlx4_is_slave(dev)) {
1853 err = mlx4_init_mcg_table(dev);
1855 mlx4_err(dev, "Failed to initialize multicast group table, aborting.\n");
1856 goto err_mr_table_free;
1860 err = mlx4_init_eq_table(dev);
1862 mlx4_err(dev, "Failed to initialize "
1863 "event queue table, aborting.\n");
1864 goto err_mcg_table_free;
1867 err = mlx4_cmd_use_events(dev);
1869 mlx4_err(dev, "Failed to switch to event-driven "
1870 "firmware commands, aborting.\n");
1871 goto err_eq_table_free;
1874 err = mlx4_NOP(dev);
1876 if (dev->flags & MLX4_FLAG_MSI_X) {
1877 mlx4_warn(dev, "NOP command failed to generate MSI-X "
1878 "interrupt IRQ %d).\n",
1879 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1880 mlx4_warn(dev, "Trying again without MSI-X.\n");
1882 mlx4_err(dev, "NOP command failed to generate interrupt "
1883 "(IRQ %d), aborting.\n",
1884 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1885 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
1891 mlx4_dbg(dev, "NOP command IRQ test passed\n");
1893 err = mlx4_init_cq_table(dev);
1895 mlx4_err(dev, "Failed to initialize "
1896 "completion queue table, aborting.\n");
1900 err = mlx4_init_srq_table(dev);
1902 mlx4_err(dev, "Failed to initialize "
1903 "shared receive queue table, aborting.\n");
1904 goto err_cq_table_free;
1907 err = mlx4_init_qp_table(dev);
1909 mlx4_err(dev, "Failed to initialize "
1910 "queue pair table, aborting.\n");
1911 goto err_srq_table_free;
1914 err = mlx4_init_counters_table(dev);
1915 if (err && err != -ENOENT) {
1916 mlx4_err(dev, "Failed to initialize counters table, aborting.\n");
1917 goto err_qp_table_free;
1920 if (!mlx4_is_slave(dev)) {
1921 for (port = 1; port <= dev->caps.num_ports; port++) {
1922 ib_port_default_caps = 0;
1923 err = mlx4_get_port_ib_caps(dev, port,
1924 &ib_port_default_caps);
1926 mlx4_warn(dev, "failed to get port %d default "
1927 "ib capabilities (%d). Continuing "
1928 "with caps = 0\n", port, err);
1929 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
1931 /* initialize per-slave default ib port capabilities */
1932 if (mlx4_is_master(dev)) {
1934 for (i = 0; i < dev->num_slaves; i++) {
1935 if (i == mlx4_master_func_num(dev))
1937 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
1938 ib_port_default_caps;
1942 if (mlx4_is_mfunc(dev))
1943 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
1945 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
1947 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
1948 dev->caps.pkey_table_len[port] : -1);
1950 mlx4_err(dev, "Failed to set port %d, aborting\n",
1952 goto err_counters_table_free;
1959 err_counters_table_free:
1960 mlx4_cleanup_counters_table(dev);
1963 mlx4_cleanup_qp_table(dev);
1966 mlx4_cleanup_srq_table(dev);
1969 mlx4_cleanup_cq_table(dev);
1972 mlx4_cmd_use_polling(dev);
1975 mlx4_cleanup_eq_table(dev);
1978 if (!mlx4_is_slave(dev))
1979 mlx4_cleanup_mcg_table(dev);
1982 mlx4_cleanup_mr_table(dev);
1984 err_xrcd_table_free:
1985 mlx4_cleanup_xrcd_table(dev);
1988 mlx4_cleanup_pd_table(dev);
1994 mlx4_uar_free(dev, &priv->driver_uar);
1997 mlx4_cleanup_uar_table(dev);
2001 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
2003 struct mlx4_priv *priv = mlx4_priv(dev);
2004 struct msix_entry *entries;
2005 int nreq = min_t(int, dev->caps.num_ports *
2006 min_t(int, num_online_cpus() + 1,
2007 MAX_MSIX_P_PORT) + MSIX_LEGACY_SZ, MAX_MSIX);
2011 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
2014 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
2018 for (i = 0; i < nreq; ++i)
2019 entries[i].entry = i;
2021 nreq = pci_enable_msix_range(dev->pdev, entries, 2, nreq);
2026 } else if (nreq < MSIX_LEGACY_SZ +
2027 dev->caps.num_ports * MIN_MSIX_P_PORT) {
2028 /*Working in legacy mode , all EQ's shared*/
2029 dev->caps.comp_pool = 0;
2030 dev->caps.num_comp_vectors = nreq - 1;
2032 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
2033 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
2035 for (i = 0; i < nreq; ++i)
2036 priv->eq_table.eq[i].irq = entries[i].vector;
2038 dev->flags |= MLX4_FLAG_MSI_X;
2045 dev->caps.num_comp_vectors = 1;
2046 dev->caps.comp_pool = 0;
2048 for (i = 0; i < 2; ++i)
2049 priv->eq_table.eq[i].irq = dev->pdev->irq;
2052 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2054 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
2059 if (!mlx4_is_slave(dev)) {
2060 mlx4_init_mac_table(dev, &info->mac_table);
2061 mlx4_init_vlan_table(dev, &info->vlan_table);
2062 mlx4_init_roce_gid_table(dev, &info->gid_table);
2063 info->base_qpn = mlx4_get_base_qpn(dev, port);
2066 sprintf(info->dev_name, "mlx4_port%d", port);
2067 info->port_attr.attr.name = info->dev_name;
2068 if (mlx4_is_mfunc(dev))
2069 info->port_attr.attr.mode = S_IRUGO;
2071 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
2072 info->port_attr.store = set_port_type;
2074 info->port_attr.show = show_port_type;
2075 sysfs_attr_init(&info->port_attr.attr);
2077 err = device_create_file(&dev->pdev->dev, &info->port_attr);
2079 mlx4_err(dev, "Failed to create file for port %d\n", port);
2083 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
2084 info->port_mtu_attr.attr.name = info->dev_mtu_name;
2085 if (mlx4_is_mfunc(dev))
2086 info->port_mtu_attr.attr.mode = S_IRUGO;
2088 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
2089 info->port_mtu_attr.store = set_port_ib_mtu;
2091 info->port_mtu_attr.show = show_port_ib_mtu;
2092 sysfs_attr_init(&info->port_mtu_attr.attr);
2094 err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr);
2096 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
2097 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
2104 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
2109 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
2110 device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr);
2113 static int mlx4_init_steering(struct mlx4_dev *dev)
2115 struct mlx4_priv *priv = mlx4_priv(dev);
2116 int num_entries = dev->caps.num_ports;
2119 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
2123 for (i = 0; i < num_entries; i++)
2124 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2125 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
2126 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
2131 static void mlx4_clear_steering(struct mlx4_dev *dev)
2133 struct mlx4_priv *priv = mlx4_priv(dev);
2134 struct mlx4_steer_index *entry, *tmp_entry;
2135 struct mlx4_promisc_qp *pqp, *tmp_pqp;
2136 int num_entries = dev->caps.num_ports;
2139 for (i = 0; i < num_entries; i++) {
2140 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2141 list_for_each_entry_safe(pqp, tmp_pqp,
2142 &priv->steer[i].promisc_qps[j],
2144 list_del(&pqp->list);
2147 list_for_each_entry_safe(entry, tmp_entry,
2148 &priv->steer[i].steer_entries[j],
2150 list_del(&entry->list);
2151 list_for_each_entry_safe(pqp, tmp_pqp,
2154 list_del(&pqp->list);
2164 static int extended_func_num(struct pci_dev *pdev)
2166 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
2169 #define MLX4_OWNER_BASE 0x8069c
2170 #define MLX4_OWNER_SIZE 4
2172 static int mlx4_get_ownership(struct mlx4_dev *dev)
2174 void __iomem *owner;
2177 if (pci_channel_offline(dev->pdev))
2180 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2183 mlx4_err(dev, "Failed to obtain ownership bit\n");
2192 static void mlx4_free_ownership(struct mlx4_dev *dev)
2194 void __iomem *owner;
2196 if (pci_channel_offline(dev->pdev))
2199 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2202 mlx4_err(dev, "Failed to obtain ownership bit\n");
2210 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data)
2212 struct mlx4_priv *priv;
2213 struct mlx4_dev *dev;
2216 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
2217 int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0};
2218 const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = {
2219 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
2220 unsigned total_vfs = 0;
2221 int sriov_initialized = 0;
2224 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
2226 err = pci_enable_device(pdev);
2228 dev_err(&pdev->dev, "Cannot enable PCI device, "
2233 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
2234 * per port, we must limit the number of VFs to 63 (since their are
2237 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && i < num_vfs_argc;
2238 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) {
2239 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i];
2241 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n");
2245 for (i = 0; i < sizeof(prb_vf)/sizeof(prb_vf[0]) && i < probe_vfs_argc;
2247 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i];
2248 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) {
2249 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
2253 if (total_vfs >= MLX4_MAX_NUM_VF) {
2255 "Requested more VF's (%d) than allowed (%d)\n",
2256 total_vfs, MLX4_MAX_NUM_VF - 1);
2260 for (i = 0; i < MLX4_MAX_PORTS; i++) {
2261 if (nvfs[i] + nvfs[2] >= MLX4_MAX_NUM_VF_P_PORT) {
2263 "Requested more VF's (%d) for port (%d) than allowed (%d)\n",
2264 nvfs[i] + nvfs[2], i + 1,
2265 MLX4_MAX_NUM_VF_P_PORT - 1);
2274 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
2275 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2276 dev_err(&pdev->dev, "Missing DCS, aborting."
2277 "(driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
2278 pci_dev_data, pci_resource_flags(pdev, 0));
2280 goto err_disable_pdev;
2282 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
2283 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
2285 goto err_disable_pdev;
2288 err = pci_request_regions(pdev, DRV_NAME);
2290 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
2291 goto err_disable_pdev;
2294 pci_set_master(pdev);
2296 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
2298 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
2299 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2301 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
2302 goto err_release_regions;
2305 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
2307 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
2308 "consistent PCI DMA mask.\n");
2309 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2311 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
2313 goto err_release_regions;
2317 /* Allow large DMA segments, up to the firmware limit of 1 GB */
2318 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
2320 dev = pci_get_drvdata(pdev);
2321 priv = mlx4_priv(dev);
2323 INIT_LIST_HEAD(&priv->ctx_list);
2324 spin_lock_init(&priv->ctx_lock);
2326 mutex_init(&priv->port_mutex);
2328 INIT_LIST_HEAD(&priv->pgdir_list);
2329 mutex_init(&priv->pgdir_mutex);
2331 INIT_LIST_HEAD(&priv->bf_list);
2332 mutex_init(&priv->bf_mutex);
2334 dev->rev_id = pdev->revision;
2335 dev->numa_node = dev_to_node(&pdev->dev);
2336 /* Detect if this device is a virtual function */
2337 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
2338 /* When acting as pf, we normally skip vfs unless explicitly
2339 * requested to probe them. */
2341 unsigned vfs_offset = 0;
2342 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) &&
2343 vfs_offset + nvfs[i] < extended_func_num(pdev);
2344 vfs_offset += nvfs[i], i++)
2346 if (i == sizeof(nvfs)/sizeof(nvfs[0])) {
2350 if ((extended_func_num(pdev) - vfs_offset)
2352 mlx4_warn(dev, "Skipping virtual function:%d\n",
2353 extended_func_num(pdev));
2358 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
2359 dev->flags |= MLX4_FLAG_SLAVE;
2361 /* We reset the device and enable SRIOV only for physical
2362 * devices. Try to claim ownership on the device;
2363 * if already taken, skip -- do not allow multiple PFs */
2364 err = mlx4_get_ownership(dev);
2369 mlx4_warn(dev, "Multiple PFs not yet supported."
2377 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n",
2379 dev->dev_vfs = kzalloc(
2380 total_vfs * sizeof(*dev->dev_vfs),
2382 if (NULL == dev->dev_vfs) {
2383 mlx4_err(dev, "Failed to allocate memory for VFs\n");
2386 atomic_inc(&pf_loading);
2387 err = pci_enable_sriov(pdev, total_vfs);
2389 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d).\n",
2391 atomic_dec(&pf_loading);
2394 mlx4_warn(dev, "Running in master mode\n");
2395 dev->flags |= MLX4_FLAG_SRIOV |
2397 dev->num_vfs = total_vfs;
2398 sriov_initialized = 1;
2403 atomic_set(&priv->opreq_count, 0);
2404 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
2407 * Now reset the HCA before we touch the PCI capabilities or
2408 * attempt a firmware command, since a boot ROM may have left
2409 * the HCA in an undefined state.
2411 err = mlx4_reset(dev);
2413 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
2419 err = mlx4_cmd_init(dev);
2421 mlx4_err(dev, "Failed to init command interface, aborting.\n");
2425 /* In slave functions, the communication channel must be initialized
2426 * before posting commands. Also, init num_slaves before calling
2428 if (mlx4_is_mfunc(dev)) {
2429 if (mlx4_is_master(dev))
2430 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
2432 dev->num_slaves = 0;
2433 err = mlx4_multi_func_init(dev);
2435 mlx4_err(dev, "Failed to init slave mfunc"
2436 " interface, aborting.\n");
2442 err = mlx4_init_hca(dev);
2444 if (err == -EACCES) {
2445 /* Not primary Physical function
2446 * Running in slave mode */
2447 mlx4_cmd_cleanup(dev);
2448 dev->flags |= MLX4_FLAG_SLAVE;
2449 dev->flags &= ~MLX4_FLAG_MASTER;
2455 /* check if the device is functioning at its maximum possible speed.
2456 * No return code for this call, just warn the user in case of PCI
2457 * express device capabilities are under-satisfied by the bus.
2459 if (!mlx4_is_slave(dev))
2460 mlx4_check_pcie_caps(dev);
2462 /* In master functions, the communication channel must be initialized
2463 * after obtaining its address from fw */
2464 if (mlx4_is_master(dev)) {
2466 err = mlx4_multi_func_init(dev);
2468 mlx4_err(dev, "Failed to init master mfunc"
2469 "interface, aborting.\n");
2472 if (sriov_initialized) {
2474 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2478 (num_vfs_argc > 1 || probe_vfs_argc > 1)) {
2480 "Invalid syntax of num_vfs/probe_vfs "
2481 "with IB port. Single port VFs syntax"
2482 " is only supported when all ports "
2483 "are configured as ethernet\n");
2486 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]); i++) {
2488 for (j = 0; j < nvfs[i]; ++sum, ++j) {
2489 dev->dev_vfs[sum].min_port =
2491 dev->dev_vfs[sum].n_ports = i < 2 ? 1 :
2492 dev->caps.num_ports;
2498 err = mlx4_alloc_eq_table(dev);
2500 goto err_master_mfunc;
2502 priv->msix_ctl.pool_bm = 0;
2503 mutex_init(&priv->msix_ctl.pool_lock);
2505 mlx4_enable_msi_x(dev);
2506 if ((mlx4_is_mfunc(dev)) &&
2507 !(dev->flags & MLX4_FLAG_MSI_X)) {
2509 mlx4_err(dev, "INTx is not supported in multi-function mode."
2514 if (!mlx4_is_slave(dev)) {
2515 err = mlx4_init_steering(dev);
2520 err = mlx4_setup_hca(dev);
2521 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
2522 !mlx4_is_mfunc(dev)) {
2523 dev->flags &= ~MLX4_FLAG_MSI_X;
2524 dev->caps.num_comp_vectors = 1;
2525 dev->caps.comp_pool = 0;
2526 pci_disable_msix(pdev);
2527 err = mlx4_setup_hca(dev);
2533 mlx4_init_quotas(dev);
2535 for (port = 1; port <= dev->caps.num_ports; port++) {
2536 err = mlx4_init_port_info(dev, port);
2541 err = mlx4_register_device(dev);
2545 mlx4_request_modules(dev);
2547 mlx4_sense_init(dev);
2548 mlx4_start_sense(dev);
2552 if (mlx4_is_master(dev) && dev->num_vfs)
2553 atomic_dec(&pf_loading);
2558 for (--port; port >= 1; --port)
2559 mlx4_cleanup_port_info(&priv->port[port]);
2561 mlx4_cleanup_counters_table(dev);
2562 mlx4_cleanup_qp_table(dev);
2563 mlx4_cleanup_srq_table(dev);
2564 mlx4_cleanup_cq_table(dev);
2565 mlx4_cmd_use_polling(dev);
2566 mlx4_cleanup_eq_table(dev);
2567 mlx4_cleanup_mcg_table(dev);
2568 mlx4_cleanup_mr_table(dev);
2569 mlx4_cleanup_xrcd_table(dev);
2570 mlx4_cleanup_pd_table(dev);
2571 mlx4_cleanup_uar_table(dev);
2574 if (!mlx4_is_slave(dev))
2575 mlx4_clear_steering(dev);
2578 mlx4_free_eq_table(dev);
2581 if (mlx4_is_master(dev))
2582 mlx4_multi_func_cleanup(dev);
2584 if (mlx4_is_slave(dev)) {
2585 kfree(dev->caps.qp0_qkey);
2586 kfree(dev->caps.qp0_tunnel);
2587 kfree(dev->caps.qp0_proxy);
2588 kfree(dev->caps.qp1_tunnel);
2589 kfree(dev->caps.qp1_proxy);
2593 if (dev->flags & MLX4_FLAG_MSI_X)
2594 pci_disable_msix(pdev);
2596 mlx4_close_hca(dev);
2599 if (mlx4_is_slave(dev))
2600 mlx4_multi_func_cleanup(dev);
2603 mlx4_cmd_cleanup(dev);
2606 if (dev->flags & MLX4_FLAG_SRIOV)
2607 pci_disable_sriov(pdev);
2610 if (!mlx4_is_slave(dev))
2611 mlx4_free_ownership(dev);
2613 if (mlx4_is_master(dev) && dev->num_vfs)
2614 atomic_dec(&pf_loading);
2616 kfree(priv->dev.dev_vfs);
2621 err_release_regions:
2622 pci_release_regions(pdev);
2625 pci_disable_device(pdev);
2626 pci_set_drvdata(pdev, NULL);
2630 static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
2632 struct mlx4_priv *priv;
2633 struct mlx4_dev *dev;
2635 printk_once(KERN_INFO "%s", mlx4_version);
2637 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
2642 pci_set_drvdata(pdev, dev);
2643 priv->pci_dev_data = id->driver_data;
2645 return __mlx4_init_one(pdev, id->driver_data);
2648 static void __mlx4_remove_one(struct pci_dev *pdev)
2650 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2651 struct mlx4_priv *priv = mlx4_priv(dev);
2658 pci_dev_data = priv->pci_dev_data;
2660 /* in SRIOV it is not allowed to unload the pf's
2661 * driver while there are alive vf's */
2662 if (mlx4_is_master(dev) && mlx4_how_many_lives_vf(dev))
2663 printk(KERN_ERR "Removing PF when there are assigned VF's !!!\n");
2664 mlx4_stop_sense(dev);
2665 mlx4_unregister_device(dev);
2667 for (p = 1; p <= dev->caps.num_ports; p++) {
2668 mlx4_cleanup_port_info(&priv->port[p]);
2669 mlx4_CLOSE_PORT(dev, p);
2672 if (mlx4_is_master(dev))
2673 mlx4_free_resource_tracker(dev,
2674 RES_TR_FREE_SLAVES_ONLY);
2676 mlx4_cleanup_counters_table(dev);
2677 mlx4_cleanup_qp_table(dev);
2678 mlx4_cleanup_srq_table(dev);
2679 mlx4_cleanup_cq_table(dev);
2680 mlx4_cmd_use_polling(dev);
2681 mlx4_cleanup_eq_table(dev);
2682 mlx4_cleanup_mcg_table(dev);
2683 mlx4_cleanup_mr_table(dev);
2684 mlx4_cleanup_xrcd_table(dev);
2685 mlx4_cleanup_pd_table(dev);
2687 if (mlx4_is_master(dev))
2688 mlx4_free_resource_tracker(dev,
2689 RES_TR_FREE_STRUCTS_ONLY);
2692 mlx4_uar_free(dev, &priv->driver_uar);
2693 mlx4_cleanup_uar_table(dev);
2694 if (!mlx4_is_slave(dev))
2695 mlx4_clear_steering(dev);
2696 mlx4_free_eq_table(dev);
2697 if (mlx4_is_master(dev))
2698 mlx4_multi_func_cleanup(dev);
2699 mlx4_close_hca(dev);
2700 if (mlx4_is_slave(dev))
2701 mlx4_multi_func_cleanup(dev);
2702 mlx4_cmd_cleanup(dev);
2704 if (dev->flags & MLX4_FLAG_MSI_X)
2705 pci_disable_msix(pdev);
2706 if (dev->flags & MLX4_FLAG_SRIOV) {
2707 mlx4_warn(dev, "Disabling SR-IOV\n");
2708 pci_disable_sriov(pdev);
2712 if (!mlx4_is_slave(dev))
2713 mlx4_free_ownership(dev);
2715 kfree(dev->caps.qp0_qkey);
2716 kfree(dev->caps.qp0_tunnel);
2717 kfree(dev->caps.qp0_proxy);
2718 kfree(dev->caps.qp1_tunnel);
2719 kfree(dev->caps.qp1_proxy);
2720 kfree(dev->dev_vfs);
2722 pci_release_regions(pdev);
2723 pci_disable_device(pdev);
2724 memset(priv, 0, sizeof(*priv));
2725 priv->pci_dev_data = pci_dev_data;
2729 static void mlx4_remove_one(struct pci_dev *pdev)
2731 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2732 struct mlx4_priv *priv = mlx4_priv(dev);
2734 __mlx4_remove_one(pdev);
2736 pci_set_drvdata(pdev, NULL);
2739 int mlx4_restart_one(struct pci_dev *pdev)
2741 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2742 struct mlx4_priv *priv = mlx4_priv(dev);
2745 pci_dev_data = priv->pci_dev_data;
2746 __mlx4_remove_one(pdev);
2747 return __mlx4_init_one(pdev, pci_dev_data);
2750 static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
2751 /* MT25408 "Hermon" SDR */
2752 { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2753 /* MT25408 "Hermon" DDR */
2754 { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2755 /* MT25408 "Hermon" QDR */
2756 { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2757 /* MT25408 "Hermon" DDR PCIe gen2 */
2758 { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2759 /* MT25408 "Hermon" QDR PCIe gen2 */
2760 { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2761 /* MT25408 "Hermon" EN 10GigE */
2762 { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2763 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
2764 { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2765 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
2766 { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2767 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
2768 { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2769 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
2770 { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2771 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
2772 { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2773 /* MT26478 ConnectX2 40GigE PCIe gen2 */
2774 { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2775 /* MT25400 Family [ConnectX-2 Virtual Function] */
2776 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
2777 /* MT27500 Family [ConnectX-3] */
2778 { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
2779 /* MT27500 Family [ConnectX-3 Virtual Function] */
2780 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
2781 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
2782 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
2783 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
2784 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
2785 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
2786 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
2787 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
2788 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
2789 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
2790 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
2791 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
2792 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
2796 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
2798 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
2799 pci_channel_state_t state)
2801 __mlx4_remove_one(pdev);
2803 return state == pci_channel_io_perm_failure ?
2804 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
2807 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
2809 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2810 struct mlx4_priv *priv = mlx4_priv(dev);
2813 ret = __mlx4_init_one(pdev, priv->pci_dev_data);
2815 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
2818 static const struct pci_error_handlers mlx4_err_handler = {
2819 .error_detected = mlx4_pci_err_detected,
2820 .slot_reset = mlx4_pci_slot_reset,
2823 static struct pci_driver mlx4_driver = {
2825 .id_table = mlx4_pci_table,
2826 .probe = mlx4_init_one,
2827 .shutdown = mlx4_remove_one,
2828 .remove = mlx4_remove_one,
2829 .err_handler = &mlx4_err_handler,
2832 static int __init mlx4_verify_params(void)
2834 if ((log_num_mac < 0) || (log_num_mac > 7)) {
2835 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
2839 if (log_num_vlan != 0)
2840 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
2841 MLX4_LOG_NUM_VLANS);
2843 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
2844 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
2848 /* Check if module param for ports type has legal combination */
2849 if (port_type_array[0] == false && port_type_array[1] == true) {
2850 printk(KERN_WARNING "Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
2851 port_type_array[0] = true;
2854 if (mlx4_log_num_mgm_entry_size != -1 &&
2855 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
2856 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE)) {
2857 pr_warning("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not "
2858 "in legal range (-1 or %d..%d)\n",
2859 mlx4_log_num_mgm_entry_size,
2860 MLX4_MIN_MGM_LOG_ENTRY_SIZE,
2861 MLX4_MAX_MGM_LOG_ENTRY_SIZE);
2868 static int __init mlx4_init(void)
2872 if (mlx4_verify_params())
2877 mlx4_wq = create_singlethread_workqueue("mlx4");
2881 ret = pci_register_driver(&mlx4_driver);
2883 destroy_workqueue(mlx4_wq);
2884 return ret < 0 ? ret : 0;
2887 static void __exit mlx4_cleanup(void)
2889 pci_unregister_driver(&mlx4_driver);
2890 destroy_workqueue(mlx4_wq);
2893 module_init(mlx4_init);
2894 module_exit(mlx4_cleanup);