2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/module.h>
37 #include <linux/kernel.h>
38 #include <linux/init.h>
39 #include <linux/errno.h>
40 #include <linux/pci.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/slab.h>
43 #include <linux/io-mapping.h>
44 #include <linux/delay.h>
45 #include <linux/kmod.h>
46 #include <linux/etherdevice.h>
47 #include <net/devlink.h>
49 #include <uapi/rdma/mlx4-abi.h>
50 #include <linux/mlx4/device.h>
51 #include <linux/mlx4/doorbell.h>
57 MODULE_AUTHOR("Roland Dreier");
58 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
59 MODULE_LICENSE("Dual BSD/GPL");
60 MODULE_VERSION(DRV_VERSION);
62 struct workqueue_struct *mlx4_wq;
64 #ifdef CONFIG_MLX4_DEBUG
66 int mlx4_debug_level = 0;
67 module_param_named(debug_level, mlx4_debug_level, int, 0644);
68 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
70 #endif /* CONFIG_MLX4_DEBUG */
75 module_param(msi_x, int, 0444);
76 MODULE_PARM_DESC(msi_x, "0 - don't use MSI-X, 1 - use MSI-X, >1 - limit number of MSI-X irqs to msi_x");
78 #else /* CONFIG_PCI_MSI */
82 #endif /* CONFIG_PCI_MSI */
84 static uint8_t num_vfs[3] = {0, 0, 0};
85 static int num_vfs_argc;
86 module_param_array(num_vfs, byte , &num_vfs_argc, 0444);
87 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n"
88 "num_vfs=port1,port2,port1+2");
90 static uint8_t probe_vf[3] = {0, 0, 0};
91 static int probe_vfs_argc;
92 module_param_array(probe_vf, byte, &probe_vfs_argc, 0444);
93 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n"
94 "probe_vf=port1,port2,port1+2");
96 static int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
97 module_param_named(log_num_mgm_entry_size,
98 mlx4_log_num_mgm_entry_size, int, 0444);
99 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
100 " of qp per mcg, for example:"
101 " 10 gives 248.range: 7 <="
102 " log_num_mgm_entry_size <= 12."
103 " To activate device managed"
104 " flow steering when available, set to -1");
106 static bool enable_64b_cqe_eqe = true;
107 module_param(enable_64b_cqe_eqe, bool, 0444);
108 MODULE_PARM_DESC(enable_64b_cqe_eqe,
109 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
111 static bool enable_4k_uar;
112 module_param(enable_4k_uar, bool, 0444);
113 MODULE_PARM_DESC(enable_4k_uar,
114 "Enable using 4K UAR. Should not be enabled if have VFs which do not support 4K UARs (default: false)");
116 #define PF_CONTEXT_BEHAVIOUR_MASK (MLX4_FUNC_CAP_64B_EQE_CQE | \
117 MLX4_FUNC_CAP_EQE_CQE_STRIDE | \
118 MLX4_FUNC_CAP_DMFS_A0_STATIC)
120 #define RESET_PERSIST_MASK_FLAGS (MLX4_FLAG_SRIOV)
122 static char mlx4_version[] =
123 DRV_NAME ": Mellanox ConnectX core driver v"
126 static const struct mlx4_profile default_profile = {
129 .rdmarc_per_qp = 1 << 4,
133 .num_mtt = 1 << 20, /* It is really num mtt segements */
136 static const struct mlx4_profile low_mem_profile = {
139 .rdmarc_per_qp = 1 << 4,
146 static int log_num_mac = 7;
147 module_param_named(log_num_mac, log_num_mac, int, 0444);
148 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
150 static int log_num_vlan;
151 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
152 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
153 /* Log2 max number of VLANs per ETH port (0-7) */
154 #define MLX4_LOG_NUM_VLANS 7
155 #define MLX4_MIN_LOG_NUM_VLANS 0
156 #define MLX4_MIN_LOG_NUM_MAC 1
158 static bool use_prio;
159 module_param_named(use_prio, use_prio, bool, 0444);
160 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)");
162 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
163 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
164 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
166 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
167 static int arr_argc = 2;
168 module_param_array(port_type_array, int, &arr_argc, 0444);
169 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
170 "1 for IB, 2 for Ethernet");
172 struct mlx4_port_config {
173 struct list_head list;
174 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
175 struct pci_dev *pdev;
178 static atomic_t pf_loading = ATOMIC_INIT(0);
180 static inline void mlx4_set_num_reserved_uars(struct mlx4_dev *dev,
181 struct mlx4_dev_cap *dev_cap)
183 /* The reserved_uars is calculated by system page size unit.
184 * Therefore, adjustment is added when the uar page size is less
185 * than the system page size
187 dev->caps.reserved_uars =
189 mlx4_get_num_reserved_uar(dev),
190 dev_cap->reserved_uars /
191 (1 << (PAGE_SHIFT - dev->uar_page_shift)));
194 int mlx4_check_port_params(struct mlx4_dev *dev,
195 enum mlx4_port_type *port_type)
199 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
200 for (i = 0; i < dev->caps.num_ports - 1; i++) {
201 if (port_type[i] != port_type[i + 1]) {
202 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n");
208 for (i = 0; i < dev->caps.num_ports; i++) {
209 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
210 mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n",
218 static void mlx4_set_port_mask(struct mlx4_dev *dev)
222 for (i = 1; i <= dev->caps.num_ports; ++i)
223 dev->caps.port_mask[i] = dev->caps.port_type[i];
227 MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0,
230 static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
233 struct mlx4_func func;
235 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
236 err = mlx4_QUERY_FUNC(dev, &func, 0);
238 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
241 dev_cap->max_eqs = func.max_eq;
242 dev_cap->reserved_eqs = func.rsvd_eqs;
243 dev_cap->reserved_uars = func.rsvd_uars;
244 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS;
249 static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev)
251 struct mlx4_caps *dev_cap = &dev->caps;
253 /* FW not supporting or cancelled by user */
254 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) ||
255 !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE))
258 /* Must have 64B CQE_EQE enabled by FW to use bigger stride
259 * When FW has NCSI it may decide not to report 64B CQE/EQEs
261 if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) ||
262 !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) {
263 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
264 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
268 if (cache_line_size() == 128 || cache_line_size() == 256) {
269 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n");
270 /* Changing the real data inside CQE size to 32B */
271 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
272 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
274 if (mlx4_is_master(dev))
275 dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE;
277 if (cache_line_size() != 32 && cache_line_size() != 64)
278 mlx4_dbg(dev, "Disabling CQE stride, cacheLine size unsupported\n");
279 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
280 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
284 static int _mlx4_dev_port(struct mlx4_dev *dev, int port,
285 struct mlx4_port_cap *port_cap)
287 dev->caps.vl_cap[port] = port_cap->max_vl;
288 dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu;
289 dev->phys_caps.gid_phys_table_len[port] = port_cap->max_gids;
290 dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys;
291 /* set gid and pkey table operating lengths by default
292 * to non-sriov values
294 dev->caps.gid_table_len[port] = port_cap->max_gids;
295 dev->caps.pkey_table_len[port] = port_cap->max_pkeys;
296 dev->caps.port_width_cap[port] = port_cap->max_port_width;
297 dev->caps.eth_mtu_cap[port] = port_cap->eth_mtu;
298 dev->caps.max_tc_eth = port_cap->max_tc_eth;
299 dev->caps.def_mac[port] = port_cap->def_mac;
300 dev->caps.supported_type[port] = port_cap->supported_port_types;
301 dev->caps.suggested_type[port] = port_cap->suggested_type;
302 dev->caps.default_sense[port] = port_cap->default_sense;
303 dev->caps.trans_type[port] = port_cap->trans_type;
304 dev->caps.vendor_oui[port] = port_cap->vendor_oui;
305 dev->caps.wavelength[port] = port_cap->wavelength;
306 dev->caps.trans_code[port] = port_cap->trans_code;
311 static int mlx4_dev_port(struct mlx4_dev *dev, int port,
312 struct mlx4_port_cap *port_cap)
316 err = mlx4_QUERY_PORT(dev, port, port_cap);
319 mlx4_err(dev, "QUERY_PORT command failed.\n");
324 static inline void mlx4_enable_ignore_fcs(struct mlx4_dev *dev)
326 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS))
329 if (mlx4_is_mfunc(dev)) {
330 mlx4_dbg(dev, "SRIOV mode - Disabling Ignore FCS");
331 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
335 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
337 "Keep FCS is not supported - Disabling Ignore FCS");
338 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
343 #define MLX4_A0_STEERING_TABLE_SIZE 256
344 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
349 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
351 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
354 mlx4_dev_cap_dump(dev, dev_cap);
356 if (dev_cap->min_page_sz > PAGE_SIZE) {
357 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
358 dev_cap->min_page_sz, PAGE_SIZE);
361 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
362 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
363 dev_cap->num_ports, MLX4_MAX_PORTS);
367 if (dev_cap->uar_size > pci_resource_len(dev->persist->pdev, 2)) {
368 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
371 pci_resource_len(dev->persist->pdev, 2));
375 dev->caps.num_ports = dev_cap->num_ports;
376 dev->caps.num_sys_eqs = dev_cap->num_sys_eqs;
377 dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ?
378 dev->caps.num_sys_eqs :
380 for (i = 1; i <= dev->caps.num_ports; ++i) {
381 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i);
383 mlx4_err(dev, "QUERY_PORT command failed, aborting\n");
388 dev->caps.uar_page_size = PAGE_SIZE;
389 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
390 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
391 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
392 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
393 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
394 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
395 dev->caps.max_wqes = dev_cap->max_qp_sz;
396 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
397 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
398 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
399 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
400 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
401 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
403 * Subtract 1 from the limit because we need to allocate a
404 * spare CQE so the HCA HW can tell the difference between an
405 * empty CQ and a full CQ.
407 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
408 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
409 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
410 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
411 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
413 dev->caps.reserved_pds = dev_cap->reserved_pds;
414 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
415 dev_cap->reserved_xrcds : 0;
416 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
417 dev_cap->max_xrcds : 0;
418 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
420 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
421 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
422 dev->caps.flags = dev_cap->flags;
423 dev->caps.flags2 = dev_cap->flags2;
424 dev->caps.bmme_flags = dev_cap->bmme_flags;
425 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
426 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
427 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
428 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
429 dev->caps.wol_port[1] = dev_cap->wol_port[1];
430 dev->caps.wol_port[2] = dev_cap->wol_port[2];
432 /* Save uar page shift */
433 if (!mlx4_is_slave(dev)) {
434 /* Virtual PCI function needs to determine UAR page size from
435 * firmware. Only master PCI function can set the uar page size
437 if (enable_4k_uar || !dev->persist->num_vfs)
438 dev->uar_page_shift = DEFAULT_UAR_PAGE_SHIFT;
440 dev->uar_page_shift = PAGE_SHIFT;
442 mlx4_set_num_reserved_uars(dev, dev_cap);
445 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN) {
446 struct mlx4_init_hca_param hca_param;
448 memset(&hca_param, 0, sizeof(hca_param));
449 err = mlx4_QUERY_HCA(dev, &hca_param);
450 /* Turn off PHV_EN flag in case phv_check_en is set.
451 * phv_check_en is a HW check that parse the packet and verify
452 * phv bit was reported correctly in the wqe. To allow QinQ
453 * PHV_EN flag should be set and phv_check_en must be cleared
454 * otherwise QinQ packets will be drop by the HW.
456 if (err || hca_param.phv_check_en)
457 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_PHV_EN;
460 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
461 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
462 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
463 /* Don't do sense port on multifunction devices (for now at least) */
464 if (mlx4_is_mfunc(dev))
465 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
467 if (mlx4_low_memory_profile()) {
468 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC;
469 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS;
471 dev->caps.log_num_macs = log_num_mac;
472 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
475 for (i = 1; i <= dev->caps.num_ports; ++i) {
476 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
477 if (dev->caps.supported_type[i]) {
478 /* if only ETH is supported - assign ETH */
479 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
480 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
481 /* if only IB is supported, assign IB */
482 else if (dev->caps.supported_type[i] ==
484 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
486 /* if IB and ETH are supported, we set the port
487 * type according to user selection of port type;
488 * if user selected none, take the FW hint */
489 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
490 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
491 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
493 dev->caps.port_type[i] = port_type_array[i - 1];
497 * Link sensing is allowed on the port if 3 conditions are true:
498 * 1. Both protocols are supported on the port.
499 * 2. Different types are supported on the port
500 * 3. FW declared that it supports link sensing
502 mlx4_priv(dev)->sense.sense_allowed[i] =
503 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
504 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
505 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
508 * If "default_sense" bit is set, we move the port to "AUTO" mode
509 * and perform sense_port FW command to try and set the correct
510 * port type from beginning
512 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
513 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
514 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
515 mlx4_SENSE_PORT(dev, i, &sensed_port);
516 if (sensed_port != MLX4_PORT_TYPE_NONE)
517 dev->caps.port_type[i] = sensed_port;
519 dev->caps.possible_type[i] = dev->caps.port_type[i];
522 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) {
523 dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs;
524 mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n",
525 i, 1 << dev->caps.log_num_macs);
527 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) {
528 dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans;
529 mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n",
530 i, 1 << dev->caps.log_num_vlans);
534 if (mlx4_is_master(dev) && (dev->caps.num_ports == 2) &&
535 (port_type_array[0] == MLX4_PORT_TYPE_IB) &&
536 (port_type_array[1] == MLX4_PORT_TYPE_ETH)) {
538 "Granular QoS per VF not supported with IB/Eth configuration\n");
539 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_QOS_VPP;
542 dev->caps.max_counters = dev_cap->max_counters;
544 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
545 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
546 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
547 (1 << dev->caps.log_num_macs) *
548 (1 << dev->caps.log_num_vlans) *
550 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
552 if (dev_cap->dmfs_high_rate_qpn_base > 0 &&
553 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)
554 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base;
556 dev->caps.dmfs_high_rate_qpn_base =
557 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
559 if (dev_cap->dmfs_high_rate_qpn_range > 0 &&
560 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) {
561 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range;
562 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT;
563 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0;
565 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED;
566 dev->caps.dmfs_high_rate_qpn_base =
567 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
568 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE;
571 dev->caps.rl_caps = dev_cap->rl_caps;
573 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] =
574 dev->caps.dmfs_high_rate_qpn_range;
576 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
577 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
578 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
579 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
581 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
583 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
585 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
586 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
587 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
588 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
591 if (dev_cap->flags2 &
592 (MLX4_DEV_CAP_FLAG2_CQE_STRIDE |
593 MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) {
594 mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n");
595 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
596 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
600 if ((dev->caps.flags &
601 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
603 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
605 if (!mlx4_is_slave(dev)) {
606 mlx4_enable_cqe_eqe_stride(dev);
607 dev->caps.alloc_res_qp_mask =
608 (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) |
611 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) &&
612 dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) {
613 mlx4_warn(dev, "Old device ETS support detected\n");
614 mlx4_warn(dev, "Consider upgrading device FW.\n");
615 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG;
619 dev->caps.alloc_res_qp_mask = 0;
622 mlx4_enable_ignore_fcs(dev);
627 /*The function checks if there are live vf, return the num of them*/
628 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
630 struct mlx4_priv *priv = mlx4_priv(dev);
631 struct mlx4_slave_state *s_state;
635 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
636 s_state = &priv->mfunc.master.slave_state[i];
637 if (s_state->active && s_state->last_cmd !=
638 MLX4_COMM_CMD_RESET) {
639 mlx4_warn(dev, "%s: slave: %d is still active\n",
647 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
649 u32 qk = MLX4_RESERVED_QKEY_BASE;
651 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
652 qpn < dev->phys_caps.base_proxy_sqpn)
655 if (qpn >= dev->phys_caps.base_tunnel_sqpn)
657 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
659 qk += qpn - dev->phys_caps.base_proxy_sqpn;
663 EXPORT_SYMBOL(mlx4_get_parav_qkey);
665 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
667 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
669 if (!mlx4_is_master(dev))
672 priv->virt2phys_pkey[slave][port - 1][i] = val;
674 EXPORT_SYMBOL(mlx4_sync_pkey_table);
676 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
678 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
680 if (!mlx4_is_master(dev))
683 priv->slave_node_guids[slave] = guid;
685 EXPORT_SYMBOL(mlx4_put_slave_node_guid);
687 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
689 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
691 if (!mlx4_is_master(dev))
694 return priv->slave_node_guids[slave];
696 EXPORT_SYMBOL(mlx4_get_slave_node_guid);
698 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
700 struct mlx4_priv *priv = mlx4_priv(dev);
701 struct mlx4_slave_state *s_slave;
703 if (!mlx4_is_master(dev))
706 s_slave = &priv->mfunc.master.slave_state[slave];
707 return !!s_slave->active;
709 EXPORT_SYMBOL(mlx4_is_slave_active);
711 void mlx4_handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl,
712 struct _rule_hw *eth_header)
714 if (is_multicast_ether_addr(eth_header->eth.dst_mac) ||
715 is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
716 struct mlx4_net_trans_rule_hw_eth *eth =
717 (struct mlx4_net_trans_rule_hw_eth *)eth_header;
718 struct _rule_hw *next_rule = (struct _rule_hw *)(eth + 1);
719 bool last_rule = next_rule->size == 0 && next_rule->id == 0 &&
720 next_rule->rsvd == 0;
723 ctrl->prio = cpu_to_be16(MLX4_DOMAIN_NIC);
726 EXPORT_SYMBOL(mlx4_handle_eth_header_mcast_prio);
728 static void slave_adjust_steering_mode(struct mlx4_dev *dev,
729 struct mlx4_dev_cap *dev_cap,
730 struct mlx4_init_hca_param *hca_param)
732 dev->caps.steering_mode = hca_param->steering_mode;
733 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
734 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
735 dev->caps.fs_log_max_ucast_qp_range_size =
736 dev_cap->fs_log_max_ucast_qp_range_size;
738 dev->caps.num_qp_per_mgm =
739 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
741 mlx4_dbg(dev, "Steering mode is: %s\n",
742 mlx4_steering_mode_str(dev->caps.steering_mode));
745 static void mlx4_slave_destroy_special_qp_cap(struct mlx4_dev *dev)
747 kfree(dev->caps.spec_qps);
748 dev->caps.spec_qps = NULL;
751 static int mlx4_slave_special_qp_cap(struct mlx4_dev *dev)
753 struct mlx4_func_cap *func_cap = NULL;
754 struct mlx4_caps *caps = &dev->caps;
757 func_cap = kzalloc(sizeof(*func_cap), GFP_KERNEL);
758 caps->spec_qps = kcalloc(caps->num_ports, sizeof(*caps->spec_qps), GFP_KERNEL);
760 if (!func_cap || !caps->spec_qps) {
761 mlx4_err(dev, "Failed to allocate memory for special qps cap\n");
766 for (i = 1; i <= caps->num_ports; ++i) {
767 err = mlx4_QUERY_FUNC_CAP(dev, i, func_cap);
769 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n",
773 caps->spec_qps[i - 1] = func_cap->spec_qps;
774 caps->port_mask[i] = caps->port_type[i];
775 caps->phys_port_id[i] = func_cap->phys_port_id;
776 err = mlx4_get_slave_pkey_gid_tbl_len(dev, i,
777 &caps->gid_table_len[i],
778 &caps->pkey_table_len[i]);
780 mlx4_err(dev, "QUERY_PORT command failed for port %d, aborting (%d)\n",
788 mlx4_slave_destroy_special_qp_cap(dev);
793 static int mlx4_slave_cap(struct mlx4_dev *dev)
797 struct mlx4_dev_cap *dev_cap = NULL;
798 struct mlx4_func_cap *func_cap = NULL;
799 struct mlx4_init_hca_param *hca_param = NULL;
801 hca_param = kzalloc(sizeof(*hca_param), GFP_KERNEL);
802 func_cap = kzalloc(sizeof(*func_cap), GFP_KERNEL);
803 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL);
804 if (!hca_param || !func_cap || !dev_cap) {
805 mlx4_err(dev, "Failed to allocate memory for slave_cap\n");
810 err = mlx4_QUERY_HCA(dev, hca_param);
812 mlx4_err(dev, "QUERY_HCA command failed, aborting\n");
816 /* fail if the hca has an unknown global capability
817 * at this time global_caps should be always zeroed
819 if (hca_param->global_caps) {
820 mlx4_err(dev, "Unknown hca global capabilities\n");
825 dev->caps.hca_core_clock = hca_param->hca_core_clock;
827 dev->caps.max_qp_dest_rdma = 1 << hca_param->log_rd_per_qp;
828 err = mlx4_dev_cap(dev, dev_cap);
830 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
834 err = mlx4_QUERY_FW(dev);
836 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n");
838 page_size = ~dev->caps.page_size_cap + 1;
839 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
840 if (page_size > PAGE_SIZE) {
841 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
842 page_size, PAGE_SIZE);
847 /* Set uar_page_shift for VF */
848 dev->uar_page_shift = hca_param->uar_page_sz + 12;
850 /* Make sure the master uar page size is valid */
851 if (dev->uar_page_shift > PAGE_SHIFT) {
853 "Invalid configuration: uar page size is larger than system page size\n");
858 /* Set reserved_uars based on the uar_page_shift */
859 mlx4_set_num_reserved_uars(dev, dev_cap);
861 /* Although uar page size in FW differs from system page size,
862 * upper software layers (mlx4_ib, mlx4_en and part of mlx4_core)
863 * still works with assumption that uar page size == system page size
865 dev->caps.uar_page_size = PAGE_SIZE;
867 err = mlx4_QUERY_FUNC_CAP(dev, 0, func_cap);
869 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n",
874 if ((func_cap->pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
875 PF_CONTEXT_BEHAVIOUR_MASK) {
876 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n",
877 func_cap->pf_context_behaviour,
878 PF_CONTEXT_BEHAVIOUR_MASK);
883 dev->caps.num_ports = func_cap->num_ports;
884 dev->quotas.qp = func_cap->qp_quota;
885 dev->quotas.srq = func_cap->srq_quota;
886 dev->quotas.cq = func_cap->cq_quota;
887 dev->quotas.mpt = func_cap->mpt_quota;
888 dev->quotas.mtt = func_cap->mtt_quota;
889 dev->caps.num_qps = 1 << hca_param->log_num_qps;
890 dev->caps.num_srqs = 1 << hca_param->log_num_srqs;
891 dev->caps.num_cqs = 1 << hca_param->log_num_cqs;
892 dev->caps.num_mpts = 1 << hca_param->log_mpt_sz;
893 dev->caps.num_eqs = func_cap->max_eq;
894 dev->caps.reserved_eqs = func_cap->reserved_eq;
895 dev->caps.reserved_lkey = func_cap->reserved_lkey;
896 dev->caps.num_pds = MLX4_NUM_PDS;
897 dev->caps.num_mgms = 0;
898 dev->caps.num_amgms = 0;
900 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
901 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
902 dev->caps.num_ports, MLX4_MAX_PORTS);
907 mlx4_replace_zero_macs(dev);
909 err = mlx4_slave_special_qp_cap(dev);
911 mlx4_err(dev, "Set special QP caps failed. aborting\n");
915 if (dev->caps.uar_page_size * (dev->caps.num_uars -
916 dev->caps.reserved_uars) >
917 pci_resource_len(dev->persist->pdev,
919 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
920 dev->caps.uar_page_size * dev->caps.num_uars,
922 pci_resource_len(dev->persist->pdev, 2));
927 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
928 dev->caps.eqe_size = 64;
929 dev->caps.eqe_factor = 1;
931 dev->caps.eqe_size = 32;
932 dev->caps.eqe_factor = 0;
935 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
936 dev->caps.cqe_size = 64;
937 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
939 dev->caps.cqe_size = 32;
942 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) {
943 dev->caps.eqe_size = hca_param->eqe_size;
944 dev->caps.eqe_factor = 0;
947 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) {
948 dev->caps.cqe_size = hca_param->cqe_size;
949 /* User still need to know when CQE > 32B */
950 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
953 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
954 mlx4_warn(dev, "Timestamping is not supported in slave mode\n");
956 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_USER_MAC_EN;
957 mlx4_dbg(dev, "User MAC FW update is not supported in slave mode\n");
959 slave_adjust_steering_mode(dev, dev_cap, hca_param);
960 mlx4_dbg(dev, "RSS support for IP fragments is %s\n",
961 hca_param->rss_ip_frags ? "on" : "off");
963 if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP &&
964 dev->caps.bf_reg_size)
965 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP;
967 if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP)
968 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP;
972 mlx4_slave_destroy_special_qp_cap(dev);
980 static void mlx4_request_modules(struct mlx4_dev *dev)
983 int has_ib_port = false;
984 int has_eth_port = false;
985 #define EN_DRV_NAME "mlx4_en"
986 #define IB_DRV_NAME "mlx4_ib"
988 for (port = 1; port <= dev->caps.num_ports; port++) {
989 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
991 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
996 request_module_nowait(EN_DRV_NAME);
997 if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
998 request_module_nowait(IB_DRV_NAME);
1002 * Change the port configuration of the device.
1003 * Every user of this function must hold the port mutex.
1005 int mlx4_change_port_types(struct mlx4_dev *dev,
1006 enum mlx4_port_type *port_types)
1012 for (port = 0; port < dev->caps.num_ports; port++) {
1013 /* Change the port type only if the new type is different
1014 * from the current, and not set to Auto */
1015 if (port_types[port] != dev->caps.port_type[port + 1])
1019 mlx4_unregister_device(dev);
1020 for (port = 1; port <= dev->caps.num_ports; port++) {
1021 mlx4_CLOSE_PORT(dev, port);
1022 dev->caps.port_type[port] = port_types[port - 1];
1023 err = mlx4_SET_PORT(dev, port, -1);
1025 mlx4_err(dev, "Failed to set port %d, aborting\n",
1030 mlx4_set_port_mask(dev);
1031 err = mlx4_register_device(dev);
1033 mlx4_err(dev, "Failed to register device\n");
1036 mlx4_request_modules(dev);
1043 static ssize_t show_port_type(struct device *dev,
1044 struct device_attribute *attr,
1047 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1049 struct mlx4_dev *mdev = info->dev;
1053 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
1055 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
1056 sprintf(buf, "auto (%s)\n", type);
1058 sprintf(buf, "%s\n", type);
1063 static int __set_port_type(struct mlx4_port_info *info,
1064 enum mlx4_port_type port_type)
1066 struct mlx4_dev *mdev = info->dev;
1067 struct mlx4_priv *priv = mlx4_priv(mdev);
1068 enum mlx4_port_type types[MLX4_MAX_PORTS];
1069 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
1073 if ((port_type & mdev->caps.supported_type[info->port]) != port_type) {
1075 "Requested port type for port %d is not supported on this HCA\n",
1081 mlx4_stop_sense(mdev);
1082 mutex_lock(&priv->port_mutex);
1083 info->tmp_type = port_type;
1085 /* Possible type is always the one that was delivered */
1086 mdev->caps.possible_type[info->port] = info->tmp_type;
1088 for (i = 0; i < mdev->caps.num_ports; i++) {
1089 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
1090 mdev->caps.possible_type[i+1];
1091 if (types[i] == MLX4_PORT_TYPE_AUTO)
1092 types[i] = mdev->caps.port_type[i+1];
1095 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
1096 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
1097 for (i = 1; i <= mdev->caps.num_ports; i++) {
1098 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
1099 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
1105 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n");
1109 mlx4_do_sense_ports(mdev, new_types, types);
1111 err = mlx4_check_port_params(mdev, new_types);
1115 /* We are about to apply the changes after the configuration
1116 * was verified, no need to remember the temporary types
1118 for (i = 0; i < mdev->caps.num_ports; i++)
1119 priv->port[i + 1].tmp_type = 0;
1121 err = mlx4_change_port_types(mdev, new_types);
1124 mlx4_start_sense(mdev);
1125 mutex_unlock(&priv->port_mutex);
1130 static ssize_t set_port_type(struct device *dev,
1131 struct device_attribute *attr,
1132 const char *buf, size_t count)
1134 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1136 struct mlx4_dev *mdev = info->dev;
1137 enum mlx4_port_type port_type;
1138 static DEFINE_MUTEX(set_port_type_mutex);
1141 mutex_lock(&set_port_type_mutex);
1143 if (!strcmp(buf, "ib\n")) {
1144 port_type = MLX4_PORT_TYPE_IB;
1145 } else if (!strcmp(buf, "eth\n")) {
1146 port_type = MLX4_PORT_TYPE_ETH;
1147 } else if (!strcmp(buf, "auto\n")) {
1148 port_type = MLX4_PORT_TYPE_AUTO;
1150 mlx4_err(mdev, "%s is not supported port type\n", buf);
1155 err = __set_port_type(info, port_type);
1158 mutex_unlock(&set_port_type_mutex);
1160 return err ? err : count;
1171 static inline int int_to_ibta_mtu(int mtu)
1174 case 256: return IB_MTU_256;
1175 case 512: return IB_MTU_512;
1176 case 1024: return IB_MTU_1024;
1177 case 2048: return IB_MTU_2048;
1178 case 4096: return IB_MTU_4096;
1183 static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
1186 case IB_MTU_256: return 256;
1187 case IB_MTU_512: return 512;
1188 case IB_MTU_1024: return 1024;
1189 case IB_MTU_2048: return 2048;
1190 case IB_MTU_4096: return 4096;
1195 static ssize_t show_port_ib_mtu(struct device *dev,
1196 struct device_attribute *attr,
1199 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1201 struct mlx4_dev *mdev = info->dev;
1203 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
1204 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1206 sprintf(buf, "%d\n",
1207 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
1211 static ssize_t set_port_ib_mtu(struct device *dev,
1212 struct device_attribute *attr,
1213 const char *buf, size_t count)
1215 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1217 struct mlx4_dev *mdev = info->dev;
1218 struct mlx4_priv *priv = mlx4_priv(mdev);
1219 int err, port, mtu, ibta_mtu = -1;
1221 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
1222 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1226 err = kstrtoint(buf, 0, &mtu);
1228 ibta_mtu = int_to_ibta_mtu(mtu);
1230 if (err || ibta_mtu < 0) {
1231 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
1235 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
1237 mlx4_stop_sense(mdev);
1238 mutex_lock(&priv->port_mutex);
1239 mlx4_unregister_device(mdev);
1240 for (port = 1; port <= mdev->caps.num_ports; port++) {
1241 mlx4_CLOSE_PORT(mdev, port);
1242 err = mlx4_SET_PORT(mdev, port, -1);
1244 mlx4_err(mdev, "Failed to set port %d, aborting\n",
1249 err = mlx4_register_device(mdev);
1251 mutex_unlock(&priv->port_mutex);
1252 mlx4_start_sense(mdev);
1253 return err ? err : count;
1256 /* bond for multi-function device */
1257 #define MAX_MF_BOND_ALLOWED_SLAVES 63
1258 static int mlx4_mf_bond(struct mlx4_dev *dev)
1262 struct mlx4_slaves_pport slaves_port1;
1263 struct mlx4_slaves_pport slaves_port2;
1264 DECLARE_BITMAP(slaves_port_1_2, MLX4_MFUNC_MAX);
1266 slaves_port1 = mlx4_phys_to_slaves_pport(dev, 1);
1267 slaves_port2 = mlx4_phys_to_slaves_pport(dev, 2);
1268 bitmap_and(slaves_port_1_2,
1269 slaves_port1.slaves, slaves_port2.slaves,
1270 dev->persist->num_vfs + 1);
1272 /* only single port vfs are allowed */
1273 if (bitmap_weight(slaves_port_1_2, dev->persist->num_vfs + 1) > 1) {
1274 mlx4_warn(dev, "HA mode unsupported for dual ported VFs\n");
1278 /* number of virtual functions is number of total functions minus one
1279 * physical function for each port.
1281 nvfs = bitmap_weight(slaves_port1.slaves, dev->persist->num_vfs + 1) +
1282 bitmap_weight(slaves_port2.slaves, dev->persist->num_vfs + 1) - 2;
1284 /* limit on maximum allowed VFs */
1285 if (nvfs > MAX_MF_BOND_ALLOWED_SLAVES) {
1286 mlx4_warn(dev, "HA mode is not supported for %d VFs (max %d are allowed)\n",
1287 nvfs, MAX_MF_BOND_ALLOWED_SLAVES);
1291 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
1292 mlx4_warn(dev, "HA mode unsupported for NON DMFS steering\n");
1296 err = mlx4_bond_mac_table(dev);
1299 err = mlx4_bond_vlan_table(dev);
1302 err = mlx4_bond_fs_rules(dev);
1308 (void)mlx4_unbond_vlan_table(dev);
1310 (void)mlx4_unbond_mac_table(dev);
1314 static int mlx4_mf_unbond(struct mlx4_dev *dev)
1318 ret = mlx4_unbond_fs_rules(dev);
1320 mlx4_warn(dev, "multifunction unbond for flow rules failed (%d)\n", ret);
1321 ret1 = mlx4_unbond_mac_table(dev);
1323 mlx4_warn(dev, "multifunction unbond for MAC table failed (%d)\n", ret1);
1326 ret1 = mlx4_unbond_vlan_table(dev);
1328 mlx4_warn(dev, "multifunction unbond for VLAN table failed (%d)\n", ret1);
1334 int mlx4_bond(struct mlx4_dev *dev)
1337 struct mlx4_priv *priv = mlx4_priv(dev);
1339 mutex_lock(&priv->bond_mutex);
1341 if (!mlx4_is_bonded(dev)) {
1342 ret = mlx4_do_bond(dev, true);
1344 mlx4_err(dev, "Failed to bond device: %d\n", ret);
1345 if (!ret && mlx4_is_master(dev)) {
1346 ret = mlx4_mf_bond(dev);
1348 mlx4_err(dev, "bond for multifunction failed\n");
1349 mlx4_do_bond(dev, false);
1354 mutex_unlock(&priv->bond_mutex);
1356 mlx4_dbg(dev, "Device is bonded\n");
1360 EXPORT_SYMBOL_GPL(mlx4_bond);
1362 int mlx4_unbond(struct mlx4_dev *dev)
1365 struct mlx4_priv *priv = mlx4_priv(dev);
1367 mutex_lock(&priv->bond_mutex);
1369 if (mlx4_is_bonded(dev)) {
1372 ret = mlx4_do_bond(dev, false);
1374 mlx4_err(dev, "Failed to unbond device: %d\n", ret);
1375 if (mlx4_is_master(dev))
1376 ret2 = mlx4_mf_unbond(dev);
1378 mlx4_warn(dev, "Failed to unbond device for multifunction (%d)\n", ret2);
1383 mutex_unlock(&priv->bond_mutex);
1385 mlx4_dbg(dev, "Device is unbonded\n");
1389 EXPORT_SYMBOL_GPL(mlx4_unbond);
1392 int mlx4_port_map_set(struct mlx4_dev *dev, struct mlx4_port_map *v2p)
1394 u8 port1 = v2p->port1;
1395 u8 port2 = v2p->port2;
1396 struct mlx4_priv *priv = mlx4_priv(dev);
1399 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP))
1402 mutex_lock(&priv->bond_mutex);
1404 /* zero means keep current mapping for this port */
1406 port1 = priv->v2p.port1;
1408 port2 = priv->v2p.port2;
1410 if ((port1 < 1) || (port1 > MLX4_MAX_PORTS) ||
1411 (port2 < 1) || (port2 > MLX4_MAX_PORTS) ||
1412 (port1 == 2 && port2 == 1)) {
1413 /* besides boundary checks cross mapping makes
1414 * no sense and therefore not allowed */
1416 } else if ((port1 == priv->v2p.port1) &&
1417 (port2 == priv->v2p.port2)) {
1420 err = mlx4_virt2phy_port_map(dev, port1, port2);
1422 mlx4_dbg(dev, "port map changed: [%d][%d]\n",
1424 priv->v2p.port1 = port1;
1425 priv->v2p.port2 = port2;
1427 mlx4_err(dev, "Failed to change port mape: %d\n", err);
1431 mutex_unlock(&priv->bond_mutex);
1434 EXPORT_SYMBOL_GPL(mlx4_port_map_set);
1436 static int mlx4_load_fw(struct mlx4_dev *dev)
1438 struct mlx4_priv *priv = mlx4_priv(dev);
1441 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
1442 GFP_HIGHUSER | __GFP_NOWARN, 0);
1443 if (!priv->fw.fw_icm) {
1444 mlx4_err(dev, "Couldn't allocate FW area, aborting\n");
1448 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1450 mlx4_err(dev, "MAP_FA command failed, aborting\n");
1454 err = mlx4_RUN_FW(dev);
1456 mlx4_err(dev, "RUN_FW command failed, aborting\n");
1466 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1470 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1473 struct mlx4_priv *priv = mlx4_priv(dev);
1477 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1479 ((u64) (MLX4_CMPT_TYPE_QP *
1480 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1481 cmpt_entry_sz, dev->caps.num_qps,
1482 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1487 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1489 ((u64) (MLX4_CMPT_TYPE_SRQ *
1490 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1491 cmpt_entry_sz, dev->caps.num_srqs,
1492 dev->caps.reserved_srqs, 0, 0);
1496 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1498 ((u64) (MLX4_CMPT_TYPE_CQ *
1499 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1500 cmpt_entry_sz, dev->caps.num_cqs,
1501 dev->caps.reserved_cqs, 0, 0);
1505 num_eqs = dev->phys_caps.num_phys_eqs;
1506 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1508 ((u64) (MLX4_CMPT_TYPE_EQ *
1509 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1510 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
1517 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1520 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1523 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1529 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1530 struct mlx4_init_hca_param *init_hca, u64 icm_size)
1532 struct mlx4_priv *priv = mlx4_priv(dev);
1537 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1539 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n");
1543 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n",
1544 (unsigned long long) icm_size >> 10,
1545 (unsigned long long) aux_pages << 2);
1547 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
1548 GFP_HIGHUSER | __GFP_NOWARN, 0);
1549 if (!priv->fw.aux_icm) {
1550 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n");
1554 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1556 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n");
1560 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1562 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n");
1567 num_eqs = dev->phys_caps.num_phys_eqs;
1568 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1569 init_hca->eqc_base, dev_cap->eqc_entry_sz,
1570 num_eqs, num_eqs, 0, 0);
1572 mlx4_err(dev, "Failed to map EQ context memory, aborting\n");
1573 goto err_unmap_cmpt;
1577 * Reserved MTT entries must be aligned up to a cacheline
1578 * boundary, since the FW will write to them, while the driver
1579 * writes to all other MTT entries. (The variable
1580 * dev->caps.mtt_entry_sz below is really the MTT segment
1581 * size, not the raw entry size)
1583 dev->caps.reserved_mtts =
1584 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1585 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1587 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1589 dev->caps.mtt_entry_sz,
1591 dev->caps.reserved_mtts, 1, 0);
1593 mlx4_err(dev, "Failed to map MTT context memory, aborting\n");
1597 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1598 init_hca->dmpt_base,
1599 dev_cap->dmpt_entry_sz,
1601 dev->caps.reserved_mrws, 1, 1);
1603 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n");
1607 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1609 dev_cap->qpc_entry_sz,
1611 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1614 mlx4_err(dev, "Failed to map QP context memory, aborting\n");
1615 goto err_unmap_dmpt;
1618 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1619 init_hca->auxc_base,
1620 dev_cap->aux_entry_sz,
1622 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1625 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n");
1629 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1630 init_hca->altc_base,
1631 dev_cap->altc_entry_sz,
1633 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1636 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n");
1637 goto err_unmap_auxc;
1640 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1641 init_hca->rdmarc_base,
1642 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1644 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1647 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1648 goto err_unmap_altc;
1651 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1653 dev_cap->cqc_entry_sz,
1655 dev->caps.reserved_cqs, 0, 0);
1657 mlx4_err(dev, "Failed to map CQ context memory, aborting\n");
1658 goto err_unmap_rdmarc;
1661 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1662 init_hca->srqc_base,
1663 dev_cap->srq_entry_sz,
1665 dev->caps.reserved_srqs, 0, 0);
1667 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n");
1672 * For flow steering device managed mode it is required to use
1673 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1674 * required, but for simplicity just map the whole multicast
1675 * group table now. The table isn't very big and it's a lot
1676 * easier than trying to track ref counts.
1678 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
1680 mlx4_get_mgm_entry_size(dev),
1681 dev->caps.num_mgms + dev->caps.num_amgms,
1682 dev->caps.num_mgms + dev->caps.num_amgms,
1685 mlx4_err(dev, "Failed to map MCG context memory, aborting\n");
1692 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1695 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1698 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1701 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1704 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1707 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1710 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1713 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1716 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1719 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1720 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1721 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1722 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1725 mlx4_UNMAP_ICM_AUX(dev);
1728 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1733 static void mlx4_free_icms(struct mlx4_dev *dev)
1735 struct mlx4_priv *priv = mlx4_priv(dev);
1737 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1738 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1739 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1740 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1741 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1742 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1743 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1744 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1745 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1746 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1747 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1748 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1749 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1750 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1752 mlx4_UNMAP_ICM_AUX(dev);
1753 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1756 static void mlx4_slave_exit(struct mlx4_dev *dev)
1758 struct mlx4_priv *priv = mlx4_priv(dev);
1760 mutex_lock(&priv->cmd.slave_cmd_mutex);
1761 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP,
1763 mlx4_warn(dev, "Failed to close slave function\n");
1764 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1767 static int map_bf_area(struct mlx4_dev *dev)
1769 struct mlx4_priv *priv = mlx4_priv(dev);
1770 resource_size_t bf_start;
1771 resource_size_t bf_len;
1774 if (!dev->caps.bf_reg_size)
1777 bf_start = pci_resource_start(dev->persist->pdev, 2) +
1778 (dev->caps.num_uars << PAGE_SHIFT);
1779 bf_len = pci_resource_len(dev->persist->pdev, 2) -
1780 (dev->caps.num_uars << PAGE_SHIFT);
1781 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1782 if (!priv->bf_mapping)
1788 static void unmap_bf_area(struct mlx4_dev *dev)
1790 if (mlx4_priv(dev)->bf_mapping)
1791 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1794 u64 mlx4_read_clock(struct mlx4_dev *dev)
1796 u32 clockhi, clocklo, clockhi1;
1799 struct mlx4_priv *priv = mlx4_priv(dev);
1801 for (i = 0; i < 10; i++) {
1802 clockhi = swab32(readl(priv->clock_mapping));
1803 clocklo = swab32(readl(priv->clock_mapping + 4));
1804 clockhi1 = swab32(readl(priv->clock_mapping));
1805 if (clockhi == clockhi1)
1809 cycles = (u64) clockhi << 32 | (u64) clocklo;
1813 EXPORT_SYMBOL_GPL(mlx4_read_clock);
1816 static int map_internal_clock(struct mlx4_dev *dev)
1818 struct mlx4_priv *priv = mlx4_priv(dev);
1820 priv->clock_mapping =
1821 ioremap(pci_resource_start(dev->persist->pdev,
1822 priv->fw.clock_bar) +
1823 priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1825 if (!priv->clock_mapping)
1831 int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1832 struct mlx4_clock_params *params)
1834 struct mlx4_priv *priv = mlx4_priv(dev);
1836 if (mlx4_is_slave(dev))
1842 params->bar = priv->fw.clock_bar;
1843 params->offset = priv->fw.clock_offset;
1844 params->size = MLX4_CLOCK_SIZE;
1848 EXPORT_SYMBOL_GPL(mlx4_get_internal_clock_params);
1850 static void unmap_internal_clock(struct mlx4_dev *dev)
1852 struct mlx4_priv *priv = mlx4_priv(dev);
1854 if (priv->clock_mapping)
1855 iounmap(priv->clock_mapping);
1858 static void mlx4_close_hca(struct mlx4_dev *dev)
1860 unmap_internal_clock(dev);
1862 if (mlx4_is_slave(dev))
1863 mlx4_slave_exit(dev);
1865 mlx4_CLOSE_HCA(dev, 0);
1866 mlx4_free_icms(dev);
1870 static void mlx4_close_fw(struct mlx4_dev *dev)
1872 if (!mlx4_is_slave(dev)) {
1874 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1878 static int mlx4_comm_check_offline(struct mlx4_dev *dev)
1880 #define COMM_CHAN_OFFLINE_OFFSET 0x09
1885 struct mlx4_priv *priv = mlx4_priv(dev);
1887 end = msecs_to_jiffies(MLX4_COMM_OFFLINE_TIME_OUT) + jiffies;
1888 while (time_before(jiffies, end)) {
1889 comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm +
1890 MLX4_COMM_CHAN_FLAGS));
1891 offline_bit = (comm_flags &
1892 (u32)(1 << COMM_CHAN_OFFLINE_OFFSET));
1896 /* If device removal has been requested,
1897 * do not continue retrying.
1899 if (dev->persist->interface_state &
1900 MLX4_INTERFACE_STATE_NOWAIT)
1903 /* There are cases as part of AER/Reset flow that PF needs
1904 * around 100 msec to load. We therefore sleep for 100 msec
1905 * to allow other tasks to make use of that CPU during this
1910 mlx4_err(dev, "Communication channel is offline.\n");
1914 static void mlx4_reset_vf_support(struct mlx4_dev *dev)
1916 #define COMM_CHAN_RST_OFFSET 0x1e
1918 struct mlx4_priv *priv = mlx4_priv(dev);
1922 comm_caps = swab32(readl((__iomem char *)priv->mfunc.comm +
1923 MLX4_COMM_CHAN_CAPS));
1924 comm_rst = (comm_caps & (u32)(1 << COMM_CHAN_RST_OFFSET));
1927 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET;
1930 static int mlx4_init_slave(struct mlx4_dev *dev)
1932 struct mlx4_priv *priv = mlx4_priv(dev);
1933 u64 dma = (u64) priv->mfunc.vhcr_dma;
1934 int ret_from_reset = 0;
1936 u32 cmd_channel_ver;
1938 if (atomic_read(&pf_loading)) {
1939 mlx4_warn(dev, "PF is not ready - Deferring probe\n");
1940 return -EPROBE_DEFER;
1943 mutex_lock(&priv->cmd.slave_cmd_mutex);
1944 priv->cmd.max_cmds = 1;
1945 if (mlx4_comm_check_offline(dev)) {
1946 mlx4_err(dev, "PF is not responsive, skipping initialization\n");
1950 mlx4_reset_vf_support(dev);
1951 mlx4_warn(dev, "Sending reset\n");
1952 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1953 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME);
1954 /* if we are in the middle of flr the slave will try
1955 * NUM_OF_RESET_RETRIES times before leaving.*/
1956 if (ret_from_reset) {
1957 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1958 mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n");
1959 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1960 return -EPROBE_DEFER;
1965 /* check the driver version - the slave I/F revision
1966 * must match the master's */
1967 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1968 cmd_channel_ver = mlx4_comm_get_version();
1970 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1971 MLX4_COMM_GET_IF_REV(slave_read)) {
1972 mlx4_err(dev, "slave driver version is not supported by the master\n");
1976 mlx4_warn(dev, "Sending vhcr0\n");
1977 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1978 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
1980 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1981 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
1983 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1984 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
1986 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma,
1987 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
1990 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1994 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 0);
1996 mutex_unlock(&priv->cmd.slave_cmd_mutex);
2000 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
2004 for (i = 1; i <= dev->caps.num_ports; i++) {
2005 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
2006 dev->caps.gid_table_len[i] =
2007 mlx4_get_slave_num_gids(dev, 0, i);
2009 dev->caps.gid_table_len[i] = 1;
2010 dev->caps.pkey_table_len[i] =
2011 dev->phys_caps.pkey_phys_table_len[i] - 1;
2015 static int choose_log_fs_mgm_entry_size(int qp_per_entry)
2017 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
2019 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
2021 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
2025 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
2028 static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode)
2030 switch (dmfs_high_steer_mode) {
2031 case MLX4_STEERING_DMFS_A0_DEFAULT:
2032 return "default performance";
2034 case MLX4_STEERING_DMFS_A0_DYNAMIC:
2035 return "dynamic hybrid mode";
2037 case MLX4_STEERING_DMFS_A0_STATIC:
2038 return "performance optimized for limited rule configuration (static)";
2040 case MLX4_STEERING_DMFS_A0_DISABLE:
2041 return "disabled performance optimized steering";
2043 case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED:
2044 return "performance optimized steering not supported";
2047 return "Unrecognized mode";
2051 #define MLX4_DMFS_A0_STEERING (1UL << 2)
2053 static void choose_steering_mode(struct mlx4_dev *dev,
2054 struct mlx4_dev_cap *dev_cap)
2056 if (mlx4_log_num_mgm_entry_size <= 0) {
2057 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) {
2058 if (dev->caps.dmfs_high_steer_mode ==
2059 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2060 mlx4_err(dev, "DMFS high rate mode not supported\n");
2062 dev->caps.dmfs_high_steer_mode =
2063 MLX4_STEERING_DMFS_A0_STATIC;
2067 if (mlx4_log_num_mgm_entry_size <= 0 &&
2068 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
2069 (!mlx4_is_mfunc(dev) ||
2070 (dev_cap->fs_max_num_qp_per_entry >=
2071 (dev->persist->num_vfs + 1))) &&
2072 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
2073 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
2074 dev->oper_log_mgm_entry_size =
2075 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
2076 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
2077 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
2078 dev->caps.fs_log_max_ucast_qp_range_size =
2079 dev_cap->fs_log_max_ucast_qp_range_size;
2081 if (dev->caps.dmfs_high_steer_mode !=
2082 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2083 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE;
2084 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
2085 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
2086 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
2088 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
2090 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
2091 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
2092 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n");
2094 dev->oper_log_mgm_entry_size =
2095 mlx4_log_num_mgm_entry_size > 0 ?
2096 mlx4_log_num_mgm_entry_size :
2097 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
2098 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
2100 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n",
2101 mlx4_steering_mode_str(dev->caps.steering_mode),
2102 dev->oper_log_mgm_entry_size,
2103 mlx4_log_num_mgm_entry_size);
2106 static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
2107 struct mlx4_dev_cap *dev_cap)
2109 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
2110 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS)
2111 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
2113 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
2115 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode
2116 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
2119 static int mlx4_validate_optimized_steering(struct mlx4_dev *dev)
2122 struct mlx4_port_cap port_cap;
2124 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2127 for (i = 1; i <= dev->caps.num_ports; i++) {
2128 if (mlx4_dev_port(dev, i, &port_cap)) {
2130 "QUERY_DEV_CAP command failed, can't veify DMFS high rate steering.\n");
2131 } else if ((dev->caps.dmfs_high_steer_mode !=
2132 MLX4_STEERING_DMFS_A0_DEFAULT) &&
2133 (port_cap.dmfs_optimized_state ==
2134 !!(dev->caps.dmfs_high_steer_mode ==
2135 MLX4_STEERING_DMFS_A0_DISABLE))) {
2137 "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n",
2138 dmfs_high_rate_steering_mode_str(
2139 dev->caps.dmfs_high_steer_mode),
2140 (port_cap.dmfs_optimized_state ?
2141 "enabled" : "disabled"));
2148 static int mlx4_init_fw(struct mlx4_dev *dev)
2150 struct mlx4_mod_stat_cfg mlx4_cfg;
2153 if (!mlx4_is_slave(dev)) {
2154 err = mlx4_QUERY_FW(dev);
2157 mlx4_info(dev, "non-primary physical function, skipping\n");
2159 mlx4_err(dev, "QUERY_FW command failed, aborting\n");
2163 err = mlx4_load_fw(dev);
2165 mlx4_err(dev, "Failed to start FW, aborting\n");
2169 mlx4_cfg.log_pg_sz_m = 1;
2170 mlx4_cfg.log_pg_sz = 0;
2171 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
2173 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
2179 static int mlx4_init_hca(struct mlx4_dev *dev)
2181 struct mlx4_priv *priv = mlx4_priv(dev);
2182 struct mlx4_adapter adapter;
2183 struct mlx4_dev_cap dev_cap;
2184 struct mlx4_profile profile;
2185 struct mlx4_init_hca_param init_hca;
2187 struct mlx4_config_dev_params params;
2190 if (!mlx4_is_slave(dev)) {
2191 err = mlx4_dev_cap(dev, &dev_cap);
2193 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
2197 choose_steering_mode(dev, &dev_cap);
2198 choose_tunnel_offload_mode(dev, &dev_cap);
2200 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC &&
2201 mlx4_is_master(dev))
2202 dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC;
2204 err = mlx4_get_phys_port_id(dev);
2206 mlx4_err(dev, "Fail to get physical port id\n");
2208 if (mlx4_is_master(dev))
2209 mlx4_parav_master_pf_caps(dev);
2211 if (mlx4_low_memory_profile()) {
2212 mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n");
2213 profile = low_mem_profile;
2215 profile = default_profile;
2217 if (dev->caps.steering_mode ==
2218 MLX4_STEERING_MODE_DEVICE_MANAGED)
2219 profile.num_mcg = MLX4_FS_NUM_MCG;
2221 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
2223 if ((long long) icm_size < 0) {
2228 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
2230 if (enable_4k_uar || !dev->persist->num_vfs) {
2231 init_hca.log_uar_sz = ilog2(dev->caps.num_uars) +
2232 PAGE_SHIFT - DEFAULT_UAR_PAGE_SHIFT;
2233 init_hca.uar_page_sz = DEFAULT_UAR_PAGE_SHIFT - 12;
2235 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
2236 init_hca.uar_page_sz = PAGE_SHIFT - 12;
2239 init_hca.mw_enabled = 0;
2240 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2241 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
2242 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
2244 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
2248 err = mlx4_INIT_HCA(dev, &init_hca);
2250 mlx4_err(dev, "INIT_HCA command failed, aborting\n");
2254 if (dev_cap.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
2255 err = mlx4_query_func(dev, &dev_cap);
2257 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n");
2259 } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) {
2260 dev->caps.num_eqs = dev_cap.max_eqs;
2261 dev->caps.reserved_eqs = dev_cap.reserved_eqs;
2262 dev->caps.reserved_uars = dev_cap.reserved_uars;
2267 * If TS is supported by FW
2268 * read HCA frequency by QUERY_HCA command
2270 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
2271 memset(&init_hca, 0, sizeof(init_hca));
2272 err = mlx4_QUERY_HCA(dev, &init_hca);
2274 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n");
2275 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2277 dev->caps.hca_core_clock =
2278 init_hca.hca_core_clock;
2281 /* In case we got HCA frequency 0 - disable timestamping
2282 * to avoid dividing by zero
2284 if (!dev->caps.hca_core_clock) {
2285 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2287 "HCA frequency is 0 - timestamping is not supported\n");
2288 } else if (map_internal_clock(dev)) {
2290 * Map internal clock,
2291 * in case of failure disable timestamping
2293 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2294 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n");
2298 if (dev->caps.dmfs_high_steer_mode !=
2299 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) {
2300 if (mlx4_validate_optimized_steering(dev))
2301 mlx4_warn(dev, "Optimized steering validation failed\n");
2303 if (dev->caps.dmfs_high_steer_mode ==
2304 MLX4_STEERING_DMFS_A0_DISABLE) {
2305 dev->caps.dmfs_high_rate_qpn_base =
2306 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
2307 dev->caps.dmfs_high_rate_qpn_range =
2308 MLX4_A0_STEERING_TABLE_SIZE;
2311 mlx4_info(dev, "DMFS high rate steer mode is: %s\n",
2312 dmfs_high_rate_steering_mode_str(
2313 dev->caps.dmfs_high_steer_mode));
2316 err = mlx4_init_slave(dev);
2318 if (err != -EPROBE_DEFER)
2319 mlx4_err(dev, "Failed to initialize slave\n");
2323 err = mlx4_slave_cap(dev);
2325 mlx4_err(dev, "Failed to obtain slave caps\n");
2330 if (map_bf_area(dev))
2331 mlx4_dbg(dev, "Failed to map blue flame area\n");
2333 /*Only the master set the ports, all the rest got it from it.*/
2334 if (!mlx4_is_slave(dev))
2335 mlx4_set_port_mask(dev);
2337 err = mlx4_QUERY_ADAPTER(dev, &adapter);
2339 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n");
2343 /* Query CONFIG_DEV parameters */
2344 err = mlx4_config_dev_retrieval(dev, ¶ms);
2345 if (err && err != -EOPNOTSUPP) {
2346 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n");
2348 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1;
2349 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2;
2351 priv->eq_table.inta_pin = adapter.inta_pin;
2352 memcpy(dev->board_id, adapter.board_id, sizeof(dev->board_id));
2357 unmap_internal_clock(dev);
2360 if (mlx4_is_slave(dev))
2361 mlx4_slave_destroy_special_qp_cap(dev);
2364 if (mlx4_is_slave(dev))
2365 mlx4_slave_exit(dev);
2367 mlx4_CLOSE_HCA(dev, 0);
2370 if (!mlx4_is_slave(dev))
2371 mlx4_free_icms(dev);
2376 static int mlx4_init_counters_table(struct mlx4_dev *dev)
2378 struct mlx4_priv *priv = mlx4_priv(dev);
2381 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2384 if (!dev->caps.max_counters)
2387 nent_pow2 = roundup_pow_of_two(dev->caps.max_counters);
2388 /* reserve last counter index for sink counter */
2389 return mlx4_bitmap_init(&priv->counters_bitmap, nent_pow2,
2391 nent_pow2 - dev->caps.max_counters + 1);
2394 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
2396 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2399 if (!dev->caps.max_counters)
2402 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
2405 static void mlx4_cleanup_default_counters(struct mlx4_dev *dev)
2407 struct mlx4_priv *priv = mlx4_priv(dev);
2410 for (port = 0; port < dev->caps.num_ports; port++)
2411 if (priv->def_counter[port] != -1)
2412 mlx4_counter_free(dev, priv->def_counter[port]);
2415 static int mlx4_allocate_default_counters(struct mlx4_dev *dev)
2417 struct mlx4_priv *priv = mlx4_priv(dev);
2421 for (port = 0; port < dev->caps.num_ports; port++)
2422 priv->def_counter[port] = -1;
2424 for (port = 0; port < dev->caps.num_ports; port++) {
2425 err = mlx4_counter_alloc(dev, &idx, MLX4_RES_USAGE_DRIVER);
2427 if (!err || err == -ENOSPC) {
2428 priv->def_counter[port] = idx;
2429 } else if (err == -ENOENT) {
2432 } else if (mlx4_is_slave(dev) && err == -EINVAL) {
2433 priv->def_counter[port] = MLX4_SINK_COUNTER_INDEX(dev);
2434 mlx4_warn(dev, "can't allocate counter from old PF driver, using index %d\n",
2435 MLX4_SINK_COUNTER_INDEX(dev));
2438 mlx4_err(dev, "%s: failed to allocate default counter port %d err %d\n",
2439 __func__, port + 1, err);
2440 mlx4_cleanup_default_counters(dev);
2444 mlx4_dbg(dev, "%s: default counter index %d for port %d\n",
2445 __func__, priv->def_counter[port], port + 1);
2451 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
2453 struct mlx4_priv *priv = mlx4_priv(dev);
2455 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2458 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
2460 *idx = MLX4_SINK_COUNTER_INDEX(dev);
2467 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx, u8 usage)
2469 u32 in_modifier = RES_COUNTER | (((u32)usage & 3) << 30);
2473 if (mlx4_is_mfunc(dev)) {
2474 err = mlx4_cmd_imm(dev, 0, &out_param, in_modifier,
2475 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
2476 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
2478 *idx = get_param_l(&out_param);
2482 return __mlx4_counter_alloc(dev, idx);
2484 EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
2486 static int __mlx4_clear_if_stat(struct mlx4_dev *dev,
2489 struct mlx4_cmd_mailbox *if_stat_mailbox;
2491 u32 if_stat_in_mod = (counter_index & 0xff) | MLX4_QUERY_IF_STAT_RESET;
2493 if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev);
2494 if (IS_ERR(if_stat_mailbox))
2495 return PTR_ERR(if_stat_mailbox);
2497 err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, if_stat_in_mod, 0,
2498 MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C,
2501 mlx4_free_cmd_mailbox(dev, if_stat_mailbox);
2505 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
2507 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2510 if (idx == MLX4_SINK_COUNTER_INDEX(dev))
2513 __mlx4_clear_if_stat(dev, idx);
2515 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
2519 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
2523 if (mlx4_is_mfunc(dev)) {
2524 set_param_l(&in_param, idx);
2525 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
2526 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
2530 __mlx4_counter_free(dev, idx);
2532 EXPORT_SYMBOL_GPL(mlx4_counter_free);
2534 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port)
2536 struct mlx4_priv *priv = mlx4_priv(dev);
2538 return priv->def_counter[port - 1];
2540 EXPORT_SYMBOL_GPL(mlx4_get_default_counter_index);
2542 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, int port)
2544 struct mlx4_priv *priv = mlx4_priv(dev);
2546 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2548 EXPORT_SYMBOL_GPL(mlx4_set_admin_guid);
2550 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port)
2552 struct mlx4_priv *priv = mlx4_priv(dev);
2554 return priv->mfunc.master.vf_admin[entry].vport[port].guid;
2556 EXPORT_SYMBOL_GPL(mlx4_get_admin_guid);
2558 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port)
2560 struct mlx4_priv *priv = mlx4_priv(dev);
2567 get_random_bytes((char *)&guid, sizeof(guid));
2568 guid &= ~(cpu_to_be64(1ULL << 56));
2569 guid |= cpu_to_be64(1ULL << 57);
2570 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2573 static int mlx4_setup_hca(struct mlx4_dev *dev)
2575 struct mlx4_priv *priv = mlx4_priv(dev);
2578 __be32 ib_port_default_caps;
2580 err = mlx4_init_uar_table(dev);
2582 mlx4_err(dev, "Failed to initialize user access region table, aborting\n");
2586 err = mlx4_uar_alloc(dev, &priv->driver_uar);
2588 mlx4_err(dev, "Failed to allocate driver access region, aborting\n");
2589 goto err_uar_table_free;
2592 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
2594 mlx4_err(dev, "Couldn't map kernel access region, aborting\n");
2599 err = mlx4_init_pd_table(dev);
2601 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n");
2605 err = mlx4_init_xrcd_table(dev);
2607 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n");
2608 goto err_pd_table_free;
2611 err = mlx4_init_mr_table(dev);
2613 mlx4_err(dev, "Failed to initialize memory region table, aborting\n");
2614 goto err_xrcd_table_free;
2617 if (!mlx4_is_slave(dev)) {
2618 err = mlx4_init_mcg_table(dev);
2620 mlx4_err(dev, "Failed to initialize multicast group table, aborting\n");
2621 goto err_mr_table_free;
2623 err = mlx4_config_mad_demux(dev);
2625 mlx4_err(dev, "Failed in config_mad_demux, aborting\n");
2626 goto err_mcg_table_free;
2630 err = mlx4_init_eq_table(dev);
2632 mlx4_err(dev, "Failed to initialize event queue table, aborting\n");
2633 goto err_mcg_table_free;
2636 err = mlx4_cmd_use_events(dev);
2638 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n");
2639 goto err_eq_table_free;
2642 err = mlx4_NOP(dev);
2644 if (dev->flags & MLX4_FLAG_MSI_X) {
2645 mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n",
2646 priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
2647 mlx4_warn(dev, "Trying again without MSI-X\n");
2649 mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n",
2650 priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
2651 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
2657 mlx4_dbg(dev, "NOP command IRQ test passed\n");
2659 err = mlx4_init_cq_table(dev);
2661 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n");
2665 err = mlx4_init_srq_table(dev);
2667 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n");
2668 goto err_cq_table_free;
2671 err = mlx4_init_qp_table(dev);
2673 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n");
2674 goto err_srq_table_free;
2677 if (!mlx4_is_slave(dev)) {
2678 err = mlx4_init_counters_table(dev);
2679 if (err && err != -ENOENT) {
2680 mlx4_err(dev, "Failed to initialize counters table, aborting\n");
2681 goto err_qp_table_free;
2685 err = mlx4_allocate_default_counters(dev);
2687 mlx4_err(dev, "Failed to allocate default counters, aborting\n");
2688 goto err_counters_table_free;
2691 if (!mlx4_is_slave(dev)) {
2692 for (port = 1; port <= dev->caps.num_ports; port++) {
2693 ib_port_default_caps = 0;
2694 err = mlx4_get_port_ib_caps(dev, port,
2695 &ib_port_default_caps);
2697 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
2699 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
2701 /* initialize per-slave default ib port capabilities */
2702 if (mlx4_is_master(dev)) {
2704 for (i = 0; i < dev->num_slaves; i++) {
2705 if (i == mlx4_master_func_num(dev))
2707 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
2708 ib_port_default_caps;
2712 if (mlx4_is_mfunc(dev))
2713 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
2715 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
2717 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
2718 dev->caps.pkey_table_len[port] : -1);
2720 mlx4_err(dev, "Failed to set port %d, aborting\n",
2722 goto err_default_countes_free;
2729 err_default_countes_free:
2730 mlx4_cleanup_default_counters(dev);
2732 err_counters_table_free:
2733 if (!mlx4_is_slave(dev))
2734 mlx4_cleanup_counters_table(dev);
2737 mlx4_cleanup_qp_table(dev);
2740 mlx4_cleanup_srq_table(dev);
2743 mlx4_cleanup_cq_table(dev);
2746 mlx4_cmd_use_polling(dev);
2749 mlx4_cleanup_eq_table(dev);
2752 if (!mlx4_is_slave(dev))
2753 mlx4_cleanup_mcg_table(dev);
2756 mlx4_cleanup_mr_table(dev);
2758 err_xrcd_table_free:
2759 mlx4_cleanup_xrcd_table(dev);
2762 mlx4_cleanup_pd_table(dev);
2768 mlx4_uar_free(dev, &priv->driver_uar);
2771 mlx4_cleanup_uar_table(dev);
2775 static int mlx4_init_affinity_hint(struct mlx4_dev *dev, int port, int eqn)
2777 int requested_cpu = 0;
2778 struct mlx4_priv *priv = mlx4_priv(dev);
2783 if (eqn > dev->caps.num_comp_vectors)
2786 for (i = 1; i < port; i++)
2787 off += mlx4_get_eqs_per_port(dev, i);
2789 requested_cpu = eqn - off - !!(eqn > MLX4_EQ_ASYNC);
2791 /* Meaning EQs are shared, and this call comes from the second port */
2792 if (requested_cpu < 0)
2795 eq = &priv->eq_table.eq[eqn];
2797 if (!zalloc_cpumask_var(&eq->affinity_mask, GFP_KERNEL))
2800 cpumask_set_cpu(requested_cpu, eq->affinity_mask);
2805 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
2807 struct mlx4_priv *priv = mlx4_priv(dev);
2808 struct msix_entry *entries;
2813 int nreq = min3(dev->caps.num_ports *
2814 (int)num_online_cpus() + 1,
2815 dev->caps.num_eqs - dev->caps.reserved_eqs,
2819 nreq = min_t(int, nreq, msi_x);
2821 entries = kcalloc(nreq, sizeof(*entries), GFP_KERNEL);
2825 for (i = 0; i < nreq; ++i)
2826 entries[i].entry = i;
2828 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2,
2831 if (nreq < 0 || nreq < MLX4_EQ_ASYNC) {
2835 /* 1 is reserved for events (asyncrounous EQ) */
2836 dev->caps.num_comp_vectors = nreq - 1;
2838 priv->eq_table.eq[MLX4_EQ_ASYNC].irq = entries[0].vector;
2839 bitmap_zero(priv->eq_table.eq[MLX4_EQ_ASYNC].actv_ports.ports,
2840 dev->caps.num_ports);
2842 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) {
2843 if (i == MLX4_EQ_ASYNC)
2846 priv->eq_table.eq[i].irq =
2847 entries[i + 1 - !!(i > MLX4_EQ_ASYNC)].vector;
2849 if (MLX4_IS_LEGACY_EQ_MODE(dev->caps)) {
2850 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,
2851 dev->caps.num_ports);
2852 /* We don't set affinity hint when there
2857 priv->eq_table.eq[i].actv_ports.ports);
2858 if (mlx4_init_affinity_hint(dev, port + 1, i))
2859 mlx4_warn(dev, "Couldn't init hint cpumask for EQ %d\n",
2862 /* We divide the Eqs evenly between the two ports.
2863 * (dev->caps.num_comp_vectors / dev->caps.num_ports)
2864 * refers to the number of Eqs per port
2865 * (i.e eqs_per_port). Theoretically, we would like to
2866 * write something like (i + 1) % eqs_per_port == 0.
2867 * However, since there's an asynchronous Eq, we have
2868 * to skip over it by comparing this condition to
2869 * !!((i + 1) > MLX4_EQ_ASYNC).
2871 if ((dev->caps.num_comp_vectors > dev->caps.num_ports) &&
2873 (dev->caps.num_comp_vectors / dev->caps.num_ports)) ==
2874 !!((i + 1) > MLX4_EQ_ASYNC))
2875 /* If dev->caps.num_comp_vectors < dev->caps.num_ports,
2876 * everything is shared anyway.
2881 dev->flags |= MLX4_FLAG_MSI_X;
2888 dev->caps.num_comp_vectors = 1;
2890 BUG_ON(MLX4_EQ_ASYNC >= 2);
2891 for (i = 0; i < 2; ++i) {
2892 priv->eq_table.eq[i].irq = dev->persist->pdev->irq;
2893 if (i != MLX4_EQ_ASYNC) {
2894 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,
2895 dev->caps.num_ports);
2900 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2902 struct devlink *devlink = priv_to_devlink(mlx4_priv(dev));
2903 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
2906 err = devlink_port_register(devlink, &info->devlink_port, port);
2912 if (!mlx4_is_slave(dev)) {
2913 mlx4_init_mac_table(dev, &info->mac_table);
2914 mlx4_init_vlan_table(dev, &info->vlan_table);
2915 mlx4_init_roce_gid_table(dev, &info->gid_table);
2916 info->base_qpn = mlx4_get_base_qpn(dev, port);
2919 sprintf(info->dev_name, "mlx4_port%d", port);
2920 info->port_attr.attr.name = info->dev_name;
2921 if (mlx4_is_mfunc(dev)) {
2922 info->port_attr.attr.mode = 0444;
2924 info->port_attr.attr.mode = 0644;
2925 info->port_attr.store = set_port_type;
2927 info->port_attr.show = show_port_type;
2928 sysfs_attr_init(&info->port_attr.attr);
2930 err = device_create_file(&dev->persist->pdev->dev, &info->port_attr);
2932 mlx4_err(dev, "Failed to create file for port %d\n", port);
2933 devlink_port_unregister(&info->devlink_port);
2938 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
2939 info->port_mtu_attr.attr.name = info->dev_mtu_name;
2940 if (mlx4_is_mfunc(dev)) {
2941 info->port_mtu_attr.attr.mode = 0444;
2943 info->port_mtu_attr.attr.mode = 0644;
2944 info->port_mtu_attr.store = set_port_ib_mtu;
2946 info->port_mtu_attr.show = show_port_ib_mtu;
2947 sysfs_attr_init(&info->port_mtu_attr.attr);
2949 err = device_create_file(&dev->persist->pdev->dev,
2950 &info->port_mtu_attr);
2952 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
2953 device_remove_file(&info->dev->persist->pdev->dev,
2955 devlink_port_unregister(&info->devlink_port);
2963 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
2968 device_remove_file(&info->dev->persist->pdev->dev, &info->port_attr);
2969 device_remove_file(&info->dev->persist->pdev->dev,
2970 &info->port_mtu_attr);
2971 devlink_port_unregister(&info->devlink_port);
2973 #ifdef CONFIG_RFS_ACCEL
2974 free_irq_cpu_rmap(info->rmap);
2979 static int mlx4_init_steering(struct mlx4_dev *dev)
2981 struct mlx4_priv *priv = mlx4_priv(dev);
2982 int num_entries = dev->caps.num_ports;
2985 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
2989 for (i = 0; i < num_entries; i++)
2990 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2991 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
2992 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
2997 static void mlx4_clear_steering(struct mlx4_dev *dev)
2999 struct mlx4_priv *priv = mlx4_priv(dev);
3000 struct mlx4_steer_index *entry, *tmp_entry;
3001 struct mlx4_promisc_qp *pqp, *tmp_pqp;
3002 int num_entries = dev->caps.num_ports;
3005 for (i = 0; i < num_entries; i++) {
3006 for (j = 0; j < MLX4_NUM_STEERS; j++) {
3007 list_for_each_entry_safe(pqp, tmp_pqp,
3008 &priv->steer[i].promisc_qps[j],
3010 list_del(&pqp->list);
3013 list_for_each_entry_safe(entry, tmp_entry,
3014 &priv->steer[i].steer_entries[j],
3016 list_del(&entry->list);
3017 list_for_each_entry_safe(pqp, tmp_pqp,
3020 list_del(&pqp->list);
3030 static int extended_func_num(struct pci_dev *pdev)
3032 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
3035 #define MLX4_OWNER_BASE 0x8069c
3036 #define MLX4_OWNER_SIZE 4
3038 static int mlx4_get_ownership(struct mlx4_dev *dev)
3040 void __iomem *owner;
3043 if (pci_channel_offline(dev->persist->pdev))
3046 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
3050 mlx4_err(dev, "Failed to obtain ownership bit\n");
3059 static void mlx4_free_ownership(struct mlx4_dev *dev)
3061 void __iomem *owner;
3063 if (pci_channel_offline(dev->persist->pdev))
3066 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
3070 mlx4_err(dev, "Failed to obtain ownership bit\n");
3078 #define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\
3079 !!((flags) & MLX4_FLAG_MASTER))
3081 static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev,
3082 u8 total_vfs, int existing_vfs, int reset_flow)
3084 u64 dev_flags = dev->flags;
3086 int fw_enabled_sriov_vfs = min(pci_sriov_get_totalvfs(pdev),
3090 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs),
3097 atomic_inc(&pf_loading);
3098 if (dev->flags & MLX4_FLAG_SRIOV) {
3099 if (existing_vfs != total_vfs) {
3100 mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n",
3101 existing_vfs, total_vfs);
3102 total_vfs = existing_vfs;
3106 dev->dev_vfs = kzalloc(total_vfs * sizeof(*dev->dev_vfs), GFP_KERNEL);
3107 if (NULL == dev->dev_vfs) {
3108 mlx4_err(dev, "Failed to allocate memory for VFs\n");
3112 if (!(dev->flags & MLX4_FLAG_SRIOV)) {
3113 if (total_vfs > fw_enabled_sriov_vfs) {
3114 mlx4_err(dev, "requested vfs (%d) > available vfs (%d). Continuing without SR_IOV\n",
3115 total_vfs, fw_enabled_sriov_vfs);
3119 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs);
3120 err = pci_enable_sriov(pdev, total_vfs);
3123 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n",
3127 mlx4_warn(dev, "Running in master mode\n");
3128 dev_flags |= MLX4_FLAG_SRIOV |
3130 dev_flags &= ~MLX4_FLAG_SLAVE;
3131 dev->persist->num_vfs = total_vfs;
3136 atomic_dec(&pf_loading);
3138 dev->persist->num_vfs = 0;
3139 kfree(dev->dev_vfs);
3140 dev->dev_vfs = NULL;
3141 return dev_flags & ~MLX4_FLAG_MASTER;
3145 MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1,
3148 static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
3151 int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2];
3152 /* Checking for 64 VFs as a limitation of CX2 */
3153 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) &&
3154 requested_vfs >= 64) {
3155 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n",
3157 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64;
3162 static int mlx4_pci_enable_device(struct mlx4_dev *dev)
3164 struct pci_dev *pdev = dev->persist->pdev;
3167 mutex_lock(&dev->persist->pci_status_mutex);
3168 if (dev->persist->pci_status == MLX4_PCI_STATUS_DISABLED) {
3169 err = pci_enable_device(pdev);
3171 dev->persist->pci_status = MLX4_PCI_STATUS_ENABLED;
3173 mutex_unlock(&dev->persist->pci_status_mutex);
3178 static void mlx4_pci_disable_device(struct mlx4_dev *dev)
3180 struct pci_dev *pdev = dev->persist->pdev;
3182 mutex_lock(&dev->persist->pci_status_mutex);
3183 if (dev->persist->pci_status == MLX4_PCI_STATUS_ENABLED) {
3184 pci_disable_device(pdev);
3185 dev->persist->pci_status = MLX4_PCI_STATUS_DISABLED;
3187 mutex_unlock(&dev->persist->pci_status_mutex);
3190 static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data,
3191 int total_vfs, int *nvfs, struct mlx4_priv *priv,
3194 struct mlx4_dev *dev;
3199 struct mlx4_dev_cap *dev_cap = NULL;
3200 int existing_vfs = 0;
3204 INIT_LIST_HEAD(&priv->ctx_list);
3205 spin_lock_init(&priv->ctx_lock);
3207 mutex_init(&priv->port_mutex);
3208 mutex_init(&priv->bond_mutex);
3210 INIT_LIST_HEAD(&priv->pgdir_list);
3211 mutex_init(&priv->pgdir_mutex);
3212 spin_lock_init(&priv->cmd.context_lock);
3214 INIT_LIST_HEAD(&priv->bf_list);
3215 mutex_init(&priv->bf_mutex);
3217 dev->rev_id = pdev->revision;
3218 dev->numa_node = dev_to_node(&pdev->dev);
3220 /* Detect if this device is a virtual function */
3221 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
3222 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
3223 dev->flags |= MLX4_FLAG_SLAVE;
3225 /* We reset the device and enable SRIOV only for physical
3226 * devices. Try to claim ownership on the device;
3227 * if already taken, skip -- do not allow multiple PFs */
3228 err = mlx4_get_ownership(dev);
3233 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n");
3238 atomic_set(&priv->opreq_count, 0);
3239 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
3242 * Now reset the HCA before we touch the PCI capabilities or
3243 * attempt a firmware command, since a boot ROM may have left
3244 * the HCA in an undefined state.
3246 err = mlx4_reset(dev);
3248 mlx4_err(dev, "Failed to reset HCA, aborting\n");
3253 dev->flags = MLX4_FLAG_MASTER;
3254 existing_vfs = pci_num_vf(pdev);
3256 dev->flags |= MLX4_FLAG_SRIOV;
3257 dev->persist->num_vfs = total_vfs;
3261 /* on load remove any previous indication of internal error,
3264 dev->persist->state = MLX4_DEVICE_STATE_UP;
3267 err = mlx4_cmd_init(dev);
3269 mlx4_err(dev, "Failed to init command interface, aborting\n");
3273 /* In slave functions, the communication channel must be initialized
3274 * before posting commands. Also, init num_slaves before calling
3276 if (mlx4_is_mfunc(dev)) {
3277 if (mlx4_is_master(dev)) {
3278 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
3281 dev->num_slaves = 0;
3282 err = mlx4_multi_func_init(dev);
3284 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n");
3290 err = mlx4_init_fw(dev);
3292 mlx4_err(dev, "Failed to init fw, aborting.\n");
3296 if (mlx4_is_master(dev)) {
3297 /* when we hit the goto slave_start below, dev_cap already initialized */
3299 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL);
3306 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
3308 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
3312 if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
3315 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
3316 u64 dev_flags = mlx4_enable_sriov(dev, pdev,
3322 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3323 dev->flags = dev_flags;
3324 if (!SRIOV_VALID_STATE(dev->flags)) {
3325 mlx4_err(dev, "Invalid SRIOV state\n");
3328 err = mlx4_reset(dev);
3330 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
3336 /* Legacy mode FW requires SRIOV to be enabled before
3337 * doing QUERY_DEV_CAP, since max_eq's value is different if
3340 memset(dev_cap, 0, sizeof(*dev_cap));
3341 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
3343 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
3347 if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
3352 err = mlx4_init_hca(dev);
3354 if (err == -EACCES) {
3355 /* Not primary Physical function
3356 * Running in slave mode */
3357 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3358 /* We're not a PF */
3359 if (dev->flags & MLX4_FLAG_SRIOV) {
3361 pci_disable_sriov(pdev);
3362 if (mlx4_is_master(dev) && !reset_flow)
3363 atomic_dec(&pf_loading);
3364 dev->flags &= ~MLX4_FLAG_SRIOV;
3366 if (!mlx4_is_slave(dev))
3367 mlx4_free_ownership(dev);
3368 dev->flags |= MLX4_FLAG_SLAVE;
3369 dev->flags &= ~MLX4_FLAG_MASTER;
3375 if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
3376 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs,
3377 existing_vfs, reset_flow);
3379 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) {
3380 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR);
3381 dev->flags = dev_flags;
3382 err = mlx4_cmd_init(dev);
3384 /* Only VHCR is cleaned up, so could still
3387 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n");
3391 dev->flags = dev_flags;
3394 if (!SRIOV_VALID_STATE(dev->flags)) {
3395 mlx4_err(dev, "Invalid SRIOV state\n");
3400 /* check if the device is functioning at its maximum possible speed.
3401 * No return code for this call, just warn the user in case of PCI
3402 * express device capabilities are under-satisfied by the bus.
3404 if (!mlx4_is_slave(dev))
3405 pcie_print_link_status(dev->persist->pdev);
3407 /* In master functions, the communication channel must be initialized
3408 * after obtaining its address from fw */
3409 if (mlx4_is_master(dev)) {
3410 if (dev->caps.num_ports < 2 &&
3414 "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n",
3415 dev->caps.num_ports);
3418 memcpy(dev->persist->nvfs, nvfs, sizeof(dev->persist->nvfs));
3421 i < sizeof(dev->persist->nvfs)/
3422 sizeof(dev->persist->nvfs[0]); i++) {
3425 for (j = 0; j < dev->persist->nvfs[i]; ++sum, ++j) {
3426 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1;
3427 dev->dev_vfs[sum].n_ports = i < 2 ? 1 :
3428 dev->caps.num_ports;
3432 /* In master functions, the communication channel
3433 * must be initialized after obtaining its address from fw
3435 err = mlx4_multi_func_init(dev);
3437 mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n");
3442 err = mlx4_alloc_eq_table(dev);
3444 goto err_master_mfunc;
3446 bitmap_zero(priv->msix_ctl.pool_bm, MAX_MSIX);
3447 mutex_init(&priv->msix_ctl.pool_lock);
3449 mlx4_enable_msi_x(dev);
3450 if ((mlx4_is_mfunc(dev)) &&
3451 !(dev->flags & MLX4_FLAG_MSI_X)) {
3453 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n");
3457 if (!mlx4_is_slave(dev)) {
3458 err = mlx4_init_steering(dev);
3460 goto err_disable_msix;
3463 mlx4_init_quotas(dev);
3465 err = mlx4_setup_hca(dev);
3466 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
3467 !mlx4_is_mfunc(dev)) {
3468 dev->flags &= ~MLX4_FLAG_MSI_X;
3469 dev->caps.num_comp_vectors = 1;
3470 pci_disable_msix(pdev);
3471 err = mlx4_setup_hca(dev);
3477 /* When PF resources are ready arm its comm channel to enable
3480 if (mlx4_is_master(dev)) {
3481 err = mlx4_ARM_COMM_CHANNEL(dev);
3483 mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
3489 for (port = 1; port <= dev->caps.num_ports; port++) {
3490 err = mlx4_init_port_info(dev, port);
3495 priv->v2p.port1 = 1;
3496 priv->v2p.port2 = 2;
3498 err = mlx4_register_device(dev);
3502 mlx4_request_modules(dev);
3504 mlx4_sense_init(dev);
3505 mlx4_start_sense(dev);
3509 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
3510 atomic_dec(&pf_loading);
3516 for (--port; port >= 1; --port)
3517 mlx4_cleanup_port_info(&priv->port[port]);
3519 mlx4_cleanup_default_counters(dev);
3520 if (!mlx4_is_slave(dev))
3521 mlx4_cleanup_counters_table(dev);
3522 mlx4_cleanup_qp_table(dev);
3523 mlx4_cleanup_srq_table(dev);
3524 mlx4_cleanup_cq_table(dev);
3525 mlx4_cmd_use_polling(dev);
3526 mlx4_cleanup_eq_table(dev);
3527 mlx4_cleanup_mcg_table(dev);
3528 mlx4_cleanup_mr_table(dev);
3529 mlx4_cleanup_xrcd_table(dev);
3530 mlx4_cleanup_pd_table(dev);
3531 mlx4_cleanup_uar_table(dev);
3534 if (!mlx4_is_slave(dev))
3535 mlx4_clear_steering(dev);
3538 if (dev->flags & MLX4_FLAG_MSI_X)
3539 pci_disable_msix(pdev);
3542 mlx4_free_eq_table(dev);
3545 if (mlx4_is_master(dev)) {
3546 mlx4_free_resource_tracker(dev, RES_TR_FREE_STRUCTS_ONLY);
3547 mlx4_multi_func_cleanup(dev);
3550 if (mlx4_is_slave(dev))
3551 mlx4_slave_destroy_special_qp_cap(dev);
3554 mlx4_close_hca(dev);
3560 if (mlx4_is_slave(dev))
3561 mlx4_multi_func_cleanup(dev);
3564 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3567 if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs) {
3568 pci_disable_sriov(pdev);
3569 dev->flags &= ~MLX4_FLAG_SRIOV;
3572 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
3573 atomic_dec(&pf_loading);
3575 kfree(priv->dev.dev_vfs);
3577 if (!mlx4_is_slave(dev))
3578 mlx4_free_ownership(dev);
3584 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data,
3585 struct mlx4_priv *priv)
3588 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3589 int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3590 const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = {
3591 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
3592 unsigned total_vfs = 0;
3595 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
3597 err = mlx4_pci_enable_device(&priv->dev);
3599 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
3603 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
3604 * per port, we must limit the number of VFs to 63 (since their are
3607 for (i = 0; i < ARRAY_SIZE(nvfs) && i < num_vfs_argc;
3608 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) {
3609 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i];
3611 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n");
3613 goto err_disable_pdev;
3616 for (i = 0; i < ARRAY_SIZE(prb_vf) && i < probe_vfs_argc;
3618 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i];
3619 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) {
3620 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
3622 goto err_disable_pdev;
3625 if (total_vfs > MLX4_MAX_NUM_VF) {
3627 "Requested more VF's (%d) than allowed by hw (%d)\n",
3628 total_vfs, MLX4_MAX_NUM_VF);
3630 goto err_disable_pdev;
3633 for (i = 0; i < MLX4_MAX_PORTS; i++) {
3634 if (nvfs[i] + nvfs[2] > MLX4_MAX_NUM_VF_P_PORT) {
3636 "Requested more VF's (%d) for port (%d) than allowed by driver (%d)\n",
3637 nvfs[i] + nvfs[2], i + 1,
3638 MLX4_MAX_NUM_VF_P_PORT);
3640 goto err_disable_pdev;
3644 /* Check for BARs. */
3645 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
3646 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3647 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
3648 pci_dev_data, pci_resource_flags(pdev, 0));
3650 goto err_disable_pdev;
3652 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
3653 dev_err(&pdev->dev, "Missing UAR, aborting\n");
3655 goto err_disable_pdev;
3658 err = pci_request_regions(pdev, DRV_NAME);
3660 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
3661 goto err_disable_pdev;
3664 pci_set_master(pdev);
3666 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3668 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
3669 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3671 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
3672 goto err_release_regions;
3675 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3677 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
3678 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3680 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n");
3681 goto err_release_regions;
3685 /* Allow large DMA segments, up to the firmware limit of 1 GB */
3686 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
3687 /* Detect if this device is a virtual function */
3688 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
3689 /* When acting as pf, we normally skip vfs unless explicitly
3690 * requested to probe them.
3693 unsigned vfs_offset = 0;
3695 for (i = 0; i < ARRAY_SIZE(nvfs) &&
3696 vfs_offset + nvfs[i] < extended_func_num(pdev);
3697 vfs_offset += nvfs[i], i++)
3699 if (i == ARRAY_SIZE(nvfs)) {
3701 goto err_release_regions;
3703 if ((extended_func_num(pdev) - vfs_offset)
3705 dev_warn(&pdev->dev, "Skipping virtual function:%d\n",
3706 extended_func_num(pdev));
3708 goto err_release_regions;
3713 err = mlx4_catas_init(&priv->dev);
3715 goto err_release_regions;
3717 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 0);
3724 mlx4_catas_end(&priv->dev);
3726 err_release_regions:
3727 pci_release_regions(pdev);
3730 mlx4_pci_disable_device(&priv->dev);
3734 static int mlx4_devlink_port_type_set(struct devlink_port *devlink_port,
3735 enum devlink_port_type port_type)
3737 struct mlx4_port_info *info = container_of(devlink_port,
3738 struct mlx4_port_info,
3740 enum mlx4_port_type mlx4_port_type;
3742 switch (port_type) {
3743 case DEVLINK_PORT_TYPE_AUTO:
3744 mlx4_port_type = MLX4_PORT_TYPE_AUTO;
3746 case DEVLINK_PORT_TYPE_ETH:
3747 mlx4_port_type = MLX4_PORT_TYPE_ETH;
3749 case DEVLINK_PORT_TYPE_IB:
3750 mlx4_port_type = MLX4_PORT_TYPE_IB;
3756 return __set_port_type(info, mlx4_port_type);
3759 static const struct devlink_ops mlx4_devlink_ops = {
3760 .port_type_set = mlx4_devlink_port_type_set,
3763 static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
3765 struct devlink *devlink;
3766 struct mlx4_priv *priv;
3767 struct mlx4_dev *dev;
3770 printk_once(KERN_INFO "%s", mlx4_version);
3772 devlink = devlink_alloc(&mlx4_devlink_ops, sizeof(*priv));
3775 priv = devlink_priv(devlink);
3778 dev->persist = kzalloc(sizeof(*dev->persist), GFP_KERNEL);
3779 if (!dev->persist) {
3781 goto err_devlink_free;
3783 dev->persist->pdev = pdev;
3784 dev->persist->dev = dev;
3785 pci_set_drvdata(pdev, dev->persist);
3786 priv->pci_dev_data = id->driver_data;
3787 mutex_init(&dev->persist->device_state_mutex);
3788 mutex_init(&dev->persist->interface_state_mutex);
3789 mutex_init(&dev->persist->pci_status_mutex);
3791 ret = devlink_register(devlink, &pdev->dev);
3793 goto err_persist_free;
3795 ret = __mlx4_init_one(pdev, id->driver_data, priv);
3797 goto err_devlink_unregister;
3799 pci_save_state(pdev);
3802 err_devlink_unregister:
3803 devlink_unregister(devlink);
3805 kfree(dev->persist);
3807 devlink_free(devlink);
3811 static void mlx4_clean_dev(struct mlx4_dev *dev)
3813 struct mlx4_dev_persistent *persist = dev->persist;
3814 struct mlx4_priv *priv = mlx4_priv(dev);
3815 unsigned long flags = (dev->flags & RESET_PERSIST_MASK_FLAGS);
3817 memset(priv, 0, sizeof(*priv));
3818 priv->dev.persist = persist;
3819 priv->dev.flags = flags;
3822 static void mlx4_unload_one(struct pci_dev *pdev)
3824 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3825 struct mlx4_dev *dev = persist->dev;
3826 struct mlx4_priv *priv = mlx4_priv(dev);
3833 /* saving current ports type for further use */
3834 for (i = 0; i < dev->caps.num_ports; i++) {
3835 dev->persist->curr_port_type[i] = dev->caps.port_type[i + 1];
3836 dev->persist->curr_port_poss_type[i] = dev->caps.
3837 possible_type[i + 1];
3840 pci_dev_data = priv->pci_dev_data;
3842 mlx4_stop_sense(dev);
3843 mlx4_unregister_device(dev);
3845 for (p = 1; p <= dev->caps.num_ports; p++) {
3846 mlx4_cleanup_port_info(&priv->port[p]);
3847 mlx4_CLOSE_PORT(dev, p);
3850 if (mlx4_is_master(dev))
3851 mlx4_free_resource_tracker(dev,
3852 RES_TR_FREE_SLAVES_ONLY);
3854 mlx4_cleanup_default_counters(dev);
3855 if (!mlx4_is_slave(dev))
3856 mlx4_cleanup_counters_table(dev);
3857 mlx4_cleanup_qp_table(dev);
3858 mlx4_cleanup_srq_table(dev);
3859 mlx4_cleanup_cq_table(dev);
3860 mlx4_cmd_use_polling(dev);
3861 mlx4_cleanup_eq_table(dev);
3862 mlx4_cleanup_mcg_table(dev);
3863 mlx4_cleanup_mr_table(dev);
3864 mlx4_cleanup_xrcd_table(dev);
3865 mlx4_cleanup_pd_table(dev);
3867 if (mlx4_is_master(dev))
3868 mlx4_free_resource_tracker(dev,
3869 RES_TR_FREE_STRUCTS_ONLY);
3872 mlx4_uar_free(dev, &priv->driver_uar);
3873 mlx4_cleanup_uar_table(dev);
3874 if (!mlx4_is_slave(dev))
3875 mlx4_clear_steering(dev);
3876 mlx4_free_eq_table(dev);
3877 if (mlx4_is_master(dev))
3878 mlx4_multi_func_cleanup(dev);
3879 mlx4_close_hca(dev);
3881 if (mlx4_is_slave(dev))
3882 mlx4_multi_func_cleanup(dev);
3883 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3885 if (dev->flags & MLX4_FLAG_MSI_X)
3886 pci_disable_msix(pdev);
3888 if (!mlx4_is_slave(dev))
3889 mlx4_free_ownership(dev);
3891 mlx4_slave_destroy_special_qp_cap(dev);
3892 kfree(dev->dev_vfs);
3894 mlx4_clean_dev(dev);
3895 priv->pci_dev_data = pci_dev_data;
3899 static void mlx4_remove_one(struct pci_dev *pdev)
3901 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3902 struct mlx4_dev *dev = persist->dev;
3903 struct mlx4_priv *priv = mlx4_priv(dev);
3904 struct devlink *devlink = priv_to_devlink(priv);
3907 if (mlx4_is_slave(dev))
3908 persist->interface_state |= MLX4_INTERFACE_STATE_NOWAIT;
3910 mutex_lock(&persist->interface_state_mutex);
3911 persist->interface_state |= MLX4_INTERFACE_STATE_DELETION;
3912 mutex_unlock(&persist->interface_state_mutex);
3914 /* Disabling SR-IOV is not allowed while there are active vf's */
3915 if (mlx4_is_master(dev) && dev->flags & MLX4_FLAG_SRIOV) {
3916 active_vfs = mlx4_how_many_lives_vf(dev);
3918 pr_warn("Removing PF when there are active VF's !!\n");
3919 pr_warn("Will not disable SR-IOV.\n");
3923 /* device marked to be under deletion running now without the lock
3924 * letting other tasks to be terminated
3926 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
3927 mlx4_unload_one(pdev);
3929 mlx4_info(dev, "%s: interface is down\n", __func__);
3930 mlx4_catas_end(dev);
3931 if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) {
3932 mlx4_warn(dev, "Disabling SR-IOV\n");
3933 pci_disable_sriov(pdev);
3936 pci_release_regions(pdev);
3937 mlx4_pci_disable_device(dev);
3938 devlink_unregister(devlink);
3939 kfree(dev->persist);
3940 devlink_free(devlink);
3943 static int restore_current_port_types(struct mlx4_dev *dev,
3944 enum mlx4_port_type *types,
3945 enum mlx4_port_type *poss_types)
3947 struct mlx4_priv *priv = mlx4_priv(dev);
3950 mlx4_stop_sense(dev);
3952 mutex_lock(&priv->port_mutex);
3953 for (i = 0; i < dev->caps.num_ports; i++)
3954 dev->caps.possible_type[i + 1] = poss_types[i];
3955 err = mlx4_change_port_types(dev, types);
3956 mlx4_start_sense(dev);
3957 mutex_unlock(&priv->port_mutex);
3962 int mlx4_restart_one(struct pci_dev *pdev)
3964 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3965 struct mlx4_dev *dev = persist->dev;
3966 struct mlx4_priv *priv = mlx4_priv(dev);
3967 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3968 int pci_dev_data, err, total_vfs;
3970 pci_dev_data = priv->pci_dev_data;
3971 total_vfs = dev->persist->num_vfs;
3972 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
3974 mlx4_unload_one(pdev);
3975 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 1);
3977 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n",
3978 __func__, pci_name(pdev), err);
3982 err = restore_current_port_types(dev, dev->persist->curr_port_type,
3983 dev->persist->curr_port_poss_type);
3985 mlx4_err(dev, "could not restore original port types (%d)\n",
3991 #define MLX_SP(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_FORCE_SENSE_PORT }
3992 #define MLX_VF(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_IS_VF }
3993 #define MLX_GN(id) { PCI_VDEVICE(MELLANOX, id), 0 }
3995 static const struct pci_device_id mlx4_pci_table[] = {
3996 #ifdef CONFIG_MLX4_CORE_GEN2
3997 /* MT25408 "Hermon" */
3998 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_SDR), /* SDR */
3999 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR), /* DDR */
4000 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR), /* QDR */
4001 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2), /* DDR Gen2 */
4002 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2), /* QDR Gen2 */
4003 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN), /* EN 10GigE */
4004 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2), /* EN 10GigE Gen2 */
4005 /* MT25458 ConnectX EN 10GBASE-T */
4006 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN),
4007 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2), /* Gen2 */
4008 /* MT26468 ConnectX EN 10GigE PCIe Gen2*/
4009 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2),
4010 /* MT26438 ConnectX EN 40GigE PCIe Gen2 5GT/s */
4011 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2),
4012 /* MT26478 ConnectX2 40GigE PCIe Gen2 */
4013 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX2),
4014 /* MT25400 Family [ConnectX-2] */
4015 MLX_VF(0x1002), /* Virtual Function */
4016 #endif /* CONFIG_MLX4_CORE_GEN2 */
4017 /* MT27500 Family [ConnectX-3] */
4018 MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3),
4019 MLX_VF(0x1004), /* Virtual Function */
4020 MLX_GN(0x1005), /* MT27510 Family */
4021 MLX_GN(0x1006), /* MT27511 Family */
4022 MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO), /* MT27520 Family */
4023 MLX_GN(0x1008), /* MT27521 Family */
4024 MLX_GN(0x1009), /* MT27530 Family */
4025 MLX_GN(0x100a), /* MT27531 Family */
4026 MLX_GN(0x100b), /* MT27540 Family */
4027 MLX_GN(0x100c), /* MT27541 Family */
4028 MLX_GN(0x100d), /* MT27550 Family */
4029 MLX_GN(0x100e), /* MT27551 Family */
4030 MLX_GN(0x100f), /* MT27560 Family */
4031 MLX_GN(0x1010), /* MT27561 Family */
4034 * See the mellanox_check_broken_intx_masking() quirk when
4041 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
4043 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
4044 pci_channel_state_t state)
4046 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4048 mlx4_err(persist->dev, "mlx4_pci_err_detected was called\n");
4049 mlx4_enter_error_state(persist);
4051 mutex_lock(&persist->interface_state_mutex);
4052 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
4053 mlx4_unload_one(pdev);
4055 mutex_unlock(&persist->interface_state_mutex);
4056 if (state == pci_channel_io_perm_failure)
4057 return PCI_ERS_RESULT_DISCONNECT;
4059 mlx4_pci_disable_device(persist->dev);
4060 return PCI_ERS_RESULT_NEED_RESET;
4063 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
4065 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4066 struct mlx4_dev *dev = persist->dev;
4069 mlx4_err(dev, "mlx4_pci_slot_reset was called\n");
4070 err = mlx4_pci_enable_device(dev);
4072 mlx4_err(dev, "Can not re-enable device, err=%d\n", err);
4073 return PCI_ERS_RESULT_DISCONNECT;
4076 pci_set_master(pdev);
4077 pci_restore_state(pdev);
4078 pci_save_state(pdev);
4079 return PCI_ERS_RESULT_RECOVERED;
4082 static void mlx4_pci_resume(struct pci_dev *pdev)
4084 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4085 struct mlx4_dev *dev = persist->dev;
4086 struct mlx4_priv *priv = mlx4_priv(dev);
4087 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
4091 mlx4_err(dev, "%s was called\n", __func__);
4092 total_vfs = dev->persist->num_vfs;
4093 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
4095 mutex_lock(&persist->interface_state_mutex);
4096 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) {
4097 err = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, nvfs,
4100 mlx4_err(dev, "%s: mlx4_load_one failed, err=%d\n",
4105 err = restore_current_port_types(dev, dev->persist->
4106 curr_port_type, dev->persist->
4107 curr_port_poss_type);
4109 mlx4_err(dev, "could not restore original port types (%d)\n", err);
4112 mutex_unlock(&persist->interface_state_mutex);
4116 static void mlx4_shutdown(struct pci_dev *pdev)
4118 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4120 mlx4_info(persist->dev, "mlx4_shutdown was called\n");
4121 mutex_lock(&persist->interface_state_mutex);
4122 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
4123 mlx4_unload_one(pdev);
4124 mutex_unlock(&persist->interface_state_mutex);
4127 static const struct pci_error_handlers mlx4_err_handler = {
4128 .error_detected = mlx4_pci_err_detected,
4129 .slot_reset = mlx4_pci_slot_reset,
4130 .resume = mlx4_pci_resume,
4133 static int mlx4_suspend(struct pci_dev *pdev, pm_message_t state)
4135 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4136 struct mlx4_dev *dev = persist->dev;
4138 mlx4_err(dev, "suspend was called\n");
4139 mutex_lock(&persist->interface_state_mutex);
4140 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
4141 mlx4_unload_one(pdev);
4142 mutex_unlock(&persist->interface_state_mutex);
4147 static int mlx4_resume(struct pci_dev *pdev)
4149 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4150 struct mlx4_dev *dev = persist->dev;
4151 struct mlx4_priv *priv = mlx4_priv(dev);
4152 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
4156 mlx4_err(dev, "resume was called\n");
4157 total_vfs = dev->persist->num_vfs;
4158 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
4160 mutex_lock(&persist->interface_state_mutex);
4161 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) {
4162 ret = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs,
4165 ret = restore_current_port_types(dev,
4166 dev->persist->curr_port_type,
4167 dev->persist->curr_port_poss_type);
4169 mlx4_err(dev, "resume: could not restore original port types (%d)\n", ret);
4172 mutex_unlock(&persist->interface_state_mutex);
4177 static struct pci_driver mlx4_driver = {
4179 .id_table = mlx4_pci_table,
4180 .probe = mlx4_init_one,
4181 .shutdown = mlx4_shutdown,
4182 .remove = mlx4_remove_one,
4183 .suspend = mlx4_suspend,
4184 .resume = mlx4_resume,
4185 .err_handler = &mlx4_err_handler,
4188 static int __init mlx4_verify_params(void)
4191 pr_warn("mlx4_core: bad msi_x: %d\n", msi_x);
4195 if ((log_num_mac < 0) || (log_num_mac > 7)) {
4196 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac);
4200 if (log_num_vlan != 0)
4201 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
4202 MLX4_LOG_NUM_VLANS);
4205 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n");
4207 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
4208 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n",
4213 /* Check if module param for ports type has legal combination */
4214 if (port_type_array[0] == false && port_type_array[1] == true) {
4215 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
4216 port_type_array[0] = true;
4219 if (mlx4_log_num_mgm_entry_size < -7 ||
4220 (mlx4_log_num_mgm_entry_size > 0 &&
4221 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
4222 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE))) {
4223 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-7..0 or %d..%d)\n",
4224 mlx4_log_num_mgm_entry_size,
4225 MLX4_MIN_MGM_LOG_ENTRY_SIZE,
4226 MLX4_MAX_MGM_LOG_ENTRY_SIZE);
4233 static int __init mlx4_init(void)
4237 if (mlx4_verify_params())
4241 mlx4_wq = create_singlethread_workqueue("mlx4");
4245 ret = pci_register_driver(&mlx4_driver);
4247 destroy_workqueue(mlx4_wq);
4248 return ret < 0 ? ret : 0;
4251 static void __exit mlx4_cleanup(void)
4253 pci_unregister_driver(&mlx4_driver);
4254 destroy_workqueue(mlx4_wq);
4257 module_init(mlx4_init);
4258 module_exit(mlx4_cleanup);