2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/etherdevice.h>
36 #include <linux/mlx4/cmd.h>
37 #include <linux/module.h>
38 #include <linux/cache.h>
44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
49 extern void __buggy_use_of_MLX4_GET(void);
50 extern void __buggy_use_of_MLX4_PUT(void);
52 static bool enable_qos;
53 module_param(enable_qos, bool, 0444);
54 MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
56 #define MLX4_GET(dest, source, offset) \
58 void *__p = (char *) (source) + (offset); \
59 switch (sizeof (dest)) { \
60 case 1: (dest) = *(u8 *) __p; break; \
61 case 2: (dest) = be16_to_cpup(__p); break; \
62 case 4: (dest) = be32_to_cpup(__p); break; \
63 case 8: (dest) = be64_to_cpup(__p); break; \
64 default: __buggy_use_of_MLX4_GET(); \
68 #define MLX4_PUT(dest, source, offset) \
70 void *__d = ((char *) (dest) + (offset)); \
71 switch (sizeof(source)) { \
72 case 1: *(u8 *) __d = (source); break; \
73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
76 default: __buggy_use_of_MLX4_PUT(); \
80 static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
82 static const char *fname[] = {
83 [ 0] = "RC transport",
84 [ 1] = "UC transport",
85 [ 2] = "UD transport",
86 [ 3] = "XRC transport",
88 [ 7] = "IPoIB checksum offload",
89 [ 8] = "P_Key violation counter",
90 [ 9] = "Q_Key violation counter",
91 [12] = "Dual Port Different Protocol (DPDP) support",
92 [15] = "Big LSO headers",
95 [18] = "Atomic ops support",
96 [19] = "Raw multicast support",
97 [20] = "Address vector port checking support",
98 [21] = "UD multicast support",
99 [30] = "IBoE support",
100 [32] = "Unicast loopback support",
101 [34] = "FCS header control",
102 [37] = "Wake On LAN (port1) support",
103 [38] = "Wake On LAN (port2) support",
104 [40] = "UDP RSS support",
105 [41] = "Unicast VEP steering support",
106 [42] = "Multicast VEP steering support",
107 [48] = "Counters support",
108 [53] = "Port ETS Scheduler support",
109 [55] = "Port link type sensing support",
110 [59] = "Port management change event support",
111 [61] = "64 byte EQE support",
112 [62] = "64 byte CQE support",
116 mlx4_dbg(dev, "DEV_CAP flags:\n");
117 for (i = 0; i < ARRAY_SIZE(fname); ++i)
118 if (fname[i] && (flags & (1LL << i)))
119 mlx4_dbg(dev, " %s\n", fname[i]);
122 static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
124 static const char * const fname[] = {
126 [1] = "RSS Toeplitz Hash Function support",
127 [2] = "RSS XOR Hash Function support",
128 [3] = "Device managed flow steering support",
129 [4] = "Automatic MAC reassignment support",
130 [5] = "Time stamping support",
131 [6] = "VST (control vlan insertion/stripping) support",
132 [7] = "FSM (MAC anti-spoofing) support",
133 [8] = "Dynamic QP updates support",
134 [9] = "Device managed flow steering IPoIB support",
135 [10] = "TCP/IP offloads/flow-steering for VXLAN support",
136 [11] = "MAD DEMUX (Secure-Host) support",
137 [12] = "Large cache line (>64B) CQE stride support",
138 [13] = "Large cache line (>64B) EQE stride support",
139 [14] = "Ethernet protocol control support",
140 [15] = "Ethernet Backplane autoneg support",
141 [16] = "CONFIG DEV support",
142 [17] = "Asymmetric EQs support",
143 [18] = "More than 80 VFs support",
144 [19] = "Performance optimized for limited rule configuration flow steering support",
145 [20] = "Recoverable error events support",
146 [21] = "Port Remap support",
147 [22] = "QCN support",
148 [23] = "QP rate limiting support"
152 for (i = 0; i < ARRAY_SIZE(fname); ++i)
153 if (fname[i] && (flags & (1LL << i)))
154 mlx4_dbg(dev, " %s\n", fname[i]);
157 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
159 struct mlx4_cmd_mailbox *mailbox;
163 #define MOD_STAT_CFG_IN_SIZE 0x100
165 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
166 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
168 mailbox = mlx4_alloc_cmd_mailbox(dev);
170 return PTR_ERR(mailbox);
171 inbox = mailbox->buf;
173 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
174 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
176 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
177 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
179 mlx4_free_cmd_mailbox(dev, mailbox);
183 int mlx4_QUERY_FUNC(struct mlx4_dev *dev, struct mlx4_func *func, int slave)
185 struct mlx4_cmd_mailbox *mailbox;
192 #define QUERY_FUNC_BUS_OFFSET 0x00
193 #define QUERY_FUNC_DEVICE_OFFSET 0x01
194 #define QUERY_FUNC_FUNCTION_OFFSET 0x01
195 #define QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET 0x03
196 #define QUERY_FUNC_RSVD_EQS_OFFSET 0x04
197 #define QUERY_FUNC_MAX_EQ_OFFSET 0x06
198 #define QUERY_FUNC_RSVD_UARS_OFFSET 0x0b
200 mailbox = mlx4_alloc_cmd_mailbox(dev);
202 return PTR_ERR(mailbox);
203 outbox = mailbox->buf;
207 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, 0,
209 MLX4_CMD_TIME_CLASS_A,
214 MLX4_GET(field, outbox, QUERY_FUNC_BUS_OFFSET);
215 func->bus = field & 0xf;
216 MLX4_GET(field, outbox, QUERY_FUNC_DEVICE_OFFSET);
217 func->device = field & 0xf1;
218 MLX4_GET(field, outbox, QUERY_FUNC_FUNCTION_OFFSET);
219 func->function = field & 0x7;
220 MLX4_GET(field, outbox, QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET);
221 func->physical_function = field & 0xf;
222 MLX4_GET(field16, outbox, QUERY_FUNC_RSVD_EQS_OFFSET);
223 func->rsvd_eqs = field16 & 0xffff;
224 MLX4_GET(field16, outbox, QUERY_FUNC_MAX_EQ_OFFSET);
225 func->max_eq = field16 & 0xffff;
226 MLX4_GET(field, outbox, QUERY_FUNC_RSVD_UARS_OFFSET);
227 func->rsvd_uars = field & 0x0f;
229 mlx4_dbg(dev, "Bus: %d, Device: %d, Function: %d, Physical function: %d, Max EQs: %d, Reserved EQs: %d, Reserved UARs: %d\n",
230 func->bus, func->device, func->function, func->physical_function,
231 func->max_eq, func->rsvd_eqs, func->rsvd_uars);
234 mlx4_free_cmd_mailbox(dev, mailbox);
238 int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
239 struct mlx4_vhcr *vhcr,
240 struct mlx4_cmd_mailbox *inbox,
241 struct mlx4_cmd_mailbox *outbox,
242 struct mlx4_cmd_info *cmd)
244 struct mlx4_priv *priv = mlx4_priv(dev);
246 u32 size, proxy_qp, qkey;
248 struct mlx4_func func;
250 #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
251 #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
252 #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
253 #define QUERY_FUNC_CAP_FMR_OFFSET 0x8
254 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10
255 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14
256 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18
257 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20
258 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24
259 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28
260 #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
261 #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30
262 #define QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET 0x48
264 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50
265 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54
266 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58
267 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60
268 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64
269 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68
271 #define QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET 0x6c
273 #define QUERY_FUNC_CAP_FMR_FLAG 0x80
274 #define QUERY_FUNC_CAP_FLAG_RDMA 0x40
275 #define QUERY_FUNC_CAP_FLAG_ETH 0x80
276 #define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10
277 #define QUERY_FUNC_CAP_FLAG_RESD_LKEY 0x08
278 #define QUERY_FUNC_CAP_FLAG_VALID_MAILBOX 0x04
280 #define QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG (1UL << 31)
281 #define QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG (1UL << 30)
283 /* when opcode modifier = 1 */
284 #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
285 #define QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET 0x4
286 #define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8
287 #define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc
289 #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10
290 #define QUERY_FUNC_CAP_QP0_PROXY 0x14
291 #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18
292 #define QUERY_FUNC_CAP_QP1_PROXY 0x1c
293 #define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28
295 #define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40
296 #define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80
297 #define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10
298 #define QUERY_FUNC_CAP_VF_ENABLE_QP0 0x08
300 #define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80
301 #define QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS (1 << 31)
303 if (vhcr->op_modifier == 1) {
304 struct mlx4_active_ports actv_ports =
305 mlx4_get_active_ports(dev, slave);
306 int converted_port = mlx4_slave_convert_port(
307 dev, slave, vhcr->in_modifier);
309 if (converted_port < 0)
312 vhcr->in_modifier = converted_port;
313 /* phys-port = logical-port */
314 field = vhcr->in_modifier -
315 find_first_bit(actv_ports.ports, dev->caps.num_ports);
316 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
318 port = vhcr->in_modifier;
319 proxy_qp = dev->phys_caps.base_proxy_sqpn + 8 * slave + port - 1;
321 /* Set nic_info bit to mark new fields support */
322 field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO;
324 if (mlx4_vf_smi_enabled(dev, slave, port) &&
325 !mlx4_get_parav_qkey(dev, proxy_qp, &qkey)) {
326 field |= QUERY_FUNC_CAP_VF_ENABLE_QP0;
327 MLX4_PUT(outbox->buf, qkey,
328 QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET);
330 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET);
332 /* size is now the QP number */
333 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + port - 1;
334 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL);
337 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL);
339 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP0_PROXY);
341 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP1_PROXY);
343 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier],
344 QUERY_FUNC_CAP_PHYS_PORT_ID);
346 } else if (vhcr->op_modifier == 0) {
347 struct mlx4_active_ports actv_ports =
348 mlx4_get_active_ports(dev, slave);
349 /* enable rdma and ethernet interfaces, new quota locations,
352 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA |
353 QUERY_FUNC_CAP_FLAG_QUOTAS | QUERY_FUNC_CAP_FLAG_VALID_MAILBOX |
354 QUERY_FUNC_CAP_FLAG_RESD_LKEY);
355 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
358 bitmap_weight(actv_ports.ports, dev->caps.num_ports),
359 dev->caps.num_ports);
360 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
362 size = dev->caps.function_caps; /* set PF behaviours */
363 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
365 field = 0; /* protected FMR support not available as yet */
366 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);
368 size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave];
369 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
370 size = dev->caps.num_qps;
371 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
373 size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave];
374 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
375 size = dev->caps.num_srqs;
376 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
378 size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave];
379 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
380 size = dev->caps.num_cqs;
381 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
383 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) ||
384 mlx4_QUERY_FUNC(dev, &func, slave)) {
385 size = vhcr->in_modifier &
386 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ?
388 rounddown_pow_of_two(dev->caps.num_eqs);
389 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
390 size = dev->caps.reserved_eqs;
391 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
393 size = vhcr->in_modifier &
394 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ?
396 rounddown_pow_of_two(func.max_eq);
397 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
398 size = func.rsvd_eqs;
399 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
402 size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave];
403 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
404 size = dev->caps.num_mpts;
405 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
407 size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave];
408 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
409 size = dev->caps.num_mtts;
410 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
412 size = dev->caps.num_mgms + dev->caps.num_amgms;
413 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
414 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
416 size = QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG |
417 QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG;
418 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET);
420 size = dev->caps.reserved_lkey + ((slave << 8) & 0xFF00);
421 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET);
428 int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u8 gen_or_port,
429 struct mlx4_func_cap *func_cap)
431 struct mlx4_cmd_mailbox *mailbox;
433 u8 field, op_modifier;
435 int err = 0, quotas = 0;
438 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */
439 in_modifier = op_modifier ? gen_or_port :
440 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS;
442 mailbox = mlx4_alloc_cmd_mailbox(dev);
444 return PTR_ERR(mailbox);
446 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, op_modifier,
447 MLX4_CMD_QUERY_FUNC_CAP,
448 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
452 outbox = mailbox->buf;
455 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
456 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) {
457 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n");
458 err = -EPROTONOSUPPORT;
461 func_cap->flags = field;
462 quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS);
464 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
465 func_cap->num_ports = field;
467 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
468 func_cap->pf_context_behaviour = size;
471 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
472 func_cap->qp_quota = size & 0xFFFFFF;
474 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
475 func_cap->srq_quota = size & 0xFFFFFF;
477 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
478 func_cap->cq_quota = size & 0xFFFFFF;
480 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
481 func_cap->mpt_quota = size & 0xFFFFFF;
483 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
484 func_cap->mtt_quota = size & 0xFFFFFF;
486 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
487 func_cap->mcg_quota = size & 0xFFFFFF;
490 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
491 func_cap->qp_quota = size & 0xFFFFFF;
493 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
494 func_cap->srq_quota = size & 0xFFFFFF;
496 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
497 func_cap->cq_quota = size & 0xFFFFFF;
499 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
500 func_cap->mpt_quota = size & 0xFFFFFF;
502 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
503 func_cap->mtt_quota = size & 0xFFFFFF;
505 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
506 func_cap->mcg_quota = size & 0xFFFFFF;
508 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
509 func_cap->max_eq = size & 0xFFFFFF;
511 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
512 func_cap->reserved_eq = size & 0xFFFFFF;
514 if (func_cap->flags & QUERY_FUNC_CAP_FLAG_RESD_LKEY) {
515 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET);
516 func_cap->reserved_lkey = size;
518 func_cap->reserved_lkey = 0;
521 func_cap->extra_flags = 0;
523 /* Mailbox data from 0x6c and onward should only be treated if
524 * QUERY_FUNC_CAP_FLAG_VALID_MAILBOX is set in func_cap->flags
526 if (func_cap->flags & QUERY_FUNC_CAP_FLAG_VALID_MAILBOX) {
527 MLX4_GET(size, outbox, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET);
528 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG)
529 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_BF_RES_QP;
530 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG)
531 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_A0_RES_QP;
537 /* logical port query */
538 if (gen_or_port > dev->caps.num_ports) {
543 MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET);
544 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) {
545 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN) {
546 mlx4_err(dev, "VLAN is enforced on this port\n");
547 err = -EPROTONOSUPPORT;
551 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) {
552 mlx4_err(dev, "Force mac is enabled on this port\n");
553 err = -EPROTONOSUPPORT;
556 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) {
557 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET);
558 if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) {
559 mlx4_err(dev, "phy_wqe_gid is enforced on this ib port\n");
560 err = -EPROTONOSUPPORT;
565 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
566 func_cap->physical_port = field;
567 if (func_cap->physical_port != gen_or_port) {
572 if (func_cap->flags1 & QUERY_FUNC_CAP_VF_ENABLE_QP0) {
573 MLX4_GET(qkey, outbox, QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET);
574 func_cap->qp0_qkey = qkey;
576 func_cap->qp0_qkey = 0;
579 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL);
580 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF;
582 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY);
583 func_cap->qp0_proxy_qpn = size & 0xFFFFFF;
585 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL);
586 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF;
588 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY);
589 func_cap->qp1_proxy_qpn = size & 0xFFFFFF;
591 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_NIC_INFO)
592 MLX4_GET(func_cap->phys_port_id, outbox,
593 QUERY_FUNC_CAP_PHYS_PORT_ID);
595 /* All other resources are allocated by the master, but we still report
596 * 'num' and 'reserved' capabilities as follows:
597 * - num remains the maximum resource index
598 * - 'num - reserved' is the total available objects of a resource, but
599 * resource indices may be less than 'reserved'
600 * TODO: set per-resource quotas */
603 mlx4_free_cmd_mailbox(dev, mailbox);
608 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
610 struct mlx4_cmd_mailbox *mailbox;
613 u32 field32, flags, ext_flags;
619 #define QUERY_DEV_CAP_OUT_SIZE 0x100
620 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
621 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
622 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
623 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
624 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
625 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
626 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
627 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
628 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
629 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
630 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
631 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
632 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
633 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
634 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
635 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
636 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
637 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
638 #define QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET 0x26
639 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
640 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
641 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
642 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
643 #define QUERY_DEV_CAP_RSS_OFFSET 0x2e
644 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
645 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
646 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
647 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
648 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
649 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
650 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
651 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
652 #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e
653 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
654 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
655 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
656 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
657 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
658 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
659 #define QUERY_DEV_CAP_BF_OFFSET 0x4c
660 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
661 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
662 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
663 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
664 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
665 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
666 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
667 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
668 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
669 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
670 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
671 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
672 #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
673 #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
674 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
675 #define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70
676 #define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74
677 #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
678 #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
679 #define QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE 0x7a
680 #define QUERY_DEV_CAP_ECN_QCN_VER_OFFSET 0x7b
681 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
682 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
683 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
684 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
685 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
686 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
687 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
688 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
689 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
690 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
691 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
692 #define QUERY_DEV_CAP_CONFIG_DEV_OFFSET 0x94
693 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
694 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
695 #define QUERY_DEV_CAP_ETH_BACKPL_OFFSET 0x9c
696 #define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d
697 #define QUERY_DEV_CAP_VXLAN 0x9e
698 #define QUERY_DEV_CAP_MAD_DEMUX_OFFSET 0xb0
699 #define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET 0xa8
700 #define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET 0xac
701 #define QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET 0xcc
702 #define QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET 0xd0
703 #define QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET 0xd2
707 mailbox = mlx4_alloc_cmd_mailbox(dev);
709 return PTR_ERR(mailbox);
710 outbox = mailbox->buf;
712 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
713 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
717 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
718 dev_cap->reserved_qps = 1 << (field & 0xf);
719 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
720 dev_cap->max_qps = 1 << (field & 0x1f);
721 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
722 dev_cap->reserved_srqs = 1 << (field >> 4);
723 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
724 dev_cap->max_srqs = 1 << (field & 0x1f);
725 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
726 dev_cap->max_cq_sz = 1 << field;
727 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
728 dev_cap->reserved_cqs = 1 << (field & 0xf);
729 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
730 dev_cap->max_cqs = 1 << (field & 0x1f);
731 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
732 dev_cap->max_mpts = 1 << (field & 0x3f);
733 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
734 dev_cap->reserved_eqs = 1 << (field & 0xf);
735 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
736 dev_cap->max_eqs = 1 << (field & 0xf);
737 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
738 dev_cap->reserved_mtts = 1 << (field >> 4);
739 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
740 dev_cap->max_mrw_sz = 1 << field;
741 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
742 dev_cap->reserved_mrws = 1 << (field & 0xf);
743 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
744 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
745 MLX4_GET(size, outbox, QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET);
746 dev_cap->num_sys_eqs = size & 0xfff;
747 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
748 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
749 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
750 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
751 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
754 dev_cap->max_gso_sz = 0;
756 dev_cap->max_gso_sz = 1 << field;
758 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
760 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
762 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
765 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
766 dev_cap->max_rss_tbl_sz = 1 << field;
768 dev_cap->max_rss_tbl_sz = 0;
769 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
770 dev_cap->max_rdma_global = 1 << (field & 0x3f);
771 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
772 dev_cap->local_ca_ack_delay = field & 0x1f;
773 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
774 dev_cap->num_ports = field & 0xf;
775 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
776 dev_cap->max_msg_sz = 1 << (field & 0x1f);
777 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
779 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
780 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
781 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
783 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB;
784 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
785 dev_cap->fs_max_num_qp_per_entry = field;
786 MLX4_GET(field, outbox, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET);
788 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QCN;
789 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
790 dev_cap->stat_rate_support = stat_rate;
791 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
793 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS;
794 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
795 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
796 dev_cap->flags = flags | (u64)ext_flags << 32;
797 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
798 dev_cap->reserved_uars = field >> 4;
799 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
800 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
801 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
802 dev_cap->min_page_sz = 1 << field;
804 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
806 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
807 dev_cap->bf_reg_size = 1 << (field & 0x1f);
808 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
809 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
811 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
813 dev_cap->bf_reg_size = 0;
816 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
817 dev_cap->max_sq_sg = field;
818 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
819 dev_cap->max_sq_desc_sz = size;
821 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
822 dev_cap->max_qp_per_mcg = 1 << field;
823 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
824 dev_cap->reserved_mgms = field & 0xf;
825 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
826 dev_cap->max_mcgs = 1 << field;
827 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
828 dev_cap->reserved_pds = field >> 4;
829 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
830 dev_cap->max_pds = 1 << (field & 0x3f);
831 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
832 dev_cap->reserved_xrcds = field >> 4;
833 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET);
834 dev_cap->max_xrcds = 1 << (field & 0x1f);
836 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
837 dev_cap->rdmarc_entry_sz = size;
838 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
839 dev_cap->qpc_entry_sz = size;
840 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
841 dev_cap->aux_entry_sz = size;
842 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
843 dev_cap->altc_entry_sz = size;
844 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
845 dev_cap->eqc_entry_sz = size;
846 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
847 dev_cap->cqc_entry_sz = size;
848 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
849 dev_cap->srq_entry_sz = size;
850 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
851 dev_cap->cmpt_entry_sz = size;
852 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
853 dev_cap->mtt_entry_sz = size;
854 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
855 dev_cap->dmpt_entry_sz = size;
857 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
858 dev_cap->max_srq_sz = 1 << field;
859 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
860 dev_cap->max_qp_sz = 1 << field;
861 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
862 dev_cap->resize_srq = field & 1;
863 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
864 dev_cap->max_rq_sg = field;
865 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
866 dev_cap->max_rq_desc_sz = size;
867 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE);
868 if (field & (1 << 5))
869 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL;
870 if (field & (1 << 6))
871 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
872 if (field & (1 << 7))
873 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
874 MLX4_GET(dev_cap->bmme_flags, outbox,
875 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
876 if (dev_cap->bmme_flags & MLX4_FLAG_PORT_REMAP)
877 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_REMAP;
878 MLX4_GET(field, outbox, QUERY_DEV_CAP_CONFIG_DEV_OFFSET);
880 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CONFIG_DEV;
881 MLX4_GET(dev_cap->reserved_lkey, outbox,
882 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
883 MLX4_GET(field32, outbox, QUERY_DEV_CAP_ETH_BACKPL_OFFSET);
884 if (field32 & (1 << 0))
885 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP;
886 if (field32 & (1 << 7))
887 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT;
888 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC);
890 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN;
891 MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN);
893 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS;
894 MLX4_GET(dev_cap->max_icm_sz, outbox,
895 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
896 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
897 MLX4_GET(dev_cap->max_counters, outbox,
898 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
900 MLX4_GET(field32, outbox,
901 QUERY_DEV_CAP_MAD_DEMUX_OFFSET);
902 if (field32 & (1 << 0))
903 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX;
905 MLX4_GET(dev_cap->dmfs_high_rate_qpn_base, outbox,
906 QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET);
907 dev_cap->dmfs_high_rate_qpn_base &= MGM_QPN_MASK;
908 MLX4_GET(dev_cap->dmfs_high_rate_qpn_range, outbox,
909 QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET);
910 dev_cap->dmfs_high_rate_qpn_range &= MGM_QPN_MASK;
912 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET);
913 dev_cap->rl_caps.num_rates = size;
914 if (dev_cap->rl_caps.num_rates) {
915 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT;
916 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET);
917 dev_cap->rl_caps.max_val = size & 0xfff;
918 dev_cap->rl_caps.max_unit = size >> 14;
919 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET);
920 dev_cap->rl_caps.min_val = size & 0xfff;
921 dev_cap->rl_caps.min_unit = size >> 14;
924 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
925 if (field32 & (1 << 16))
926 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP;
927 if (field32 & (1 << 26))
928 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL;
929 if (field32 & (1 << 20))
930 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM;
931 if (field32 & (1 << 21))
932 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_80_VFS;
934 for (i = 1; i <= dev_cap->num_ports; i++) {
935 err = mlx4_QUERY_PORT(dev, i, dev_cap->port_cap + i);
941 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
942 * we can't use any EQs whose doorbell falls on that page,
943 * even if the EQ itself isn't reserved.
945 if (dev_cap->num_sys_eqs == 0)
946 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
947 dev_cap->reserved_eqs);
949 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SYS_EQS;
952 mlx4_free_cmd_mailbox(dev, mailbox);
956 void mlx4_dev_cap_dump(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
958 if (dev_cap->bf_reg_size > 0)
959 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
960 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
962 mlx4_dbg(dev, "BlueFlame not available\n");
964 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
965 dev_cap->bmme_flags, dev_cap->reserved_lkey);
966 mlx4_dbg(dev, "Max ICM size %lld MB\n",
967 (unsigned long long) dev_cap->max_icm_sz >> 20);
968 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
969 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
970 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
971 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
972 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
973 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
974 mlx4_dbg(dev, "Num sys EQs: %d, max EQs: %d, reserved EQs: %d, entry size: %d\n",
975 dev_cap->num_sys_eqs, dev_cap->max_eqs, dev_cap->reserved_eqs,
976 dev_cap->eqc_entry_sz);
977 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
978 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
979 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
980 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
981 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
982 dev_cap->max_pds, dev_cap->reserved_mgms);
983 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
984 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
985 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
986 dev_cap->local_ca_ack_delay, 128 << dev_cap->port_cap[1].ib_mtu,
987 dev_cap->port_cap[1].max_port_width);
988 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
989 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
990 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
991 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
992 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
993 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
994 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
995 mlx4_dbg(dev, "DMFS high rate steer QPn base: %d\n",
996 dev_cap->dmfs_high_rate_qpn_base);
997 mlx4_dbg(dev, "DMFS high rate steer QPn range: %d\n",
998 dev_cap->dmfs_high_rate_qpn_range);
1000 if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT) {
1001 struct mlx4_rate_limit_caps *rl_caps = &dev_cap->rl_caps;
1003 mlx4_dbg(dev, "QP Rate-Limit: #rates %d, unit/val max %d/%d, min %d/%d\n",
1004 rl_caps->num_rates, rl_caps->max_unit, rl_caps->max_val,
1005 rl_caps->min_unit, rl_caps->min_val);
1008 dump_dev_cap_flags(dev, dev_cap->flags);
1009 dump_dev_cap_flags2(dev, dev_cap->flags2);
1012 int mlx4_QUERY_PORT(struct mlx4_dev *dev, int port, struct mlx4_port_cap *port_cap)
1014 struct mlx4_cmd_mailbox *mailbox;
1020 mailbox = mlx4_alloc_cmd_mailbox(dev);
1021 if (IS_ERR(mailbox))
1022 return PTR_ERR(mailbox);
1023 outbox = mailbox->buf;
1025 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
1026 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
1027 MLX4_CMD_TIME_CLASS_A,
1033 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
1034 port_cap->max_vl = field >> 4;
1035 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
1036 port_cap->ib_mtu = field >> 4;
1037 port_cap->max_port_width = field & 0xf;
1038 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
1039 port_cap->max_gids = 1 << (field & 0xf);
1040 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
1041 port_cap->max_pkeys = 1 << (field & 0xf);
1043 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
1044 #define QUERY_PORT_MTU_OFFSET 0x01
1045 #define QUERY_PORT_ETH_MTU_OFFSET 0x02
1046 #define QUERY_PORT_WIDTH_OFFSET 0x06
1047 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
1048 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
1049 #define QUERY_PORT_MAX_VL_OFFSET 0x0b
1050 #define QUERY_PORT_MAC_OFFSET 0x10
1051 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
1052 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
1053 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20
1055 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, MLX4_CMD_QUERY_PORT,
1056 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1060 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
1061 port_cap->supported_port_types = field & 3;
1062 port_cap->suggested_type = (field >> 3) & 1;
1063 port_cap->default_sense = (field >> 4) & 1;
1064 port_cap->dmfs_optimized_state = (field >> 5) & 1;
1065 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
1066 port_cap->ib_mtu = field & 0xf;
1067 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
1068 port_cap->max_port_width = field & 0xf;
1069 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
1070 port_cap->max_gids = 1 << (field >> 4);
1071 port_cap->max_pkeys = 1 << (field & 0xf);
1072 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
1073 port_cap->max_vl = field & 0xf;
1074 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
1075 port_cap->log_max_macs = field & 0xf;
1076 port_cap->log_max_vlans = field >> 4;
1077 MLX4_GET(port_cap->eth_mtu, outbox, QUERY_PORT_ETH_MTU_OFFSET);
1078 MLX4_GET(port_cap->def_mac, outbox, QUERY_PORT_MAC_OFFSET);
1079 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
1080 port_cap->trans_type = field32 >> 24;
1081 port_cap->vendor_oui = field32 & 0xffffff;
1082 MLX4_GET(port_cap->wavelength, outbox, QUERY_PORT_WAVELENGTH_OFFSET);
1083 MLX4_GET(port_cap->trans_code, outbox, QUERY_PORT_TRANS_CODE_OFFSET);
1087 mlx4_free_cmd_mailbox(dev, mailbox);
1091 #define DEV_CAP_EXT_2_FLAG_VLAN_CONTROL (1 << 26)
1092 #define DEV_CAP_EXT_2_FLAG_80_VFS (1 << 21)
1093 #define DEV_CAP_EXT_2_FLAG_FSM (1 << 20)
1095 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1096 struct mlx4_vhcr *vhcr,
1097 struct mlx4_cmd_mailbox *inbox,
1098 struct mlx4_cmd_mailbox *outbox,
1099 struct mlx4_cmd_info *cmd)
1105 u32 bmme_flags, field32;
1109 struct mlx4_active_ports actv_ports;
1111 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
1112 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1116 /* add port mng change event capability and disable mw type 1
1117 * unconditionally to slaves
1119 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
1120 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV;
1121 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW;
1122 actv_ports = mlx4_get_active_ports(dev, slave);
1123 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
1124 for (slave_port = 0, real_port = first_port;
1125 real_port < first_port +
1126 bitmap_weight(actv_ports.ports, dev->caps.num_ports);
1127 ++real_port, ++slave_port) {
1128 if (flags & (MLX4_DEV_CAP_FLAG_WOL_PORT1 << real_port))
1129 flags |= MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port;
1131 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port);
1133 for (; slave_port < dev->caps.num_ports; ++slave_port)
1134 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port);
1135 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
1137 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET);
1139 field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F;
1140 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET);
1142 /* For guests, disable timestamp */
1143 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
1145 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
1147 /* For guests, disable vxlan tunneling */
1148 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN);
1150 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN);
1152 /* For guests, report Blueflame disabled */
1153 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
1155 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
1157 /* For guests, disable mw type 2 and port remap*/
1158 MLX4_GET(bmme_flags, outbox->buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
1159 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN;
1160 bmme_flags &= ~MLX4_FLAG_PORT_REMAP;
1161 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
1163 /* turn off device-managed steering capability if not enabled */
1164 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
1165 MLX4_GET(field, outbox->buf,
1166 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
1168 MLX4_PUT(outbox->buf, field,
1169 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
1172 /* turn off ipoib managed steering for guests */
1173 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
1175 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
1177 /* turn off host side virt features (VST, FSM, etc) for guests */
1178 MLX4_GET(field32, outbox->buf, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
1179 field32 &= ~(DEV_CAP_EXT_2_FLAG_VLAN_CONTROL | DEV_CAP_EXT_2_FLAG_80_VFS |
1180 DEV_CAP_EXT_2_FLAG_FSM);
1181 MLX4_PUT(outbox->buf, field32, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
1183 /* turn off QCN for guests */
1184 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET);
1186 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET);
1188 /* turn off QP max-rate limiting for guests */
1190 MLX4_PUT(outbox->buf, field16, QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET);
1195 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1196 struct mlx4_vhcr *vhcr,
1197 struct mlx4_cmd_mailbox *inbox,
1198 struct mlx4_cmd_mailbox *outbox,
1199 struct mlx4_cmd_info *cmd)
1201 struct mlx4_priv *priv = mlx4_priv(dev);
1206 int admin_link_state;
1207 int port = mlx4_slave_convert_port(dev, slave,
1208 vhcr->in_modifier & 0xFF);
1210 #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0
1211 #define MLX4_PORT_LINK_UP_MASK 0x80
1212 #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c
1213 #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e
1218 /* Protect against untrusted guests: enforce that this is the
1219 * QUERY_PORT general query.
1221 if (vhcr->op_modifier || vhcr->in_modifier & ~0xFF)
1224 vhcr->in_modifier = port;
1226 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
1227 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
1230 if (!err && dev->caps.function != slave) {
1231 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac;
1232 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
1234 /* get port type - currently only eth is enabled */
1235 MLX4_GET(port_type, outbox->buf,
1236 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
1238 /* No link sensing allowed */
1239 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK;
1240 /* set port type to currently operating port type */
1241 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3);
1243 admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state;
1244 if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state)
1245 port_type |= MLX4_PORT_LINK_UP_MASK;
1246 else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state)
1247 port_type &= ~MLX4_PORT_LINK_UP_MASK;
1249 MLX4_PUT(outbox->buf, port_type,
1250 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
1252 if (dev->caps.port_type[vhcr->in_modifier] == MLX4_PORT_TYPE_ETH)
1253 short_field = mlx4_get_slave_num_gids(dev, slave, port);
1255 short_field = 1; /* slave max gids */
1256 MLX4_PUT(outbox->buf, short_field,
1257 QUERY_PORT_CUR_MAX_GID_OFFSET);
1259 short_field = dev->caps.pkey_table_len[vhcr->in_modifier];
1260 MLX4_PUT(outbox->buf, short_field,
1261 QUERY_PORT_CUR_MAX_PKEY_OFFSET);
1267 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1268 int *gid_tbl_len, int *pkey_tbl_len)
1270 struct mlx4_cmd_mailbox *mailbox;
1275 mailbox = mlx4_alloc_cmd_mailbox(dev);
1276 if (IS_ERR(mailbox))
1277 return PTR_ERR(mailbox);
1279 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0,
1280 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
1285 outbox = mailbox->buf;
1287 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);
1288 *gid_tbl_len = field;
1290 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);
1291 *pkey_tbl_len = field;
1294 mlx4_free_cmd_mailbox(dev, mailbox);
1297 EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len);
1299 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
1301 struct mlx4_cmd_mailbox *mailbox;
1302 struct mlx4_icm_iter iter;
1310 mailbox = mlx4_alloc_cmd_mailbox(dev);
1311 if (IS_ERR(mailbox))
1312 return PTR_ERR(mailbox);
1313 pages = mailbox->buf;
1315 for (mlx4_icm_first(icm, &iter);
1316 !mlx4_icm_last(&iter);
1317 mlx4_icm_next(&iter)) {
1319 * We have to pass pages that are aligned to their
1320 * size, so find the least significant 1 in the
1321 * address or size and use that as our log2 size.
1323 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
1324 if (lg < MLX4_ICM_PAGE_SHIFT) {
1325 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx)\n",
1327 (unsigned long long) mlx4_icm_addr(&iter),
1328 mlx4_icm_size(&iter));
1333 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
1335 pages[nent * 2] = cpu_to_be64(virt);
1339 pages[nent * 2 + 1] =
1340 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
1341 (lg - MLX4_ICM_PAGE_SHIFT));
1342 ts += 1 << (lg - 10);
1345 if (++nent == MLX4_MAILBOX_SIZE / 16) {
1346 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
1347 MLX4_CMD_TIME_CLASS_B,
1357 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
1358 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1363 case MLX4_CMD_MAP_FA:
1364 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW\n", tc, ts);
1366 case MLX4_CMD_MAP_ICM_AUX:
1367 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux\n", tc, ts);
1369 case MLX4_CMD_MAP_ICM:
1370 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM\n",
1371 tc, ts, (unsigned long long) virt - (ts << 10));
1376 mlx4_free_cmd_mailbox(dev, mailbox);
1380 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
1382 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
1385 int mlx4_UNMAP_FA(struct mlx4_dev *dev)
1387 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
1388 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1392 int mlx4_RUN_FW(struct mlx4_dev *dev)
1394 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
1395 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1398 int mlx4_QUERY_FW(struct mlx4_dev *dev)
1400 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
1401 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
1402 struct mlx4_cmd_mailbox *mailbox;
1409 #define QUERY_FW_OUT_SIZE 0x100
1410 #define QUERY_FW_VER_OFFSET 0x00
1411 #define QUERY_FW_PPF_ID 0x09
1412 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
1413 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
1414 #define QUERY_FW_ERR_START_OFFSET 0x30
1415 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
1416 #define QUERY_FW_ERR_BAR_OFFSET 0x3c
1418 #define QUERY_FW_SIZE_OFFSET 0x00
1419 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
1420 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
1422 #define QUERY_FW_COMM_BASE_OFFSET 0x40
1423 #define QUERY_FW_COMM_BAR_OFFSET 0x48
1425 #define QUERY_FW_CLOCK_OFFSET 0x50
1426 #define QUERY_FW_CLOCK_BAR 0x58
1428 mailbox = mlx4_alloc_cmd_mailbox(dev);
1429 if (IS_ERR(mailbox))
1430 return PTR_ERR(mailbox);
1431 outbox = mailbox->buf;
1433 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1434 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1438 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
1440 * FW subminor version is at more significant bits than minor
1441 * version, so swap here.
1443 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
1444 ((fw_ver & 0xffff0000ull) >> 16) |
1445 ((fw_ver & 0x0000ffffull) << 16);
1447 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
1448 dev->caps.function = lg;
1450 if (mlx4_is_slave(dev))
1454 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
1455 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
1456 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
1457 mlx4_err(dev, "Installed FW has unsupported command interface revision %d\n",
1459 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
1460 (int) (dev->caps.fw_ver >> 32),
1461 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1462 (int) dev->caps.fw_ver & 0xffff);
1463 mlx4_err(dev, "This driver version supports only revisions %d to %d\n",
1464 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
1469 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
1470 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
1472 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
1473 cmd->max_cmds = 1 << lg;
1475 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
1476 (int) (dev->caps.fw_ver >> 32),
1477 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1478 (int) dev->caps.fw_ver & 0xffff,
1479 cmd_if_rev, cmd->max_cmds);
1481 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
1482 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
1483 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
1484 fw->catas_bar = (fw->catas_bar >> 6) * 2;
1486 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
1487 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
1489 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
1490 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
1491 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
1492 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
1494 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
1495 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
1496 fw->comm_bar = (fw->comm_bar >> 6) * 2;
1497 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
1498 fw->comm_bar, fw->comm_base);
1499 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
1501 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET);
1502 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR);
1503 fw->clock_bar = (fw->clock_bar >> 6) * 2;
1504 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n",
1505 fw->clock_bar, fw->clock_offset);
1508 * Round up number of system pages needed in case
1509 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1512 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1513 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1515 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
1516 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
1519 mlx4_free_cmd_mailbox(dev, mailbox);
1523 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1524 struct mlx4_vhcr *vhcr,
1525 struct mlx4_cmd_mailbox *inbox,
1526 struct mlx4_cmd_mailbox *outbox,
1527 struct mlx4_cmd_info *cmd)
1532 outbuf = outbox->buf;
1533 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1534 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1538 /* for slaves, set pci PPF ID to invalid and zero out everything
1539 * else except FW version */
1540 outbuf[0] = outbuf[1] = 0;
1541 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8);
1542 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID;
1547 static void get_board_id(void *vsd, char *board_id)
1551 #define VSD_OFFSET_SIG1 0x00
1552 #define VSD_OFFSET_SIG2 0xde
1553 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
1554 #define VSD_OFFSET_TS_BOARD_ID 0x20
1556 #define VSD_SIGNATURE_TOPSPIN 0x5ad
1558 memset(board_id, 0, MLX4_BOARD_ID_LEN);
1560 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1561 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1562 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
1565 * The board ID is a string but the firmware byte
1566 * swaps each 4-byte word before passing it back to
1567 * us. Therefore we need to swab it before printing.
1569 for (i = 0; i < 4; ++i)
1570 ((u32 *) board_id)[i] =
1571 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1575 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
1577 struct mlx4_cmd_mailbox *mailbox;
1581 #define QUERY_ADAPTER_OUT_SIZE 0x100
1582 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1583 #define QUERY_ADAPTER_VSD_OFFSET 0x20
1585 mailbox = mlx4_alloc_cmd_mailbox(dev);
1586 if (IS_ERR(mailbox))
1587 return PTR_ERR(mailbox);
1588 outbox = mailbox->buf;
1590 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
1591 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1595 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1597 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1601 mlx4_free_cmd_mailbox(dev, mailbox);
1605 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1607 struct mlx4_cmd_mailbox *mailbox;
1610 static const u8 a0_dmfs_hw_steering[] = {
1611 [MLX4_STEERING_DMFS_A0_DEFAULT] = 0,
1612 [MLX4_STEERING_DMFS_A0_DYNAMIC] = 1,
1613 [MLX4_STEERING_DMFS_A0_STATIC] = 2,
1614 [MLX4_STEERING_DMFS_A0_DISABLE] = 3
1617 #define INIT_HCA_IN_SIZE 0x200
1618 #define INIT_HCA_VERSION_OFFSET 0x000
1619 #define INIT_HCA_VERSION 2
1620 #define INIT_HCA_VXLAN_OFFSET 0x0c
1621 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
1622 #define INIT_HCA_FLAGS_OFFSET 0x014
1623 #define INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET 0x018
1624 #define INIT_HCA_QPC_OFFSET 0x020
1625 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1626 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1627 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1628 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1629 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1630 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
1631 #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
1632 #define INIT_HCA_EQE_CQE_STRIDE_OFFSET (INIT_HCA_QPC_OFFSET + 0x3b)
1633 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1634 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1635 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1636 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1637 #define INIT_HCA_NUM_SYS_EQS_OFFSET (INIT_HCA_QPC_OFFSET + 0x6a)
1638 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1639 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1640 #define INIT_HCA_MCAST_OFFSET 0x0c0
1641 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1642 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1643 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1644 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
1645 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1646 #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1647 #define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1648 #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1649 #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
1650 #define INIT_HCA_FS_A0_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x18)
1651 #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b)
1652 #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21)
1653 #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22)
1654 #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25)
1655 #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26)
1656 #define INIT_HCA_TPT_OFFSET 0x0f0
1657 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
1658 #define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08)
1659 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1660 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1661 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1662 #define INIT_HCA_UAR_OFFSET 0x120
1663 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1664 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1666 mailbox = mlx4_alloc_cmd_mailbox(dev);
1667 if (IS_ERR(mailbox))
1668 return PTR_ERR(mailbox);
1669 inbox = mailbox->buf;
1671 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1673 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1674 (ilog2(cache_line_size()) - 4) << 5;
1676 #if defined(__LITTLE_ENDIAN)
1677 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1678 #elif defined(__BIG_ENDIAN)
1679 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1681 #error Host endianness not defined
1683 /* Check port for UD address vector: */
1684 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1686 /* Enable IPoIB checksumming if we can: */
1687 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1688 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1690 /* Enable QoS support if module parameter set */
1692 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1694 /* enable counters */
1695 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1696 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1698 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1699 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) {
1700 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29);
1701 dev->caps.eqe_size = 64;
1702 dev->caps.eqe_factor = 1;
1704 dev->caps.eqe_size = 32;
1705 dev->caps.eqe_factor = 0;
1708 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) {
1709 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30);
1710 dev->caps.cqe_size = 64;
1711 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
1713 dev->caps.cqe_size = 32;
1716 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */
1717 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) &&
1718 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) {
1719 dev->caps.eqe_size = cache_line_size();
1720 dev->caps.cqe_size = cache_line_size();
1721 dev->caps.eqe_factor = 0;
1722 MLX4_PUT(inbox, (u8)((ilog2(dev->caps.eqe_size) - 5) << 4 |
1723 (ilog2(dev->caps.eqe_size) - 5)),
1724 INIT_HCA_EQE_CQE_STRIDE_OFFSET);
1726 /* User still need to know to support CQE > 32B */
1727 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
1730 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT)
1731 *(inbox + INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET / 4) |= cpu_to_be32(1 << 31);
1733 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1735 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1736 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1737 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1738 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1739 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1740 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1741 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1742 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1743 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1744 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1745 MLX4_PUT(inbox, param->num_sys_eqs, INIT_HCA_NUM_SYS_EQS_OFFSET);
1746 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1747 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1749 /* steering attributes */
1750 if (dev->caps.steering_mode ==
1751 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1752 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |=
1754 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN);
1756 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET);
1757 MLX4_PUT(inbox, param->log_mc_entry_sz,
1758 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1759 MLX4_PUT(inbox, param->log_mc_table_sz,
1760 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1761 /* Enable Ethernet flow steering
1762 * with udp unicast and tcp unicast
1764 if (dev->caps.dmfs_high_steer_mode !=
1765 MLX4_STEERING_DMFS_A0_STATIC)
1767 (u8)(MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
1768 INIT_HCA_FS_ETH_BITS_OFFSET);
1769 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1770 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET);
1771 /* Enable IPoIB flow steering
1772 * with udp unicast and tcp unicast
1774 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
1775 INIT_HCA_FS_IB_BITS_OFFSET);
1776 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1777 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET);
1779 if (dev->caps.dmfs_high_steer_mode !=
1780 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1782 ((u8)(a0_dmfs_hw_steering[dev->caps.dmfs_high_steer_mode]
1784 INIT_HCA_FS_A0_OFFSET);
1786 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1787 MLX4_PUT(inbox, param->log_mc_entry_sz,
1788 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1789 MLX4_PUT(inbox, param->log_mc_hash_sz,
1790 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1791 MLX4_PUT(inbox, param->log_mc_table_sz,
1792 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1793 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0)
1794 MLX4_PUT(inbox, (u8) (1 << 3),
1795 INIT_HCA_UC_STEERING_OFFSET);
1798 /* TPT attributes */
1800 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
1801 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET);
1802 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1803 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1804 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1806 /* UAR attributes */
1808 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1809 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1811 /* set parser VXLAN attributes */
1812 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) {
1813 u8 parser_params = 0;
1814 MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET);
1817 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA,
1818 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
1821 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1823 mlx4_free_cmd_mailbox(dev, mailbox);
1827 int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1828 struct mlx4_init_hca_param *param)
1830 struct mlx4_cmd_mailbox *mailbox;
1835 static const u8 a0_dmfs_query_hw_steering[] = {
1836 [0] = MLX4_STEERING_DMFS_A0_DEFAULT,
1837 [1] = MLX4_STEERING_DMFS_A0_DYNAMIC,
1838 [2] = MLX4_STEERING_DMFS_A0_STATIC,
1839 [3] = MLX4_STEERING_DMFS_A0_DISABLE
1842 #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
1843 #define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c
1845 mailbox = mlx4_alloc_cmd_mailbox(dev);
1846 if (IS_ERR(mailbox))
1847 return PTR_ERR(mailbox);
1848 outbox = mailbox->buf;
1850 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1852 MLX4_CMD_TIME_CLASS_B,
1853 !mlx4_is_slave(dev));
1857 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
1858 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
1860 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1862 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1863 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1864 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1865 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1866 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1867 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1868 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1869 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1870 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1871 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
1872 MLX4_GET(param->num_sys_eqs, outbox, INIT_HCA_NUM_SYS_EQS_OFFSET);
1873 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1874 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1876 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET);
1877 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) {
1878 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1880 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET);
1881 if (byte_field & 0x8)
1882 param->steering_mode = MLX4_STEERING_MODE_B0;
1884 param->steering_mode = MLX4_STEERING_MODE_A0;
1886 /* steering attributes */
1887 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
1888 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET);
1889 MLX4_GET(param->log_mc_entry_sz, outbox,
1890 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1891 MLX4_GET(param->log_mc_table_sz, outbox,
1892 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1893 MLX4_GET(byte_field, outbox,
1894 INIT_HCA_FS_A0_OFFSET);
1895 param->dmfs_high_steer_mode =
1896 a0_dmfs_query_hw_steering[(byte_field >> 6) & 3];
1898 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
1899 MLX4_GET(param->log_mc_entry_sz, outbox,
1900 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1901 MLX4_GET(param->log_mc_hash_sz, outbox,
1902 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1903 MLX4_GET(param->log_mc_table_sz, outbox,
1904 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1907 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1908 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS);
1909 if (byte_field & 0x20) /* 64-bytes eqe enabled */
1910 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
1911 if (byte_field & 0x40) /* 64-bytes cqe enabled */
1912 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
1914 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */
1915 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_STRIDE_OFFSET);
1917 param->dev_cap_enabled |= MLX4_DEV_CAP_EQE_STRIDE_ENABLED;
1918 param->dev_cap_enabled |= MLX4_DEV_CAP_CQE_STRIDE_ENABLED;
1919 param->cqe_size = 1 << ((byte_field &
1920 MLX4_CQE_SIZE_MASK_STRIDE) + 5);
1921 param->eqe_size = 1 << (((byte_field &
1922 MLX4_EQE_SIZE_MASK_STRIDE) >> 4) + 5);
1925 /* TPT attributes */
1927 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
1928 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET);
1929 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
1930 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
1931 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
1933 /* UAR attributes */
1935 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1936 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
1939 mlx4_free_cmd_mailbox(dev, mailbox);
1944 static int mlx4_hca_core_clock_update(struct mlx4_dev *dev)
1946 struct mlx4_cmd_mailbox *mailbox;
1950 mailbox = mlx4_alloc_cmd_mailbox(dev);
1951 if (IS_ERR(mailbox)) {
1952 mlx4_warn(dev, "hca_core_clock mailbox allocation failed\n");
1953 return PTR_ERR(mailbox);
1955 outbox = mailbox->buf;
1957 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1959 MLX4_CMD_TIME_CLASS_B,
1960 !mlx4_is_slave(dev));
1962 mlx4_warn(dev, "hca_core_clock update failed\n");
1966 MLX4_GET(dev->caps.hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
1969 mlx4_free_cmd_mailbox(dev, mailbox);
1974 /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0
1975 * and real QP0 are active, so that the paravirtualized QP0 is ready
1977 static int check_qp0_state(struct mlx4_dev *dev, int function, int port)
1979 struct mlx4_priv *priv = mlx4_priv(dev);
1980 /* irrelevant if not infiniband */
1981 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active &&
1982 priv->mfunc.master.qp0_state[port].qp0_active)
1987 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1988 struct mlx4_vhcr *vhcr,
1989 struct mlx4_cmd_mailbox *inbox,
1990 struct mlx4_cmd_mailbox *outbox,
1991 struct mlx4_cmd_info *cmd)
1993 struct mlx4_priv *priv = mlx4_priv(dev);
1994 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier);
2000 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
2003 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
2004 /* Enable port only if it was previously disabled */
2005 if (!priv->mfunc.master.init_port_ref[port]) {
2006 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
2007 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2011 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
2013 if (slave == mlx4_master_func_num(dev)) {
2014 if (check_qp0_state(dev, slave, port) &&
2015 !priv->mfunc.master.qp0_state[port].port_active) {
2016 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
2017 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2020 priv->mfunc.master.qp0_state[port].port_active = 1;
2021 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
2024 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
2026 ++priv->mfunc.master.init_port_ref[port];
2030 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
2032 struct mlx4_cmd_mailbox *mailbox;
2038 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
2039 #define INIT_PORT_IN_SIZE 256
2040 #define INIT_PORT_FLAGS_OFFSET 0x00
2041 #define INIT_PORT_FLAG_SIG (1 << 18)
2042 #define INIT_PORT_FLAG_NG (1 << 17)
2043 #define INIT_PORT_FLAG_G0 (1 << 16)
2044 #define INIT_PORT_VL_SHIFT 4
2045 #define INIT_PORT_PORT_WIDTH_SHIFT 8
2046 #define INIT_PORT_MTU_OFFSET 0x04
2047 #define INIT_PORT_MAX_GID_OFFSET 0x06
2048 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a
2049 #define INIT_PORT_GUID0_OFFSET 0x10
2050 #define INIT_PORT_NODE_GUID_OFFSET 0x18
2051 #define INIT_PORT_SI_GUID_OFFSET 0x20
2053 mailbox = mlx4_alloc_cmd_mailbox(dev);
2054 if (IS_ERR(mailbox))
2055 return PTR_ERR(mailbox);
2056 inbox = mailbox->buf;
2059 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
2060 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
2061 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
2063 field = 128 << dev->caps.ib_mtu_cap[port];
2064 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
2065 field = dev->caps.gid_table_len[port];
2066 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
2067 field = dev->caps.pkey_table_len[port];
2068 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
2070 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
2071 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2073 mlx4_free_cmd_mailbox(dev, mailbox);
2075 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
2076 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
2079 mlx4_hca_core_clock_update(dev);
2083 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
2085 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
2086 struct mlx4_vhcr *vhcr,
2087 struct mlx4_cmd_mailbox *inbox,
2088 struct mlx4_cmd_mailbox *outbox,
2089 struct mlx4_cmd_info *cmd)
2091 struct mlx4_priv *priv = mlx4_priv(dev);
2092 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier);
2098 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
2102 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
2103 if (priv->mfunc.master.init_port_ref[port] == 1) {
2104 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
2105 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2109 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
2111 /* infiniband port */
2112 if (slave == mlx4_master_func_num(dev)) {
2113 if (!priv->mfunc.master.qp0_state[port].qp0_active &&
2114 priv->mfunc.master.qp0_state[port].port_active) {
2115 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
2116 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2119 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
2120 priv->mfunc.master.qp0_state[port].port_active = 0;
2123 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
2125 --priv->mfunc.master.init_port_ref[port];
2129 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
2131 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
2132 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
2134 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
2136 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
2138 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA,
2139 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
2142 struct mlx4_config_dev {
2143 __be32 update_flags;
2145 __be16 vxlan_udp_dport;
2155 #define MLX4_VXLAN_UDP_DPORT (1 << 0)
2156 #define MLX4_DISABLE_RX_PORT BIT(18)
2158 static int mlx4_CONFIG_DEV_set(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev)
2161 struct mlx4_cmd_mailbox *mailbox;
2163 mailbox = mlx4_alloc_cmd_mailbox(dev);
2164 if (IS_ERR(mailbox))
2165 return PTR_ERR(mailbox);
2167 memcpy(mailbox->buf, config_dev, sizeof(*config_dev));
2169 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_CONFIG_DEV,
2170 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2172 mlx4_free_cmd_mailbox(dev, mailbox);
2176 static int mlx4_CONFIG_DEV_get(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev)
2179 struct mlx4_cmd_mailbox *mailbox;
2181 mailbox = mlx4_alloc_cmd_mailbox(dev);
2182 if (IS_ERR(mailbox))
2183 return PTR_ERR(mailbox);
2185 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 1, MLX4_CMD_CONFIG_DEV,
2186 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2189 memcpy(config_dev, mailbox->buf, sizeof(*config_dev));
2191 mlx4_free_cmd_mailbox(dev, mailbox);
2195 /* Conversion between the HW values and the actual functionality.
2196 * The value represented by the array index,
2197 * and the functionality determined by the flags.
2199 static const u8 config_dev_csum_flags[] = {
2201 [1] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP,
2202 [2] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP |
2203 MLX4_RX_CSUM_MODE_L4,
2204 [3] = MLX4_RX_CSUM_MODE_L4 |
2205 MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP |
2206 MLX4_RX_CSUM_MODE_MULTI_VLAN
2209 int mlx4_config_dev_retrieval(struct mlx4_dev *dev,
2210 struct mlx4_config_dev_params *params)
2212 struct mlx4_config_dev config_dev = {0};
2216 #define CONFIG_DEV_RX_CSUM_MODE_MASK 0x7
2217 #define CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET 0
2218 #define CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET 4
2220 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CONFIG_DEV))
2223 err = mlx4_CONFIG_DEV_get(dev, &config_dev);
2227 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET) &
2228 CONFIG_DEV_RX_CSUM_MODE_MASK;
2230 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0]))
2232 params->rx_csum_flags_port_1 = config_dev_csum_flags[csum_mask];
2234 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET) &
2235 CONFIG_DEV_RX_CSUM_MODE_MASK;
2237 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0]))
2239 params->rx_csum_flags_port_2 = config_dev_csum_flags[csum_mask];
2241 params->vxlan_udp_dport = be16_to_cpu(config_dev.vxlan_udp_dport);
2245 EXPORT_SYMBOL_GPL(mlx4_config_dev_retrieval);
2247 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port)
2249 struct mlx4_config_dev config_dev;
2251 memset(&config_dev, 0, sizeof(config_dev));
2252 config_dev.update_flags = cpu_to_be32(MLX4_VXLAN_UDP_DPORT);
2253 config_dev.vxlan_udp_dport = udp_port;
2255 return mlx4_CONFIG_DEV_set(dev, &config_dev);
2257 EXPORT_SYMBOL_GPL(mlx4_config_vxlan_port);
2259 #define CONFIG_DISABLE_RX_PORT BIT(15)
2260 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis)
2262 struct mlx4_config_dev config_dev;
2264 memset(&config_dev, 0, sizeof(config_dev));
2265 config_dev.update_flags = cpu_to_be32(MLX4_DISABLE_RX_PORT);
2267 config_dev.roce_flags =
2268 cpu_to_be32(CONFIG_DISABLE_RX_PORT);
2270 return mlx4_CONFIG_DEV_set(dev, &config_dev);
2273 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2)
2275 struct mlx4_cmd_mailbox *mailbox;
2282 mailbox = mlx4_alloc_cmd_mailbox(dev);
2283 if (IS_ERR(mailbox))
2287 v2p->v_port1 = cpu_to_be32(port1);
2288 v2p->v_port2 = cpu_to_be32(port2);
2290 err = mlx4_cmd(dev, mailbox->dma, 0,
2291 MLX4_SET_PORT_VIRT2PHY, MLX4_CMD_VIRT_PORT_MAP,
2292 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2294 mlx4_free_cmd_mailbox(dev, mailbox);
2299 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
2301 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
2302 MLX4_CMD_SET_ICM_SIZE,
2303 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2308 * Round up number of system pages needed in case
2309 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
2311 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
2312 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
2317 int mlx4_NOP(struct mlx4_dev *dev)
2319 /* Input modifier of 0x1f means "finish as soon as possible." */
2320 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, MLX4_CMD_TIME_CLASS_A,
2324 int mlx4_get_phys_port_id(struct mlx4_dev *dev)
2328 struct mlx4_cmd_mailbox *mailbox;
2330 u32 guid_hi, guid_lo;
2332 #define MOD_STAT_CFG_PORT_OFFSET 8
2333 #define MOD_STAT_CFG_GUID_H 0X14
2334 #define MOD_STAT_CFG_GUID_L 0X1c
2336 mailbox = mlx4_alloc_cmd_mailbox(dev);
2337 if (IS_ERR(mailbox))
2338 return PTR_ERR(mailbox);
2339 outbox = mailbox->buf;
2341 for (port = 1; port <= dev->caps.num_ports; port++) {
2342 in_mod = port << MOD_STAT_CFG_PORT_OFFSET;
2343 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_mod, 0x2,
2344 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
2347 mlx4_err(dev, "Fail to get port %d uplink guid\n",
2351 MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H);
2352 MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L);
2353 dev->caps.phys_port_id[port] = (u64)guid_lo |
2357 mlx4_free_cmd_mailbox(dev, mailbox);
2361 #define MLX4_WOL_SETUP_MODE (5 << 28)
2362 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
2364 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
2366 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
2367 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
2370 EXPORT_SYMBOL_GPL(mlx4_wol_read);
2372 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
2374 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
2376 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
2377 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2379 EXPORT_SYMBOL_GPL(mlx4_wol_write);
2386 void mlx4_opreq_action(struct work_struct *work)
2388 struct mlx4_priv *priv = container_of(work, struct mlx4_priv,
2390 struct mlx4_dev *dev = &priv->dev;
2391 int num_tasks = atomic_read(&priv->opreq_count);
2392 struct mlx4_cmd_mailbox *mailbox;
2393 struct mlx4_mgm *mgm;
2405 #define GET_OP_REQ_MODIFIER_OFFSET 0x08
2406 #define GET_OP_REQ_TOKEN_OFFSET 0x14
2407 #define GET_OP_REQ_TYPE_OFFSET 0x1a
2408 #define GET_OP_REQ_DATA_OFFSET 0x20
2410 mailbox = mlx4_alloc_cmd_mailbox(dev);
2411 if (IS_ERR(mailbox)) {
2412 mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n");
2415 outbox = mailbox->buf;
2418 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
2419 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
2422 mlx4_err(dev, "Failed to retrieve required operation: %d\n",
2426 MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET);
2427 MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET);
2428 MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET);
2433 if (dev->caps.steering_mode ==
2434 MLX4_STEERING_MODE_DEVICE_MANAGED) {
2435 mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n");
2439 mgm = (struct mlx4_mgm *)((u8 *)(outbox) +
2440 GET_OP_REQ_DATA_OFFSET);
2441 num_qps = be32_to_cpu(mgm->members_count) &
2443 rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1;
2444 prot = ((u8 *)(&mgm->members_count))[0] >> 6;
2446 for (i = 0; i < num_qps; i++) {
2447 qp.qpn = be32_to_cpu(mgm->qp[i]);
2449 err = mlx4_multicast_detach(dev, &qp,
2453 err = mlx4_multicast_attach(dev, &qp,
2463 mlx4_warn(dev, "Bad type for required operation\n");
2467 err = mlx4_cmd(dev, 0, ((u32) err |
2468 (__force u32)cpu_to_be32(token) << 16),
2469 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
2472 mlx4_err(dev, "Failed to acknowledge required request: %d\n",
2476 memset(outbox, 0, 0xffc);
2477 num_tasks = atomic_dec_return(&priv->opreq_count);
2481 mlx4_free_cmd_mailbox(dev, mailbox);
2484 static int mlx4_check_smp_firewall_active(struct mlx4_dev *dev,
2485 struct mlx4_cmd_mailbox *mailbox)
2487 #define MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET 0x10
2488 #define MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET 0x20
2489 #define MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET 0x40
2490 #define MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET 0x70
2492 u32 set_attr_mask, getresp_attr_mask;
2493 u32 trap_attr_mask, traprepress_attr_mask;
2495 MLX4_GET(set_attr_mask, mailbox->buf,
2496 MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET);
2497 mlx4_dbg(dev, "SMP firewall set_attribute_mask = 0x%x\n",
2500 MLX4_GET(getresp_attr_mask, mailbox->buf,
2501 MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET);
2502 mlx4_dbg(dev, "SMP firewall getresp_attribute_mask = 0x%x\n",
2505 MLX4_GET(trap_attr_mask, mailbox->buf,
2506 MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET);
2507 mlx4_dbg(dev, "SMP firewall trap_attribute_mask = 0x%x\n",
2510 MLX4_GET(traprepress_attr_mask, mailbox->buf,
2511 MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET);
2512 mlx4_dbg(dev, "SMP firewall traprepress_attribute_mask = 0x%x\n",
2513 traprepress_attr_mask);
2515 if (set_attr_mask && getresp_attr_mask && trap_attr_mask &&
2516 traprepress_attr_mask)
2522 int mlx4_config_mad_demux(struct mlx4_dev *dev)
2524 struct mlx4_cmd_mailbox *mailbox;
2525 int secure_host_active;
2528 /* Check if mad_demux is supported */
2529 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX))
2532 mailbox = mlx4_alloc_cmd_mailbox(dev);
2533 if (IS_ERR(mailbox)) {
2534 mlx4_warn(dev, "Failed to allocate mailbox for cmd MAD_DEMUX");
2538 /* Query mad_demux to find out which MADs are handled by internal sma */
2539 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0x01 /* subn mgmt class */,
2540 MLX4_CMD_MAD_DEMUX_QUERY_RESTR, MLX4_CMD_MAD_DEMUX,
2541 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2543 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: query restrictions failed (%d)\n",
2548 secure_host_active = mlx4_check_smp_firewall_active(dev, mailbox);
2550 /* Config mad_demux to handle all MADs returned by the query above */
2551 err = mlx4_cmd(dev, mailbox->dma, 0x01 /* subn mgmt class */,
2552 MLX4_CMD_MAD_DEMUX_CONFIG, MLX4_CMD_MAD_DEMUX,
2553 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2555 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: configure failed (%d)\n", err);
2559 if (secure_host_active)
2560 mlx4_warn(dev, "HCA operating in secure-host mode. SMP firewall activated.\n");
2562 mlx4_free_cmd_mailbox(dev, mailbox);
2566 /* Access Reg commands */
2567 enum mlx4_access_reg_masks {
2568 MLX4_ACCESS_REG_STATUS_MASK = 0x7f,
2569 MLX4_ACCESS_REG_METHOD_MASK = 0x7f,
2570 MLX4_ACCESS_REG_LEN_MASK = 0x7ff
2573 struct mlx4_access_reg {
2583 #define MLX4_ACCESS_REG_HEADER_SIZE (20)
2584 u8 reg_data[MLX4_MAILBOX_SIZE-MLX4_ACCESS_REG_HEADER_SIZE];
2585 } __attribute__((__packed__));
2588 * mlx4_ACCESS_REG - Generic access reg command.
2590 * @reg_id: register ID to access.
2591 * @method: Access method Read/Write.
2592 * @reg_len: register length to Read/Write in bytes.
2593 * @reg_data: reg_data pointer to Read/Write From/To.
2595 * Access ConnectX registers FW command.
2596 * Returns 0 on success and copies outbox mlx4_access_reg data
2597 * field into reg_data or a negative error code.
2599 static int mlx4_ACCESS_REG(struct mlx4_dev *dev, u16 reg_id,
2600 enum mlx4_access_reg_method method,
2601 u16 reg_len, void *reg_data)
2603 struct mlx4_cmd_mailbox *inbox, *outbox;
2604 struct mlx4_access_reg *inbuf, *outbuf;
2607 inbox = mlx4_alloc_cmd_mailbox(dev);
2609 return PTR_ERR(inbox);
2611 outbox = mlx4_alloc_cmd_mailbox(dev);
2612 if (IS_ERR(outbox)) {
2613 mlx4_free_cmd_mailbox(dev, inbox);
2614 return PTR_ERR(outbox);
2618 outbuf = outbox->buf;
2620 inbuf->constant1 = cpu_to_be16(0x1<<11 | 0x4);
2621 inbuf->constant2 = 0x1;
2622 inbuf->reg_id = cpu_to_be16(reg_id);
2623 inbuf->method = method & MLX4_ACCESS_REG_METHOD_MASK;
2625 reg_len = min(reg_len, (u16)(sizeof(inbuf->reg_data)));
2627 cpu_to_be16(((reg_len/4 + 1) & MLX4_ACCESS_REG_LEN_MASK) |
2630 memcpy(inbuf->reg_data, reg_data, reg_len);
2631 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, 0, 0,
2632 MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C,
2637 if (outbuf->status & MLX4_ACCESS_REG_STATUS_MASK) {
2638 err = outbuf->status & MLX4_ACCESS_REG_STATUS_MASK;
2640 "MLX4_CMD_ACCESS_REG(%x) returned REG status (%x)\n",
2645 memcpy(reg_data, outbuf->reg_data, reg_len);
2647 mlx4_free_cmd_mailbox(dev, inbox);
2648 mlx4_free_cmd_mailbox(dev, outbox);
2652 /* ConnectX registers IDs */
2654 MLX4_REG_ID_PTYS = 0x5004,
2658 * mlx4_ACCESS_PTYS_REG - Access PTYs (Port Type and Speed)
2661 * @method: Access method Read/Write.
2662 * @ptys_reg: PTYS register data pointer.
2664 * Access ConnectX PTYS register, to Read/Write Port Type/Speed
2666 * Returns 0 on success or a negative error code.
2668 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
2669 enum mlx4_access_reg_method method,
2670 struct mlx4_ptys_reg *ptys_reg)
2672 return mlx4_ACCESS_REG(dev, MLX4_REG_ID_PTYS,
2673 method, sizeof(*ptys_reg), ptys_reg);
2675 EXPORT_SYMBOL_GPL(mlx4_ACCESS_PTYS_REG);
2677 int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave,
2678 struct mlx4_vhcr *vhcr,
2679 struct mlx4_cmd_mailbox *inbox,
2680 struct mlx4_cmd_mailbox *outbox,
2681 struct mlx4_cmd_info *cmd)
2683 struct mlx4_access_reg *inbuf = inbox->buf;
2684 u8 method = inbuf->method & MLX4_ACCESS_REG_METHOD_MASK;
2685 u16 reg_id = be16_to_cpu(inbuf->reg_id);
2687 if (slave != mlx4_master_func_num(dev) &&
2688 method == MLX4_ACCESS_REG_WRITE)
2691 if (reg_id == MLX4_REG_ID_PTYS) {
2692 struct mlx4_ptys_reg *ptys_reg =
2693 (struct mlx4_ptys_reg *)inbuf->reg_data;
2695 ptys_reg->local_port =
2696 mlx4_slave_convert_port(dev, slave,
2697 ptys_reg->local_port);
2700 return mlx4_cmd_box(dev, inbox->dma, outbox->dma, vhcr->in_modifier,
2701 0, MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C,