2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/etherdevice.h>
36 #include <linux/mlx4/cmd.h>
37 #include <linux/module.h>
38 #include <linux/cache.h>
44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
49 extern void __buggy_use_of_MLX4_GET(void);
50 extern void __buggy_use_of_MLX4_PUT(void);
52 static bool enable_qos;
53 module_param(enable_qos, bool, 0444);
54 MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
56 #define MLX4_GET(dest, source, offset) \
58 void *__p = (char *) (source) + (offset); \
59 switch (sizeof (dest)) { \
60 case 1: (dest) = *(u8 *) __p; break; \
61 case 2: (dest) = be16_to_cpup(__p); break; \
62 case 4: (dest) = be32_to_cpup(__p); break; \
63 case 8: (dest) = be64_to_cpup(__p); break; \
64 default: __buggy_use_of_MLX4_GET(); \
68 #define MLX4_PUT(dest, source, offset) \
70 void *__d = ((char *) (dest) + (offset)); \
71 switch (sizeof(source)) { \
72 case 1: *(u8 *) __d = (source); break; \
73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
76 default: __buggy_use_of_MLX4_PUT(); \
80 static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
82 static const char *fname[] = {
83 [ 0] = "RC transport",
84 [ 1] = "UC transport",
85 [ 2] = "UD transport",
86 [ 3] = "XRC transport",
87 [ 4] = "reliable multicast",
88 [ 5] = "FCoIB support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
94 [12] = "Dual Port Different Protocol (DPDP) support",
95 [15] = "Big LSO headers",
98 [18] = "Atomic ops support",
99 [19] = "Raw multicast support",
100 [20] = "Address vector port checking support",
101 [21] = "UD multicast support",
102 [24] = "Demand paging support",
103 [25] = "Router support",
104 [30] = "IBoE support",
105 [32] = "Unicast loopback support",
106 [34] = "FCS header control",
107 [38] = "Wake On LAN support",
108 [40] = "UDP RSS support",
109 [41] = "Unicast VEP steering support",
110 [42] = "Multicast VEP steering support",
111 [48] = "Counters support",
112 [53] = "Port ETS Scheduler support",
113 [55] = "Port link type sensing support",
114 [59] = "Port management change event support",
115 [61] = "64 byte EQE support",
116 [62] = "64 byte CQE support",
120 mlx4_dbg(dev, "DEV_CAP flags:\n");
121 for (i = 0; i < ARRAY_SIZE(fname); ++i)
122 if (fname[i] && (flags & (1LL << i)))
123 mlx4_dbg(dev, " %s\n", fname[i]);
126 static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
128 static const char * const fname[] = {
130 [1] = "RSS Toeplitz Hash Function support",
131 [2] = "RSS XOR Hash Function support",
132 [3] = "Device managed flow steering support",
133 [4] = "Automatic MAC reassignment support",
134 [5] = "Time stamping support",
135 [6] = "VST (control vlan insertion/stripping) support",
136 [7] = "FSM (MAC anti-spoofing) support",
137 [8] = "Dynamic QP updates support",
138 [9] = "Device managed flow steering IPoIB support",
139 [10] = "TCP/IP offloads/flow-steering for VXLAN support"
143 for (i = 0; i < ARRAY_SIZE(fname); ++i)
144 if (fname[i] && (flags & (1LL << i)))
145 mlx4_dbg(dev, " %s\n", fname[i]);
148 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
150 struct mlx4_cmd_mailbox *mailbox;
154 #define MOD_STAT_CFG_IN_SIZE 0x100
156 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
157 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
159 mailbox = mlx4_alloc_cmd_mailbox(dev);
161 return PTR_ERR(mailbox);
162 inbox = mailbox->buf;
164 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
165 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
167 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
168 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
170 mlx4_free_cmd_mailbox(dev, mailbox);
174 int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
175 struct mlx4_vhcr *vhcr,
176 struct mlx4_cmd_mailbox *inbox,
177 struct mlx4_cmd_mailbox *outbox,
178 struct mlx4_cmd_info *cmd)
180 struct mlx4_priv *priv = mlx4_priv(dev);
185 #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
186 #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
187 #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
188 #define QUERY_FUNC_CAP_FMR_OFFSET 0x8
189 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10
190 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14
191 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18
192 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20
193 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24
194 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28
195 #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
196 #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30
198 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50
199 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54
200 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58
201 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60
202 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64
203 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68
205 #define QUERY_FUNC_CAP_FMR_FLAG 0x80
206 #define QUERY_FUNC_CAP_FLAG_RDMA 0x40
207 #define QUERY_FUNC_CAP_FLAG_ETH 0x80
208 #define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10
210 /* when opcode modifier = 1 */
211 #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
212 #define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8
213 #define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc
215 #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10
216 #define QUERY_FUNC_CAP_QP0_PROXY 0x14
217 #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18
218 #define QUERY_FUNC_CAP_QP1_PROXY 0x1c
219 #define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28
221 #define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40
222 #define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80
223 #define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10
225 #define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80
227 if (vhcr->op_modifier == 1) {
228 struct mlx4_active_ports actv_ports =
229 mlx4_get_active_ports(dev, slave);
230 int converted_port = mlx4_slave_convert_port(
231 dev, slave, vhcr->in_modifier);
233 if (converted_port < 0)
236 vhcr->in_modifier = converted_port;
237 /* Set nic_info bit to mark new fields support */
238 field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO;
239 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET);
241 /* phys-port = logical-port */
242 field = vhcr->in_modifier -
243 find_first_bit(actv_ports.ports, dev->caps.num_ports);
244 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
246 field = vhcr->in_modifier;
247 /* size is now the QP number */
248 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + field - 1;
249 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL);
252 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL);
254 size = dev->phys_caps.base_proxy_sqpn + 8 * slave + field - 1;
255 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_PROXY);
258 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_PROXY);
260 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier],
261 QUERY_FUNC_CAP_PHYS_PORT_ID);
263 } else if (vhcr->op_modifier == 0) {
264 struct mlx4_active_ports actv_ports =
265 mlx4_get_active_ports(dev, slave);
266 /* enable rdma and ethernet interfaces, and new quota locations */
267 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA |
268 QUERY_FUNC_CAP_FLAG_QUOTAS);
269 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
272 bitmap_weight(actv_ports.ports, dev->caps.num_ports),
273 dev->caps.num_ports);
274 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
276 size = dev->caps.function_caps; /* set PF behaviours */
277 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
279 field = 0; /* protected FMR support not available as yet */
280 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);
282 size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave];
283 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
284 size = dev->caps.num_qps;
285 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
287 size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave];
288 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
289 size = dev->caps.num_srqs;
290 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
292 size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave];
293 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
294 size = dev->caps.num_cqs;
295 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
297 size = dev->caps.num_eqs;
298 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
300 size = dev->caps.reserved_eqs;
301 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
303 size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave];
304 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
305 size = dev->caps.num_mpts;
306 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
308 size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave];
309 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
310 size = dev->caps.num_mtts;
311 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
313 size = dev->caps.num_mgms + dev->caps.num_amgms;
314 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
315 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
323 int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u32 gen_or_port,
324 struct mlx4_func_cap *func_cap)
326 struct mlx4_cmd_mailbox *mailbox;
328 u8 field, op_modifier;
330 int err = 0, quotas = 0;
332 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */
334 mailbox = mlx4_alloc_cmd_mailbox(dev);
336 return PTR_ERR(mailbox);
338 err = mlx4_cmd_box(dev, 0, mailbox->dma, gen_or_port, op_modifier,
339 MLX4_CMD_QUERY_FUNC_CAP,
340 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
344 outbox = mailbox->buf;
347 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
348 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) {
349 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n");
350 err = -EPROTONOSUPPORT;
353 func_cap->flags = field;
354 quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS);
356 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
357 func_cap->num_ports = field;
359 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
360 func_cap->pf_context_behaviour = size;
363 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
364 func_cap->qp_quota = size & 0xFFFFFF;
366 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
367 func_cap->srq_quota = size & 0xFFFFFF;
369 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
370 func_cap->cq_quota = size & 0xFFFFFF;
372 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
373 func_cap->mpt_quota = size & 0xFFFFFF;
375 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
376 func_cap->mtt_quota = size & 0xFFFFFF;
378 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
379 func_cap->mcg_quota = size & 0xFFFFFF;
382 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
383 func_cap->qp_quota = size & 0xFFFFFF;
385 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
386 func_cap->srq_quota = size & 0xFFFFFF;
388 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
389 func_cap->cq_quota = size & 0xFFFFFF;
391 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
392 func_cap->mpt_quota = size & 0xFFFFFF;
394 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
395 func_cap->mtt_quota = size & 0xFFFFFF;
397 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
398 func_cap->mcg_quota = size & 0xFFFFFF;
400 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
401 func_cap->max_eq = size & 0xFFFFFF;
403 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
404 func_cap->reserved_eq = size & 0xFFFFFF;
409 /* logical port query */
410 if (gen_or_port > dev->caps.num_ports) {
415 MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET);
416 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) {
417 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_OFFSET) {
418 mlx4_err(dev, "VLAN is enforced on this port\n");
419 err = -EPROTONOSUPPORT;
423 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) {
424 mlx4_err(dev, "Force mac is enabled on this port\n");
425 err = -EPROTONOSUPPORT;
428 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) {
429 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET);
430 if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) {
431 mlx4_err(dev, "phy_wqe_gid is "
432 "enforced on this ib port\n");
433 err = -EPROTONOSUPPORT;
438 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
439 func_cap->physical_port = field;
440 if (func_cap->physical_port != gen_or_port) {
445 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL);
446 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF;
448 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY);
449 func_cap->qp0_proxy_qpn = size & 0xFFFFFF;
451 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL);
452 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF;
454 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY);
455 func_cap->qp1_proxy_qpn = size & 0xFFFFFF;
457 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_NIC_INFO)
458 MLX4_GET(func_cap->phys_port_id, outbox,
459 QUERY_FUNC_CAP_PHYS_PORT_ID);
461 /* All other resources are allocated by the master, but we still report
462 * 'num' and 'reserved' capabilities as follows:
463 * - num remains the maximum resource index
464 * - 'num - reserved' is the total available objects of a resource, but
465 * resource indices may be less than 'reserved'
466 * TODO: set per-resource quotas */
469 mlx4_free_cmd_mailbox(dev, mailbox);
474 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
476 struct mlx4_cmd_mailbox *mailbox;
479 u32 field32, flags, ext_flags;
485 #define QUERY_DEV_CAP_OUT_SIZE 0x100
486 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
487 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
488 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
489 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
490 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
491 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
492 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
493 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
494 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
495 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
496 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
497 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
498 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
499 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
500 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
501 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
502 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
503 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
504 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
505 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
506 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
507 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
508 #define QUERY_DEV_CAP_RSS_OFFSET 0x2e
509 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
510 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
511 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
512 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
513 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
514 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
515 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
516 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
517 #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e
518 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
519 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
520 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
521 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
522 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
523 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
524 #define QUERY_DEV_CAP_BF_OFFSET 0x4c
525 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
526 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
527 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
528 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
529 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
530 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
531 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
532 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
533 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
534 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
535 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
536 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
537 #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
538 #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
539 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
540 #define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70
541 #define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74
542 #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
543 #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
544 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
545 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
546 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
547 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
548 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
549 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
550 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
551 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
552 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
553 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
554 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
555 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
556 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
557 #define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d
558 #define QUERY_DEV_CAP_VXLAN 0x9e
561 mailbox = mlx4_alloc_cmd_mailbox(dev);
563 return PTR_ERR(mailbox);
564 outbox = mailbox->buf;
566 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
567 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
571 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
572 dev_cap->reserved_qps = 1 << (field & 0xf);
573 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
574 dev_cap->max_qps = 1 << (field & 0x1f);
575 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
576 dev_cap->reserved_srqs = 1 << (field >> 4);
577 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
578 dev_cap->max_srqs = 1 << (field & 0x1f);
579 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
580 dev_cap->max_cq_sz = 1 << field;
581 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
582 dev_cap->reserved_cqs = 1 << (field & 0xf);
583 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
584 dev_cap->max_cqs = 1 << (field & 0x1f);
585 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
586 dev_cap->max_mpts = 1 << (field & 0x3f);
587 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
588 dev_cap->reserved_eqs = field & 0xf;
589 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
590 dev_cap->max_eqs = 1 << (field & 0xf);
591 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
592 dev_cap->reserved_mtts = 1 << (field >> 4);
593 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
594 dev_cap->max_mrw_sz = 1 << field;
595 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
596 dev_cap->reserved_mrws = 1 << (field & 0xf);
597 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
598 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
599 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
600 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
601 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
602 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
603 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
606 dev_cap->max_gso_sz = 0;
608 dev_cap->max_gso_sz = 1 << field;
610 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
612 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
614 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
617 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
618 dev_cap->max_rss_tbl_sz = 1 << field;
620 dev_cap->max_rss_tbl_sz = 0;
621 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
622 dev_cap->max_rdma_global = 1 << (field & 0x3f);
623 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
624 dev_cap->local_ca_ack_delay = field & 0x1f;
625 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
626 dev_cap->num_ports = field & 0xf;
627 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
628 dev_cap->max_msg_sz = 1 << (field & 0x1f);
629 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
631 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
632 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
633 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
635 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB;
636 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
637 dev_cap->fs_max_num_qp_per_entry = field;
638 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
639 dev_cap->stat_rate_support = stat_rate;
640 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
642 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS;
643 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
644 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
645 dev_cap->flags = flags | (u64)ext_flags << 32;
646 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
647 dev_cap->reserved_uars = field >> 4;
648 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
649 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
650 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
651 dev_cap->min_page_sz = 1 << field;
653 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
655 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
656 dev_cap->bf_reg_size = 1 << (field & 0x1f);
657 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
658 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
660 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
661 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
662 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
664 dev_cap->bf_reg_size = 0;
665 mlx4_dbg(dev, "BlueFlame not available\n");
668 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
669 dev_cap->max_sq_sg = field;
670 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
671 dev_cap->max_sq_desc_sz = size;
673 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
674 dev_cap->max_qp_per_mcg = 1 << field;
675 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
676 dev_cap->reserved_mgms = field & 0xf;
677 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
678 dev_cap->max_mcgs = 1 << field;
679 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
680 dev_cap->reserved_pds = field >> 4;
681 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
682 dev_cap->max_pds = 1 << (field & 0x3f);
683 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
684 dev_cap->reserved_xrcds = field >> 4;
685 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET);
686 dev_cap->max_xrcds = 1 << (field & 0x1f);
688 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
689 dev_cap->rdmarc_entry_sz = size;
690 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
691 dev_cap->qpc_entry_sz = size;
692 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
693 dev_cap->aux_entry_sz = size;
694 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
695 dev_cap->altc_entry_sz = size;
696 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
697 dev_cap->eqc_entry_sz = size;
698 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
699 dev_cap->cqc_entry_sz = size;
700 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
701 dev_cap->srq_entry_sz = size;
702 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
703 dev_cap->cmpt_entry_sz = size;
704 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
705 dev_cap->mtt_entry_sz = size;
706 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
707 dev_cap->dmpt_entry_sz = size;
709 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
710 dev_cap->max_srq_sz = 1 << field;
711 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
712 dev_cap->max_qp_sz = 1 << field;
713 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
714 dev_cap->resize_srq = field & 1;
715 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
716 dev_cap->max_rq_sg = field;
717 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
718 dev_cap->max_rq_desc_sz = size;
720 MLX4_GET(dev_cap->bmme_flags, outbox,
721 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
722 MLX4_GET(dev_cap->reserved_lkey, outbox,
723 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
724 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC);
726 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN;
727 MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN);
729 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS;
730 MLX4_GET(dev_cap->max_icm_sz, outbox,
731 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
732 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
733 MLX4_GET(dev_cap->max_counters, outbox,
734 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
736 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
737 if (field32 & (1 << 16))
738 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP;
739 if (field32 & (1 << 26))
740 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL;
741 if (field32 & (1 << 20))
742 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM;
744 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
745 for (i = 1; i <= dev_cap->num_ports; ++i) {
746 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
747 dev_cap->max_vl[i] = field >> 4;
748 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
749 dev_cap->ib_mtu[i] = field >> 4;
750 dev_cap->max_port_width[i] = field & 0xf;
751 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
752 dev_cap->max_gids[i] = 1 << (field & 0xf);
753 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
754 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
757 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
758 #define QUERY_PORT_MTU_OFFSET 0x01
759 #define QUERY_PORT_ETH_MTU_OFFSET 0x02
760 #define QUERY_PORT_WIDTH_OFFSET 0x06
761 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
762 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
763 #define QUERY_PORT_MAX_VL_OFFSET 0x0b
764 #define QUERY_PORT_MAC_OFFSET 0x10
765 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
766 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
767 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20
769 for (i = 1; i <= dev_cap->num_ports; ++i) {
770 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
771 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
775 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
776 dev_cap->supported_port_types[i] = field & 3;
777 dev_cap->suggested_type[i] = (field >> 3) & 1;
778 dev_cap->default_sense[i] = (field >> 4) & 1;
779 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
780 dev_cap->ib_mtu[i] = field & 0xf;
781 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
782 dev_cap->max_port_width[i] = field & 0xf;
783 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
784 dev_cap->max_gids[i] = 1 << (field >> 4);
785 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
786 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
787 dev_cap->max_vl[i] = field & 0xf;
788 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
789 dev_cap->log_max_macs[i] = field & 0xf;
790 dev_cap->log_max_vlans[i] = field >> 4;
791 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
792 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
793 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
794 dev_cap->trans_type[i] = field32 >> 24;
795 dev_cap->vendor_oui[i] = field32 & 0xffffff;
796 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
797 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
801 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
802 dev_cap->bmme_flags, dev_cap->reserved_lkey);
805 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
806 * we can't use any EQs whose doorbell falls on that page,
807 * even if the EQ itself isn't reserved.
809 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
810 dev_cap->reserved_eqs);
812 mlx4_dbg(dev, "Max ICM size %lld MB\n",
813 (unsigned long long) dev_cap->max_icm_sz >> 20);
814 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
815 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
816 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
817 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
818 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
819 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
820 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
821 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
822 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
823 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
824 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
825 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
826 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
827 dev_cap->max_pds, dev_cap->reserved_mgms);
828 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
829 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
830 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
831 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
832 dev_cap->max_port_width[1]);
833 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
834 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
835 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
836 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
837 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
838 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
839 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
841 dump_dev_cap_flags(dev, dev_cap->flags);
842 dump_dev_cap_flags2(dev, dev_cap->flags2);
845 mlx4_free_cmd_mailbox(dev, mailbox);
849 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
850 struct mlx4_vhcr *vhcr,
851 struct mlx4_cmd_mailbox *inbox,
852 struct mlx4_cmd_mailbox *outbox,
853 struct mlx4_cmd_info *cmd)
862 struct mlx4_active_ports actv_ports;
864 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
865 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
869 /* add port mng change event capability and disable mw type 1
870 * unconditionally to slaves
872 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
873 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV;
874 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW;
875 actv_ports = mlx4_get_active_ports(dev, slave);
876 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
877 for (slave_port = 0, real_port = first_port;
878 real_port < first_port +
879 bitmap_weight(actv_ports.ports, dev->caps.num_ports);
880 ++real_port, ++slave_port) {
881 if (flags & (MLX4_DEV_CAP_FLAG_WOL_PORT1 << real_port))
882 flags |= MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port;
884 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port);
886 for (; slave_port < dev->caps.num_ports; ++slave_port)
887 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port);
888 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
890 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET);
892 field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F;
893 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET);
895 /* For guests, disable timestamp */
896 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
898 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
900 /* For guests, disable vxlan tunneling */
901 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN);
903 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN);
905 /* For guests, report Blueflame disabled */
906 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
908 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
910 /* For guests, disable mw type 2 */
911 MLX4_GET(bmme_flags, outbox->buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
912 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN;
913 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
915 /* turn off device-managed steering capability if not enabled */
916 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
917 MLX4_GET(field, outbox->buf,
918 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
920 MLX4_PUT(outbox->buf, field,
921 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
924 /* turn off ipoib managed steering for guests */
925 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
927 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
932 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
933 struct mlx4_vhcr *vhcr,
934 struct mlx4_cmd_mailbox *inbox,
935 struct mlx4_cmd_mailbox *outbox,
936 struct mlx4_cmd_info *cmd)
938 struct mlx4_priv *priv = mlx4_priv(dev);
943 int admin_link_state;
944 int port = mlx4_slave_convert_port(dev, slave,
945 vhcr->in_modifier & 0xFF);
947 #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0
948 #define MLX4_PORT_LINK_UP_MASK 0x80
949 #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c
950 #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e
955 vhcr->in_modifier = (vhcr->in_modifier & ~0xFF) |
958 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
959 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
962 if (!err && dev->caps.function != slave) {
963 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac;
964 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
966 /* get port type - currently only eth is enabled */
967 MLX4_GET(port_type, outbox->buf,
968 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
970 /* No link sensing allowed */
971 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK;
972 /* set port type to currently operating port type */
973 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3);
975 admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state;
976 if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state)
977 port_type |= MLX4_PORT_LINK_UP_MASK;
978 else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state)
979 port_type &= ~MLX4_PORT_LINK_UP_MASK;
981 MLX4_PUT(outbox->buf, port_type,
982 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
984 if (dev->caps.port_type[vhcr->in_modifier] == MLX4_PORT_TYPE_ETH)
985 short_field = mlx4_get_slave_num_gids(dev, slave, port);
987 short_field = 1; /* slave max gids */
988 MLX4_PUT(outbox->buf, short_field,
989 QUERY_PORT_CUR_MAX_GID_OFFSET);
991 short_field = dev->caps.pkey_table_len[vhcr->in_modifier];
992 MLX4_PUT(outbox->buf, short_field,
993 QUERY_PORT_CUR_MAX_PKEY_OFFSET);
999 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1000 int *gid_tbl_len, int *pkey_tbl_len)
1002 struct mlx4_cmd_mailbox *mailbox;
1007 mailbox = mlx4_alloc_cmd_mailbox(dev);
1008 if (IS_ERR(mailbox))
1009 return PTR_ERR(mailbox);
1011 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0,
1012 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
1017 outbox = mailbox->buf;
1019 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);
1020 *gid_tbl_len = field;
1022 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);
1023 *pkey_tbl_len = field;
1026 mlx4_free_cmd_mailbox(dev, mailbox);
1029 EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len);
1031 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
1033 struct mlx4_cmd_mailbox *mailbox;
1034 struct mlx4_icm_iter iter;
1042 mailbox = mlx4_alloc_cmd_mailbox(dev);
1043 if (IS_ERR(mailbox))
1044 return PTR_ERR(mailbox);
1045 pages = mailbox->buf;
1047 for (mlx4_icm_first(icm, &iter);
1048 !mlx4_icm_last(&iter);
1049 mlx4_icm_next(&iter)) {
1051 * We have to pass pages that are aligned to their
1052 * size, so find the least significant 1 in the
1053 * address or size and use that as our log2 size.
1055 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
1056 if (lg < MLX4_ICM_PAGE_SHIFT) {
1057 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
1059 (unsigned long long) mlx4_icm_addr(&iter),
1060 mlx4_icm_size(&iter));
1065 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
1067 pages[nent * 2] = cpu_to_be64(virt);
1071 pages[nent * 2 + 1] =
1072 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
1073 (lg - MLX4_ICM_PAGE_SHIFT));
1074 ts += 1 << (lg - 10);
1077 if (++nent == MLX4_MAILBOX_SIZE / 16) {
1078 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
1079 MLX4_CMD_TIME_CLASS_B,
1089 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
1090 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1095 case MLX4_CMD_MAP_FA:
1096 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
1098 case MLX4_CMD_MAP_ICM_AUX:
1099 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
1101 case MLX4_CMD_MAP_ICM:
1102 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
1103 tc, ts, (unsigned long long) virt - (ts << 10));
1108 mlx4_free_cmd_mailbox(dev, mailbox);
1112 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
1114 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
1117 int mlx4_UNMAP_FA(struct mlx4_dev *dev)
1119 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
1120 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1124 int mlx4_RUN_FW(struct mlx4_dev *dev)
1126 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
1127 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1130 int mlx4_QUERY_FW(struct mlx4_dev *dev)
1132 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
1133 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
1134 struct mlx4_cmd_mailbox *mailbox;
1141 #define QUERY_FW_OUT_SIZE 0x100
1142 #define QUERY_FW_VER_OFFSET 0x00
1143 #define QUERY_FW_PPF_ID 0x09
1144 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
1145 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
1146 #define QUERY_FW_ERR_START_OFFSET 0x30
1147 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
1148 #define QUERY_FW_ERR_BAR_OFFSET 0x3c
1150 #define QUERY_FW_SIZE_OFFSET 0x00
1151 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
1152 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
1154 #define QUERY_FW_COMM_BASE_OFFSET 0x40
1155 #define QUERY_FW_COMM_BAR_OFFSET 0x48
1157 #define QUERY_FW_CLOCK_OFFSET 0x50
1158 #define QUERY_FW_CLOCK_BAR 0x58
1160 mailbox = mlx4_alloc_cmd_mailbox(dev);
1161 if (IS_ERR(mailbox))
1162 return PTR_ERR(mailbox);
1163 outbox = mailbox->buf;
1165 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1166 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1170 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
1172 * FW subminor version is at more significant bits than minor
1173 * version, so swap here.
1175 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
1176 ((fw_ver & 0xffff0000ull) >> 16) |
1177 ((fw_ver & 0x0000ffffull) << 16);
1179 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
1180 dev->caps.function = lg;
1182 if (mlx4_is_slave(dev))
1186 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
1187 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
1188 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
1189 mlx4_err(dev, "Installed FW has unsupported "
1190 "command interface revision %d.\n",
1192 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
1193 (int) (dev->caps.fw_ver >> 32),
1194 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1195 (int) dev->caps.fw_ver & 0xffff);
1196 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
1197 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
1202 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
1203 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
1205 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
1206 cmd->max_cmds = 1 << lg;
1208 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
1209 (int) (dev->caps.fw_ver >> 32),
1210 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1211 (int) dev->caps.fw_ver & 0xffff,
1212 cmd_if_rev, cmd->max_cmds);
1214 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
1215 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
1216 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
1217 fw->catas_bar = (fw->catas_bar >> 6) * 2;
1219 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
1220 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
1222 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
1223 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
1224 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
1225 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
1227 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
1228 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
1229 fw->comm_bar = (fw->comm_bar >> 6) * 2;
1230 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
1231 fw->comm_bar, fw->comm_base);
1232 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
1234 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET);
1235 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR);
1236 fw->clock_bar = (fw->clock_bar >> 6) * 2;
1237 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n",
1238 fw->clock_bar, fw->clock_offset);
1241 * Round up number of system pages needed in case
1242 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1245 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1246 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1248 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
1249 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
1252 mlx4_free_cmd_mailbox(dev, mailbox);
1256 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1257 struct mlx4_vhcr *vhcr,
1258 struct mlx4_cmd_mailbox *inbox,
1259 struct mlx4_cmd_mailbox *outbox,
1260 struct mlx4_cmd_info *cmd)
1265 outbuf = outbox->buf;
1266 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1267 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1271 /* for slaves, set pci PPF ID to invalid and zero out everything
1272 * else except FW version */
1273 outbuf[0] = outbuf[1] = 0;
1274 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8);
1275 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID;
1280 static void get_board_id(void *vsd, char *board_id)
1284 #define VSD_OFFSET_SIG1 0x00
1285 #define VSD_OFFSET_SIG2 0xde
1286 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
1287 #define VSD_OFFSET_TS_BOARD_ID 0x20
1289 #define VSD_SIGNATURE_TOPSPIN 0x5ad
1291 memset(board_id, 0, MLX4_BOARD_ID_LEN);
1293 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1294 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1295 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
1298 * The board ID is a string but the firmware byte
1299 * swaps each 4-byte word before passing it back to
1300 * us. Therefore we need to swab it before printing.
1302 for (i = 0; i < 4; ++i)
1303 ((u32 *) board_id)[i] =
1304 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1308 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
1310 struct mlx4_cmd_mailbox *mailbox;
1314 #define QUERY_ADAPTER_OUT_SIZE 0x100
1315 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1316 #define QUERY_ADAPTER_VSD_OFFSET 0x20
1318 mailbox = mlx4_alloc_cmd_mailbox(dev);
1319 if (IS_ERR(mailbox))
1320 return PTR_ERR(mailbox);
1321 outbox = mailbox->buf;
1323 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
1324 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1328 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1330 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1334 mlx4_free_cmd_mailbox(dev, mailbox);
1338 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1340 struct mlx4_cmd_mailbox *mailbox;
1344 #define INIT_HCA_IN_SIZE 0x200
1345 #define INIT_HCA_VERSION_OFFSET 0x000
1346 #define INIT_HCA_VERSION 2
1347 #define INIT_HCA_VXLAN_OFFSET 0x0c
1348 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
1349 #define INIT_HCA_FLAGS_OFFSET 0x014
1350 #define INIT_HCA_QPC_OFFSET 0x020
1351 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1352 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1353 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1354 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1355 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1356 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
1357 #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
1358 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1359 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1360 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1361 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1362 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1363 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1364 #define INIT_HCA_MCAST_OFFSET 0x0c0
1365 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1366 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1367 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1368 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
1369 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1370 #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1371 #define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1372 #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1373 #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
1374 #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b)
1375 #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21)
1376 #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22)
1377 #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25)
1378 #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26)
1379 #define INIT_HCA_TPT_OFFSET 0x0f0
1380 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
1381 #define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08)
1382 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1383 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1384 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1385 #define INIT_HCA_UAR_OFFSET 0x120
1386 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1387 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1389 mailbox = mlx4_alloc_cmd_mailbox(dev);
1390 if (IS_ERR(mailbox))
1391 return PTR_ERR(mailbox);
1392 inbox = mailbox->buf;
1394 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1396 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1397 (ilog2(cache_line_size()) - 4) << 5;
1399 #if defined(__LITTLE_ENDIAN)
1400 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1401 #elif defined(__BIG_ENDIAN)
1402 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1404 #error Host endianness not defined
1406 /* Check port for UD address vector: */
1407 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1409 /* Enable IPoIB checksumming if we can: */
1410 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1411 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1413 /* Enable QoS support if module parameter set */
1415 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1417 /* enable counters */
1418 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1419 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1421 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1422 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) {
1423 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29);
1424 dev->caps.eqe_size = 64;
1425 dev->caps.eqe_factor = 1;
1427 dev->caps.eqe_size = 32;
1428 dev->caps.eqe_factor = 0;
1431 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) {
1432 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30);
1433 dev->caps.cqe_size = 64;
1434 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE;
1436 dev->caps.cqe_size = 32;
1439 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1441 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1442 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1443 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1444 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1445 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1446 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1447 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1448 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1449 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1450 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1451 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1452 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1454 /* steering attributes */
1455 if (dev->caps.steering_mode ==
1456 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1457 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |=
1459 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN);
1461 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET);
1462 MLX4_PUT(inbox, param->log_mc_entry_sz,
1463 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1464 MLX4_PUT(inbox, param->log_mc_table_sz,
1465 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1466 /* Enable Ethernet flow steering
1467 * with udp unicast and tcp unicast
1469 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
1470 INIT_HCA_FS_ETH_BITS_OFFSET);
1471 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1472 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET);
1473 /* Enable IPoIB flow steering
1474 * with udp unicast and tcp unicast
1476 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
1477 INIT_HCA_FS_IB_BITS_OFFSET);
1478 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1479 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET);
1481 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1482 MLX4_PUT(inbox, param->log_mc_entry_sz,
1483 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1484 MLX4_PUT(inbox, param->log_mc_hash_sz,
1485 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1486 MLX4_PUT(inbox, param->log_mc_table_sz,
1487 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1488 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0)
1489 MLX4_PUT(inbox, (u8) (1 << 3),
1490 INIT_HCA_UC_STEERING_OFFSET);
1493 /* TPT attributes */
1495 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
1496 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET);
1497 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1498 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1499 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1501 /* UAR attributes */
1503 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1504 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1506 /* set parser VXLAN attributes */
1507 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) {
1508 u8 parser_params = 0;
1509 MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET);
1512 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000,
1516 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1518 mlx4_free_cmd_mailbox(dev, mailbox);
1522 int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1523 struct mlx4_init_hca_param *param)
1525 struct mlx4_cmd_mailbox *mailbox;
1531 #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
1532 #define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c
1534 mailbox = mlx4_alloc_cmd_mailbox(dev);
1535 if (IS_ERR(mailbox))
1536 return PTR_ERR(mailbox);
1537 outbox = mailbox->buf;
1539 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1541 MLX4_CMD_TIME_CLASS_B,
1542 !mlx4_is_slave(dev));
1546 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
1547 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
1549 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1551 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1552 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1553 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1554 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1555 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1556 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1557 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1558 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1559 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1560 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
1561 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1562 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1564 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET);
1565 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) {
1566 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1568 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET);
1569 if (byte_field & 0x8)
1570 param->steering_mode = MLX4_STEERING_MODE_B0;
1572 param->steering_mode = MLX4_STEERING_MODE_A0;
1574 /* steering attributes */
1575 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
1576 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET);
1577 MLX4_GET(param->log_mc_entry_sz, outbox,
1578 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1579 MLX4_GET(param->log_mc_table_sz, outbox,
1580 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1582 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
1583 MLX4_GET(param->log_mc_entry_sz, outbox,
1584 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1585 MLX4_GET(param->log_mc_hash_sz, outbox,
1586 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1587 MLX4_GET(param->log_mc_table_sz, outbox,
1588 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1591 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1592 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS);
1593 if (byte_field & 0x20) /* 64-bytes eqe enabled */
1594 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
1595 if (byte_field & 0x40) /* 64-bytes cqe enabled */
1596 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
1598 /* TPT attributes */
1600 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
1601 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET);
1602 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
1603 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
1604 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
1606 /* UAR attributes */
1608 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1609 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
1612 mlx4_free_cmd_mailbox(dev, mailbox);
1617 /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0
1618 * and real QP0 are active, so that the paravirtualized QP0 is ready
1620 static int check_qp0_state(struct mlx4_dev *dev, int function, int port)
1622 struct mlx4_priv *priv = mlx4_priv(dev);
1623 /* irrelevant if not infiniband */
1624 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active &&
1625 priv->mfunc.master.qp0_state[port].qp0_active)
1630 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1631 struct mlx4_vhcr *vhcr,
1632 struct mlx4_cmd_mailbox *inbox,
1633 struct mlx4_cmd_mailbox *outbox,
1634 struct mlx4_cmd_info *cmd)
1636 struct mlx4_priv *priv = mlx4_priv(dev);
1637 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier);
1643 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
1646 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1647 /* Enable port only if it was previously disabled */
1648 if (!priv->mfunc.master.init_port_ref[port]) {
1649 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1650 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1654 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1656 if (slave == mlx4_master_func_num(dev)) {
1657 if (check_qp0_state(dev, slave, port) &&
1658 !priv->mfunc.master.qp0_state[port].port_active) {
1659 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1660 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1663 priv->mfunc.master.qp0_state[port].port_active = 1;
1664 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1667 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1669 ++priv->mfunc.master.init_port_ref[port];
1673 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
1675 struct mlx4_cmd_mailbox *mailbox;
1681 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
1682 #define INIT_PORT_IN_SIZE 256
1683 #define INIT_PORT_FLAGS_OFFSET 0x00
1684 #define INIT_PORT_FLAG_SIG (1 << 18)
1685 #define INIT_PORT_FLAG_NG (1 << 17)
1686 #define INIT_PORT_FLAG_G0 (1 << 16)
1687 #define INIT_PORT_VL_SHIFT 4
1688 #define INIT_PORT_PORT_WIDTH_SHIFT 8
1689 #define INIT_PORT_MTU_OFFSET 0x04
1690 #define INIT_PORT_MAX_GID_OFFSET 0x06
1691 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a
1692 #define INIT_PORT_GUID0_OFFSET 0x10
1693 #define INIT_PORT_NODE_GUID_OFFSET 0x18
1694 #define INIT_PORT_SI_GUID_OFFSET 0x20
1696 mailbox = mlx4_alloc_cmd_mailbox(dev);
1697 if (IS_ERR(mailbox))
1698 return PTR_ERR(mailbox);
1699 inbox = mailbox->buf;
1702 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
1703 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
1704 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
1706 field = 128 << dev->caps.ib_mtu_cap[port];
1707 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
1708 field = dev->caps.gid_table_len[port];
1709 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
1710 field = dev->caps.pkey_table_len[port];
1711 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
1713 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
1714 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1716 mlx4_free_cmd_mailbox(dev, mailbox);
1718 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1719 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1723 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
1725 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1726 struct mlx4_vhcr *vhcr,
1727 struct mlx4_cmd_mailbox *inbox,
1728 struct mlx4_cmd_mailbox *outbox,
1729 struct mlx4_cmd_info *cmd)
1731 struct mlx4_priv *priv = mlx4_priv(dev);
1732 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier);
1738 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
1742 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1743 if (priv->mfunc.master.init_port_ref[port] == 1) {
1744 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1745 1000, MLX4_CMD_NATIVE);
1749 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1751 /* infiniband port */
1752 if (slave == mlx4_master_func_num(dev)) {
1753 if (!priv->mfunc.master.qp0_state[port].qp0_active &&
1754 priv->mfunc.master.qp0_state[port].port_active) {
1755 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1756 1000, MLX4_CMD_NATIVE);
1759 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1760 priv->mfunc.master.qp0_state[port].port_active = 0;
1763 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1765 --priv->mfunc.master.init_port_ref[port];
1769 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
1771 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1774 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
1776 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
1778 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000,
1782 struct mlx4_config_dev {
1783 __be32 update_flags;
1785 __be16 vxlan_udp_dport;
1789 #define MLX4_VXLAN_UDP_DPORT (1 << 0)
1791 static int mlx4_CONFIG_DEV(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev)
1794 struct mlx4_cmd_mailbox *mailbox;
1796 mailbox = mlx4_alloc_cmd_mailbox(dev);
1797 if (IS_ERR(mailbox))
1798 return PTR_ERR(mailbox);
1800 memcpy(mailbox->buf, config_dev, sizeof(*config_dev));
1802 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_CONFIG_DEV,
1803 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1805 mlx4_free_cmd_mailbox(dev, mailbox);
1809 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port)
1811 struct mlx4_config_dev config_dev;
1813 memset(&config_dev, 0, sizeof(config_dev));
1814 config_dev.update_flags = cpu_to_be32(MLX4_VXLAN_UDP_DPORT);
1815 config_dev.vxlan_udp_dport = udp_port;
1817 return mlx4_CONFIG_DEV(dev, &config_dev);
1819 EXPORT_SYMBOL_GPL(mlx4_config_vxlan_port);
1822 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
1824 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
1825 MLX4_CMD_SET_ICM_SIZE,
1826 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1831 * Round up number of system pages needed in case
1832 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1834 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1835 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1840 int mlx4_NOP(struct mlx4_dev *dev)
1842 /* Input modifier of 0x1f means "finish as soon as possible." */
1843 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE);
1846 int mlx4_get_phys_port_id(struct mlx4_dev *dev)
1850 struct mlx4_cmd_mailbox *mailbox;
1852 u32 guid_hi, guid_lo;
1854 #define MOD_STAT_CFG_PORT_OFFSET 8
1855 #define MOD_STAT_CFG_GUID_H 0X14
1856 #define MOD_STAT_CFG_GUID_L 0X1c
1858 mailbox = mlx4_alloc_cmd_mailbox(dev);
1859 if (IS_ERR(mailbox))
1860 return PTR_ERR(mailbox);
1861 outbox = mailbox->buf;
1863 for (port = 1; port <= dev->caps.num_ports; port++) {
1864 in_mod = port << MOD_STAT_CFG_PORT_OFFSET;
1865 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_mod, 0x2,
1866 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
1869 mlx4_err(dev, "Fail to get port %d uplink guid\n",
1873 MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H);
1874 MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L);
1875 dev->caps.phys_port_id[port] = (u64)guid_lo |
1879 mlx4_free_cmd_mailbox(dev, mailbox);
1883 #define MLX4_WOL_SETUP_MODE (5 << 28)
1884 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
1886 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1888 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
1889 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
1892 EXPORT_SYMBOL_GPL(mlx4_wol_read);
1894 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
1896 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1898 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
1899 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1901 EXPORT_SYMBOL_GPL(mlx4_wol_write);
1908 void mlx4_opreq_action(struct work_struct *work)
1910 struct mlx4_priv *priv = container_of(work, struct mlx4_priv,
1912 struct mlx4_dev *dev = &priv->dev;
1913 int num_tasks = atomic_read(&priv->opreq_count);
1914 struct mlx4_cmd_mailbox *mailbox;
1915 struct mlx4_mgm *mgm;
1927 #define GET_OP_REQ_MODIFIER_OFFSET 0x08
1928 #define GET_OP_REQ_TOKEN_OFFSET 0x14
1929 #define GET_OP_REQ_TYPE_OFFSET 0x1a
1930 #define GET_OP_REQ_DATA_OFFSET 0x20
1932 mailbox = mlx4_alloc_cmd_mailbox(dev);
1933 if (IS_ERR(mailbox)) {
1934 mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n");
1937 outbox = mailbox->buf;
1940 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1941 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
1944 mlx4_err(dev, "Failed to retrieve required operation: %d\n",
1948 MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET);
1949 MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET);
1950 MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET);
1955 if (dev->caps.steering_mode ==
1956 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1957 mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n");
1961 mgm = (struct mlx4_mgm *)((u8 *)(outbox) +
1962 GET_OP_REQ_DATA_OFFSET);
1963 num_qps = be32_to_cpu(mgm->members_count) &
1965 rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1;
1966 prot = ((u8 *)(&mgm->members_count))[0] >> 6;
1968 for (i = 0; i < num_qps; i++) {
1969 qp.qpn = be32_to_cpu(mgm->qp[i]);
1971 err = mlx4_multicast_detach(dev, &qp,
1975 err = mlx4_multicast_attach(dev, &qp,
1985 mlx4_warn(dev, "Bad type for required operation\n");
1989 err = mlx4_cmd(dev, 0, ((u32) err |
1990 (__force u32)cpu_to_be32(token) << 16),
1991 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
1994 mlx4_err(dev, "Failed to acknowledge required request: %d\n",
1998 memset(outbox, 0, 0xffc);
1999 num_tasks = atomic_dec_return(&priv->opreq_count);
2003 mlx4_free_cmd_mailbox(dev, mailbox);