2 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/interrupt.h>
35 #include <linux/slab.h>
36 #include <linux/export.h>
38 #include <linux/dma-mapping.h>
40 #include <linux/mlx4/cmd.h>
41 #include <linux/cpu_rmap.h>
47 MLX4_IRQNAME_SIZE = 32
51 MLX4_NUM_ASYNC_EQE = 0x100,
52 MLX4_NUM_SPARE_EQE = 0x80,
53 MLX4_EQ_ENTRY_SIZE = 0x20
56 #define MLX4_EQ_STATUS_OK ( 0 << 28)
57 #define MLX4_EQ_STATUS_WRITE_FAIL (10 << 28)
58 #define MLX4_EQ_OWNER_SW ( 0 << 24)
59 #define MLX4_EQ_OWNER_HW ( 1 << 24)
60 #define MLX4_EQ_FLAG_EC ( 1 << 18)
61 #define MLX4_EQ_FLAG_OI ( 1 << 17)
62 #define MLX4_EQ_STATE_ARMED ( 9 << 8)
63 #define MLX4_EQ_STATE_FIRED (10 << 8)
64 #define MLX4_EQ_STATE_ALWAYS_ARMED (11 << 8)
66 #define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG) | \
67 (1ull << MLX4_EVENT_TYPE_COMM_EST) | \
68 (1ull << MLX4_EVENT_TYPE_SQ_DRAINED) | \
69 (1ull << MLX4_EVENT_TYPE_CQ_ERROR) | \
70 (1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR) | \
71 (1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR) | \
72 (1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED) | \
73 (1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
74 (1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR) | \
75 (1ull << MLX4_EVENT_TYPE_PORT_CHANGE) | \
76 (1ull << MLX4_EVENT_TYPE_ECC_DETECT) | \
77 (1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR) | \
78 (1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE) | \
79 (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) | \
80 (1ull << MLX4_EVENT_TYPE_CMD) | \
81 (1ull << MLX4_EVENT_TYPE_OP_REQUIRED) | \
82 (1ull << MLX4_EVENT_TYPE_COMM_CHANNEL) | \
83 (1ull << MLX4_EVENT_TYPE_FLR_EVENT) | \
84 (1ull << MLX4_EVENT_TYPE_FATAL_WARNING))
86 static u64 get_async_ev_mask(struct mlx4_dev *dev)
88 u64 async_ev_mask = MLX4_ASYNC_EVENT_MASK;
89 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV)
90 async_ev_mask |= (1ull << MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT);
95 static void eq_set_ci(struct mlx4_eq *eq, int req_not)
97 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) |
100 /* We still want ordering, just not swabbing, so add a barrier */
104 static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry, u8 eqe_factor,
107 /* (entry & (eq->nent - 1)) gives us a cyclic array */
108 unsigned long offset = (entry & (eq->nent - 1)) * eqe_size;
109 /* CX3 is capable of extending the EQE from 32 to 64 bytes with
110 * strides of 64B,128B and 256B.
111 * When 64B EQE is used, the first (in the lower addresses)
112 * 32 bytes in the 64 byte EQE are reserved and the next 32 bytes
113 * contain the legacy EQE information.
114 * In all other cases, the first 32B contains the legacy EQE info.
116 return eq->page_list[offset / PAGE_SIZE].buf + (offset + (eqe_factor ? MLX4_EQ_ENTRY_SIZE : 0)) % PAGE_SIZE;
119 static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq, u8 eqe_factor, u8 size)
121 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index, eqe_factor, size);
122 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe;
125 static struct mlx4_eqe *next_slave_event_eqe(struct mlx4_slave_event_eq *slave_eq)
127 struct mlx4_eqe *eqe =
128 &slave_eq->event_eqe[slave_eq->cons & (SLAVE_EVENT_EQ_SIZE - 1)];
129 return (!!(eqe->owner & 0x80) ^
130 !!(slave_eq->cons & SLAVE_EVENT_EQ_SIZE)) ?
134 void mlx4_gen_slave_eqe(struct work_struct *work)
136 struct mlx4_mfunc_master_ctx *master =
137 container_of(work, struct mlx4_mfunc_master_ctx,
139 struct mlx4_mfunc *mfunc =
140 container_of(master, struct mlx4_mfunc, master);
141 struct mlx4_priv *priv = container_of(mfunc, struct mlx4_priv, mfunc);
142 struct mlx4_dev *dev = &priv->dev;
143 struct mlx4_slave_event_eq *slave_eq = &mfunc->master.slave_eq;
144 struct mlx4_eqe *eqe;
148 for (eqe = next_slave_event_eqe(slave_eq); eqe;
149 eqe = next_slave_event_eqe(slave_eq)) {
150 slave = eqe->slave_id;
152 /* All active slaves need to receive the event */
153 if (slave == ALL_SLAVES) {
154 for (i = 0; i < dev->num_slaves; i++) {
155 if (i != dev->caps.function &&
156 master->slave_state[i].active)
157 if (mlx4_GEN_EQE(dev, i, eqe))
158 mlx4_warn(dev, "Failed to generate event for slave %d\n",
162 if (mlx4_GEN_EQE(dev, slave, eqe))
163 mlx4_warn(dev, "Failed to generate event for slave %d\n",
171 static void slave_event(struct mlx4_dev *dev, u8 slave, struct mlx4_eqe *eqe)
173 struct mlx4_priv *priv = mlx4_priv(dev);
174 struct mlx4_slave_event_eq *slave_eq = &priv->mfunc.master.slave_eq;
175 struct mlx4_eqe *s_eqe;
178 spin_lock_irqsave(&slave_eq->event_lock, flags);
179 s_eqe = &slave_eq->event_eqe[slave_eq->prod & (SLAVE_EVENT_EQ_SIZE - 1)];
180 if ((!!(s_eqe->owner & 0x80)) ^
181 (!!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE))) {
182 mlx4_warn(dev, "Master failed to generate an EQE for slave: %d. No free EQE on slave events queue\n",
184 spin_unlock_irqrestore(&slave_eq->event_lock, flags);
188 memcpy(s_eqe, eqe, dev->caps.eqe_size - 1);
189 s_eqe->slave_id = slave;
190 /* ensure all information is written before setting the ownersip bit */
192 s_eqe->owner = !!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE) ? 0x0 : 0x80;
195 queue_work(priv->mfunc.master.comm_wq,
196 &priv->mfunc.master.slave_event_work);
197 spin_unlock_irqrestore(&slave_eq->event_lock, flags);
200 static void mlx4_slave_event(struct mlx4_dev *dev, int slave,
201 struct mlx4_eqe *eqe)
203 struct mlx4_priv *priv = mlx4_priv(dev);
204 struct mlx4_slave_state *s_slave =
205 &priv->mfunc.master.slave_state[slave];
207 if (!s_slave->active) {
208 /*mlx4_warn(dev, "Trying to pass event to inactive slave\n");*/
212 slave_event(dev, slave, eqe);
215 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port)
219 struct mlx4_priv *priv = mlx4_priv(dev);
220 struct mlx4_slave_state *s_slave = &priv->mfunc.master.slave_state[slave];
222 if (!s_slave->active)
225 memset(&eqe, 0, sizeof eqe);
227 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
228 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE;
229 eqe.event.port_mgmt_change.port = port;
231 return mlx4_GEN_EQE(dev, slave, &eqe);
233 EXPORT_SYMBOL(mlx4_gen_pkey_eqe);
235 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port)
239 /*don't send if we don't have the that slave */
240 if (dev->num_vfs < slave)
242 memset(&eqe, 0, sizeof eqe);
244 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
245 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_GUID_INFO;
246 eqe.event.port_mgmt_change.port = port;
248 return mlx4_GEN_EQE(dev, slave, &eqe);
250 EXPORT_SYMBOL(mlx4_gen_guid_change_eqe);
252 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port,
253 u8 port_subtype_change)
257 /*don't send if we don't have the that slave */
258 if (dev->num_vfs < slave)
260 memset(&eqe, 0, sizeof eqe);
262 eqe.type = MLX4_EVENT_TYPE_PORT_CHANGE;
263 eqe.subtype = port_subtype_change;
264 eqe.event.port_change.port = cpu_to_be32(port << 28);
266 mlx4_dbg(dev, "%s: sending: %d to slave: %d on port: %d\n", __func__,
267 port_subtype_change, slave, port);
268 return mlx4_GEN_EQE(dev, slave, &eqe);
270 EXPORT_SYMBOL(mlx4_gen_port_state_change_eqe);
272 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port)
274 struct mlx4_priv *priv = mlx4_priv(dev);
275 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state;
276 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
278 if (slave >= dev->num_slaves || port > dev->caps.num_ports ||
279 port <= 0 || !test_bit(port - 1, actv_ports.ports)) {
280 pr_err("%s: Error: asking for slave:%d, port:%d\n",
281 __func__, slave, port);
282 return SLAVE_PORT_DOWN;
284 return s_state[slave].port_state[port];
286 EXPORT_SYMBOL(mlx4_get_slave_port_state);
288 static int mlx4_set_slave_port_state(struct mlx4_dev *dev, int slave, u8 port,
289 enum slave_port_state state)
291 struct mlx4_priv *priv = mlx4_priv(dev);
292 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state;
293 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
295 if (slave >= dev->num_slaves || port > dev->caps.num_ports ||
296 port <= 0 || !test_bit(port - 1, actv_ports.ports)) {
297 pr_err("%s: Error: asking for slave:%d, port:%d\n",
298 __func__, slave, port);
301 s_state[slave].port_state[port] = state;
306 static void set_all_slave_state(struct mlx4_dev *dev, u8 port, int event)
309 enum slave_port_gen_event gen_event;
310 struct mlx4_slaves_pport slaves_pport = mlx4_phys_to_slaves_pport(dev,
313 for (i = 0; i < dev->num_vfs + 1; i++)
314 if (test_bit(i, slaves_pport.slaves))
315 set_and_calc_slave_port_state(dev, i, port,
318 /**************************************************************************
319 The function get as input the new event to that port,
320 and according to the prev state change the slave's port state.
322 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
323 MLX4_PORT_STATE_DEV_EVENT_PORT_UP
324 MLX4_PORT_STATE_IB_EVENT_GID_VALID
325 MLX4_PORT_STATE_IB_EVENT_GID_INVALID
326 ***************************************************************************/
327 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave,
329 enum slave_port_gen_event *gen_event)
331 struct mlx4_priv *priv = mlx4_priv(dev);
332 struct mlx4_slave_state *ctx = NULL;
335 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
336 enum slave_port_state cur_state =
337 mlx4_get_slave_port_state(dev, slave, port);
339 *gen_event = SLAVE_PORT_GEN_EVENT_NONE;
341 if (slave >= dev->num_slaves || port > dev->caps.num_ports ||
342 port <= 0 || !test_bit(port - 1, actv_ports.ports)) {
343 pr_err("%s: Error: asking for slave:%d, port:%d\n",
344 __func__, slave, port);
348 ctx = &priv->mfunc.master.slave_state[slave];
349 spin_lock_irqsave(&ctx->lock, flags);
352 case SLAVE_PORT_DOWN:
353 if (MLX4_PORT_STATE_DEV_EVENT_PORT_UP == event)
354 mlx4_set_slave_port_state(dev, slave, port,
357 case SLAVE_PENDING_UP:
358 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event)
359 mlx4_set_slave_port_state(dev, slave, port,
361 else if (MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID == event) {
362 mlx4_set_slave_port_state(dev, slave, port,
364 *gen_event = SLAVE_PORT_GEN_EVENT_UP;
368 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event) {
369 mlx4_set_slave_port_state(dev, slave, port,
371 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN;
372 } else if (MLX4_PORT_STATE_IB_EVENT_GID_INVALID ==
374 mlx4_set_slave_port_state(dev, slave, port,
376 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN;
380 pr_err("%s: BUG!!! UNKNOWN state: slave:%d, port:%d\n",
381 __func__, slave, port);
384 ret = mlx4_get_slave_port_state(dev, slave, port);
387 spin_unlock_irqrestore(&ctx->lock, flags);
391 EXPORT_SYMBOL(set_and_calc_slave_port_state);
393 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr)
397 memset(&eqe, 0, sizeof eqe);
399 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
400 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PORT_INFO;
401 eqe.event.port_mgmt_change.port = port;
402 eqe.event.port_mgmt_change.params.port_info.changed_attr =
403 cpu_to_be32((u32) attr);
405 slave_event(dev, ALL_SLAVES, &eqe);
408 EXPORT_SYMBOL(mlx4_gen_slaves_port_mgt_ev);
410 void mlx4_master_handle_slave_flr(struct work_struct *work)
412 struct mlx4_mfunc_master_ctx *master =
413 container_of(work, struct mlx4_mfunc_master_ctx,
414 slave_flr_event_work);
415 struct mlx4_mfunc *mfunc =
416 container_of(master, struct mlx4_mfunc, master);
417 struct mlx4_priv *priv =
418 container_of(mfunc, struct mlx4_priv, mfunc);
419 struct mlx4_dev *dev = &priv->dev;
420 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
425 mlx4_dbg(dev, "mlx4_handle_slave_flr\n");
427 for (i = 0 ; i < dev->num_slaves; i++) {
429 if (MLX4_COMM_CMD_FLR == slave_state[i].last_cmd) {
430 mlx4_dbg(dev, "mlx4_handle_slave_flr: clean slave: %d\n",
433 mlx4_delete_all_resources_for_slave(dev, i);
434 /*return the slave to running mode*/
435 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
436 slave_state[i].last_cmd = MLX4_COMM_CMD_RESET;
437 slave_state[i].is_slave_going_down = 0;
438 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
440 err = mlx4_cmd(dev, 0, i, 0, MLX4_CMD_INFORM_FLR_DONE,
441 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
443 mlx4_warn(dev, "Failed to notify FW on FLR done (slave:%d)\n",
449 static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq)
451 struct mlx4_priv *priv = mlx4_priv(dev);
452 struct mlx4_eqe *eqe;
460 u8 update_slave_state;
462 enum slave_port_gen_event gen_event;
464 struct mlx4_vport_state *s_info;
465 int eqe_size = dev->caps.eqe_size;
467 while ((eqe = next_eqe_sw(eq, dev->caps.eqe_factor, eqe_size))) {
469 * Make sure we read EQ entry contents after we've
470 * checked the ownership bit.
475 case MLX4_EVENT_TYPE_COMP:
476 cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff;
477 mlx4_cq_completion(dev, cqn);
480 case MLX4_EVENT_TYPE_PATH_MIG:
481 case MLX4_EVENT_TYPE_COMM_EST:
482 case MLX4_EVENT_TYPE_SQ_DRAINED:
483 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
484 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
485 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
486 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
487 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
488 mlx4_dbg(dev, "event %d arrived\n", eqe->type);
489 if (mlx4_is_master(dev)) {
490 /* forward only to slave owning the QP */
491 ret = mlx4_get_slave_from_resource_id(dev,
493 be32_to_cpu(eqe->event.qp.qpn)
495 if (ret && ret != -ENOENT) {
496 mlx4_dbg(dev, "QP event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n",
497 eqe->type, eqe->subtype,
498 eq->eqn, eq->cons_index, ret);
502 if (!ret && slave != dev->caps.function) {
503 mlx4_slave_event(dev, slave, eqe);
508 mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) &
509 0xffffff, eqe->type);
512 case MLX4_EVENT_TYPE_SRQ_LIMIT:
513 mlx4_dbg(dev, "%s: MLX4_EVENT_TYPE_SRQ_LIMIT\n",
515 case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR:
516 if (mlx4_is_master(dev)) {
517 /* forward only to slave owning the SRQ */
518 ret = mlx4_get_slave_from_resource_id(dev,
520 be32_to_cpu(eqe->event.srq.srqn)
523 if (ret && ret != -ENOENT) {
524 mlx4_warn(dev, "SRQ event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n",
525 eqe->type, eqe->subtype,
526 eq->eqn, eq->cons_index, ret);
529 mlx4_warn(dev, "%s: slave:%d, srq_no:0x%x, event: %02x(%02x)\n",
531 be32_to_cpu(eqe->event.srq.srqn),
532 eqe->type, eqe->subtype);
534 if (!ret && slave != dev->caps.function) {
535 mlx4_warn(dev, "%s: sending event %02x(%02x) to slave:%d\n",
537 eqe->subtype, slave);
538 mlx4_slave_event(dev, slave, eqe);
542 mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) &
543 0xffffff, eqe->type);
546 case MLX4_EVENT_TYPE_CMD:
548 be16_to_cpu(eqe->event.cmd.token),
549 eqe->event.cmd.status,
550 be64_to_cpu(eqe->event.cmd.out_param));
553 case MLX4_EVENT_TYPE_PORT_CHANGE: {
554 struct mlx4_slaves_pport slaves_port;
555 port = be32_to_cpu(eqe->event.port_change.port) >> 28;
556 slaves_port = mlx4_phys_to_slaves_pport(dev, port);
557 if (eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN) {
558 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_DOWN,
560 mlx4_priv(dev)->sense.do_sense_port[port] = 1;
561 if (!mlx4_is_master(dev))
563 for (i = 0; i < dev->num_vfs + 1; i++) {
564 if (!test_bit(i, slaves_port.slaves))
566 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) {
567 if (i == mlx4_master_func_num(dev))
569 mlx4_dbg(dev, "%s: Sending MLX4_PORT_CHANGE_SUBTYPE_DOWN to slave: %d, port:%d\n",
571 s_info = &priv->mfunc.master.vf_oper[slave].vport[port].state;
572 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) {
573 eqe->event.port_change.port =
575 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF)
576 | (mlx4_phys_to_slave_port(dev, i, port) << 28));
577 mlx4_slave_event(dev, i, eqe);
579 } else { /* IB port */
580 set_and_calc_slave_port_state(dev, i, port,
581 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
583 /*we can be in pending state, then do not send port_down event*/
584 if (SLAVE_PORT_GEN_EVENT_DOWN == gen_event) {
585 if (i == mlx4_master_func_num(dev))
587 mlx4_slave_event(dev, i, eqe);
592 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_UP, port);
594 mlx4_priv(dev)->sense.do_sense_port[port] = 0;
596 if (!mlx4_is_master(dev))
598 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
599 for (i = 0; i < dev->num_vfs + 1; i++) {
600 if (!test_bit(i, slaves_port.slaves))
602 if (i == mlx4_master_func_num(dev))
604 s_info = &priv->mfunc.master.vf_oper[slave].vport[port].state;
605 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) {
606 eqe->event.port_change.port =
608 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF)
609 | (mlx4_phys_to_slave_port(dev, i, port) << 28));
610 mlx4_slave_event(dev, i, eqe);
614 /* port-up event will be sent to a slave when the
615 * slave's alias-guid is set. This is done in alias_GUID.c
617 set_all_slave_state(dev, port, MLX4_DEV_EVENT_PORT_UP);
622 case MLX4_EVENT_TYPE_CQ_ERROR:
623 mlx4_warn(dev, "CQ %s on CQN %06x\n",
624 eqe->event.cq_err.syndrome == 1 ?
625 "overrun" : "access violation",
626 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff);
627 if (mlx4_is_master(dev)) {
628 ret = mlx4_get_slave_from_resource_id(dev,
630 be32_to_cpu(eqe->event.cq_err.cqn)
632 if (ret && ret != -ENOENT) {
633 mlx4_dbg(dev, "CQ event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n",
634 eqe->type, eqe->subtype,
635 eq->eqn, eq->cons_index, ret);
639 if (!ret && slave != dev->caps.function) {
640 mlx4_slave_event(dev, slave, eqe);
645 be32_to_cpu(eqe->event.cq_err.cqn)
650 case MLX4_EVENT_TYPE_EQ_OVERFLOW:
651 mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn);
654 case MLX4_EVENT_TYPE_OP_REQUIRED:
655 atomic_inc(&priv->opreq_count);
656 /* FW commands can't be executed from interrupt context
657 * working in deferred task
659 queue_work(mlx4_wq, &priv->opreq_task);
662 case MLX4_EVENT_TYPE_COMM_CHANNEL:
663 if (!mlx4_is_master(dev)) {
664 mlx4_warn(dev, "Received comm channel event for non master device\n");
667 memcpy(&priv->mfunc.master.comm_arm_bit_vector,
668 eqe->event.comm_channel_arm.bit_vec,
669 sizeof eqe->event.comm_channel_arm.bit_vec);
670 queue_work(priv->mfunc.master.comm_wq,
671 &priv->mfunc.master.comm_work);
674 case MLX4_EVENT_TYPE_FLR_EVENT:
675 flr_slave = be32_to_cpu(eqe->event.flr_event.slave_id);
676 if (!mlx4_is_master(dev)) {
677 mlx4_warn(dev, "Non-master function received FLR event\n");
681 mlx4_dbg(dev, "FLR event for slave: %d\n", flr_slave);
683 if (flr_slave >= dev->num_slaves) {
685 "Got FLR for unknown function: %d\n",
687 update_slave_state = 0;
689 update_slave_state = 1;
691 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
692 if (update_slave_state) {
693 priv->mfunc.master.slave_state[flr_slave].active = false;
694 priv->mfunc.master.slave_state[flr_slave].last_cmd = MLX4_COMM_CMD_FLR;
695 priv->mfunc.master.slave_state[flr_slave].is_slave_going_down = 1;
697 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
698 queue_work(priv->mfunc.master.comm_wq,
699 &priv->mfunc.master.slave_flr_event_work);
702 case MLX4_EVENT_TYPE_FATAL_WARNING:
703 if (eqe->subtype == MLX4_FATAL_WARNING_SUBTYPE_WARMING) {
704 if (mlx4_is_master(dev))
705 for (i = 0; i < dev->num_slaves; i++) {
706 mlx4_dbg(dev, "%s: Sending MLX4_FATAL_WARNING_SUBTYPE_WARMING to slave: %d\n",
708 if (i == dev->caps.function)
710 mlx4_slave_event(dev, i, eqe);
712 mlx4_err(dev, "Temperature Threshold was reached! Threshold: %d celsius degrees; Current Temperature: %d\n",
713 be16_to_cpu(eqe->event.warming.warning_threshold),
714 be16_to_cpu(eqe->event.warming.current_temperature));
716 mlx4_warn(dev, "Unhandled event FATAL WARNING (%02x), subtype %02x on EQ %d at index %u. owner=%x, nent=0x%x, slave=%x, ownership=%s\n",
717 eqe->type, eqe->subtype, eq->eqn,
718 eq->cons_index, eqe->owner, eq->nent,
720 !!(eqe->owner & 0x80) ^
721 !!(eq->cons_index & eq->nent) ? "HW" : "SW");
725 case MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT:
726 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_MGMT_CHANGE,
727 (unsigned long) eqe);
730 case MLX4_EVENT_TYPE_EEC_CATAS_ERROR:
731 case MLX4_EVENT_TYPE_ECC_DETECT:
733 mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at index %u. owner=%x, nent=0x%x, slave=%x, ownership=%s\n",
734 eqe->type, eqe->subtype, eq->eqn,
735 eq->cons_index, eqe->owner, eq->nent,
737 !!(eqe->owner & 0x80) ^
738 !!(eq->cons_index & eq->nent) ? "HW" : "SW");
747 * The HCA will think the queue has overflowed if we
748 * don't tell it we've been processing events. We
749 * create our EQs with MLX4_NUM_SPARE_EQE extra
750 * entries, so we must update our consumer index at
753 if (unlikely(set_ci >= MLX4_NUM_SPARE_EQE)) {
764 static irqreturn_t mlx4_interrupt(int irq, void *dev_ptr)
766 struct mlx4_dev *dev = dev_ptr;
767 struct mlx4_priv *priv = mlx4_priv(dev);
771 writel(priv->eq_table.clr_mask, priv->eq_table.clr_int);
773 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
774 work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]);
776 return IRQ_RETVAL(work);
779 static irqreturn_t mlx4_msi_x_interrupt(int irq, void *eq_ptr)
781 struct mlx4_eq *eq = eq_ptr;
782 struct mlx4_dev *dev = eq->dev;
784 mlx4_eq_int(dev, eq);
786 /* MSI-X vectors always belong to us */
790 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
791 struct mlx4_vhcr *vhcr,
792 struct mlx4_cmd_mailbox *inbox,
793 struct mlx4_cmd_mailbox *outbox,
794 struct mlx4_cmd_info *cmd)
796 struct mlx4_priv *priv = mlx4_priv(dev);
797 struct mlx4_slave_event_eq_info *event_eq =
798 priv->mfunc.master.slave_state[slave].event_eq;
799 u32 in_modifier = vhcr->in_modifier;
800 u32 eqn = in_modifier & 0x3FF;
801 u64 in_param = vhcr->in_param;
805 if (slave == dev->caps.function)
806 err = mlx4_cmd(dev, in_param, (in_modifier & 0x80000000) | eqn,
807 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B,
810 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i)
811 if (in_param & (1LL << i))
812 event_eq[i].eqn = in_modifier >> 31 ? -1 : eqn;
817 static int mlx4_MAP_EQ(struct mlx4_dev *dev, u64 event_mask, int unmap,
820 return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num,
821 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B,
825 static int mlx4_SW2HW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
828 return mlx4_cmd(dev, mailbox->dma, eq_num, 0,
829 MLX4_CMD_SW2HW_EQ, MLX4_CMD_TIME_CLASS_A,
833 static int mlx4_HW2SW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
836 return mlx4_cmd_box(dev, 0, mailbox->dma, eq_num,
837 0, MLX4_CMD_HW2SW_EQ, MLX4_CMD_TIME_CLASS_A,
841 static int mlx4_num_eq_uar(struct mlx4_dev *dev)
844 * Each UAR holds 4 EQ doorbells. To figure out how many UARs
845 * we need to map, take the difference of highest index and
846 * the lowest index we'll use and add 1.
848 return (dev->caps.num_comp_vectors + 1 + dev->caps.reserved_eqs +
849 dev->caps.comp_pool)/4 - dev->caps.reserved_eqs/4 + 1;
852 static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq)
854 struct mlx4_priv *priv = mlx4_priv(dev);
857 index = eq->eqn / 4 - dev->caps.reserved_eqs / 4;
859 if (!priv->eq_table.uar_map[index]) {
860 priv->eq_table.uar_map[index] =
861 ioremap(pci_resource_start(dev->pdev, 2) +
862 ((eq->eqn / 4) << PAGE_SHIFT),
864 if (!priv->eq_table.uar_map[index]) {
865 mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n",
871 return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4);
874 static void mlx4_unmap_uar(struct mlx4_dev *dev)
876 struct mlx4_priv *priv = mlx4_priv(dev);
879 for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
880 if (priv->eq_table.uar_map[i]) {
881 iounmap(priv->eq_table.uar_map[i]);
882 priv->eq_table.uar_map[i] = NULL;
886 static int mlx4_create_eq(struct mlx4_dev *dev, int nent,
887 u8 intr, struct mlx4_eq *eq)
889 struct mlx4_priv *priv = mlx4_priv(dev);
890 struct mlx4_cmd_mailbox *mailbox;
891 struct mlx4_eq_context *eq_context;
893 u64 *dma_list = NULL;
900 eq->nent = roundup_pow_of_two(max(nent, 2));
901 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes, with
902 * strides of 64B,128B and 256B.
904 npages = PAGE_ALIGN(eq->nent * dev->caps.eqe_size) / PAGE_SIZE;
906 eq->page_list = kmalloc(npages * sizeof *eq->page_list,
911 for (i = 0; i < npages; ++i)
912 eq->page_list[i].buf = NULL;
914 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
918 mailbox = mlx4_alloc_cmd_mailbox(dev);
921 eq_context = mailbox->buf;
923 for (i = 0; i < npages; ++i) {
924 eq->page_list[i].buf = dma_alloc_coherent(&dev->pdev->dev,
925 PAGE_SIZE, &t, GFP_KERNEL);
926 if (!eq->page_list[i].buf)
927 goto err_out_free_pages;
930 eq->page_list[i].map = t;
932 memset(eq->page_list[i].buf, 0, PAGE_SIZE);
935 eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap);
937 goto err_out_free_pages;
939 eq->doorbell = mlx4_get_eq_uar(dev, eq);
942 goto err_out_free_eq;
945 err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt);
947 goto err_out_free_eq;
949 err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list);
951 goto err_out_free_mtt;
953 eq_context->flags = cpu_to_be32(MLX4_EQ_STATUS_OK |
954 MLX4_EQ_STATE_ARMED);
955 eq_context->log_eq_size = ilog2(eq->nent);
956 eq_context->intr = intr;
957 eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT;
959 mtt_addr = mlx4_mtt_addr(dev, &eq->mtt);
960 eq_context->mtt_base_addr_h = mtt_addr >> 32;
961 eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
963 err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn);
965 mlx4_warn(dev, "SW2HW_EQ failed (%d)\n", err);
966 goto err_out_free_mtt;
970 mlx4_free_cmd_mailbox(dev, mailbox);
977 mlx4_mtt_cleanup(dev, &eq->mtt);
980 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR);
983 for (i = 0; i < npages; ++i)
984 if (eq->page_list[i].buf)
985 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
986 eq->page_list[i].buf,
987 eq->page_list[i].map);
989 mlx4_free_cmd_mailbox(dev, mailbox);
992 kfree(eq->page_list);
999 static void mlx4_free_eq(struct mlx4_dev *dev,
1002 struct mlx4_priv *priv = mlx4_priv(dev);
1003 struct mlx4_cmd_mailbox *mailbox;
1006 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes, with
1007 * strides of 64B,128B and 256B
1009 int npages = PAGE_ALIGN(dev->caps.eqe_size * eq->nent) / PAGE_SIZE;
1011 mailbox = mlx4_alloc_cmd_mailbox(dev);
1012 if (IS_ERR(mailbox))
1015 err = mlx4_HW2SW_EQ(dev, mailbox, eq->eqn);
1017 mlx4_warn(dev, "HW2SW_EQ failed (%d)\n", err);
1020 mlx4_dbg(dev, "Dumping EQ context %02x:\n", eq->eqn);
1021 for (i = 0; i < sizeof (struct mlx4_eq_context) / 4; ++i) {
1023 pr_cont("[%02x] ", i * 4);
1024 pr_cont(" %08x", be32_to_cpup(mailbox->buf + i * 4));
1025 if ((i + 1) % 4 == 0)
1029 synchronize_irq(eq->irq);
1031 mlx4_mtt_cleanup(dev, &eq->mtt);
1032 for (i = 0; i < npages; ++i)
1033 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
1034 eq->page_list[i].buf,
1035 eq->page_list[i].map);
1037 kfree(eq->page_list);
1038 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR);
1039 mlx4_free_cmd_mailbox(dev, mailbox);
1042 static void mlx4_free_irqs(struct mlx4_dev *dev)
1044 struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table;
1045 struct mlx4_priv *priv = mlx4_priv(dev);
1048 if (eq_table->have_irq)
1049 free_irq(dev->pdev->irq, dev);
1051 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
1052 if (eq_table->eq[i].have_irq) {
1053 free_irq(eq_table->eq[i].irq, eq_table->eq + i);
1054 eq_table->eq[i].have_irq = 0;
1057 for (i = 0; i < dev->caps.comp_pool; i++) {
1059 * Freeing the assigned irq's
1060 * all bits should be 0, but we need to validate
1062 if (priv->msix_ctl.pool_bm & 1ULL << i) {
1063 /* NO need protecting*/
1064 vec = dev->caps.num_comp_vectors + 1 + i;
1065 free_irq(priv->eq_table.eq[vec].irq,
1066 &priv->eq_table.eq[vec]);
1071 kfree(eq_table->irq_names);
1074 static int mlx4_map_clr_int(struct mlx4_dev *dev)
1076 struct mlx4_priv *priv = mlx4_priv(dev);
1078 priv->clr_base = ioremap(pci_resource_start(dev->pdev, priv->fw.clr_int_bar) +
1079 priv->fw.clr_int_base, MLX4_CLR_INT_SIZE);
1080 if (!priv->clr_base) {
1081 mlx4_err(dev, "Couldn't map interrupt clear register, aborting\n");
1088 static void mlx4_unmap_clr_int(struct mlx4_dev *dev)
1090 struct mlx4_priv *priv = mlx4_priv(dev);
1092 iounmap(priv->clr_base);
1095 int mlx4_alloc_eq_table(struct mlx4_dev *dev)
1097 struct mlx4_priv *priv = mlx4_priv(dev);
1099 priv->eq_table.eq = kcalloc(dev->caps.num_eqs - dev->caps.reserved_eqs,
1100 sizeof *priv->eq_table.eq, GFP_KERNEL);
1101 if (!priv->eq_table.eq)
1107 void mlx4_free_eq_table(struct mlx4_dev *dev)
1109 kfree(mlx4_priv(dev)->eq_table.eq);
1112 int mlx4_init_eq_table(struct mlx4_dev *dev)
1114 struct mlx4_priv *priv = mlx4_priv(dev);
1118 priv->eq_table.uar_map = kcalloc(mlx4_num_eq_uar(dev),
1119 sizeof *priv->eq_table.uar_map,
1121 if (!priv->eq_table.uar_map) {
1126 err = mlx4_bitmap_init(&priv->eq_table.bitmap,
1127 roundup_pow_of_two(dev->caps.num_eqs),
1128 dev->caps.num_eqs - 1,
1129 dev->caps.reserved_eqs,
1130 roundup_pow_of_two(dev->caps.num_eqs) -
1135 for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
1136 priv->eq_table.uar_map[i] = NULL;
1138 if (!mlx4_is_slave(dev)) {
1139 err = mlx4_map_clr_int(dev);
1141 goto err_out_bitmap;
1143 priv->eq_table.clr_mask =
1144 swab32(1 << (priv->eq_table.inta_pin & 31));
1145 priv->eq_table.clr_int = priv->clr_base +
1146 (priv->eq_table.inta_pin < 32 ? 4 : 0);
1149 priv->eq_table.irq_names =
1150 kmalloc(MLX4_IRQNAME_SIZE * (dev->caps.num_comp_vectors + 1 +
1151 dev->caps.comp_pool),
1153 if (!priv->eq_table.irq_names) {
1155 goto err_out_bitmap;
1158 for (i = 0; i < dev->caps.num_comp_vectors; ++i) {
1159 err = mlx4_create_eq(dev, dev->caps.num_cqs -
1160 dev->caps.reserved_cqs +
1162 (dev->flags & MLX4_FLAG_MSI_X) ? i : 0,
1163 &priv->eq_table.eq[i]);
1170 err = mlx4_create_eq(dev, MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE,
1171 (dev->flags & MLX4_FLAG_MSI_X) ? dev->caps.num_comp_vectors : 0,
1172 &priv->eq_table.eq[dev->caps.num_comp_vectors]);
1176 /*if additional completion vectors poolsize is 0 this loop will not run*/
1177 for (i = dev->caps.num_comp_vectors + 1;
1178 i < dev->caps.num_comp_vectors + dev->caps.comp_pool + 1; ++i) {
1180 err = mlx4_create_eq(dev, dev->caps.num_cqs -
1181 dev->caps.reserved_cqs +
1183 (dev->flags & MLX4_FLAG_MSI_X) ? i : 0,
1184 &priv->eq_table.eq[i]);
1192 if (dev->flags & MLX4_FLAG_MSI_X) {
1193 const char *eq_name;
1195 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) {
1196 if (i < dev->caps.num_comp_vectors) {
1197 snprintf(priv->eq_table.irq_names +
1198 i * MLX4_IRQNAME_SIZE,
1200 "mlx4-comp-%d@pci:%s", i,
1201 pci_name(dev->pdev));
1203 snprintf(priv->eq_table.irq_names +
1204 i * MLX4_IRQNAME_SIZE,
1206 "mlx4-async@pci:%s",
1207 pci_name(dev->pdev));
1210 eq_name = priv->eq_table.irq_names +
1211 i * MLX4_IRQNAME_SIZE;
1212 err = request_irq(priv->eq_table.eq[i].irq,
1213 mlx4_msi_x_interrupt, 0, eq_name,
1214 priv->eq_table.eq + i);
1218 priv->eq_table.eq[i].have_irq = 1;
1221 snprintf(priv->eq_table.irq_names,
1224 pci_name(dev->pdev));
1225 err = request_irq(dev->pdev->irq, mlx4_interrupt,
1226 IRQF_SHARED, priv->eq_table.irq_names, dev);
1230 priv->eq_table.have_irq = 1;
1233 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1234 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
1236 mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n",
1237 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn, err);
1239 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
1240 eq_set_ci(&priv->eq_table.eq[i], 1);
1245 mlx4_free_eq(dev, &priv->eq_table.eq[dev->caps.num_comp_vectors]);
1248 i = dev->caps.num_comp_vectors - 1;
1252 mlx4_free_eq(dev, &priv->eq_table.eq[i]);
1255 if (!mlx4_is_slave(dev))
1256 mlx4_unmap_clr_int(dev);
1257 mlx4_free_irqs(dev);
1260 mlx4_unmap_uar(dev);
1261 mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
1264 kfree(priv->eq_table.uar_map);
1269 void mlx4_cleanup_eq_table(struct mlx4_dev *dev)
1271 struct mlx4_priv *priv = mlx4_priv(dev);
1274 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 1,
1275 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
1277 mlx4_free_irqs(dev);
1279 for (i = 0; i < dev->caps.num_comp_vectors + dev->caps.comp_pool + 1; ++i)
1280 mlx4_free_eq(dev, &priv->eq_table.eq[i]);
1282 if (!mlx4_is_slave(dev))
1283 mlx4_unmap_clr_int(dev);
1285 mlx4_unmap_uar(dev);
1286 mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
1288 kfree(priv->eq_table.uar_map);
1291 /* A test that verifies that we can accept interrupts on all
1292 * the irq vectors of the device.
1293 * Interrupts are checked using the NOP command.
1295 int mlx4_test_interrupts(struct mlx4_dev *dev)
1297 struct mlx4_priv *priv = mlx4_priv(dev);
1301 err = mlx4_NOP(dev);
1302 /* When not in MSI_X, there is only one irq to check */
1303 if (!(dev->flags & MLX4_FLAG_MSI_X) || mlx4_is_slave(dev))
1306 /* A loop over all completion vectors, for each vector we will check
1307 * whether it works by mapping command completions to that vector
1308 * and performing a NOP command
1310 for(i = 0; !err && (i < dev->caps.num_comp_vectors); ++i) {
1311 /* Temporary use polling for command completions */
1312 mlx4_cmd_use_polling(dev);
1314 /* Map the new eq to handle all asynchronous events */
1315 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1316 priv->eq_table.eq[i].eqn);
1318 mlx4_warn(dev, "Failed mapping eq for interrupt test\n");
1319 mlx4_cmd_use_events(dev);
1323 /* Go back to using events */
1324 mlx4_cmd_use_events(dev);
1325 err = mlx4_NOP(dev);
1328 /* Return to default */
1329 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1330 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
1333 EXPORT_SYMBOL(mlx4_test_interrupts);
1335 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
1339 struct mlx4_priv *priv = mlx4_priv(dev);
1340 int vec = 0, err = 0, i;
1342 mutex_lock(&priv->msix_ctl.pool_lock);
1343 for (i = 0; !vec && i < dev->caps.comp_pool; i++) {
1344 if (~priv->msix_ctl.pool_bm & 1ULL << i) {
1345 priv->msix_ctl.pool_bm |= 1ULL << i;
1346 vec = dev->caps.num_comp_vectors + 1 + i;
1347 snprintf(priv->eq_table.irq_names +
1348 vec * MLX4_IRQNAME_SIZE,
1349 MLX4_IRQNAME_SIZE, "%s", name);
1350 #ifdef CONFIG_RFS_ACCEL
1352 err = irq_cpu_rmap_add(rmap,
1353 priv->eq_table.eq[vec].irq);
1355 mlx4_warn(dev, "Failed adding irq rmap\n");
1358 err = request_irq(priv->eq_table.eq[vec].irq,
1359 mlx4_msi_x_interrupt, 0,
1360 &priv->eq_table.irq_names[vec<<5],
1361 priv->eq_table.eq + vec);
1363 /*zero out bit by fliping it*/
1364 priv->msix_ctl.pool_bm ^= 1 << i;
1367 /*we dont want to break here*/
1370 eq_set_ci(&priv->eq_table.eq[vec], 1);
1373 mutex_unlock(&priv->msix_ctl.pool_lock);
1379 err = (i == dev->caps.comp_pool) ? -ENOSPC : err;
1383 EXPORT_SYMBOL(mlx4_assign_eq);
1385 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec)
1387 struct mlx4_priv *priv = mlx4_priv(dev);
1389 return priv->eq_table.eq[vec].irq;
1391 EXPORT_SYMBOL(mlx4_eq_get_irq);
1393 void mlx4_release_eq(struct mlx4_dev *dev, int vec)
1395 struct mlx4_priv *priv = mlx4_priv(dev);
1397 int i = vec - dev->caps.num_comp_vectors - 1;
1399 if (likely(i >= 0)) {
1400 /*sanity check , making sure were not trying to free irq's
1401 Belonging to a legacy EQ*/
1402 mutex_lock(&priv->msix_ctl.pool_lock);
1403 if (priv->msix_ctl.pool_bm & 1ULL << i) {
1404 free_irq(priv->eq_table.eq[vec].irq,
1405 &priv->eq_table.eq[vec]);
1406 priv->msix_ctl.pool_bm &= ~(1ULL << i);
1408 mutex_unlock(&priv->msix_ctl.pool_lock);
1412 EXPORT_SYMBOL(mlx4_release_eq);