2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/mlx4/cq.h>
36 #include <linux/slab.h>
37 #include <linux/mlx4/qp.h>
38 #include <linux/skbuff.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/vmalloc.h>
42 #include <linux/tcp.h>
44 #include <linux/moduleparam.h>
48 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
49 struct mlx4_en_tx_ring **pring, u32 size,
50 u16 stride, int node, int queue_index)
52 struct mlx4_en_dev *mdev = priv->mdev;
53 struct mlx4_en_tx_ring *ring;
57 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
59 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
61 en_err(priv, "Failed allocating TX ring\n");
67 ring->size_mask = size - 1;
68 ring->stride = stride;
70 tmp = size * sizeof(struct mlx4_en_tx_info);
71 ring->tx_info = kmalloc_node(tmp, GFP_KERNEL | __GFP_NOWARN, node);
73 ring->tx_info = vmalloc(tmp);
80 en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n",
83 ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node);
84 if (!ring->bounce_buf) {
85 ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL);
86 if (!ring->bounce_buf) {
91 ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE);
93 /* Allocate HW buffers on provided NUMA node */
94 set_dev_node(&mdev->dev->persist->pdev->dev, node);
95 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size,
97 set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);
99 en_err(priv, "Failed allocating hwq resources\n");
103 err = mlx4_en_map_buffer(&ring->wqres.buf);
105 en_err(priv, "Failed to map TX buffer\n");
109 ring->buf = ring->wqres.buf.direct.buf;
111 en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n",
112 ring, ring->buf, ring->size, ring->buf_size,
113 (unsigned long long) ring->wqres.buf.direct.map);
115 err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn,
116 MLX4_RESERVE_ETH_BF_QP);
118 en_err(priv, "failed reserving qp for TX ring\n");
122 err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp, GFP_KERNEL);
124 en_err(priv, "Failed allocating qp %d\n", ring->qpn);
127 ring->qp.event = mlx4_en_sqp_event;
129 err = mlx4_bf_alloc(mdev->dev, &ring->bf, node);
131 en_dbg(DRV, priv, "working without blueflame (%d)\n", err);
132 ring->bf.uar = &mdev->priv_uar;
133 ring->bf.uar->map = mdev->uar_map;
134 ring->bf_enabled = false;
135 ring->bf_alloced = false;
136 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME;
138 ring->bf_alloced = true;
139 ring->bf_enabled = !!(priv->pflags &
140 MLX4_EN_PRIV_FLAGS_BLUEFLAME);
143 ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type;
144 ring->queue_index = queue_index;
146 if (queue_index < priv->num_tx_rings_p_up)
147 cpumask_set_cpu_local_first(queue_index,
148 priv->mdev->dev->numa_node,
149 &ring->affinity_mask);
155 mlx4_qp_release_range(mdev->dev, ring->qpn, 1);
157 mlx4_en_unmap_buffer(&ring->wqres.buf);
159 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
161 kfree(ring->bounce_buf);
162 ring->bounce_buf = NULL;
164 kvfree(ring->tx_info);
165 ring->tx_info = NULL;
172 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
173 struct mlx4_en_tx_ring **pring)
175 struct mlx4_en_dev *mdev = priv->mdev;
176 struct mlx4_en_tx_ring *ring = *pring;
177 en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn);
179 if (ring->bf_alloced)
180 mlx4_bf_free(mdev->dev, &ring->bf);
181 mlx4_qp_remove(mdev->dev, &ring->qp);
182 mlx4_qp_free(mdev->dev, &ring->qp);
183 mlx4_en_unmap_buffer(&ring->wqres.buf);
184 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
185 kfree(ring->bounce_buf);
186 ring->bounce_buf = NULL;
187 kvfree(ring->tx_info);
188 ring->tx_info = NULL;
193 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
194 struct mlx4_en_tx_ring *ring,
195 int cq, int user_prio)
197 struct mlx4_en_dev *mdev = priv->mdev;
202 ring->cons = 0xffffffff;
203 ring->last_nr_txbb = 1;
204 memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info));
205 memset(ring->buf, 0, ring->buf_size);
207 ring->qp_state = MLX4_QP_STATE_RST;
208 ring->doorbell_qpn = cpu_to_be32(ring->qp.qpn << 8);
209 ring->mr_key = cpu_to_be32(mdev->mr.key);
211 mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn,
212 ring->cqn, user_prio, &ring->context);
213 if (ring->bf_alloced)
214 ring->context.usr_page = cpu_to_be32(ring->bf.uar->index);
216 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context,
217 &ring->qp, &ring->qp_state);
218 if (!cpumask_empty(&ring->affinity_mask))
219 netif_set_xps_queue(priv->dev, &ring->affinity_mask,
225 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
226 struct mlx4_en_tx_ring *ring)
228 struct mlx4_en_dev *mdev = priv->mdev;
230 mlx4_qp_modify(mdev->dev, NULL, ring->qp_state,
231 MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp);
234 static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv,
235 struct mlx4_en_tx_ring *ring, int index,
238 __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT));
239 struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE;
240 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
241 void *end = ring->buf + ring->buf_size;
242 __be32 *ptr = (__be32 *)tx_desc;
245 /* Optimize the common case when there are no wraparounds */
246 if (likely((void *)tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) {
247 /* Stamp the freed descriptor */
248 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE;
254 /* Stamp the freed descriptor */
255 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE;
259 if ((void *)ptr >= end) {
261 stamp ^= cpu_to_be32(0x80000000);
268 static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
269 struct mlx4_en_tx_ring *ring,
270 int index, u8 owner, u64 timestamp)
272 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
273 struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE;
274 struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset;
275 void *end = ring->buf + ring->buf_size;
276 struct sk_buff *skb = tx_info->skb;
277 int nr_maps = tx_info->nr_maps;
280 /* We do not touch skb here, so prefetch skb->users location
281 * to speedup consume_skb()
283 prefetchw(&skb->users);
285 if (unlikely(timestamp)) {
286 struct skb_shared_hwtstamps hwts;
288 mlx4_en_fill_hwtstamps(priv->mdev, &hwts, timestamp);
289 skb_tstamp_tx(skb, &hwts);
292 /* Optimize the common case when there are no wraparounds */
293 if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) {
296 dma_unmap_single(priv->ddev,
298 tx_info->map0_byte_count,
301 dma_unmap_page(priv->ddev,
303 tx_info->map0_byte_count,
305 for (i = 1; i < nr_maps; i++) {
307 dma_unmap_page(priv->ddev,
308 (dma_addr_t)be64_to_cpu(data->addr),
309 be32_to_cpu(data->byte_count),
315 if ((void *) data >= end) {
316 data = ring->buf + ((void *)data - end);
320 dma_unmap_single(priv->ddev,
322 tx_info->map0_byte_count,
325 dma_unmap_page(priv->ddev,
327 tx_info->map0_byte_count,
329 for (i = 1; i < nr_maps; i++) {
331 /* Check for wraparound before unmapping */
332 if ((void *) data >= end)
334 dma_unmap_page(priv->ddev,
335 (dma_addr_t)be64_to_cpu(data->addr),
336 be32_to_cpu(data->byte_count),
341 dev_consume_skb_any(skb);
342 return tx_info->nr_txbb;
346 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring)
348 struct mlx4_en_priv *priv = netdev_priv(dev);
351 /* Skip last polled descriptor */
352 ring->cons += ring->last_nr_txbb;
353 en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n",
354 ring->cons, ring->prod);
356 if ((u32) (ring->prod - ring->cons) > ring->size) {
357 if (netif_msg_tx_err(priv))
358 en_warn(priv, "Tx consumer passed producer!\n");
362 while (ring->cons != ring->prod) {
363 ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring,
364 ring->cons & ring->size_mask,
365 !!(ring->cons & ring->size), 0);
366 ring->cons += ring->last_nr_txbb;
370 netdev_tx_reset_queue(ring->tx_queue);
373 en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt);
378 static bool mlx4_en_process_tx_cq(struct net_device *dev,
379 struct mlx4_en_cq *cq)
381 struct mlx4_en_priv *priv = netdev_priv(dev);
382 struct mlx4_cq *mcq = &cq->mcq;
383 struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring];
384 struct mlx4_cqe *cqe;
386 u16 new_index, ring_index, stamp_index;
387 u32 txbbs_skipped = 0;
389 u32 cons_index = mcq->cons_index;
391 u32 size_mask = ring->size_mask;
392 struct mlx4_cqe *buf = cq->buf;
395 int factor = priv->cqe_factor;
398 int budget = priv->tx_work_limit;
405 netdev_txq_bql_complete_prefetchw(ring->tx_queue);
407 index = cons_index & size_mask;
408 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor;
409 last_nr_txbb = ACCESS_ONCE(ring->last_nr_txbb);
410 ring_cons = ACCESS_ONCE(ring->cons);
411 ring_index = ring_cons & size_mask;
412 stamp_index = ring_index;
414 /* Process all completed CQEs */
415 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
416 cons_index & size) && (done < budget)) {
418 * make sure we read the CQE after we read the
423 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
424 MLX4_CQE_OPCODE_ERROR)) {
425 struct mlx4_err_cqe *cqe_err = (struct mlx4_err_cqe *)cqe;
427 en_err(priv, "CQE error - vendor syndrome: 0x%x syndrome: 0x%x\n",
428 cqe_err->vendor_err_syndrome,
432 /* Skip over last polled CQE */
433 new_index = be16_to_cpu(cqe->wqe_index) & size_mask;
436 txbbs_skipped += last_nr_txbb;
437 ring_index = (ring_index + last_nr_txbb) & size_mask;
438 if (ring->tx_info[ring_index].ts_requested)
439 timestamp = mlx4_en_get_cqe_ts(cqe);
441 /* free next descriptor */
442 last_nr_txbb = mlx4_en_free_tx_desc(
443 priv, ring, ring_index,
444 !!((ring_cons + txbbs_skipped) &
445 ring->size), timestamp);
447 mlx4_en_stamp_wqe(priv, ring, stamp_index,
448 !!((ring_cons + txbbs_stamp) &
450 stamp_index = ring_index;
451 txbbs_stamp = txbbs_skipped;
453 bytes += ring->tx_info[ring_index].nr_bytes;
454 } while ((++done < budget) && (ring_index != new_index));
457 index = cons_index & size_mask;
458 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor;
463 * To prevent CQ overflow we first update CQ consumer and only then
466 mcq->cons_index = cons_index;
470 /* we want to dirty this cache line once */
471 ACCESS_ONCE(ring->last_nr_txbb) = last_nr_txbb;
472 ACCESS_ONCE(ring->cons) = ring_cons + txbbs_skipped;
474 netdev_tx_completed_queue(ring->tx_queue, packets, bytes);
477 * Wakeup Tx queue if this stopped, and at least 1 packet
480 if (netif_tx_queue_stopped(ring->tx_queue) && txbbs_skipped > 0) {
481 netif_tx_wake_queue(ring->tx_queue);
484 return done < budget;
487 void mlx4_en_tx_irq(struct mlx4_cq *mcq)
489 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
490 struct mlx4_en_priv *priv = netdev_priv(cq->dev);
492 if (likely(priv->port_up))
493 napi_schedule_irqoff(&cq->napi);
495 mlx4_en_arm_cq(priv, cq);
498 /* TX CQ polling - called by NAPI */
499 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget)
501 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
502 struct net_device *dev = cq->dev;
503 struct mlx4_en_priv *priv = netdev_priv(dev);
506 clean_complete = mlx4_en_process_tx_cq(dev, cq);
511 mlx4_en_arm_cq(priv, cq);
516 static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv,
517 struct mlx4_en_tx_ring *ring,
519 unsigned int desc_size)
521 u32 copy = (ring->size - index) * TXBB_SIZE;
524 for (i = desc_size - copy - 4; i >= 0; i -= 4) {
525 if ((i & (TXBB_SIZE - 1)) == 0)
528 *((u32 *) (ring->buf + i)) =
529 *((u32 *) (ring->bounce_buf + copy + i));
532 for (i = copy - 4; i >= 4 ; i -= 4) {
533 if ((i & (TXBB_SIZE - 1)) == 0)
536 *((u32 *) (ring->buf + index * TXBB_SIZE + i)) =
537 *((u32 *) (ring->bounce_buf + i));
540 /* Return real descriptor location */
541 return ring->buf + index * TXBB_SIZE;
544 /* Decide if skb can be inlined in tx descriptor to avoid dma mapping
546 * It seems strange we do not simply use skb_copy_bits().
547 * This would allow to inline all skbs iff skb->len <= inline_thold
549 * Note that caller already checked skb was not a gso packet
551 static bool is_inline(int inline_thold, const struct sk_buff *skb,
552 const struct skb_shared_info *shinfo,
557 if (skb->len > inline_thold || !inline_thold)
560 if (shinfo->nr_frags == 1) {
561 ptr = skb_frag_address_safe(&shinfo->frags[0]);
567 if (shinfo->nr_frags)
572 static int inline_size(const struct sk_buff *skb)
574 if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg)
575 <= MLX4_INLINE_ALIGN)
576 return ALIGN(skb->len + CTRL_SIZE +
577 sizeof(struct mlx4_wqe_inline_seg), 16);
579 return ALIGN(skb->len + CTRL_SIZE + 2 *
580 sizeof(struct mlx4_wqe_inline_seg), 16);
583 static int get_real_size(const struct sk_buff *skb,
584 const struct skb_shared_info *shinfo,
585 struct net_device *dev,
586 int *lso_header_size,
590 struct mlx4_en_priv *priv = netdev_priv(dev);
593 if (shinfo->gso_size) {
595 if (skb->encapsulation)
596 *lso_header_size = (skb_inner_transport_header(skb) - skb->data) + inner_tcp_hdrlen(skb);
598 *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb);
599 real_size = CTRL_SIZE + shinfo->nr_frags * DS_SIZE +
600 ALIGN(*lso_header_size + 4, DS_SIZE);
601 if (unlikely(*lso_header_size != skb_headlen(skb))) {
602 /* We add a segment for the skb linear buffer only if
603 * it contains data */
604 if (*lso_header_size < skb_headlen(skb))
605 real_size += DS_SIZE;
607 if (netif_msg_tx_err(priv))
608 en_warn(priv, "Non-linear headers\n");
613 *lso_header_size = 0;
614 *inline_ok = is_inline(priv->prof->inline_thold, skb,
618 real_size = inline_size(skb);
620 real_size = CTRL_SIZE +
621 (shinfo->nr_frags + 1) * DS_SIZE;
627 static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc,
628 const struct sk_buff *skb,
629 const struct skb_shared_info *shinfo,
630 int real_size, u16 *vlan_tag,
631 int tx_ind, void *fragptr)
633 struct mlx4_wqe_inline_seg *inl = &tx_desc->inl;
634 int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl;
635 unsigned int hlen = skb_headlen(skb);
637 if (skb->len <= spc) {
638 if (likely(skb->len >= MIN_PKT_LEN)) {
639 inl->byte_count = cpu_to_be32(1 << 31 | skb->len);
641 inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN);
642 memset(((void *)(inl + 1)) + skb->len, 0,
643 MIN_PKT_LEN - skb->len);
645 skb_copy_from_linear_data(skb, inl + 1, hlen);
646 if (shinfo->nr_frags)
647 memcpy(((void *)(inl + 1)) + hlen, fragptr,
648 skb_frag_size(&shinfo->frags[0]));
651 inl->byte_count = cpu_to_be32(1 << 31 | spc);
653 skb_copy_from_linear_data(skb, inl + 1, hlen);
655 memcpy(((void *)(inl + 1)) + hlen,
656 fragptr, spc - hlen);
657 fragptr += spc - hlen;
659 inl = (void *) (inl + 1) + spc;
660 memcpy(((void *)(inl + 1)), fragptr, skb->len - spc);
662 skb_copy_from_linear_data(skb, inl + 1, spc);
663 inl = (void *) (inl + 1) + spc;
664 skb_copy_from_linear_data_offset(skb, spc, inl + 1,
666 if (shinfo->nr_frags)
667 memcpy(((void *)(inl + 1)) + hlen - spc,
669 skb_frag_size(&shinfo->frags[0]));
673 inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc));
677 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
678 void *accel_priv, select_queue_fallback_t fallback)
680 struct mlx4_en_priv *priv = netdev_priv(dev);
681 u16 rings_p_up = priv->num_tx_rings_p_up;
685 return skb_tx_hash(dev, skb);
687 if (skb_vlan_tag_present(skb))
688 up = skb_vlan_tag_get(skb) >> VLAN_PRIO_SHIFT;
690 return fallback(dev, skb) % rings_p_up + up * rings_p_up;
693 static void mlx4_bf_copy(void __iomem *dst, const void *src,
694 unsigned int bytecnt)
696 __iowrite64_copy(dst, src, bytecnt / 8);
699 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev)
701 struct skb_shared_info *shinfo = skb_shinfo(skb);
702 struct mlx4_en_priv *priv = netdev_priv(dev);
703 struct device *ddev = priv->ddev;
704 struct mlx4_en_tx_ring *ring;
705 struct mlx4_en_tx_desc *tx_desc;
706 struct mlx4_wqe_data_seg *data;
707 struct mlx4_en_tx_info *tx_info;
717 void *fragptr = NULL;
727 tx_ind = skb_get_queue_mapping(skb);
728 ring = priv->tx_ring[tx_ind];
730 /* fetch ring->cons far ahead before needing it to avoid stall */
731 ring_cons = ACCESS_ONCE(ring->cons);
733 real_size = get_real_size(skb, shinfo, dev, &lso_header_size,
734 &inline_ok, &fragptr);
735 if (unlikely(!real_size))
738 /* Align descriptor to TXBB size */
739 desc_size = ALIGN(real_size, TXBB_SIZE);
740 nr_txbb = desc_size / TXBB_SIZE;
741 if (unlikely(nr_txbb > MAX_DESC_TXBBS)) {
742 if (netif_msg_tx_err(priv))
743 en_warn(priv, "Oversized header or SG list\n");
747 if (skb_vlan_tag_present(skb))
748 vlan_tag = skb_vlan_tag_get(skb);
751 netdev_txq_bql_enqueue_prefetchw(ring->tx_queue);
753 /* Track current inflight packets for performance analysis */
754 AVG_PERF_COUNTER(priv->pstats.inflight_avg,
755 (u32)(ring->prod - ring_cons - 1));
757 /* Packet is good - grab an index and transmit it */
758 index = ring->prod & ring->size_mask;
759 bf_index = ring->prod;
761 /* See if we have enough space for whole descriptor TXBB for setting
762 * SW ownership on next descriptor; if not, use a bounce buffer. */
763 if (likely(index + nr_txbb <= ring->size))
764 tx_desc = ring->buf + index * TXBB_SIZE;
766 tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf;
770 /* Save skb in tx_info ring */
771 tx_info = &ring->tx_info[index];
773 tx_info->nr_txbb = nr_txbb;
775 data = &tx_desc->data;
777 data = ((void *)&tx_desc->lso + ALIGN(lso_header_size + 4,
780 /* valid only for none inline segments */
781 tx_info->data_offset = (void *)data - (void *)tx_desc;
783 tx_info->inl = inline_ok;
785 tx_info->linear = (lso_header_size < skb_headlen(skb) &&
788 tx_info->nr_maps = shinfo->nr_frags + tx_info->linear;
789 data += tx_info->nr_maps - 1;
795 /* Map fragments if any */
796 for (i_frag = shinfo->nr_frags - 1; i_frag >= 0; i_frag--) {
797 const struct skb_frag_struct *frag;
799 frag = &shinfo->frags[i_frag];
800 byte_count = skb_frag_size(frag);
801 dma = skb_frag_dma_map(ddev, frag,
804 if (dma_mapping_error(ddev, dma))
807 data->addr = cpu_to_be64(dma);
808 data->lkey = ring->mr_key;
810 data->byte_count = cpu_to_be32(byte_count);
814 /* Map linear part if needed */
815 if (tx_info->linear) {
816 byte_count = skb_headlen(skb) - lso_header_size;
818 dma = dma_map_single(ddev, skb->data +
819 lso_header_size, byte_count,
821 if (dma_mapping_error(ddev, dma))
824 data->addr = cpu_to_be64(dma);
825 data->lkey = ring->mr_key;
827 data->byte_count = cpu_to_be32(byte_count);
829 /* tx completion can avoid cache line miss for common cases */
830 tx_info->map0_dma = dma;
831 tx_info->map0_byte_count = byte_count;
835 * For timestamping add flag to skb_shinfo and
836 * set flag for further reference
838 tx_info->ts_requested = 0;
839 if (unlikely(ring->hwtstamp_tx_type == HWTSTAMP_TX_ON &&
840 shinfo->tx_flags & SKBTX_HW_TSTAMP)) {
841 shinfo->tx_flags |= SKBTX_IN_PROGRESS;
842 tx_info->ts_requested = 1;
845 /* Prepare ctrl segement apart opcode+ownership, which depends on
846 * whether LSO is used */
847 tx_desc->ctrl.srcrb_flags = priv->ctrl_flags;
848 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
849 if (!skb->encapsulation)
850 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
851 MLX4_WQE_CTRL_TCP_UDP_CSUM);
853 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM);
857 if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) {
860 /* Copy dst mac address to wqe. This allows loopback in eSwitch,
861 * so that VFs and PF can communicate with each other
863 ethh = (struct ethhdr *)skb->data;
864 tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest);
865 tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2));
868 /* Handle LSO (TSO) packets */
869 if (lso_header_size) {
872 /* Mark opcode as LSO */
873 op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) |
874 ((ring->prod & ring->size) ?
875 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
877 /* Fill in the LSO prefix */
878 tx_desc->lso.mss_hdr_size = cpu_to_be32(
879 shinfo->gso_size << 16 | lso_header_size);
882 * note that we already verified that it is linear */
883 memcpy(tx_desc->lso.header, skb->data, lso_header_size);
887 i = ((skb->len - lso_header_size) / shinfo->gso_size) +
888 !!((skb->len - lso_header_size) % shinfo->gso_size);
889 tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size;
892 /* Normal (Non LSO) packet */
893 op_own = cpu_to_be32(MLX4_OPCODE_SEND) |
894 ((ring->prod & ring->size) ?
895 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
896 tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
899 ring->bytes += tx_info->nr_bytes;
900 netdev_tx_sent_queue(ring->tx_queue, tx_info->nr_bytes);
901 AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len);
904 build_inline_wqe(tx_desc, skb, shinfo, real_size, &vlan_tag,
907 if (skb->encapsulation) {
908 struct iphdr *ipv4 = (struct iphdr *)skb_inner_network_header(skb);
909 if (ipv4->protocol == IPPROTO_TCP || ipv4->protocol == IPPROTO_UDP)
910 op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP);
912 op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP);
915 ring->prod += nr_txbb;
917 /* If we used a bounce buffer then copy descriptor back into place */
918 if (unlikely(bounce))
919 tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size);
921 skb_tx_timestamp(skb);
923 /* Check available TXBBs And 2K spare for prefetch */
924 stop_queue = (int)(ring->prod - ring_cons) >
925 ring->size - HEADROOM - MAX_DESC_TXBBS;
926 if (unlikely(stop_queue)) {
927 netif_tx_stop_queue(ring->tx_queue);
928 ring->queue_stopped++;
930 send_doorbell = !skb->xmit_more || netif_xmit_stopped(ring->tx_queue);
932 real_size = (real_size / 16) & 0x3f;
934 if (ring->bf_enabled && desc_size <= MAX_BF && !bounce &&
935 !skb_vlan_tag_present(skb) && send_doorbell) {
936 tx_desc->ctrl.bf_qpn = ring->doorbell_qpn |
937 cpu_to_be32(real_size);
939 op_own |= htonl((bf_index & 0xffff) << 8);
940 /* Ensure new descriptor hits memory
941 * before setting ownership of this descriptor to HW
944 tx_desc->ctrl.owner_opcode = op_own;
948 mlx4_bf_copy(ring->bf.reg + ring->bf.offset, &tx_desc->ctrl,
953 ring->bf.offset ^= ring->bf.buf_size;
955 tx_desc->ctrl.vlan_tag = cpu_to_be16(vlan_tag);
956 tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN *
957 !!skb_vlan_tag_present(skb);
958 tx_desc->ctrl.fence_size = real_size;
960 /* Ensure new descriptor hits memory
961 * before setting ownership of this descriptor to HW
964 tx_desc->ctrl.owner_opcode = op_own;
967 /* Since there is no iowrite*_native() that writes the
968 * value as is, without byteswapping - using the one
969 * the doesn't do byteswapping in the relevant arch
972 #if defined(__LITTLE_ENDIAN)
978 ring->bf.uar->map + MLX4_SEND_DOORBELL);
984 if (unlikely(stop_queue)) {
985 /* If queue was emptied after the if (stop_queue) , and before
986 * the netif_tx_stop_queue() - need to wake the queue,
987 * or else it will remain stopped forever.
988 * Need a memory barrier to make sure ring->cons was not
989 * updated before queue was stopped.
993 ring_cons = ACCESS_ONCE(ring->cons);
994 if (unlikely(((int)(ring->prod - ring_cons)) <=
995 ring->size - HEADROOM - MAX_DESC_TXBBS)) {
996 netif_tx_wake_queue(ring->tx_queue);
1000 return NETDEV_TX_OK;
1003 en_err(priv, "DMA mapping error\n");
1005 while (++i_frag < shinfo->nr_frags) {
1007 dma_unmap_page(ddev, (dma_addr_t) be64_to_cpu(data->addr),
1008 be32_to_cpu(data->byte_count),
1013 dev_kfree_skb_any(skb);
1014 priv->stats.tx_dropped++;
1015 return NETDEV_TX_OK;