drivers/net/ethernet/mellanox/mlx4/en_rx.c

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #include <net/busy_poll.h>
  35 #include <linux/bpf.h>
  36 #include <linux/mlx4/cq.h>
  37 #include <linux/slab.h>
  38 #include <linux/mlx4/qp.h>
  39 #include <linux/skbuff.h>
  40 #include <linux/rculist.h>
  41 #include <linux/if_ether.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/vmalloc.h>
  44 #include <linux/irq.h>
  45
  46 #if IS_ENABLED(CONFIG_IPV6)
  47 #include <net/ip6_checksum.h>
  48 #endif
  49
  50 #include "mlx4_en.h"
  51
  52 static int mlx4_alloc_pages(struct mlx4_en_priv *priv,
  53                             struct mlx4_en_rx_alloc *page_alloc,
  54                             const struct mlx4_en_frag_info *frag_info,
  55                             gfp_t _gfp)
  56 {
  57         int order;
  58         struct page *page;
  59         dma_addr_t dma;
  60
  61         for (order = frag_info->order; ;) {
  62                 gfp_t gfp = _gfp;
  63
  64                 if (order)
  65                         gfp |= __GFP_COMP | __GFP_NOWARN | __GFP_NOMEMALLOC;
  66                 page = alloc_pages(gfp, order);
  67                 if (likely(page))
  68                         break;
  69                 if (--order < 0 ||
  70                     ((PAGE_SIZE << order) < frag_info->frag_size))
  71                         return -ENOMEM;
  72         }
  73         dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE << order,
  74                            frag_info->dma_dir);
  75         if (unlikely(dma_mapping_error(priv->ddev, dma))) {
  76                 put_page(page);
  77                 return -ENOMEM;
  78         }
  79         page_alloc->page_size = PAGE_SIZE << order;
  80         page_alloc->page = page;
  81         page_alloc->dma = dma;
  82         page_alloc->page_offset = 0;
  83         /* Not doing get_page() for each frag is a big win
  84          * on asymetric workloads. Note we can not use atomic_set().
  85          */
  86         page_ref_add(page, page_alloc->page_size / frag_info->frag_stride - 1);
  87         return 0;
  88 }
  89
  90 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv,
  91                                struct mlx4_en_rx_desc *rx_desc,
  92                                struct mlx4_en_rx_alloc *frags,
  93                                struct mlx4_en_rx_alloc *ring_alloc,
  94                                gfp_t gfp)
  95 {
  96         struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
  97         const struct mlx4_en_frag_info *frag_info;
  98         struct page *page;
  99         int i;
 100
 101         for (i = 0; i < priv->num_frags; i++) {
 102                 frag_info = &priv->frag_info[i];
 103                 page_alloc[i] = ring_alloc[i];
 104                 page_alloc[i].page_offset += frag_info->frag_stride;
 105
 106                 if (page_alloc[i].page_offset + frag_info->frag_stride <=
 107                     ring_alloc[i].page_size)
 108                         continue;
 109
 110                 if (unlikely(mlx4_alloc_pages(priv, &page_alloc[i],
 111                                               frag_info, gfp)))
 112                         goto out;
 113         }
 114
 115         for (i = 0; i < priv->num_frags; i++) {
 116                 frags[i] = ring_alloc[i];
 117                 frags[i].page_offset += priv->frag_info[i].rx_headroom;
 118                 rx_desc->data[i].addr = cpu_to_be64(frags[i].dma +
 119                                                     frags[i].page_offset);
 120                 ring_alloc[i] = page_alloc[i];
 121         }
 122
 123         return 0;
 124
 125 out:
 126         while (i--) {
 127                 if (page_alloc[i].page != ring_alloc[i].page) {
 128                         dma_unmap_page(priv->ddev, page_alloc[i].dma,
 129                                 page_alloc[i].page_size,
 130                                 priv->frag_info[i].dma_dir);
 131                         page = page_alloc[i].page;
 132                         /* Revert changes done by mlx4_alloc_pages */
 133                         page_ref_sub(page, page_alloc[i].page_size /
 134                                            priv->frag_info[i].frag_stride - 1);
 135                         put_page(page);
 136                 }
 137         }
 138         return -ENOMEM;
 139 }
 140
 141 static void mlx4_en_free_frag(struct mlx4_en_priv *priv,
 142                               struct mlx4_en_rx_alloc *frags,
 143                               int i)
 144 {
 145         const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
 146         u32 next_frag_end = frags[i].page_offset + 2 * frag_info->frag_stride;
 147
 148
 149         if (next_frag_end > frags[i].page_size)
 150                 dma_unmap_page(priv->ddev, frags[i].dma, frags[i].page_size,
 151                                frag_info->dma_dir);
 152
 153         if (frags[i].page)
 154                 put_page(frags[i].page);
 155 }
 156
 157 static int mlx4_en_init_allocator(struct mlx4_en_priv *priv,
 158                                   struct mlx4_en_rx_ring *ring)
 159 {
 160         int i;
 161         struct mlx4_en_rx_alloc *page_alloc;
 162
 163         for (i = 0; i < priv->num_frags; i++) {
 164                 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
 165
 166                 if (mlx4_alloc_pages(priv, &ring->page_alloc[i],
 167                                      frag_info, GFP_KERNEL | __GFP_COLD))
 168                         goto out;
 169
 170                 en_dbg(DRV, priv, "  frag %d allocator: - size:%d frags:%d\n",
 171                        i, ring->page_alloc[i].page_size,
 172                        page_ref_count(ring->page_alloc[i].page));
 173         }
 174         return 0;
 175
 176 out:
 177         while (i--) {
 178                 struct page *page;
 179
 180                 page_alloc = &ring->page_alloc[i];
 181                 dma_unmap_page(priv->ddev, page_alloc->dma,
 182                                page_alloc->page_size,
 183                                priv->frag_info[i].dma_dir);
 184                 page = page_alloc->page;
 185                 /* Revert changes done by mlx4_alloc_pages */
 186                 page_ref_sub(page, page_alloc->page_size /
 187                                    priv->frag_info[i].frag_stride - 1);
 188                 put_page(page);
 189                 page_alloc->page = NULL;
 190         }
 191         return -ENOMEM;
 192 }
 193
 194 static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv,
 195                                       struct mlx4_en_rx_ring *ring)
 196 {
 197         struct mlx4_en_rx_alloc *page_alloc;
 198         int i;
 199
 200         for (i = 0; i < priv->num_frags; i++) {
 201                 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
 202
 203                 page_alloc = &ring->page_alloc[i];
 204                 en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n",
 205                        i, page_count(page_alloc->page));
 206
 207                 dma_unmap_page(priv->ddev, page_alloc->dma,
 208                                 page_alloc->page_size, frag_info->dma_dir);
 209                 while (page_alloc->page_offset + frag_info->frag_stride <
 210                        page_alloc->page_size) {
 211                         put_page(page_alloc->page);
 212                         page_alloc->page_offset += frag_info->frag_stride;
 213                 }
 214                 page_alloc->page = NULL;
 215         }
 216 }
 217
 218 static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
 219                                  struct mlx4_en_rx_ring *ring, int index)
 220 {
 221         struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
 222         int possible_frags;
 223         int i;
 224
 225         /* Set size and memtype fields */
 226         for (i = 0; i < priv->num_frags; i++) {
 227                 rx_desc->data[i].byte_count =
 228                         cpu_to_be32(priv->frag_info[i].frag_size);
 229                 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
 230         }
 231
 232         /* If the number of used fragments does not fill up the ring stride,
 233          * remaining (unused) fragments must be padded with null address/size
 234          * and a special memory key */
 235         possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
 236         for (i = priv->num_frags; i < possible_frags; i++) {
 237                 rx_desc->data[i].byte_count = 0;
 238                 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
 239                 rx_desc->data[i].addr = 0;
 240         }
 241 }
 242
 243 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
 244                                    struct mlx4_en_rx_ring *ring, int index,
 245                                    gfp_t gfp)
 246 {
 247         struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
 248         struct mlx4_en_rx_alloc *frags = ring->rx_info +
 249                                         (index << priv->log_rx_info);
 250
 251         if (ring->page_cache.index > 0) {
 252                 frags[0] = ring->page_cache.buf[--ring->page_cache.index];
 253                 rx_desc->data[0].addr = cpu_to_be64(frags[0].dma +
 254                                                     frags[0].page_offset);
 255                 return 0;
 256         }
 257
 258         return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc, gfp);
 259 }
 260
 261 static inline bool mlx4_en_is_ring_empty(struct mlx4_en_rx_ring *ring)
 262 {
 263         return ring->prod == ring->cons;
 264 }
 265
 266 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
 267 {
 268         *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
 269 }
 270
 271 static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv,
 272                                  struct mlx4_en_rx_ring *ring,
 273                                  int index)
 274 {
 275         struct mlx4_en_rx_alloc *frags;
 276         int nr;
 277
 278         frags = ring->rx_info + (index << priv->log_rx_info);
 279         for (nr = 0; nr < priv->num_frags; nr++) {
 280                 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
 281                 mlx4_en_free_frag(priv, frags, nr);
 282         }
 283 }
 284
 285 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
 286 {
 287         struct mlx4_en_rx_ring *ring;
 288         int ring_ind;
 289         int buf_ind;
 290         int new_size;
 291
 292         for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
 293                 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 294                         ring = priv->rx_ring[ring_ind];
 295
 296                         if (mlx4_en_prepare_rx_desc(priv, ring,
 297                                                     ring->actual_size,
 298                                                     GFP_KERNEL | __GFP_COLD)) {
 299                                 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
 300                                         en_err(priv, "Failed to allocate enough rx buffers\n");
 301                                         return -ENOMEM;
 302                                 } else {
 303                                         new_size = rounddown_pow_of_two(ring->actual_size);
 304                                         en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n",
 305                                                 ring->actual_size, new_size);
 306                                         goto reduce_rings;
 307                                 }
 308                         }
 309                         ring->actual_size++;
 310                         ring->prod++;
 311                 }
 312         }
 313         return 0;
 314
 315 reduce_rings:
 316         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 317                 ring = priv->rx_ring[ring_ind];
 318                 while (ring->actual_size > new_size) {
 319                         ring->actual_size--;
 320                         ring->prod--;
 321                         mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
 322                 }
 323         }
 324
 325         return 0;
 326 }
 327
 328 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
 329                                 struct mlx4_en_rx_ring *ring)
 330 {
 331         int index;
 332
 333         en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
 334                ring->cons, ring->prod);
 335
 336         /* Unmap and free Rx buffers */
 337         while (!mlx4_en_is_ring_empty(ring)) {
 338                 index = ring->cons & ring->size_mask;
 339                 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
 340                 mlx4_en_free_rx_desc(priv, ring, index);
 341                 ++ring->cons;
 342         }
 343 }
 344
 345 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev)
 346 {
 347         int i;
 348         int num_of_eqs;
 349         int num_rx_rings;
 350         struct mlx4_dev *dev = mdev->dev;
 351
 352         mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {
 353                 num_of_eqs = max_t(int, MIN_RX_RINGS,
 354                                    min_t(int,
 355                                          mlx4_get_eqs_per_port(mdev->dev, i),
 356                                          DEF_RX_RINGS));
 357
 358                 num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS :
 359                         min_t(int, num_of_eqs,
 360                               netif_get_num_default_rss_queues());
 361                 mdev->profile.prof[i].rx_ring_num =
 362                         rounddown_pow_of_two(num_rx_rings);
 363         }
 364 }
 365
 366 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
 367                            struct mlx4_en_rx_ring **pring,
 368                            u32 size, u16 stride, int node)
 369 {
 370         struct mlx4_en_dev *mdev = priv->mdev;
 371         struct mlx4_en_rx_ring *ring;
 372         int err = -ENOMEM;
 373         int tmp;
 374
 375         ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
 376         if (!ring) {
 377                 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
 378                 if (!ring) {
 379                         en_err(priv, "Failed to allocate RX ring structure\n");
 380                         return -ENOMEM;
 381                 }
 382         }
 383
 384         ring->prod = 0;
 385         ring->cons = 0;
 386         ring->size = size;
 387         ring->size_mask = size - 1;
 388         ring->stride = stride;
 389         ring->log_stride = ffs(ring->stride) - 1;
 390         ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
 391
 392         tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
 393                                         sizeof(struct mlx4_en_rx_alloc));
 394         ring->rx_info = vmalloc_node(tmp, node);
 395         if (!ring->rx_info) {
 396                 ring->rx_info = vmalloc(tmp);
 397                 if (!ring->rx_info) {
 398                         err = -ENOMEM;
 399                         goto err_ring;
 400                 }
 401         }
 402
 403         en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
 404                  ring->rx_info, tmp);
 405
 406         /* Allocate HW buffers on provided NUMA node */
 407         set_dev_node(&mdev->dev->persist->pdev->dev, node);
 408         err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
 409         set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);
 410         if (err)
 411                 goto err_info;
 412
 413         ring->buf = ring->wqres.buf.direct.buf;
 414
 415         ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter;
 416
 417         *pring = ring;
 418         return 0;
 419
 420 err_info:
 421         vfree(ring->rx_info);
 422         ring->rx_info = NULL;
 423 err_ring:
 424         kfree(ring);
 425         *pring = NULL;
 426
 427         return err;
 428 }
 429
 430 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
 431 {
 432         struct mlx4_en_rx_ring *ring;
 433         int i;
 434         int ring_ind;
 435         int err;
 436         int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
 437                                         DS_SIZE * priv->num_frags);
 438
 439         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 440                 ring = priv->rx_ring[ring_ind];
 441
 442                 ring->prod = 0;
 443                 ring->cons = 0;
 444                 ring->actual_size = 0;
 445                 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn;
 446
 447                 ring->stride = stride;
 448                 if (ring->stride <= TXBB_SIZE) {
 449                         /* Stamp first unused send wqe */
 450                         __be32 *ptr = (__be32 *)ring->buf;
 451                         __be32 stamp = cpu_to_be32(1 << STAMP_SHIFT);
 452                         *ptr = stamp;
 453                         /* Move pointer to start of rx section */
 454                         ring->buf += TXBB_SIZE;
 455                 }
 456
 457                 ring->log_stride = ffs(ring->stride) - 1;
 458                 ring->buf_size = ring->size * ring->stride;
 459
 460                 memset(ring->buf, 0, ring->buf_size);
 461                 mlx4_en_update_rx_prod_db(ring);
 462
 463                 /* Initialize all descriptors */
 464                 for (i = 0; i < ring->size; i++)
 465                         mlx4_en_init_rx_desc(priv, ring, i);
 466
 467                 /* Initialize page allocators */
 468                 err = mlx4_en_init_allocator(priv, ring);
 469                 if (err) {
 470                         en_err(priv, "Failed initializing ring allocator\n");
 471                         if (ring->stride <= TXBB_SIZE)
 472                                 ring->buf -= TXBB_SIZE;
 473                         ring_ind--;
 474                         goto err_allocator;
 475                 }
 476         }
 477         err = mlx4_en_fill_rx_buffers(priv);
 478         if (err)
 479                 goto err_buffers;
 480
 481         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 482                 ring = priv->rx_ring[ring_ind];
 483
 484                 ring->size_mask = ring->actual_size - 1;
 485                 mlx4_en_update_rx_prod_db(ring);
 486         }
 487
 488         return 0;
 489
 490 err_buffers:
 491         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
 492                 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]);
 493
 494         ring_ind = priv->rx_ring_num - 1;
 495 err_allocator:
 496         while (ring_ind >= 0) {
 497                 if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE)
 498                         priv->rx_ring[ring_ind]->buf -= TXBB_SIZE;
 499                 mlx4_en_destroy_allocator(priv, priv->rx_ring[ring_ind]);
 500                 ring_ind--;
 501         }
 502         return err;
 503 }
 504
 505 /* We recover from out of memory by scheduling our napi poll
 506  * function (mlx4_en_process_cq), which tries to allocate
 507  * all missing RX buffers (call to mlx4_en_refill_rx_buffers).
 508  */
 509 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv)
 510 {
 511         int ring;
 512
 513         if (!priv->port_up)
 514                 return;
 515
 516         for (ring = 0; ring < priv->rx_ring_num; ring++) {
 517                 if (mlx4_en_is_ring_empty(priv->rx_ring[ring]))
 518                         napi_reschedule(&priv->rx_cq[ring]->napi);
 519         }
 520 }
 521
 522 /* When the rx ring is running in page-per-packet mode, a released frame can go
 523  * directly into a small cache, to avoid unmapping or touching the page
 524  * allocator. In bpf prog performance scenarios, buffers are either forwarded
 525  * or dropped, never converted to skbs, so every page can come directly from
 526  * this cache when it is sized to be a multiple of the napi budget.
 527  */
 528 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring,
 529                         struct mlx4_en_rx_alloc *frame)
 530 {
 531         struct mlx4_en_page_cache *cache = &ring->page_cache;
 532
 533         if (cache->index >= MLX4_EN_CACHE_SIZE)
 534                 return false;
 535
 536         cache->buf[cache->index++] = *frame;
 537         return true;
 538 }
 539
 540 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
 541                              struct mlx4_en_rx_ring **pring,
 542                              u32 size, u16 stride)
 543 {
 544         struct mlx4_en_dev *mdev = priv->mdev;
 545         struct mlx4_en_rx_ring *ring = *pring;
 546         struct bpf_prog *old_prog;
 547
 548         old_prog = rcu_dereference_protected(
 549                                         ring->xdp_prog,
 550                                         lockdep_is_held(&mdev->state_lock));
 551         if (old_prog)
 552                 bpf_prog_put(old_prog);
 553         mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE);
 554         vfree(ring->rx_info);
 555         ring->rx_info = NULL;
 556         kfree(ring);
 557         *pring = NULL;
 558 }
 559
 560 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
 561                                 struct mlx4_en_rx_ring *ring)
 562 {
 563         int i;
 564
 565         for (i = 0; i < ring->page_cache.index; i++) {
 566                 struct mlx4_en_rx_alloc *frame = &ring->page_cache.buf[i];
 567
 568                 dma_unmap_page(priv->ddev, frame->dma, frame->page_size,
 569                                priv->frag_info[0].dma_dir);
 570                 put_page(frame->page);
 571         }
 572         ring->page_cache.index = 0;
 573         mlx4_en_free_rx_buf(priv, ring);
 574         if (ring->stride <= TXBB_SIZE)
 575                 ring->buf -= TXBB_SIZE;
 576         mlx4_en_destroy_allocator(priv, ring);
 577 }
 578
 579
 580 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
 581                                     struct mlx4_en_rx_desc *rx_desc,
 582                                     struct mlx4_en_rx_alloc *frags,
 583                                     struct sk_buff *skb,
 584                                     int length)
 585 {
 586         struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags;
 587         struct mlx4_en_frag_info *frag_info;
 588         int nr;
 589         dma_addr_t dma;
 590
 591         /* Collect used fragments while replacing them in the HW descriptors */
 592         for (nr = 0; nr < priv->num_frags; nr++) {
 593                 frag_info = &priv->frag_info[nr];
 594                 if (length <= frag_info->frag_prefix_size)
 595                         break;
 596                 if (unlikely(!frags[nr].page))
 597                         goto fail;
 598
 599                 dma = be64_to_cpu(rx_desc->data[nr].addr);
 600                 dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size,
 601                                         DMA_FROM_DEVICE);
 602
 603                 /* Save page reference in skb */
 604                 __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page);
 605                 skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size);
 606                 skb_frags_rx[nr].page_offset = frags[nr].page_offset;
 607                 skb->truesize += frag_info->frag_stride;
 608                 frags[nr].page = NULL;
 609         }
 610         /* Adjust size of last fragment to match actual length */
 611         if (nr > 0)
 612                 skb_frag_size_set(&skb_frags_rx[nr - 1],
 613                         length - priv->frag_info[nr - 1].frag_prefix_size);
 614         return nr;
 615
 616 fail:
 617         while (nr > 0) {
 618                 nr--;
 619                 __skb_frag_unref(&skb_frags_rx[nr]);
 620         }
 621         return 0;
 622 }
 623
 624
 625 static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
 626                                       struct mlx4_en_rx_desc *rx_desc,
 627                                       struct mlx4_en_rx_alloc *frags,
 628                                       unsigned int length)
 629 {
 630         struct sk_buff *skb;
 631         void *va;
 632         int used_frags;
 633         dma_addr_t dma;
 634
 635         skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN);
 636         if (unlikely(!skb)) {
 637                 en_dbg(RX_ERR, priv, "Failed allocating skb\n");
 638                 return NULL;
 639         }
 640         skb_reserve(skb, NET_IP_ALIGN);
 641         skb->len = length;
 642
 643         /* Get pointer to first fragment so we could copy the headers into the
 644          * (linear part of the) skb */
 645         va = page_address(frags[0].page) + frags[0].page_offset;
 646
 647         if (length <= SMALL_PACKET_SIZE) {
 648                 /* We are copying all relevant data to the skb - temporarily
 649                  * sync buffers for the copy */
 650                 dma = be64_to_cpu(rx_desc->data[0].addr);
 651                 dma_sync_single_for_cpu(priv->ddev, dma, length,
 652                                         DMA_FROM_DEVICE);
 653                 skb_copy_to_linear_data(skb, va, length);
 654                 skb->tail += length;
 655         } else {
 656                 unsigned int pull_len;
 657
 658                 /* Move relevant fragments to skb */
 659                 used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags,
 660                                                         skb, length);
 661                 if (unlikely(!used_frags)) {
 662                         kfree_skb(skb);
 663                         return NULL;
 664                 }
 665                 skb_shinfo(skb)->nr_frags = used_frags;
 666
 667                 pull_len = eth_get_headlen(va, SMALL_PACKET_SIZE);
 668                 /* Copy headers into the skb linear buffer */
 669                 memcpy(skb->data, va, pull_len);
 670                 skb->tail += pull_len;
 671
 672                 /* Skip headers in first fragment */
 673                 skb_shinfo(skb)->frags[0].page_offset += pull_len;
 674
 675                 /* Adjust size of first fragment */
 676                 skb_frag_size_sub(&skb_shinfo(skb)->frags[0], pull_len);
 677                 skb->data_len = length - pull_len;
 678         }
 679         return skb;
 680 }
 681
 682 static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb)
 683 {
 684         int i;
 685         int offset = ETH_HLEN;
 686
 687         for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) {
 688                 if (*(skb->data + offset) != (unsigned char) (i & 0xff))
 689                         goto out_loopback;
 690         }
 691         /* Loopback found */
 692         priv->loopback_ok = 1;
 693
 694 out_loopback:
 695         dev_kfree_skb_any(skb);
 696 }
 697
 698 static bool mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv,
 699                                       struct mlx4_en_rx_ring *ring)
 700 {
 701         u32 missing = ring->actual_size - (ring->prod - ring->cons);
 702
 703         /* Try to batch allocations, but not too much. */
 704         if (missing < 8)
 705                 return false;
 706         do {
 707                 if (mlx4_en_prepare_rx_desc(priv, ring,
 708                                             ring->prod & ring->size_mask,
 709                                             GFP_ATOMIC | __GFP_COLD))
 710                         break;
 711                 ring->prod++;
 712         } while (--missing);
 713
 714         return true;
 715 }
 716
 717 /* When hardware doesn't strip the vlan, we need to calculate the checksum
 718  * over it and add it to the hardware's checksum calculation
 719  */
 720 static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum,
 721                                          struct vlan_hdr *vlanh)
 722 {
 723         return csum_add(hw_checksum, *(__wsum *)vlanh);
 724 }
 725
 726 /* Although the stack expects checksum which doesn't include the pseudo
 727  * header, the HW adds it. To address that, we are subtracting the pseudo
 728  * header checksum from the checksum value provided by the HW.
 729  */
 730 static void get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb,
 731                                 struct iphdr *iph)
 732 {
 733         __u16 length_for_csum = 0;
 734         __wsum csum_pseudo_header = 0;
 735
 736         length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2));
 737         csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr,
 738                                                 length_for_csum, iph->protocol, 0);
 739         skb->csum = csum_sub(hw_checksum, csum_pseudo_header);
 740 }
 741
 742 #if IS_ENABLED(CONFIG_IPV6)
 743 /* In IPv6 packets, besides subtracting the pseudo header checksum,
 744  * we also compute/add the IP header checksum which
 745  * is not added by the HW.
 746  */
 747 static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb,
 748                                struct ipv6hdr *ipv6h)
 749 {
 750         __wsum csum_pseudo_hdr = 0;
 751
 752         if (unlikely(ipv6h->nexthdr == IPPROTO_FRAGMENT ||
 753                      ipv6h->nexthdr == IPPROTO_HOPOPTS))
 754                 return -1;
 755         hw_checksum = csum_add(hw_checksum, (__force __wsum)htons(ipv6h->nexthdr));
 756
 757         csum_pseudo_hdr = csum_partial(&ipv6h->saddr,
 758                                        sizeof(ipv6h->saddr) + sizeof(ipv6h->daddr), 0);
 759         csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ipv6h->payload_len);
 760         csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ntohs(ipv6h->nexthdr));
 761
 762         skb->csum = csum_sub(hw_checksum, csum_pseudo_hdr);
 763         skb->csum = csum_add(skb->csum, csum_partial(ipv6h, sizeof(struct ipv6hdr), 0));
 764         return 0;
 765 }
 766 #endif
 767 static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va,
 768                       netdev_features_t dev_features)
 769 {
 770         __wsum hw_checksum = 0;
 771
 772         void *hdr = (u8 *)va + sizeof(struct ethhdr);
 773
 774         hw_checksum = csum_unfold((__force __sum16)cqe->checksum);
 775
 776         if (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK) &&
 777             !(dev_features & NETIF_F_HW_VLAN_CTAG_RX)) {
 778                 hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr);
 779                 hdr += sizeof(struct vlan_hdr);
 780         }
 781
 782         if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4))
 783                 get_fixed_ipv4_csum(hw_checksum, skb, hdr);
 784 #if IS_ENABLED(CONFIG_IPV6)
 785         else if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6))
 786                 if (unlikely(get_fixed_ipv6_csum(hw_checksum, skb, hdr)))
 787                         return -1;
 788 #endif
 789         return 0;
 790 }
 791
 792 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
 793 {
 794         struct mlx4_en_priv *priv = netdev_priv(dev);
 795         struct mlx4_en_dev *mdev = priv->mdev;
 796         struct mlx4_cqe *cqe;
 797         struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring];
 798         struct mlx4_en_rx_alloc *frags;
 799         struct mlx4_en_rx_desc *rx_desc;
 800         struct bpf_prog *xdp_prog;
 801         int doorbell_pending;
 802         struct sk_buff *skb;
 803         int index;
 804         int nr;
 805         unsigned int length;
 806         int polled = 0;
 807         int ip_summed;
 808         int factor = priv->cqe_factor;
 809         u64 timestamp;
 810         bool l2_tunnel;
 811
 812         if (unlikely(!priv->port_up))
 813                 return 0;
 814
 815         if (unlikely(budget <= 0))
 816                 return polled;
 817
 818         /* Protect accesses to: ring->xdp_prog, priv->mac_hash list */
 819         rcu_read_lock();
 820         xdp_prog = rcu_dereference(ring->xdp_prog);
 821         doorbell_pending = 0;
 822
 823         /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
 824          * descriptor offset can be deduced from the CQE index instead of
 825          * reading 'cqe->index' */
 826         index = cq->mcq.cons_index & ring->size_mask;
 827         cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
 828
 829         /* Process all completed CQEs */
 830         while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
 831                     cq->mcq.cons_index & cq->size)) {
 832
 833                 frags = ring->rx_info + (index << priv->log_rx_info);
 834                 rx_desc = ring->buf + (index << ring->log_stride);
 835
 836                 /*
 837                  * make sure we read the CQE after we read the ownership bit
 838                  */
 839                 dma_rmb();
 840
 841                 /* Drop packet on bad receive or bad checksum */
 842                 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
 843                                                 MLX4_CQE_OPCODE_ERROR)) {
 844                         en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n",
 845                                ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome,
 846                                ((struct mlx4_err_cqe *)cqe)->syndrome);
 847                         goto next;
 848                 }
 849                 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
 850                         en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
 851                         goto next;
 852                 }
 853
 854                 /* Check if we need to drop the packet if SRIOV is not enabled
 855                  * and not performing the selftest or flb disabled
 856                  */
 857                 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) {
 858                         struct ethhdr *ethh;
 859                         dma_addr_t dma;
 860                         /* Get pointer to first fragment since we haven't
 861                          * skb yet and cast it to ethhdr struct
 862                          */
 863                         dma = be64_to_cpu(rx_desc->data[0].addr);
 864                         dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh),
 865                                                 DMA_FROM_DEVICE);
 866                         ethh = (struct ethhdr *)(page_address(frags[0].page) +
 867                                                  frags[0].page_offset);
 868
 869                         if (is_multicast_ether_addr(ethh->h_dest)) {
 870                                 struct mlx4_mac_entry *entry;
 871                                 struct hlist_head *bucket;
 872                                 unsigned int mac_hash;
 873
 874                                 /* Drop the packet, since HW loopback-ed it */
 875                                 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX];
 876                                 bucket = &priv->mac_hash[mac_hash];
 877                                 hlist_for_each_entry_rcu(entry, bucket, hlist) {
 878                                         if (ether_addr_equal_64bits(entry->mac,
 879                                                                     ethh->h_source))
 880                                                 goto next;
 881                                 }
 882                         }
 883                 }
 884
 885                 /*
 886                  * Packet is OK - process it.
 887                  */
 888                 length = be32_to_cpu(cqe->byte_cnt);
 889                 length -= ring->fcs_del;
 890                 l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) &&
 891                         (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL));
 892
 893                 /* A bpf program gets first chance to drop the packet. It may
 894                  * read bytes but not past the end of the frag.
 895                  */
 896                 if (xdp_prog) {
 897                         struct xdp_buff xdp;
 898                         dma_addr_t dma;
 899                         void *orig_data;
 900                         u32 act;
 901
 902                         dma = be64_to_cpu(rx_desc->data[0].addr);
 903                         dma_sync_single_for_cpu(priv->ddev, dma,
 904                                                 priv->frag_info[0].frag_size,
 905                                                 DMA_FROM_DEVICE);
 906
 907                         xdp.data_hard_start = page_address(frags[0].page);
 908                         xdp.data = xdp.data_hard_start + frags[0].page_offset;
 909                         xdp.data_end = xdp.data + length;
 910                         orig_data = xdp.data;
 911
 912                         act = bpf_prog_run_xdp(xdp_prog, &xdp);
 913
 914                         if (xdp.data != orig_data) {
 915                                 length = xdp.data_end - xdp.data;
 916                                 frags[0].page_offset = xdp.data -
 917                                         xdp.data_hard_start;
 918                         }
 919
 920                         switch (act) {
 921                         case XDP_PASS:
 922                                 break;
 923                         case XDP_TX:
 924                                 if (likely(!mlx4_en_xmit_frame(ring, frags, dev,
 925                                                         length, cq->ring,
 926                                                         &doorbell_pending)))
 927                                         goto consumed;
 928                                 goto xdp_drop_no_cnt; /* Drop on xmit failure */
 929                         default:
 930                                 bpf_warn_invalid_xdp_action(act);
 931                         case XDP_ABORTED:
 932                         case XDP_DROP:
 933                                 ring->xdp_drop++;
 934 xdp_drop_no_cnt:
 935                                 if (likely(mlx4_en_rx_recycle(ring, frags)))
 936                                         goto consumed;
 937                                 goto next;
 938                         }
 939                 }
 940
 941                 ring->bytes += length;
 942                 ring->packets++;
 943
 944                 if (likely(dev->features & NETIF_F_RXCSUM)) {
 945                         if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP |
 946                                                       MLX4_CQE_STATUS_UDP)) {
 947                                 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
 948                                     cqe->checksum == cpu_to_be16(0xffff)) {
 949                                         ip_summed = CHECKSUM_UNNECESSARY;
 950                                         ring->csum_ok++;
 951                                 } else {
 952                                         ip_summed = CHECKSUM_NONE;
 953                                         ring->csum_none++;
 954                                 }
 955                         } else {
 956                                 if (priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP &&
 957                                     (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
 958                                                                MLX4_CQE_STATUS_IPV6))) {
 959                                         ip_summed = CHECKSUM_COMPLETE;
 960                                         ring->csum_complete++;
 961                                 } else {
 962                                         ip_summed = CHECKSUM_NONE;
 963                                         ring->csum_none++;
 964                                 }
 965                         }
 966                 } else {
 967                         ip_summed = CHECKSUM_NONE;
 968                         ring->csum_none++;
 969                 }
 970
 971                 /* This packet is eligible for GRO if it is:
 972                  * - DIX Ethernet (type interpretation)
 973                  * - TCP/IP (v4)
 974                  * - without IP options
 975                  * - not an IP fragment
 976                  */
 977                 if (dev->features & NETIF_F_GRO) {
 978                         struct sk_buff *gro_skb = napi_get_frags(&cq->napi);
 979                         if (!gro_skb)
 980                                 goto next;
 981
 982                         nr = mlx4_en_complete_rx_desc(priv,
 983                                 rx_desc, frags, gro_skb,
 984                                 length);
 985                         if (!nr)
 986                                 goto next;
 987
 988                         if (ip_summed == CHECKSUM_COMPLETE) {
 989                                 void *va = skb_frag_address(skb_shinfo(gro_skb)->frags);
 990                                 if (check_csum(cqe, gro_skb, va,
 991                                                dev->features)) {
 992                                         ip_summed = CHECKSUM_NONE;
 993                                         ring->csum_none++;
 994                                         ring->csum_complete--;
 995                                 }
 996                         }
 997
 998                         skb_shinfo(gro_skb)->nr_frags = nr;
 999                         gro_skb->len = length;
1000                         gro_skb->data_len = length;
1001                         gro_skb->ip_summed = ip_summed;
1002
1003                         if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
1004                                 gro_skb->csum_level = 1;
1005
1006                         if ((cqe->vlan_my_qpn &
1007                             cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK)) &&
1008                             (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1009                                 u16 vid = be16_to_cpu(cqe->sl_vid);
1010
1011                                 __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid);
1012                         } else if ((be32_to_cpu(cqe->vlan_my_qpn) &
1013                                   MLX4_CQE_SVLAN_PRESENT_MASK) &&
1014                                  (dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
1015                                 __vlan_hwaccel_put_tag(gro_skb,
1016                                                        htons(ETH_P_8021AD),
1017                                                        be16_to_cpu(cqe->sl_vid));
1018                         }
1019
1020                         if (dev->features & NETIF_F_RXHASH)
1021                                 skb_set_hash(gro_skb,
1022                                              be32_to_cpu(cqe->immed_rss_invalid),
1023                                              (ip_summed == CHECKSUM_UNNECESSARY) ?
1024                                                 PKT_HASH_TYPE_L4 :
1025                                                 PKT_HASH_TYPE_L3);
1026
1027                         skb_record_rx_queue(gro_skb, cq->ring);
1028
1029                         if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
1030                                 timestamp = mlx4_en_get_cqe_ts(cqe);
1031                                 mlx4_en_fill_hwtstamps(mdev,
1032                                                        skb_hwtstamps(gro_skb),
1033                                                        timestamp);
1034                         }
1035
1036                         napi_gro_frags(&cq->napi);
1037                         goto next;
1038                 }
1039
1040                 /* GRO not possible, complete processing here */
1041                 skb = mlx4_en_rx_skb(priv, rx_desc, frags, length);
1042                 if (unlikely(!skb)) {
1043                         ring->dropped++;
1044                         goto next;
1045                 }
1046
1047                 if (unlikely(priv->validate_loopback)) {
1048                         validate_loopback(priv, skb);
1049                         goto next;
1050                 }
1051
1052                 if (ip_summed == CHECKSUM_COMPLETE) {
1053                         if (check_csum(cqe, skb, skb->data, dev->features)) {
1054                                 ip_summed = CHECKSUM_NONE;
1055                                 ring->csum_complete--;
1056                                 ring->csum_none++;
1057                         }
1058                 }
1059
1060                 skb->ip_summed = ip_summed;
1061                 skb->protocol = eth_type_trans(skb, dev);
1062                 skb_record_rx_queue(skb, cq->ring);
1063
1064                 if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
1065                         skb->csum_level = 1;
1066
1067                 if (dev->features & NETIF_F_RXHASH)
1068                         skb_set_hash(skb,
1069                                      be32_to_cpu(cqe->immed_rss_invalid),
1070                                      (ip_summed == CHECKSUM_UNNECESSARY) ?
1071                                         PKT_HASH_TYPE_L4 :
1072                                         PKT_HASH_TYPE_L3);
1073
1074                 if ((be32_to_cpu(cqe->vlan_my_qpn) &
1075                     MLX4_CQE_CVLAN_PRESENT_MASK) &&
1076                     (dev->features & NETIF_F_HW_VLAN_CTAG_RX))
1077                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid));
1078                 else if ((be32_to_cpu(cqe->vlan_my_qpn) &
1079                           MLX4_CQE_SVLAN_PRESENT_MASK) &&
1080                          (dev->features & NETIF_F_HW_VLAN_STAG_RX))
1081                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD),
1082                                                be16_to_cpu(cqe->sl_vid));
1083
1084                 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
1085                         timestamp = mlx4_en_get_cqe_ts(cqe);
1086                         mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb),
1087                                                timestamp);
1088                 }
1089
1090                 napi_gro_receive(&cq->napi, skb);
1091 next:
1092                 for (nr = 0; nr < priv->num_frags; nr++)
1093                         mlx4_en_free_frag(priv, frags, nr);
1094
1095 consumed:
1096                 ++cq->mcq.cons_index;
1097                 index = (cq->mcq.cons_index) & ring->size_mask;
1098                 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
1099                 if (++polled == budget)
1100                         goto out;
1101         }
1102
1103 out:
1104         rcu_read_unlock();
1105
1106         if (polled) {
1107                 if (doorbell_pending)
1108                         mlx4_en_xmit_doorbell(priv->tx_ring[TX_XDP][cq->ring]);
1109
1110                 mlx4_cq_set_ci(&cq->mcq);
1111                 wmb(); /* ensure HW sees CQ consumer before we post new buffers */
1112                 ring->cons = cq->mcq.cons_index;
1113         }
1114         AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
1115
1116         if (mlx4_en_refill_rx_buffers(priv, ring))
1117                 mlx4_en_update_rx_prod_db(ring);
1118
1119         return polled;
1120 }
1121
1122
1123 void mlx4_en_rx_irq(struct mlx4_cq *mcq)
1124 {
1125         struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
1126         struct mlx4_en_priv *priv = netdev_priv(cq->dev);
1127
1128         if (likely(priv->port_up))
1129                 napi_schedule_irqoff(&cq->napi);
1130         else
1131                 mlx4_en_arm_cq(priv, cq);
1132 }
1133
1134 /* Rx CQ polling - called by NAPI */
1135 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
1136 {
1137         struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
1138         struct net_device *dev = cq->dev;
1139         struct mlx4_en_priv *priv = netdev_priv(dev);
1140         int done;
1141
1142         done = mlx4_en_process_rx_cq(dev, cq, budget);
1143
1144         /* If we used up all the quota - we're probably not done yet... */
1145         if (done == budget) {
1146                 const struct cpumask *aff;
1147                 struct irq_data *idata;
1148                 int cpu_curr;
1149
1150                 INC_PERF_COUNTER(priv->pstats.napi_quota);
1151
1152                 cpu_curr = smp_processor_id();
1153                 idata = irq_desc_get_irq_data(cq->irq_desc);
1154                 aff = irq_data_get_affinity_mask(idata);
1155
1156                 if (likely(cpumask_test_cpu(cpu_curr, aff)))
1157                         return budget;
1158
1159                 /* Current cpu is not according to smp_irq_affinity -
1160                  * probably affinity changed. Need to stop this NAPI
1161                  * poll, and restart it on the right CPU.
1162                  * Try to avoid returning a too small value (like 0),
1163                  * to not fool net_rx_action() and its netdev_budget
1164                  */
1165                 if (done)
1166                         done--;
1167         }
1168         /* Done for now */
1169         if (napi_complete_done(napi, done))
1170                 mlx4_en_arm_cq(priv, cq);
1171         return done;
1172 }
1173
1174 static const int frag_sizes[] = {
1175         FRAG_SZ0,
1176         FRAG_SZ1,
1177         FRAG_SZ2,
1178         FRAG_SZ3
1179 };
1180
1181 void mlx4_en_calc_rx_buf(struct net_device *dev)
1182 {
1183         struct mlx4_en_priv *priv = netdev_priv(dev);
1184         int eff_mtu = MLX4_EN_EFF_MTU(dev->mtu);
1185         int i = 0;
1186
1187         /* bpf requires buffers to be set up as 1 packet per page.
1188          * This only works when num_frags == 1.
1189          */
1190         if (priv->tx_ring_num[TX_XDP]) {
1191                 priv->frag_info[0].order = 0;
1192                 priv->frag_info[0].frag_size = eff_mtu;
1193                 priv->frag_info[0].frag_prefix_size = 0;
1194                 /* This will gain efficient xdp frame recycling at the
1195                  * expense of more costly truesize accounting
1196                  */
1197                 priv->frag_info[0].frag_stride = PAGE_SIZE;
1198                 priv->frag_info[0].dma_dir = PCI_DMA_BIDIRECTIONAL;
1199                 priv->frag_info[0].rx_headroom = XDP_PACKET_HEADROOM;
1200                 i = 1;
1201         } else {
1202                 int buf_size = 0;
1203
1204                 while (buf_size < eff_mtu) {
1205                         priv->frag_info[i].order = MLX4_EN_ALLOC_PREFER_ORDER;
1206                         priv->frag_info[i].frag_size =
1207                                 (eff_mtu > buf_size + frag_sizes[i]) ?
1208                                         frag_sizes[i] : eff_mtu - buf_size;
1209                         priv->frag_info[i].frag_prefix_size = buf_size;
1210                         priv->frag_info[i].frag_stride =
1211                                 ALIGN(priv->frag_info[i].frag_size,
1212                                       SMP_CACHE_BYTES);
1213                         priv->frag_info[i].dma_dir = PCI_DMA_FROMDEVICE;
1214                         priv->frag_info[i].rx_headroom = 0;
1215                         buf_size += priv->frag_info[i].frag_size;
1216                         i++;
1217                 }
1218         }
1219
1220         priv->num_frags = i;
1221         priv->rx_skb_size = eff_mtu;
1222         priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc));
1223
1224         en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n",
1225                eff_mtu, priv->num_frags);
1226         for (i = 0; i < priv->num_frags; i++) {
1227                 en_err(priv,
1228                        "  frag:%d - size:%d prefix:%d stride:%d\n",
1229                        i,
1230                        priv->frag_info[i].frag_size,
1231                        priv->frag_info[i].frag_prefix_size,
1232                        priv->frag_info[i].frag_stride);
1233         }
1234 }
1235
1236 /* RSS related functions */
1237
1238 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
1239                                  struct mlx4_en_rx_ring *ring,
1240                                  enum mlx4_qp_state *state,
1241                                  struct mlx4_qp *qp)
1242 {
1243         struct mlx4_en_dev *mdev = priv->mdev;
1244         struct mlx4_qp_context *context;
1245         int err = 0;
1246
1247         context = kmalloc(sizeof(*context), GFP_KERNEL);
1248         if (!context)
1249                 return -ENOMEM;
1250
1251         err = mlx4_qp_alloc(mdev->dev, qpn, qp, GFP_KERNEL);
1252         if (err) {
1253                 en_err(priv, "Failed to allocate qp #%x\n", qpn);
1254                 goto out;
1255         }
1256         qp->event = mlx4_en_sqp_event;
1257
1258         memset(context, 0, sizeof *context);
1259         mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
1260                                 qpn, ring->cqn, -1, context);
1261         context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
1262
1263         /* Cancel FCS removal if FW allows */
1264         if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {
1265                 context->param3 |= cpu_to_be32(1 << 29);
1266                 if (priv->dev->features & NETIF_F_RXFCS)
1267                         ring->fcs_del = 0;
1268                 else
1269                         ring->fcs_del = ETH_FCS_LEN;
1270         } else
1271                 ring->fcs_del = 0;
1272
1273         err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
1274         if (err) {
1275                 mlx4_qp_remove(mdev->dev, qp);
1276                 mlx4_qp_free(mdev->dev, qp);
1277         }
1278         mlx4_en_update_rx_prod_db(ring);
1279 out:
1280         kfree(context);
1281         return err;
1282 }
1283
1284 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv)
1285 {
1286         int err;
1287         u32 qpn;
1288
1289         err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn,
1290                                     MLX4_RESERVE_A0_QP);
1291         if (err) {
1292                 en_err(priv, "Failed reserving drop qpn\n");
1293                 return err;
1294         }
1295         err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp, GFP_KERNEL);
1296         if (err) {
1297                 en_err(priv, "Failed allocating drop qp\n");
1298                 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1299                 return err;
1300         }
1301
1302         return 0;
1303 }
1304
1305 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv)
1306 {
1307         u32 qpn;
1308
1309         qpn = priv->drop_qp.qpn;
1310         mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp);
1311         mlx4_qp_free(priv->mdev->dev, &priv->drop_qp);
1312         mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1313 }
1314
1315 /* Allocate rx qp's and configure them according to rss map */
1316 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
1317 {
1318         struct mlx4_en_dev *mdev = priv->mdev;
1319         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1320         struct mlx4_qp_context context;
1321         struct mlx4_rss_context *rss_context;
1322         int rss_rings;
1323         void *ptr;
1324         u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |
1325                         MLX4_RSS_TCP_IPV6);
1326         int i, qpn;
1327         int err = 0;
1328         int good_qps = 0;
1329
1330         en_dbg(DRV, priv, "Configuring rss steering\n");
1331         err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
1332                                     priv->rx_ring_num,
1333                                     &rss_map->base_qpn, 0);
1334         if (err) {
1335                 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
1336                 return err;
1337         }
1338
1339         for (i = 0; i < priv->rx_ring_num; i++) {
1340                 qpn = rss_map->base_qpn + i;
1341                 err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i],
1342                                             &rss_map->state[i],
1343                                             &rss_map->qps[i]);
1344                 if (err)
1345                         goto rss_err;
1346
1347                 ++good_qps;
1348         }
1349
1350         /* Configure RSS indirection qp */
1351         err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp, GFP_KERNEL);
1352         if (err) {
1353                 en_err(priv, "Failed to allocate RSS indirection QP\n");
1354                 goto rss_err;
1355         }
1356         rss_map->indir_qp.event = mlx4_en_sqp_event;
1357         mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
1358                                 priv->rx_ring[0]->cqn, -1, &context);
1359
1360         if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num)
1361                 rss_rings = priv->rx_ring_num;
1362         else
1363                 rss_rings = priv->prof->rss_rings;
1364
1365         ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path)
1366                                         + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
1367         rss_context = ptr;
1368         rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 |
1369                                             (rss_map->base_qpn));
1370         rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
1371         if (priv->mdev->profile.udp_rss) {
1372                 rss_mask |=  MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;
1373                 rss_context->base_qpn_udp = rss_context->default_qpn;
1374         }
1375
1376         if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1377                 en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n");
1378                 rss_mask |= MLX4_RSS_BY_INNER_HEADERS;
1379         }
1380
1381         rss_context->flags = rss_mask;
1382         rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1383         if (priv->rss_hash_fn == ETH_RSS_HASH_XOR) {
1384                 rss_context->hash_fn = MLX4_RSS_HASH_XOR;
1385         } else if (priv->rss_hash_fn == ETH_RSS_HASH_TOP) {
1386                 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1387                 memcpy(rss_context->rss_key, priv->rss_key,
1388                        MLX4_EN_RSS_KEY_SIZE);
1389         } else {
1390                 en_err(priv, "Unknown RSS hash function requested\n");
1391                 err = -EINVAL;
1392                 goto indir_err;
1393         }
1394         err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
1395                                &rss_map->indir_qp, &rss_map->indir_state);
1396         if (err)
1397                 goto indir_err;
1398
1399         return 0;
1400
1401 indir_err:
1402         mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1403                        MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1404         mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1405         mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1406 rss_err:
1407         for (i = 0; i < good_qps; i++) {
1408                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1409                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1410                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1411                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1412         }
1413         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1414         return err;
1415 }
1416
1417 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
1418 {
1419         struct mlx4_en_dev *mdev = priv->mdev;
1420         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1421         int i;
1422
1423         mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1424                        MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1425         mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1426         mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1427
1428         for (i = 0; i < priv->rx_ring_num; i++) {
1429                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1430                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1431                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1432                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1433         }
1434         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1435 }