2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/bpf.h>
35 #include <linux/bpf_trace.h>
36 #include <linux/mlx4/cq.h>
37 #include <linux/slab.h>
38 #include <linux/mlx4/qp.h>
39 #include <linux/skbuff.h>
40 #include <linux/rculist.h>
41 #include <linux/if_ether.h>
42 #include <linux/if_vlan.h>
43 #include <linux/vmalloc.h>
44 #include <linux/irq.h>
47 #if IS_ENABLED(CONFIG_IPV6)
48 #include <net/ip6_checksum.h>
53 static int mlx4_alloc_page(struct mlx4_en_priv *priv,
54 struct mlx4_en_rx_alloc *frag,
60 page = alloc_page(gfp);
63 dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE, priv->dma_dir);
64 if (unlikely(dma_mapping_error(priv->ddev, dma))) {
70 frag->page_offset = priv->rx_headroom;
74 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv,
75 struct mlx4_en_rx_ring *ring,
76 struct mlx4_en_rx_desc *rx_desc,
77 struct mlx4_en_rx_alloc *frags,
82 for (i = 0; i < priv->num_frags; i++, frags++) {
84 if (mlx4_alloc_page(priv, frags, gfp))
86 ring->rx_alloc_pages++;
88 rx_desc->data[i].addr = cpu_to_be64(frags->dma +
94 static void mlx4_en_free_frag(const struct mlx4_en_priv *priv,
95 struct mlx4_en_rx_alloc *frag)
98 dma_unmap_page(priv->ddev, frag->dma,
99 PAGE_SIZE, priv->dma_dir);
100 __free_page(frag->page);
102 /* We need to clear all fields, otherwise a change of priv->log_rx_info
103 * could lead to see garbage later in frag->page.
105 memset(frag, 0, sizeof(*frag));
108 static void mlx4_en_init_rx_desc(const struct mlx4_en_priv *priv,
109 struct mlx4_en_rx_ring *ring, int index)
111 struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
115 /* Set size and memtype fields */
116 for (i = 0; i < priv->num_frags; i++) {
117 rx_desc->data[i].byte_count =
118 cpu_to_be32(priv->frag_info[i].frag_size);
119 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
122 /* If the number of used fragments does not fill up the ring stride,
123 * remaining (unused) fragments must be padded with null address/size
124 * and a special memory key */
125 possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
126 for (i = priv->num_frags; i < possible_frags; i++) {
127 rx_desc->data[i].byte_count = 0;
128 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
129 rx_desc->data[i].addr = 0;
133 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
134 struct mlx4_en_rx_ring *ring, int index,
137 struct mlx4_en_rx_desc *rx_desc = ring->buf +
138 (index << ring->log_stride);
139 struct mlx4_en_rx_alloc *frags = ring->rx_info +
140 (index << priv->log_rx_info);
141 if (likely(ring->page_cache.index > 0)) {
142 /* XDP uses a single page per frame */
144 ring->page_cache.index--;
145 frags->page = ring->page_cache.buf[ring->page_cache.index].page;
146 frags->dma = ring->page_cache.buf[ring->page_cache.index].dma;
148 frags->page_offset = XDP_PACKET_HEADROOM;
149 rx_desc->data[0].addr = cpu_to_be64(frags->dma +
150 XDP_PACKET_HEADROOM);
154 return mlx4_en_alloc_frags(priv, ring, rx_desc, frags, gfp);
157 static bool mlx4_en_is_ring_empty(const struct mlx4_en_rx_ring *ring)
159 return ring->prod == ring->cons;
162 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
164 *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
168 static void mlx4_en_free_rx_desc(const struct mlx4_en_priv *priv,
169 struct mlx4_en_rx_ring *ring,
172 struct mlx4_en_rx_alloc *frags;
175 frags = ring->rx_info + (index << priv->log_rx_info);
176 for (nr = 0; nr < priv->num_frags; nr++) {
177 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
178 mlx4_en_free_frag(priv, frags + nr);
182 /* Function not in fast-path */
183 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
185 struct mlx4_en_rx_ring *ring;
190 for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
191 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
192 ring = priv->rx_ring[ring_ind];
194 if (mlx4_en_prepare_rx_desc(priv, ring,
197 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
198 en_err(priv, "Failed to allocate enough rx buffers\n");
201 new_size = rounddown_pow_of_two(ring->actual_size);
202 en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n",
203 ring->actual_size, new_size);
214 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
215 ring = priv->rx_ring[ring_ind];
216 while (ring->actual_size > new_size) {
219 mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
226 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
227 struct mlx4_en_rx_ring *ring)
231 en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
232 ring->cons, ring->prod);
234 /* Unmap and free Rx buffers */
235 for (index = 0; index < ring->size; index++) {
236 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
237 mlx4_en_free_rx_desc(priv, ring, index);
243 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev)
248 struct mlx4_dev *dev = mdev->dev;
250 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {
251 num_of_eqs = max_t(int, MIN_RX_RINGS,
253 mlx4_get_eqs_per_port(mdev->dev, i),
256 num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS :
257 min_t(int, num_of_eqs, num_online_cpus());
258 mdev->profile.prof[i].rx_ring_num =
259 rounddown_pow_of_two(num_rx_rings);
263 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
264 struct mlx4_en_rx_ring **pring,
265 u32 size, u16 stride, int node, int queue_index)
267 struct mlx4_en_dev *mdev = priv->mdev;
268 struct mlx4_en_rx_ring *ring;
272 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
274 en_err(priv, "Failed to allocate RX ring structure\n");
281 ring->size_mask = size - 1;
282 ring->stride = stride;
283 ring->log_stride = ffs(ring->stride) - 1;
284 ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
286 if (xdp_rxq_info_reg(&ring->xdp_rxq, priv->dev, queue_index) < 0)
289 tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
290 sizeof(struct mlx4_en_rx_alloc));
291 ring->rx_info = kvzalloc_node(tmp, GFP_KERNEL, node);
292 if (!ring->rx_info) {
297 en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
300 /* Allocate HW buffers on provided NUMA node */
301 set_dev_node(&mdev->dev->persist->pdev->dev, node);
302 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
303 set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);
307 ring->buf = ring->wqres.buf.direct.buf;
309 ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter;
315 kvfree(ring->rx_info);
316 ring->rx_info = NULL;
318 xdp_rxq_info_unreg(&ring->xdp_rxq);
326 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
328 struct mlx4_en_rx_ring *ring;
332 int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
333 DS_SIZE * priv->num_frags);
335 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
336 ring = priv->rx_ring[ring_ind];
340 ring->actual_size = 0;
341 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn;
343 ring->stride = stride;
344 if (ring->stride <= TXBB_SIZE) {
345 /* Stamp first unused send wqe */
346 __be32 *ptr = (__be32 *)ring->buf;
347 __be32 stamp = cpu_to_be32(1 << STAMP_SHIFT);
349 /* Move pointer to start of rx section */
350 ring->buf += TXBB_SIZE;
353 ring->log_stride = ffs(ring->stride) - 1;
354 ring->buf_size = ring->size * ring->stride;
356 memset(ring->buf, 0, ring->buf_size);
357 mlx4_en_update_rx_prod_db(ring);
359 /* Initialize all descriptors */
360 for (i = 0; i < ring->size; i++)
361 mlx4_en_init_rx_desc(priv, ring, i);
363 err = mlx4_en_fill_rx_buffers(priv);
367 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
368 ring = priv->rx_ring[ring_ind];
370 ring->size_mask = ring->actual_size - 1;
371 mlx4_en_update_rx_prod_db(ring);
377 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
378 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]);
380 ring_ind = priv->rx_ring_num - 1;
381 while (ring_ind >= 0) {
382 if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE)
383 priv->rx_ring[ring_ind]->buf -= TXBB_SIZE;
389 /* We recover from out of memory by scheduling our napi poll
390 * function (mlx4_en_process_cq), which tries to allocate
391 * all missing RX buffers (call to mlx4_en_refill_rx_buffers).
393 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv)
400 for (ring = 0; ring < priv->rx_ring_num; ring++) {
401 if (mlx4_en_is_ring_empty(priv->rx_ring[ring])) {
403 napi_reschedule(&priv->rx_cq[ring]->napi);
409 /* When the rx ring is running in page-per-packet mode, a released frame can go
410 * directly into a small cache, to avoid unmapping or touching the page
411 * allocator. In bpf prog performance scenarios, buffers are either forwarded
412 * or dropped, never converted to skbs, so every page can come directly from
413 * this cache when it is sized to be a multiple of the napi budget.
415 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring,
416 struct mlx4_en_rx_alloc *frame)
418 struct mlx4_en_page_cache *cache = &ring->page_cache;
420 if (cache->index >= MLX4_EN_CACHE_SIZE)
423 cache->buf[cache->index].page = frame->page;
424 cache->buf[cache->index].dma = frame->dma;
429 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
430 struct mlx4_en_rx_ring **pring,
431 u32 size, u16 stride)
433 struct mlx4_en_dev *mdev = priv->mdev;
434 struct mlx4_en_rx_ring *ring = *pring;
435 struct bpf_prog *old_prog;
437 old_prog = rcu_dereference_protected(
439 lockdep_is_held(&mdev->state_lock));
441 bpf_prog_put(old_prog);
442 xdp_rxq_info_unreg(&ring->xdp_rxq);
443 mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE);
444 kvfree(ring->rx_info);
445 ring->rx_info = NULL;
450 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
451 struct mlx4_en_rx_ring *ring)
455 for (i = 0; i < ring->page_cache.index; i++) {
456 dma_unmap_page(priv->ddev, ring->page_cache.buf[i].dma,
457 PAGE_SIZE, priv->dma_dir);
458 put_page(ring->page_cache.buf[i].page);
460 ring->page_cache.index = 0;
461 mlx4_en_free_rx_buf(priv, ring);
462 if (ring->stride <= TXBB_SIZE)
463 ring->buf -= TXBB_SIZE;
467 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
468 struct mlx4_en_rx_alloc *frags,
472 const struct mlx4_en_frag_info *frag_info = priv->frag_info;
473 unsigned int truesize = 0;
479 /* Collect used fragments while replacing them in the HW descriptors */
480 for (nr = 0;; frags++) {
481 frag_size = min_t(int, length, frag_info->frag_size);
488 dma_sync_single_range_for_cpu(priv->ddev, dma, frags->page_offset,
489 frag_size, priv->dma_dir);
491 __skb_fill_page_desc(skb, nr, page, frags->page_offset,
494 truesize += frag_info->frag_stride;
495 if (frag_info->frag_stride == PAGE_SIZE / 2) {
496 frags->page_offset ^= PAGE_SIZE / 2;
497 release = page_count(page) != 1 ||
498 page_is_pfmemalloc(page) ||
499 page_to_nid(page) != numa_mem_id();
500 } else if (!priv->rx_headroom) {
501 /* rx_headroom for non XDP setup is always 0.
502 * When XDP is set, the above condition will
503 * guarantee page is always released.
505 u32 sz_align = ALIGN(frag_size, SMP_CACHE_BYTES);
507 frags->page_offset += sz_align;
508 release = frags->page_offset + frag_info->frag_size > PAGE_SIZE;
511 dma_unmap_page(priv->ddev, dma, PAGE_SIZE, priv->dma_dir);
523 skb->truesize += truesize;
529 __skb_frag_unref(skb_shinfo(skb)->frags + nr);
534 static void validate_loopback(struct mlx4_en_priv *priv, void *va)
536 const unsigned char *data = va + ETH_HLEN;
539 for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++) {
540 if (data[i] != (unsigned char)i)
544 priv->loopback_ok = 1;
547 static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv,
548 struct mlx4_en_rx_ring *ring)
550 u32 missing = ring->actual_size - (ring->prod - ring->cons);
552 /* Try to batch allocations, but not too much. */
556 if (mlx4_en_prepare_rx_desc(priv, ring,
557 ring->prod & ring->size_mask,
558 GFP_ATOMIC | __GFP_MEMALLOC))
561 } while (likely(--missing));
563 mlx4_en_update_rx_prod_db(ring);
566 /* When hardware doesn't strip the vlan, we need to calculate the checksum
567 * over it and add it to the hardware's checksum calculation
569 static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum,
570 struct vlan_hdr *vlanh)
572 return csum_add(hw_checksum, *(__wsum *)vlanh);
575 /* Although the stack expects checksum which doesn't include the pseudo
576 * header, the HW adds it. To address that, we are subtracting the pseudo
577 * header checksum from the checksum value provided by the HW.
579 static int get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb,
582 __u16 length_for_csum = 0;
583 __wsum csum_pseudo_header = 0;
584 __u8 ipproto = iph->protocol;
586 if (unlikely(ipproto == IPPROTO_SCTP))
589 length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2));
590 csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr,
591 length_for_csum, ipproto, 0);
592 skb->csum = csum_sub(hw_checksum, csum_pseudo_header);
596 #if IS_ENABLED(CONFIG_IPV6)
597 /* In IPv6 packets, hw_checksum lacks 6 bytes from IPv6 header:
598 * 4 first bytes : priority, version, flow_lbl
599 * and 2 additional bytes : nexthdr, hop_limit.
601 static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb,
602 struct ipv6hdr *ipv6h)
604 __u8 nexthdr = ipv6h->nexthdr;
607 if (unlikely(nexthdr == IPPROTO_FRAGMENT ||
608 nexthdr == IPPROTO_HOPOPTS ||
609 nexthdr == IPPROTO_SCTP))
612 /* priority, version, flow_lbl */
613 temp = csum_add(hw_checksum, *(__wsum *)ipv6h);
614 /* nexthdr and hop_limit */
615 skb->csum = csum_add(temp, (__force __wsum)*(__be16 *)&ipv6h->nexthdr);
620 #define short_frame(size) ((size) <= ETH_ZLEN + ETH_FCS_LEN)
622 /* We reach this function only after checking that any of
623 * the (IPv4 | IPv6) bits are set in cqe->status.
625 static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va,
626 netdev_features_t dev_features)
628 __wsum hw_checksum = 0;
631 /* CQE csum doesn't cover padding octets in short ethernet
632 * frames. And the pad field is appended prior to calculating
633 * and appending the FCS field.
635 * Detecting these padded frames requires to verify and parse
636 * IP headers, so we simply force all those small frames to skip
639 if (short_frame(skb->len))
642 hdr = (u8 *)va + sizeof(struct ethhdr);
643 hw_checksum = csum_unfold((__force __sum16)cqe->checksum);
645 if (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK) &&
646 !(dev_features & NETIF_F_HW_VLAN_CTAG_RX)) {
647 hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr);
648 hdr += sizeof(struct vlan_hdr);
651 #if IS_ENABLED(CONFIG_IPV6)
652 if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6))
653 return get_fixed_ipv6_csum(hw_checksum, skb, hdr);
655 return get_fixed_ipv4_csum(hw_checksum, skb, hdr);
658 #if IS_ENABLED(CONFIG_IPV6)
659 #define MLX4_CQE_STATUS_IP_ANY (MLX4_CQE_STATUS_IPV4 | MLX4_CQE_STATUS_IPV6)
661 #define MLX4_CQE_STATUS_IP_ANY (MLX4_CQE_STATUS_IPV4)
664 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
666 struct mlx4_en_priv *priv = netdev_priv(dev);
667 int factor = priv->cqe_factor;
668 struct mlx4_en_rx_ring *ring;
669 struct bpf_prog *xdp_prog;
670 int cq_ring = cq->ring;
671 bool doorbell_pending;
672 struct mlx4_cqe *cqe;
677 if (unlikely(!priv->port_up || budget <= 0))
680 ring = priv->rx_ring[cq_ring];
682 /* Protect accesses to: ring->xdp_prog, priv->mac_hash list */
684 xdp_prog = rcu_dereference(ring->xdp_prog);
685 xdp.rxq = &ring->xdp_rxq;
686 doorbell_pending = 0;
688 /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
689 * descriptor offset can be deduced from the CQE index instead of
690 * reading 'cqe->index' */
691 index = cq->mcq.cons_index & ring->size_mask;
692 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
694 /* Process all completed CQEs */
695 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
696 cq->mcq.cons_index & cq->size)) {
697 struct mlx4_en_rx_alloc *frags;
698 enum pkt_hash_types hash_type;
705 frags = ring->rx_info + (index << priv->log_rx_info);
706 va = page_address(frags[0].page) + frags[0].page_offset;
709 * make sure we read the CQE after we read the ownership bit
713 /* Drop packet on bad receive or bad checksum */
714 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
715 MLX4_CQE_OPCODE_ERROR)) {
716 en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n",
717 ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome,
718 ((struct mlx4_err_cqe *)cqe)->syndrome);
721 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
722 en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
726 /* Check if we need to drop the packet if SRIOV is not enabled
727 * and not performing the selftest or flb disabled
729 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) {
730 const struct ethhdr *ethh = va;
732 /* Get pointer to first fragment since we haven't
733 * skb yet and cast it to ethhdr struct
735 dma = frags[0].dma + frags[0].page_offset;
736 dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh),
739 if (is_multicast_ether_addr(ethh->h_dest)) {
740 struct mlx4_mac_entry *entry;
741 struct hlist_head *bucket;
742 unsigned int mac_hash;
744 /* Drop the packet, since HW loopback-ed it */
745 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX];
746 bucket = &priv->mac_hash[mac_hash];
747 hlist_for_each_entry_rcu(entry, bucket, hlist) {
748 if (ether_addr_equal_64bits(entry->mac,
755 if (unlikely(priv->validate_loopback)) {
756 validate_loopback(priv, va);
761 * Packet is OK - process it.
763 length = be32_to_cpu(cqe->byte_cnt);
764 length -= ring->fcs_del;
766 /* A bpf program gets first chance to drop the packet. It may
767 * read bytes but not past the end of the frag.
774 dma = frags[0].dma + frags[0].page_offset;
775 dma_sync_single_for_cpu(priv->ddev, dma,
776 priv->frag_info[0].frag_size,
779 xdp.data_hard_start = va - frags[0].page_offset;
781 xdp_set_data_meta_invalid(&xdp);
782 xdp.data_end = xdp.data + length;
783 orig_data = xdp.data;
785 act = bpf_prog_run_xdp(xdp_prog, &xdp);
787 length = xdp.data_end - xdp.data;
788 if (xdp.data != orig_data) {
789 frags[0].page_offset = xdp.data -
798 if (likely(!mlx4_en_xmit_frame(ring, frags, priv,
800 &doorbell_pending))) {
801 frags[0].page = NULL;
804 trace_xdp_exception(dev, xdp_prog, act);
805 goto xdp_drop_no_cnt; /* Drop on xmit failure */
807 bpf_warn_invalid_xdp_action(act);
810 trace_xdp_exception(dev, xdp_prog, act);
819 ring->bytes += length;
822 skb = napi_get_frags(&cq->napi);
826 if (unlikely(ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL)) {
827 u64 timestamp = mlx4_en_get_cqe_ts(cqe);
829 mlx4_en_fill_hwtstamps(priv->mdev, skb_hwtstamps(skb),
832 skb_record_rx_queue(skb, cq_ring);
834 if (likely(dev->features & NETIF_F_RXCSUM)) {
835 /* TODO: For IP non TCP/UDP packets when csum complete is
836 * not an option (not supported or any other reason) we can
837 * actually check cqe IPOK status bit and report
838 * CHECKSUM_UNNECESSARY rather than CHECKSUM_NONE
840 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP |
841 MLX4_CQE_STATUS_UDP)) &&
842 (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
843 cqe->checksum == cpu_to_be16(0xffff)) {
846 l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) &&
847 (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL));
848 ip_summed = CHECKSUM_UNNECESSARY;
849 hash_type = PKT_HASH_TYPE_L4;
854 if (!(priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP &&
855 (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IP_ANY))))
857 if (check_csum(cqe, skb, va, dev->features))
859 ip_summed = CHECKSUM_COMPLETE;
860 hash_type = PKT_HASH_TYPE_L3;
861 ring->csum_complete++;
865 ip_summed = CHECKSUM_NONE;
866 hash_type = PKT_HASH_TYPE_L3;
869 skb->ip_summed = ip_summed;
870 if (dev->features & NETIF_F_RXHASH)
872 be32_to_cpu(cqe->immed_rss_invalid),
875 if ((cqe->vlan_my_qpn &
876 cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK)) &&
877 (dev->features & NETIF_F_HW_VLAN_CTAG_RX))
878 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
879 be16_to_cpu(cqe->sl_vid));
880 else if ((cqe->vlan_my_qpn &
881 cpu_to_be32(MLX4_CQE_SVLAN_PRESENT_MASK)) &&
882 (dev->features & NETIF_F_HW_VLAN_STAG_RX))
883 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD),
884 be16_to_cpu(cqe->sl_vid));
886 nr = mlx4_en_complete_rx_desc(priv, frags, skb, length);
888 skb_shinfo(skb)->nr_frags = nr;
890 skb->data_len = length;
891 napi_gro_frags(&cq->napi);
893 __vlan_hwaccel_clear_tag(skb);
897 ++cq->mcq.cons_index;
898 index = (cq->mcq.cons_index) & ring->size_mask;
899 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
900 if (unlikely(++polled == budget))
906 if (likely(polled)) {
907 if (doorbell_pending) {
908 priv->tx_cq[TX_XDP][cq_ring]->xdp_busy = true;
909 mlx4_en_xmit_doorbell(priv->tx_ring[TX_XDP][cq_ring]);
912 mlx4_cq_set_ci(&cq->mcq);
913 wmb(); /* ensure HW sees CQ consumer before we post new buffers */
914 ring->cons = cq->mcq.cons_index;
916 AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
918 mlx4_en_refill_rx_buffers(priv, ring);
924 void mlx4_en_rx_irq(struct mlx4_cq *mcq)
926 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
927 struct mlx4_en_priv *priv = netdev_priv(cq->dev);
929 if (likely(priv->port_up))
930 napi_schedule_irqoff(&cq->napi);
932 mlx4_en_arm_cq(priv, cq);
935 /* Rx CQ polling - called by NAPI */
936 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
938 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
939 struct net_device *dev = cq->dev;
940 struct mlx4_en_priv *priv = netdev_priv(dev);
941 struct mlx4_en_cq *xdp_tx_cq = NULL;
942 bool clean_complete = true;
945 if (priv->tx_ring_num[TX_XDP]) {
946 xdp_tx_cq = priv->tx_cq[TX_XDP][cq->ring];
947 if (xdp_tx_cq->xdp_busy) {
948 clean_complete = mlx4_en_process_tx_cq(dev, xdp_tx_cq,
950 xdp_tx_cq->xdp_busy = !clean_complete;
954 done = mlx4_en_process_rx_cq(dev, cq, budget);
956 /* If we used up all the quota - we're probably not done yet... */
957 if (done == budget || !clean_complete) {
958 const struct cpumask *aff;
959 struct irq_data *idata;
962 /* in case we got here because of !clean_complete */
965 INC_PERF_COUNTER(priv->pstats.napi_quota);
967 cpu_curr = smp_processor_id();
968 idata = irq_desc_get_irq_data(cq->irq_desc);
969 aff = irq_data_get_affinity_mask(idata);
971 if (likely(cpumask_test_cpu(cpu_curr, aff)))
974 /* Current cpu is not according to smp_irq_affinity -
975 * probably affinity changed. Need to stop this NAPI
976 * poll, and restart it on the right CPU.
977 * Try to avoid returning a too small value (like 0),
978 * to not fool net_rx_action() and its netdev_budget
984 if (likely(napi_complete_done(napi, done)))
985 mlx4_en_arm_cq(priv, cq);
989 void mlx4_en_calc_rx_buf(struct net_device *dev)
991 struct mlx4_en_priv *priv = netdev_priv(dev);
992 int eff_mtu = MLX4_EN_EFF_MTU(dev->mtu);
995 /* bpf requires buffers to be set up as 1 packet per page.
996 * This only works when num_frags == 1.
998 if (priv->tx_ring_num[TX_XDP]) {
999 priv->frag_info[0].frag_size = eff_mtu;
1000 /* This will gain efficient xdp frame recycling at the
1001 * expense of more costly truesize accounting
1003 priv->frag_info[0].frag_stride = PAGE_SIZE;
1004 priv->dma_dir = PCI_DMA_BIDIRECTIONAL;
1005 priv->rx_headroom = XDP_PACKET_HEADROOM;
1008 int frag_size_max = 2048, buf_size = 0;
1010 /* should not happen, right ? */
1011 if (eff_mtu > PAGE_SIZE + (MLX4_EN_MAX_RX_FRAGS - 1) * 2048)
1012 frag_size_max = PAGE_SIZE;
1014 while (buf_size < eff_mtu) {
1015 int frag_stride, frag_size = eff_mtu - buf_size;
1018 if (i < MLX4_EN_MAX_RX_FRAGS - 1)
1019 frag_size = min(frag_size, frag_size_max);
1021 priv->frag_info[i].frag_size = frag_size;
1022 frag_stride = ALIGN(frag_size, SMP_CACHE_BYTES);
1023 /* We can only pack 2 1536-bytes frames in on 4K page
1024 * Therefore, each frame would consume more bytes (truesize)
1026 nb = PAGE_SIZE / frag_stride;
1027 pad = (PAGE_SIZE - nb * frag_stride) / nb;
1028 pad &= ~(SMP_CACHE_BYTES - 1);
1029 priv->frag_info[i].frag_stride = frag_stride + pad;
1031 buf_size += frag_size;
1034 priv->dma_dir = PCI_DMA_FROMDEVICE;
1035 priv->rx_headroom = 0;
1038 priv->num_frags = i;
1039 priv->rx_skb_size = eff_mtu;
1040 priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc));
1042 en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n",
1043 eff_mtu, priv->num_frags);
1044 for (i = 0; i < priv->num_frags; i++) {
1047 " frag:%d - size:%d stride:%d\n",
1049 priv->frag_info[i].frag_size,
1050 priv->frag_info[i].frag_stride);
1054 /* RSS related functions */
1056 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
1057 struct mlx4_en_rx_ring *ring,
1058 enum mlx4_qp_state *state,
1061 struct mlx4_en_dev *mdev = priv->mdev;
1062 struct mlx4_qp_context *context;
1065 context = kmalloc(sizeof(*context), GFP_KERNEL);
1069 err = mlx4_qp_alloc(mdev->dev, qpn, qp);
1071 en_err(priv, "Failed to allocate qp #%x\n", qpn);
1074 qp->event = mlx4_en_sqp_event;
1076 memset(context, 0, sizeof(*context));
1077 mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
1078 qpn, ring->cqn, -1, context);
1079 context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
1081 /* Cancel FCS removal if FW allows */
1082 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {
1083 context->param3 |= cpu_to_be32(1 << 29);
1084 if (priv->dev->features & NETIF_F_RXFCS)
1087 ring->fcs_del = ETH_FCS_LEN;
1091 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
1093 mlx4_qp_remove(mdev->dev, qp);
1094 mlx4_qp_free(mdev->dev, qp);
1096 mlx4_en_update_rx_prod_db(ring);
1102 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv)
1107 err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn,
1109 MLX4_RES_USAGE_DRIVER);
1111 en_err(priv, "Failed reserving drop qpn\n");
1114 err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp);
1116 en_err(priv, "Failed allocating drop qp\n");
1117 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1124 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv)
1128 qpn = priv->drop_qp.qpn;
1129 mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp);
1130 mlx4_qp_free(priv->mdev->dev, &priv->drop_qp);
1131 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1134 /* Allocate rx qp's and configure them according to rss map */
1135 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
1137 struct mlx4_en_dev *mdev = priv->mdev;
1138 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1139 struct mlx4_qp_context context;
1140 struct mlx4_rss_context *rss_context;
1143 u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |
1150 en_dbg(DRV, priv, "Configuring rss steering\n");
1152 flags = priv->rx_ring_num == 1 ? MLX4_RESERVE_A0_QP : 0;
1153 err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
1155 &rss_map->base_qpn, flags,
1156 MLX4_RES_USAGE_DRIVER);
1158 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
1162 for (i = 0; i < priv->rx_ring_num; i++) {
1163 qpn = rss_map->base_qpn + i;
1164 err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i],
1173 if (priv->rx_ring_num == 1) {
1174 rss_map->indir_qp = &rss_map->qps[0];
1175 priv->base_qpn = rss_map->indir_qp->qpn;
1176 en_info(priv, "Optimized Non-RSS steering\n");
1180 rss_map->indir_qp = kzalloc(sizeof(*rss_map->indir_qp), GFP_KERNEL);
1181 if (!rss_map->indir_qp) {
1186 /* Configure RSS indirection qp */
1187 err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, rss_map->indir_qp);
1189 en_err(priv, "Failed to allocate RSS indirection QP\n");
1193 rss_map->indir_qp->event = mlx4_en_sqp_event;
1194 mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
1195 priv->rx_ring[0]->cqn, -1, &context);
1197 if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num)
1198 rss_rings = priv->rx_ring_num;
1200 rss_rings = priv->prof->rss_rings;
1202 ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path)
1203 + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
1205 rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 |
1206 (rss_map->base_qpn));
1207 rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
1208 if (priv->mdev->profile.udp_rss) {
1209 rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;
1210 rss_context->base_qpn_udp = rss_context->default_qpn;
1213 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1214 en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n");
1215 rss_mask |= MLX4_RSS_BY_INNER_HEADERS;
1218 rss_context->flags = rss_mask;
1219 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1220 if (priv->rss_hash_fn == ETH_RSS_HASH_XOR) {
1221 rss_context->hash_fn = MLX4_RSS_HASH_XOR;
1222 } else if (priv->rss_hash_fn == ETH_RSS_HASH_TOP) {
1223 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1224 memcpy(rss_context->rss_key, priv->rss_key,
1225 MLX4_EN_RSS_KEY_SIZE);
1227 en_err(priv, "Unknown RSS hash function requested\n");
1232 err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
1233 rss_map->indir_qp, &rss_map->indir_state);
1240 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1241 MLX4_QP_STATE_RST, NULL, 0, 0, rss_map->indir_qp);
1242 mlx4_qp_remove(mdev->dev, rss_map->indir_qp);
1243 mlx4_qp_free(mdev->dev, rss_map->indir_qp);
1245 kfree(rss_map->indir_qp);
1246 rss_map->indir_qp = NULL;
1248 for (i = 0; i < good_qps; i++) {
1249 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1250 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1251 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1252 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1254 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1258 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
1260 struct mlx4_en_dev *mdev = priv->mdev;
1261 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1264 if (priv->rx_ring_num > 1) {
1265 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1266 MLX4_QP_STATE_RST, NULL, 0, 0,
1268 mlx4_qp_remove(mdev->dev, rss_map->indir_qp);
1269 mlx4_qp_free(mdev->dev, rss_map->indir_qp);
1270 kfree(rss_map->indir_qp);
1271 rss_map->indir_qp = NULL;
1274 for (i = 0; i < priv->rx_ring_num; i++) {
1275 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1276 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1277 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1278 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1280 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);