2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <net/busy_poll.h>
35 #include <linux/bpf.h>
36 #include <linux/bpf_trace.h>
37 #include <linux/mlx4/cq.h>
38 #include <linux/slab.h>
39 #include <linux/mlx4/qp.h>
40 #include <linux/skbuff.h>
41 #include <linux/rculist.h>
42 #include <linux/if_ether.h>
43 #include <linux/if_vlan.h>
44 #include <linux/vmalloc.h>
45 #include <linux/irq.h>
47 #if IS_ENABLED(CONFIG_IPV6)
48 #include <net/ip6_checksum.h>
53 static int mlx4_alloc_page(struct mlx4_en_priv *priv,
54 struct mlx4_en_rx_alloc *frag,
60 page = alloc_page(gfp);
63 dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE, priv->dma_dir);
64 if (unlikely(dma_mapping_error(priv->ddev, dma))) {
70 frag->page_offset = priv->rx_headroom;
74 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv,
75 struct mlx4_en_rx_ring *ring,
76 struct mlx4_en_rx_desc *rx_desc,
77 struct mlx4_en_rx_alloc *frags,
82 for (i = 0; i < priv->num_frags; i++, frags++) {
84 if (mlx4_alloc_page(priv, frags, gfp))
86 ring->rx_alloc_pages++;
88 rx_desc->data[i].addr = cpu_to_be64(frags->dma +
94 static void mlx4_en_free_frag(const struct mlx4_en_priv *priv,
95 struct mlx4_en_rx_alloc *frag)
98 dma_unmap_page(priv->ddev, frag->dma,
99 PAGE_SIZE, priv->dma_dir);
100 __free_page(frag->page);
102 /* We need to clear all fields, otherwise a change of priv->log_rx_info
103 * could lead to see garbage later in frag->page.
105 memset(frag, 0, sizeof(*frag));
108 static void mlx4_en_init_rx_desc(const struct mlx4_en_priv *priv,
109 struct mlx4_en_rx_ring *ring, int index)
111 struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
115 /* Set size and memtype fields */
116 for (i = 0; i < priv->num_frags; i++) {
117 rx_desc->data[i].byte_count =
118 cpu_to_be32(priv->frag_info[i].frag_size);
119 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
122 /* If the number of used fragments does not fill up the ring stride,
123 * remaining (unused) fragments must be padded with null address/size
124 * and a special memory key */
125 possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
126 for (i = priv->num_frags; i < possible_frags; i++) {
127 rx_desc->data[i].byte_count = 0;
128 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
129 rx_desc->data[i].addr = 0;
133 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
134 struct mlx4_en_rx_ring *ring, int index,
137 struct mlx4_en_rx_desc *rx_desc = ring->buf +
138 (index << ring->log_stride);
139 struct mlx4_en_rx_alloc *frags = ring->rx_info +
140 (index << priv->log_rx_info);
141 if (likely(ring->page_cache.index > 0)) {
142 /* XDP uses a single page per frame */
144 ring->page_cache.index--;
145 frags->page = ring->page_cache.buf[ring->page_cache.index].page;
146 frags->dma = ring->page_cache.buf[ring->page_cache.index].dma;
148 frags->page_offset = XDP_PACKET_HEADROOM;
149 rx_desc->data[0].addr = cpu_to_be64(frags->dma +
150 XDP_PACKET_HEADROOM);
154 return mlx4_en_alloc_frags(priv, ring, rx_desc, frags, gfp);
157 static bool mlx4_en_is_ring_empty(const struct mlx4_en_rx_ring *ring)
159 return ring->prod == ring->cons;
162 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
164 *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
168 static void mlx4_en_free_rx_desc(const struct mlx4_en_priv *priv,
169 struct mlx4_en_rx_ring *ring,
172 struct mlx4_en_rx_alloc *frags;
175 frags = ring->rx_info + (index << priv->log_rx_info);
176 for (nr = 0; nr < priv->num_frags; nr++) {
177 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
178 mlx4_en_free_frag(priv, frags + nr);
182 /* Function not in fast-path */
183 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
185 struct mlx4_en_rx_ring *ring;
190 for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
191 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
192 ring = priv->rx_ring[ring_ind];
194 if (mlx4_en_prepare_rx_desc(priv, ring,
196 GFP_KERNEL | __GFP_COLD)) {
197 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
198 en_err(priv, "Failed to allocate enough rx buffers\n");
201 new_size = rounddown_pow_of_two(ring->actual_size);
202 en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n",
203 ring->actual_size, new_size);
214 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
215 ring = priv->rx_ring[ring_ind];
216 while (ring->actual_size > new_size) {
219 mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
226 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
227 struct mlx4_en_rx_ring *ring)
231 en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
232 ring->cons, ring->prod);
234 /* Unmap and free Rx buffers */
235 for (index = 0; index < ring->size; index++) {
236 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
237 mlx4_en_free_rx_desc(priv, ring, index);
243 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev)
248 struct mlx4_dev *dev = mdev->dev;
250 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {
251 num_of_eqs = max_t(int, MIN_RX_RINGS,
253 mlx4_get_eqs_per_port(mdev->dev, i),
256 num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS :
257 min_t(int, num_of_eqs,
258 netif_get_num_default_rss_queues());
259 mdev->profile.prof[i].rx_ring_num =
260 rounddown_pow_of_two(num_rx_rings);
264 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
265 struct mlx4_en_rx_ring **pring,
266 u32 size, u16 stride, int node)
268 struct mlx4_en_dev *mdev = priv->mdev;
269 struct mlx4_en_rx_ring *ring;
273 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
275 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
277 en_err(priv, "Failed to allocate RX ring structure\n");
285 ring->size_mask = size - 1;
286 ring->stride = stride;
287 ring->log_stride = ffs(ring->stride) - 1;
288 ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
290 tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
291 sizeof(struct mlx4_en_rx_alloc));
292 ring->rx_info = vzalloc_node(tmp, node);
293 if (!ring->rx_info) {
294 ring->rx_info = vzalloc(tmp);
295 if (!ring->rx_info) {
301 en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
304 /* Allocate HW buffers on provided NUMA node */
305 set_dev_node(&mdev->dev->persist->pdev->dev, node);
306 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
307 set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);
311 ring->buf = ring->wqres.buf.direct.buf;
313 ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter;
319 vfree(ring->rx_info);
320 ring->rx_info = NULL;
328 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
330 struct mlx4_en_rx_ring *ring;
334 int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
335 DS_SIZE * priv->num_frags);
337 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
338 ring = priv->rx_ring[ring_ind];
342 ring->actual_size = 0;
343 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn;
345 ring->stride = stride;
346 if (ring->stride <= TXBB_SIZE) {
347 /* Stamp first unused send wqe */
348 __be32 *ptr = (__be32 *)ring->buf;
349 __be32 stamp = cpu_to_be32(1 << STAMP_SHIFT);
351 /* Move pointer to start of rx section */
352 ring->buf += TXBB_SIZE;
355 ring->log_stride = ffs(ring->stride) - 1;
356 ring->buf_size = ring->size * ring->stride;
358 memset(ring->buf, 0, ring->buf_size);
359 mlx4_en_update_rx_prod_db(ring);
361 /* Initialize all descriptors */
362 for (i = 0; i < ring->size; i++)
363 mlx4_en_init_rx_desc(priv, ring, i);
365 err = mlx4_en_fill_rx_buffers(priv);
369 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
370 ring = priv->rx_ring[ring_ind];
372 ring->size_mask = ring->actual_size - 1;
373 mlx4_en_update_rx_prod_db(ring);
379 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
380 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]);
382 ring_ind = priv->rx_ring_num - 1;
383 while (ring_ind >= 0) {
384 if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE)
385 priv->rx_ring[ring_ind]->buf -= TXBB_SIZE;
391 /* We recover from out of memory by scheduling our napi poll
392 * function (mlx4_en_process_cq), which tries to allocate
393 * all missing RX buffers (call to mlx4_en_refill_rx_buffers).
395 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv)
402 for (ring = 0; ring < priv->rx_ring_num; ring++) {
403 if (mlx4_en_is_ring_empty(priv->rx_ring[ring])) {
405 napi_reschedule(&priv->rx_cq[ring]->napi);
411 /* When the rx ring is running in page-per-packet mode, a released frame can go
412 * directly into a small cache, to avoid unmapping or touching the page
413 * allocator. In bpf prog performance scenarios, buffers are either forwarded
414 * or dropped, never converted to skbs, so every page can come directly from
415 * this cache when it is sized to be a multiple of the napi budget.
417 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring,
418 struct mlx4_en_rx_alloc *frame)
420 struct mlx4_en_page_cache *cache = &ring->page_cache;
422 if (cache->index >= MLX4_EN_CACHE_SIZE)
425 cache->buf[cache->index].page = frame->page;
426 cache->buf[cache->index].dma = frame->dma;
431 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
432 struct mlx4_en_rx_ring **pring,
433 u32 size, u16 stride)
435 struct mlx4_en_dev *mdev = priv->mdev;
436 struct mlx4_en_rx_ring *ring = *pring;
437 struct bpf_prog *old_prog;
439 old_prog = rcu_dereference_protected(
441 lockdep_is_held(&mdev->state_lock));
443 bpf_prog_put(old_prog);
444 mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE);
445 vfree(ring->rx_info);
446 ring->rx_info = NULL;
451 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
452 struct mlx4_en_rx_ring *ring)
456 for (i = 0; i < ring->page_cache.index; i++) {
457 dma_unmap_page(priv->ddev, ring->page_cache.buf[i].dma,
458 PAGE_SIZE, priv->dma_dir);
459 put_page(ring->page_cache.buf[i].page);
461 ring->page_cache.index = 0;
462 mlx4_en_free_rx_buf(priv, ring);
463 if (ring->stride <= TXBB_SIZE)
464 ring->buf -= TXBB_SIZE;
468 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
469 struct mlx4_en_rx_alloc *frags,
473 const struct mlx4_en_frag_info *frag_info = priv->frag_info;
474 unsigned int truesize = 0;
480 /* Collect used fragments while replacing them in the HW descriptors */
481 for (nr = 0;; frags++) {
482 frag_size = min_t(int, length, frag_info->frag_size);
489 dma_sync_single_range_for_cpu(priv->ddev, dma, frags->page_offset,
490 frag_size, priv->dma_dir);
492 __skb_fill_page_desc(skb, nr, page, frags->page_offset,
495 truesize += frag_info->frag_stride;
496 if (frag_info->frag_stride == PAGE_SIZE / 2) {
497 frags->page_offset ^= PAGE_SIZE / 2;
498 release = page_count(page) != 1 ||
499 page_is_pfmemalloc(page) ||
500 page_to_nid(page) != numa_mem_id();
502 u32 sz_align = ALIGN(frag_size, SMP_CACHE_BYTES);
504 frags->page_offset += sz_align;
505 release = frags->page_offset + frag_info->frag_size > PAGE_SIZE;
508 dma_unmap_page(priv->ddev, dma, PAGE_SIZE, priv->dma_dir);
520 skb->truesize += truesize;
526 __skb_frag_unref(skb_shinfo(skb)->frags + nr);
531 static void validate_loopback(struct mlx4_en_priv *priv, void *va)
533 const unsigned char *data = va + ETH_HLEN;
536 for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++) {
537 if (data[i] != (unsigned char)i)
541 priv->loopback_ok = 1;
544 static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv,
545 struct mlx4_en_rx_ring *ring)
547 u32 missing = ring->actual_size - (ring->prod - ring->cons);
549 /* Try to batch allocations, but not too much. */
553 if (mlx4_en_prepare_rx_desc(priv, ring,
554 ring->prod & ring->size_mask,
555 GFP_ATOMIC | __GFP_COLD |
559 } while (likely(--missing));
561 mlx4_en_update_rx_prod_db(ring);
564 /* When hardware doesn't strip the vlan, we need to calculate the checksum
565 * over it and add it to the hardware's checksum calculation
567 static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum,
568 struct vlan_hdr *vlanh)
570 return csum_add(hw_checksum, *(__wsum *)vlanh);
573 /* Although the stack expects checksum which doesn't include the pseudo
574 * header, the HW adds it. To address that, we are subtracting the pseudo
575 * header checksum from the checksum value provided by the HW.
577 static void get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb,
580 __u16 length_for_csum = 0;
581 __wsum csum_pseudo_header = 0;
583 length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2));
584 csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr,
585 length_for_csum, iph->protocol, 0);
586 skb->csum = csum_sub(hw_checksum, csum_pseudo_header);
589 #if IS_ENABLED(CONFIG_IPV6)
590 /* In IPv6 packets, besides subtracting the pseudo header checksum,
591 * we also compute/add the IP header checksum which
592 * is not added by the HW.
594 static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb,
595 struct ipv6hdr *ipv6h)
597 __wsum csum_pseudo_hdr = 0;
599 if (unlikely(ipv6h->nexthdr == IPPROTO_FRAGMENT ||
600 ipv6h->nexthdr == IPPROTO_HOPOPTS))
602 hw_checksum = csum_add(hw_checksum, (__force __wsum)htons(ipv6h->nexthdr));
604 csum_pseudo_hdr = csum_partial(&ipv6h->saddr,
605 sizeof(ipv6h->saddr) + sizeof(ipv6h->daddr), 0);
606 csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ipv6h->payload_len);
607 csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ntohs(ipv6h->nexthdr));
609 skb->csum = csum_sub(hw_checksum, csum_pseudo_hdr);
610 skb->csum = csum_add(skb->csum, csum_partial(ipv6h, sizeof(struct ipv6hdr), 0));
614 static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va,
615 netdev_features_t dev_features)
617 __wsum hw_checksum = 0;
619 void *hdr = (u8 *)va + sizeof(struct ethhdr);
621 hw_checksum = csum_unfold((__force __sum16)cqe->checksum);
623 if (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK) &&
624 !(dev_features & NETIF_F_HW_VLAN_CTAG_RX)) {
625 hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr);
626 hdr += sizeof(struct vlan_hdr);
629 if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4))
630 get_fixed_ipv4_csum(hw_checksum, skb, hdr);
631 #if IS_ENABLED(CONFIG_IPV6)
632 else if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6))
633 if (unlikely(get_fixed_ipv6_csum(hw_checksum, skb, hdr)))
639 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
641 struct mlx4_en_priv *priv = netdev_priv(dev);
642 int factor = priv->cqe_factor;
643 struct mlx4_en_rx_ring *ring;
644 struct bpf_prog *xdp_prog;
645 int cq_ring = cq->ring;
646 bool doorbell_pending;
647 struct mlx4_cqe *cqe;
651 if (unlikely(!priv->port_up))
654 if (unlikely(budget <= 0))
657 ring = priv->rx_ring[cq_ring];
659 /* Protect accesses to: ring->xdp_prog, priv->mac_hash list */
661 xdp_prog = rcu_dereference(ring->xdp_prog);
662 doorbell_pending = 0;
664 /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
665 * descriptor offset can be deduced from the CQE index instead of
666 * reading 'cqe->index' */
667 index = cq->mcq.cons_index & ring->size_mask;
668 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
670 /* Process all completed CQEs */
671 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
672 cq->mcq.cons_index & cq->size)) {
673 struct mlx4_en_rx_alloc *frags;
674 enum pkt_hash_types hash_type;
681 frags = ring->rx_info + (index << priv->log_rx_info);
682 va = page_address(frags[0].page) + frags[0].page_offset;
685 * make sure we read the CQE after we read the ownership bit
689 /* Drop packet on bad receive or bad checksum */
690 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
691 MLX4_CQE_OPCODE_ERROR)) {
692 en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n",
693 ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome,
694 ((struct mlx4_err_cqe *)cqe)->syndrome);
697 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
698 en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
702 /* Check if we need to drop the packet if SRIOV is not enabled
703 * and not performing the selftest or flb disabled
705 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) {
706 const struct ethhdr *ethh = va;
708 /* Get pointer to first fragment since we haven't
709 * skb yet and cast it to ethhdr struct
711 dma = frags[0].dma + frags[0].page_offset;
712 dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh),
715 if (is_multicast_ether_addr(ethh->h_dest)) {
716 struct mlx4_mac_entry *entry;
717 struct hlist_head *bucket;
718 unsigned int mac_hash;
720 /* Drop the packet, since HW loopback-ed it */
721 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX];
722 bucket = &priv->mac_hash[mac_hash];
723 hlist_for_each_entry_rcu(entry, bucket, hlist) {
724 if (ether_addr_equal_64bits(entry->mac,
731 if (unlikely(priv->validate_loopback)) {
732 validate_loopback(priv, va);
737 * Packet is OK - process it.
739 length = be32_to_cpu(cqe->byte_cnt);
740 length -= ring->fcs_del;
742 /* A bpf program gets first chance to drop the packet. It may
743 * read bytes but not past the end of the frag.
751 dma = frags[0].dma + frags[0].page_offset;
752 dma_sync_single_for_cpu(priv->ddev, dma,
753 priv->frag_info[0].frag_size,
756 xdp.data_hard_start = va - frags[0].page_offset;
758 xdp.data_end = xdp.data + length;
759 orig_data = xdp.data;
761 act = bpf_prog_run_xdp(xdp_prog, &xdp);
763 if (xdp.data != orig_data) {
764 length = xdp.data_end - xdp.data;
765 frags[0].page_offset = xdp.data -
774 if (likely(!mlx4_en_xmit_frame(ring, frags, dev,
776 &doorbell_pending))) {
777 frags[0].page = NULL;
780 trace_xdp_exception(dev, xdp_prog, act);
781 goto xdp_drop_no_cnt; /* Drop on xmit failure */
783 bpf_warn_invalid_xdp_action(act);
785 trace_xdp_exception(dev, xdp_prog, act);
793 ring->bytes += length;
796 skb = napi_get_frags(&cq->napi);
800 if (unlikely(ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL)) {
801 u64 timestamp = mlx4_en_get_cqe_ts(cqe);
803 mlx4_en_fill_hwtstamps(priv->mdev, skb_hwtstamps(skb),
806 skb_record_rx_queue(skb, cq_ring);
808 if (likely(dev->features & NETIF_F_RXCSUM)) {
809 if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP |
810 MLX4_CQE_STATUS_UDP)) {
811 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
812 cqe->checksum == cpu_to_be16(0xffff)) {
813 bool l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) &&
814 (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL));
816 ip_summed = CHECKSUM_UNNECESSARY;
817 hash_type = PKT_HASH_TYPE_L4;
825 if (priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP &&
826 (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
827 MLX4_CQE_STATUS_IPV6))) {
828 if (check_csum(cqe, skb, va, dev->features)) {
831 ip_summed = CHECKSUM_COMPLETE;
832 hash_type = PKT_HASH_TYPE_L3;
833 ring->csum_complete++;
841 ip_summed = CHECKSUM_NONE;
842 hash_type = PKT_HASH_TYPE_L3;
845 skb->ip_summed = ip_summed;
846 if (dev->features & NETIF_F_RXHASH)
848 be32_to_cpu(cqe->immed_rss_invalid),
851 if ((cqe->vlan_my_qpn &
852 cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK)) &&
853 (dev->features & NETIF_F_HW_VLAN_CTAG_RX))
854 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
855 be16_to_cpu(cqe->sl_vid));
856 else if ((cqe->vlan_my_qpn &
857 cpu_to_be32(MLX4_CQE_SVLAN_PRESENT_MASK)) &&
858 (dev->features & NETIF_F_HW_VLAN_STAG_RX))
859 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD),
860 be16_to_cpu(cqe->sl_vid));
862 nr = mlx4_en_complete_rx_desc(priv, frags, skb, length);
864 skb_shinfo(skb)->nr_frags = nr;
866 skb->data_len = length;
867 napi_gro_frags(&cq->napi);
873 ++cq->mcq.cons_index;
874 index = (cq->mcq.cons_index) & ring->size_mask;
875 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
876 if (unlikely(++polled == budget))
882 if (likely(polled)) {
883 if (doorbell_pending) {
884 priv->tx_cq[TX_XDP][cq_ring]->xdp_busy = true;
885 mlx4_en_xmit_doorbell(priv->tx_ring[TX_XDP][cq_ring]);
888 mlx4_cq_set_ci(&cq->mcq);
889 wmb(); /* ensure HW sees CQ consumer before we post new buffers */
890 ring->cons = cq->mcq.cons_index;
892 AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
894 mlx4_en_refill_rx_buffers(priv, ring);
900 void mlx4_en_rx_irq(struct mlx4_cq *mcq)
902 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
903 struct mlx4_en_priv *priv = netdev_priv(cq->dev);
905 if (likely(priv->port_up))
906 napi_schedule_irqoff(&cq->napi);
908 mlx4_en_arm_cq(priv, cq);
911 /* Rx CQ polling - called by NAPI */
912 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
914 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
915 struct net_device *dev = cq->dev;
916 struct mlx4_en_priv *priv = netdev_priv(dev);
917 struct mlx4_en_cq *xdp_tx_cq = NULL;
918 bool clean_complete = true;
921 if (priv->tx_ring_num[TX_XDP]) {
922 xdp_tx_cq = priv->tx_cq[TX_XDP][cq->ring];
923 if (xdp_tx_cq->xdp_busy) {
924 clean_complete = mlx4_en_process_tx_cq(dev, xdp_tx_cq,
926 xdp_tx_cq->xdp_busy = !clean_complete;
930 done = mlx4_en_process_rx_cq(dev, cq, budget);
932 /* If we used up all the quota - we're probably not done yet... */
933 if (done == budget || !clean_complete) {
934 const struct cpumask *aff;
935 struct irq_data *idata;
938 /* in case we got here because of !clean_complete */
941 INC_PERF_COUNTER(priv->pstats.napi_quota);
943 cpu_curr = smp_processor_id();
944 idata = irq_desc_get_irq_data(cq->irq_desc);
945 aff = irq_data_get_affinity_mask(idata);
947 if (likely(cpumask_test_cpu(cpu_curr, aff)))
950 /* Current cpu is not according to smp_irq_affinity -
951 * probably affinity changed. Need to stop this NAPI
952 * poll, and restart it on the right CPU.
953 * Try to avoid returning a too small value (like 0),
954 * to not fool net_rx_action() and its netdev_budget
960 if (likely(napi_complete_done(napi, done)))
961 mlx4_en_arm_cq(priv, cq);
965 void mlx4_en_calc_rx_buf(struct net_device *dev)
967 struct mlx4_en_priv *priv = netdev_priv(dev);
968 int eff_mtu = MLX4_EN_EFF_MTU(dev->mtu);
971 /* bpf requires buffers to be set up as 1 packet per page.
972 * This only works when num_frags == 1.
974 if (priv->tx_ring_num[TX_XDP]) {
975 priv->frag_info[0].frag_size = eff_mtu;
976 /* This will gain efficient xdp frame recycling at the
977 * expense of more costly truesize accounting
979 priv->frag_info[0].frag_stride = PAGE_SIZE;
980 priv->dma_dir = PCI_DMA_BIDIRECTIONAL;
981 priv->rx_headroom = XDP_PACKET_HEADROOM;
984 int frag_size_max = 2048, buf_size = 0;
986 /* should not happen, right ? */
987 if (eff_mtu > PAGE_SIZE + (MLX4_EN_MAX_RX_FRAGS - 1) * 2048)
988 frag_size_max = PAGE_SIZE;
990 while (buf_size < eff_mtu) {
991 int frag_stride, frag_size = eff_mtu - buf_size;
994 if (i < MLX4_EN_MAX_RX_FRAGS - 1)
995 frag_size = min(frag_size, frag_size_max);
997 priv->frag_info[i].frag_size = frag_size;
998 frag_stride = ALIGN(frag_size, SMP_CACHE_BYTES);
999 /* We can only pack 2 1536-bytes frames in on 4K page
1000 * Therefore, each frame would consume more bytes (truesize)
1002 nb = PAGE_SIZE / frag_stride;
1003 pad = (PAGE_SIZE - nb * frag_stride) / nb;
1004 pad &= ~(SMP_CACHE_BYTES - 1);
1005 priv->frag_info[i].frag_stride = frag_stride + pad;
1007 buf_size += frag_size;
1010 priv->dma_dir = PCI_DMA_FROMDEVICE;
1011 priv->rx_headroom = 0;
1014 priv->num_frags = i;
1015 priv->rx_skb_size = eff_mtu;
1016 priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc));
1018 en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n",
1019 eff_mtu, priv->num_frags);
1020 for (i = 0; i < priv->num_frags; i++) {
1023 " frag:%d - size:%d stride:%d\n",
1025 priv->frag_info[i].frag_size,
1026 priv->frag_info[i].frag_stride);
1030 /* RSS related functions */
1032 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
1033 struct mlx4_en_rx_ring *ring,
1034 enum mlx4_qp_state *state,
1037 struct mlx4_en_dev *mdev = priv->mdev;
1038 struct mlx4_qp_context *context;
1041 context = kmalloc(sizeof(*context), GFP_KERNEL);
1045 err = mlx4_qp_alloc(mdev->dev, qpn, qp);
1047 en_err(priv, "Failed to allocate qp #%x\n", qpn);
1050 qp->event = mlx4_en_sqp_event;
1052 memset(context, 0, sizeof *context);
1053 mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
1054 qpn, ring->cqn, -1, context);
1055 context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
1057 /* Cancel FCS removal if FW allows */
1058 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {
1059 context->param3 |= cpu_to_be32(1 << 29);
1060 if (priv->dev->features & NETIF_F_RXFCS)
1063 ring->fcs_del = ETH_FCS_LEN;
1067 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
1069 mlx4_qp_remove(mdev->dev, qp);
1070 mlx4_qp_free(mdev->dev, qp);
1072 mlx4_en_update_rx_prod_db(ring);
1078 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv)
1083 err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn,
1084 MLX4_RESERVE_A0_QP);
1086 en_err(priv, "Failed reserving drop qpn\n");
1089 err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp);
1091 en_err(priv, "Failed allocating drop qp\n");
1092 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1099 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv)
1103 qpn = priv->drop_qp.qpn;
1104 mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp);
1105 mlx4_qp_free(priv->mdev->dev, &priv->drop_qp);
1106 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1109 /* Allocate rx qp's and configure them according to rss map */
1110 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
1112 struct mlx4_en_dev *mdev = priv->mdev;
1113 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1114 struct mlx4_qp_context context;
1115 struct mlx4_rss_context *rss_context;
1118 u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |
1125 en_dbg(DRV, priv, "Configuring rss steering\n");
1127 flags = priv->rx_ring_num == 1 ? MLX4_RESERVE_A0_QP : 0;
1128 err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
1130 &rss_map->base_qpn, flags);
1132 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
1136 for (i = 0; i < priv->rx_ring_num; i++) {
1137 qpn = rss_map->base_qpn + i;
1138 err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i],
1147 if (priv->rx_ring_num == 1) {
1148 rss_map->indir_qp = &rss_map->qps[0];
1149 priv->base_qpn = rss_map->indir_qp->qpn;
1150 en_info(priv, "Optimized Non-RSS steering\n");
1154 rss_map->indir_qp = kzalloc(sizeof(*rss_map->indir_qp), GFP_KERNEL);
1155 if (!rss_map->indir_qp) {
1160 /* Configure RSS indirection qp */
1161 err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, rss_map->indir_qp);
1163 en_err(priv, "Failed to allocate RSS indirection QP\n");
1167 rss_map->indir_qp->event = mlx4_en_sqp_event;
1168 mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
1169 priv->rx_ring[0]->cqn, -1, &context);
1171 if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num)
1172 rss_rings = priv->rx_ring_num;
1174 rss_rings = priv->prof->rss_rings;
1176 ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path)
1177 + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
1179 rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 |
1180 (rss_map->base_qpn));
1181 rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
1182 if (priv->mdev->profile.udp_rss) {
1183 rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;
1184 rss_context->base_qpn_udp = rss_context->default_qpn;
1187 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1188 en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n");
1189 rss_mask |= MLX4_RSS_BY_INNER_HEADERS;
1192 rss_context->flags = rss_mask;
1193 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1194 if (priv->rss_hash_fn == ETH_RSS_HASH_XOR) {
1195 rss_context->hash_fn = MLX4_RSS_HASH_XOR;
1196 } else if (priv->rss_hash_fn == ETH_RSS_HASH_TOP) {
1197 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1198 memcpy(rss_context->rss_key, priv->rss_key,
1199 MLX4_EN_RSS_KEY_SIZE);
1201 en_err(priv, "Unknown RSS hash function requested\n");
1206 err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
1207 rss_map->indir_qp, &rss_map->indir_state);
1214 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1215 MLX4_QP_STATE_RST, NULL, 0, 0, rss_map->indir_qp);
1216 mlx4_qp_remove(mdev->dev, rss_map->indir_qp);
1217 mlx4_qp_free(mdev->dev, rss_map->indir_qp);
1218 kfree(rss_map->indir_qp);
1219 rss_map->indir_qp = NULL;
1221 for (i = 0; i < good_qps; i++) {
1222 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1223 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1224 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1225 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1227 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1231 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
1233 struct mlx4_en_dev *mdev = priv->mdev;
1234 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1237 if (priv->rx_ring_num > 1) {
1238 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1239 MLX4_QP_STATE_RST, NULL, 0, 0,
1241 mlx4_qp_remove(mdev->dev, rss_map->indir_qp);
1242 mlx4_qp_free(mdev->dev, rss_map->indir_qp);
1243 kfree(rss_map->indir_qp);
1244 rss_map->indir_qp = NULL;
1247 for (i = 0; i < priv->rx_ring_num; i++) {
1248 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1249 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1250 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1251 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1253 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);