drivers/net/ethernet/mellanox/mlx4/en_rx.c

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #include <net/busy_poll.h>
  35 #include <linux/bpf.h>
  36 #include <linux/mlx4/cq.h>
  37 #include <linux/slab.h>
  38 #include <linux/mlx4/qp.h>
  39 #include <linux/skbuff.h>
  40 #include <linux/rculist.h>
  41 #include <linux/if_ether.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/vmalloc.h>
  44 #include <linux/irq.h>
  45
  46 #if IS_ENABLED(CONFIG_IPV6)
  47 #include <net/ip6_checksum.h>
  48 #endif
  49
  50 #include "mlx4_en.h"
  51
  52 static int mlx4_alloc_pages(struct mlx4_en_priv *priv,
  53                             struct mlx4_en_rx_alloc *page_alloc,
  54                             const struct mlx4_en_frag_info *frag_info,
  55                             gfp_t _gfp)
  56 {
  57         int order;
  58         struct page *page;
  59         dma_addr_t dma;
  60
  61         for (order = frag_info->order; ;) {
  62                 gfp_t gfp = _gfp;
  63
  64                 if (order)
  65                         gfp |= __GFP_COMP | __GFP_NOWARN | __GFP_NOMEMALLOC;
  66                 page = alloc_pages(gfp, order);
  67                 if (likely(page))
  68                         break;
  69                 if (--order < 0 ||
  70                     ((PAGE_SIZE << order) < frag_info->frag_size))
  71                         return -ENOMEM;
  72         }
  73         dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE << order,
  74                            frag_info->dma_dir);
  75         if (unlikely(dma_mapping_error(priv->ddev, dma))) {
  76                 put_page(page);
  77                 return -ENOMEM;
  78         }
  79         page_alloc->page_size = PAGE_SIZE << order;
  80         page_alloc->page = page;
  81         page_alloc->dma = dma;
  82         page_alloc->page_offset = 0;
  83         /* Not doing get_page() for each frag is a big win
  84          * on asymetric workloads. Note we can not use atomic_set().
  85          */
  86         page_ref_add(page, page_alloc->page_size / frag_info->frag_stride - 1);
  87         return 0;
  88 }
  89
  90 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv,
  91                                struct mlx4_en_rx_desc *rx_desc,
  92                                struct mlx4_en_rx_alloc *frags,
  93                                struct mlx4_en_rx_alloc *ring_alloc,
  94                                gfp_t gfp)
  95 {
  96         struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
  97         const struct mlx4_en_frag_info *frag_info;
  98         struct page *page;
  99         dma_addr_t dma;
 100         int i;
 101
 102         for (i = 0; i < priv->num_frags; i++) {
 103                 frag_info = &priv->frag_info[i];
 104                 page_alloc[i] = ring_alloc[i];
 105                 page_alloc[i].page_offset += frag_info->frag_stride;
 106
 107                 if (page_alloc[i].page_offset + frag_info->frag_stride <=
 108                     ring_alloc[i].page_size)
 109                         continue;
 110
 111                 if (unlikely(mlx4_alloc_pages(priv, &page_alloc[i],
 112                                               frag_info, gfp)))
 113                         goto out;
 114         }
 115
 116         for (i = 0; i < priv->num_frags; i++) {
 117                 frags[i] = ring_alloc[i];
 118                 dma = ring_alloc[i].dma + ring_alloc[i].page_offset;
 119                 ring_alloc[i] = page_alloc[i];
 120                 rx_desc->data[i].addr = cpu_to_be64(dma);
 121         }
 122
 123         return 0;
 124
 125 out:
 126         while (i--) {
 127                 if (page_alloc[i].page != ring_alloc[i].page) {
 128                         dma_unmap_page(priv->ddev, page_alloc[i].dma,
 129                                 page_alloc[i].page_size,
 130                                 priv->frag_info[i].dma_dir);
 131                         page = page_alloc[i].page;
 132                         /* Revert changes done by mlx4_alloc_pages */
 133                         page_ref_sub(page, page_alloc[i].page_size /
 134                                            priv->frag_info[i].frag_stride - 1);
 135                         put_page(page);
 136                 }
 137         }
 138         return -ENOMEM;
 139 }
 140
 141 static void mlx4_en_free_frag(struct mlx4_en_priv *priv,
 142                               struct mlx4_en_rx_alloc *frags,
 143                               int i)
 144 {
 145         const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
 146         u32 next_frag_end = frags[i].page_offset + 2 * frag_info->frag_stride;
 147
 148
 149         if (next_frag_end > frags[i].page_size)
 150                 dma_unmap_page(priv->ddev, frags[i].dma, frags[i].page_size,
 151                                frag_info->dma_dir);
 152
 153         if (frags[i].page)
 154                 put_page(frags[i].page);
 155 }
 156
 157 static int mlx4_en_init_allocator(struct mlx4_en_priv *priv,
 158                                   struct mlx4_en_rx_ring *ring)
 159 {
 160         int i;
 161         struct mlx4_en_rx_alloc *page_alloc;
 162
 163         for (i = 0; i < priv->num_frags; i++) {
 164                 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
 165
 166                 if (mlx4_alloc_pages(priv, &ring->page_alloc[i],
 167                                      frag_info, GFP_KERNEL | __GFP_COLD))
 168                         goto out;
 169
 170                 en_dbg(DRV, priv, "  frag %d allocator: - size:%d frags:%d\n",
 171                        i, ring->page_alloc[i].page_size,
 172                        page_ref_count(ring->page_alloc[i].page));
 173         }
 174         return 0;
 175
 176 out:
 177         while (i--) {
 178                 struct page *page;
 179
 180                 page_alloc = &ring->page_alloc[i];
 181                 dma_unmap_page(priv->ddev, page_alloc->dma,
 182                                page_alloc->page_size,
 183                                priv->frag_info[i].dma_dir);
 184                 page = page_alloc->page;
 185                 /* Revert changes done by mlx4_alloc_pages */
 186                 page_ref_sub(page, page_alloc->page_size /
 187                                    priv->frag_info[i].frag_stride - 1);
 188                 put_page(page);
 189                 page_alloc->page = NULL;
 190         }
 191         return -ENOMEM;
 192 }
 193
 194 static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv,
 195                                       struct mlx4_en_rx_ring *ring)
 196 {
 197         struct mlx4_en_rx_alloc *page_alloc;
 198         int i;
 199
 200         for (i = 0; i < priv->num_frags; i++) {
 201                 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
 202
 203                 page_alloc = &ring->page_alloc[i];
 204                 en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n",
 205                        i, page_count(page_alloc->page));
 206
 207                 dma_unmap_page(priv->ddev, page_alloc->dma,
 208                                 page_alloc->page_size, frag_info->dma_dir);
 209                 while (page_alloc->page_offset + frag_info->frag_stride <
 210                        page_alloc->page_size) {
 211                         put_page(page_alloc->page);
 212                         page_alloc->page_offset += frag_info->frag_stride;
 213                 }
 214                 page_alloc->page = NULL;
 215         }
 216 }
 217
 218 static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
 219                                  struct mlx4_en_rx_ring *ring, int index)
 220 {
 221         struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
 222         int possible_frags;
 223         int i;
 224
 225         /* Set size and memtype fields */
 226         for (i = 0; i < priv->num_frags; i++) {
 227                 rx_desc->data[i].byte_count =
 228                         cpu_to_be32(priv->frag_info[i].frag_size);
 229                 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
 230         }
 231
 232         /* If the number of used fragments does not fill up the ring stride,
 233          * remaining (unused) fragments must be padded with null address/size
 234          * and a special memory key */
 235         possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
 236         for (i = priv->num_frags; i < possible_frags; i++) {
 237                 rx_desc->data[i].byte_count = 0;
 238                 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
 239                 rx_desc->data[i].addr = 0;
 240         }
 241 }
 242
 243 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
 244                                    struct mlx4_en_rx_ring *ring, int index,
 245                                    gfp_t gfp)
 246 {
 247         struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
 248         struct mlx4_en_rx_alloc *frags = ring->rx_info +
 249                                         (index << priv->log_rx_info);
 250
 251         if (ring->page_cache.index > 0) {
 252                 frags[0] = ring->page_cache.buf[--ring->page_cache.index];
 253                 rx_desc->data[0].addr = cpu_to_be64(frags[0].dma);
 254                 return 0;
 255         }
 256
 257         return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc, gfp);
 258 }
 259
 260 static inline bool mlx4_en_is_ring_empty(struct mlx4_en_rx_ring *ring)
 261 {
 262         return ring->prod == ring->cons;
 263 }
 264
 265 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
 266 {
 267         *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
 268 }
 269
 270 static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv,
 271                                  struct mlx4_en_rx_ring *ring,
 272                                  int index)
 273 {
 274         struct mlx4_en_rx_alloc *frags;
 275         int nr;
 276
 277         frags = ring->rx_info + (index << priv->log_rx_info);
 278         for (nr = 0; nr < priv->num_frags; nr++) {
 279                 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
 280                 mlx4_en_free_frag(priv, frags, nr);
 281         }
 282 }
 283
 284 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
 285 {
 286         struct mlx4_en_rx_ring *ring;
 287         int ring_ind;
 288         int buf_ind;
 289         int new_size;
 290
 291         for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
 292                 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 293                         ring = priv->rx_ring[ring_ind];
 294
 295                         if (mlx4_en_prepare_rx_desc(priv, ring,
 296                                                     ring->actual_size,
 297                                                     GFP_KERNEL | __GFP_COLD)) {
 298                                 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
 299                                         en_err(priv, "Failed to allocate enough rx buffers\n");
 300                                         return -ENOMEM;
 301                                 } else {
 302                                         new_size = rounddown_pow_of_two(ring->actual_size);
 303                                         en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n",
 304                                                 ring->actual_size, new_size);
 305                                         goto reduce_rings;
 306                                 }
 307                         }
 308                         ring->actual_size++;
 309                         ring->prod++;
 310                 }
 311         }
 312         return 0;
 313
 314 reduce_rings:
 315         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 316                 ring = priv->rx_ring[ring_ind];
 317                 while (ring->actual_size > new_size) {
 318                         ring->actual_size--;
 319                         ring->prod--;
 320                         mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
 321                 }
 322         }
 323
 324         return 0;
 325 }
 326
 327 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
 328                                 struct mlx4_en_rx_ring *ring)
 329 {
 330         int index;
 331
 332         en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
 333                ring->cons, ring->prod);
 334
 335         /* Unmap and free Rx buffers */
 336         while (!mlx4_en_is_ring_empty(ring)) {
 337                 index = ring->cons & ring->size_mask;
 338                 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
 339                 mlx4_en_free_rx_desc(priv, ring, index);
 340                 ++ring->cons;
 341         }
 342 }
 343
 344 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev)
 345 {
 346         int i;
 347         int num_of_eqs;
 348         int num_rx_rings;
 349         struct mlx4_dev *dev = mdev->dev;
 350
 351         mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {
 352                 num_of_eqs = max_t(int, MIN_RX_RINGS,
 353                                    min_t(int,
 354                                          mlx4_get_eqs_per_port(mdev->dev, i),
 355                                          DEF_RX_RINGS));
 356
 357                 num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS :
 358                         min_t(int, num_of_eqs,
 359                               netif_get_num_default_rss_queues());
 360                 mdev->profile.prof[i].rx_ring_num =
 361                         rounddown_pow_of_two(num_rx_rings);
 362         }
 363 }
 364
 365 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
 366                            struct mlx4_en_rx_ring **pring,
 367                            u32 size, u16 stride, int node)
 368 {
 369         struct mlx4_en_dev *mdev = priv->mdev;
 370         struct mlx4_en_rx_ring *ring;
 371         int err = -ENOMEM;
 372         int tmp;
 373
 374         ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
 375         if (!ring) {
 376                 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
 377                 if (!ring) {
 378                         en_err(priv, "Failed to allocate RX ring structure\n");
 379                         return -ENOMEM;
 380                 }
 381         }
 382
 383         ring->prod = 0;
 384         ring->cons = 0;
 385         ring->size = size;
 386         ring->size_mask = size - 1;
 387         ring->stride = stride;
 388         ring->log_stride = ffs(ring->stride) - 1;
 389         ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
 390
 391         tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
 392                                         sizeof(struct mlx4_en_rx_alloc));
 393         ring->rx_info = vmalloc_node(tmp, node);
 394         if (!ring->rx_info) {
 395                 ring->rx_info = vmalloc(tmp);
 396                 if (!ring->rx_info) {
 397                         err = -ENOMEM;
 398                         goto err_ring;
 399                 }
 400         }
 401
 402         en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
 403                  ring->rx_info, tmp);
 404
 405         /* Allocate HW buffers on provided NUMA node */
 406         set_dev_node(&mdev->dev->persist->pdev->dev, node);
 407         err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
 408         set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);
 409         if (err)
 410                 goto err_info;
 411
 412         ring->buf = ring->wqres.buf.direct.buf;
 413
 414         ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter;
 415
 416         *pring = ring;
 417         return 0;
 418
 419 err_info:
 420         vfree(ring->rx_info);
 421         ring->rx_info = NULL;
 422 err_ring:
 423         kfree(ring);
 424         *pring = NULL;
 425
 426         return err;
 427 }
 428
 429 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
 430 {
 431         struct mlx4_en_rx_ring *ring;
 432         int i;
 433         int ring_ind;
 434         int err;
 435         int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
 436                                         DS_SIZE * priv->num_frags);
 437
 438         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 439                 ring = priv->rx_ring[ring_ind];
 440
 441                 ring->prod = 0;
 442                 ring->cons = 0;
 443                 ring->actual_size = 0;
 444                 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn;
 445
 446                 ring->stride = stride;
 447                 if (ring->stride <= TXBB_SIZE)
 448                         ring->buf += TXBB_SIZE;
 449
 450                 ring->log_stride = ffs(ring->stride) - 1;
 451                 ring->buf_size = ring->size * ring->stride;
 452
 453                 memset(ring->buf, 0, ring->buf_size);
 454                 mlx4_en_update_rx_prod_db(ring);
 455
 456                 /* Initialize all descriptors */
 457                 for (i = 0; i < ring->size; i++)
 458                         mlx4_en_init_rx_desc(priv, ring, i);
 459
 460                 /* Initialize page allocators */
 461                 err = mlx4_en_init_allocator(priv, ring);
 462                 if (err) {
 463                         en_err(priv, "Failed initializing ring allocator\n");
 464                         if (ring->stride <= TXBB_SIZE)
 465                                 ring->buf -= TXBB_SIZE;
 466                         ring_ind--;
 467                         goto err_allocator;
 468                 }
 469         }
 470         err = mlx4_en_fill_rx_buffers(priv);
 471         if (err)
 472                 goto err_buffers;
 473
 474         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 475                 ring = priv->rx_ring[ring_ind];
 476
 477                 ring->size_mask = ring->actual_size - 1;
 478                 mlx4_en_update_rx_prod_db(ring);
 479         }
 480
 481         return 0;
 482
 483 err_buffers:
 484         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
 485                 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]);
 486
 487         ring_ind = priv->rx_ring_num - 1;
 488 err_allocator:
 489         while (ring_ind >= 0) {
 490                 if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE)
 491                         priv->rx_ring[ring_ind]->buf -= TXBB_SIZE;
 492                 mlx4_en_destroy_allocator(priv, priv->rx_ring[ring_ind]);
 493                 ring_ind--;
 494         }
 495         return err;
 496 }
 497
 498 /* We recover from out of memory by scheduling our napi poll
 499  * function (mlx4_en_process_cq), which tries to allocate
 500  * all missing RX buffers (call to mlx4_en_refill_rx_buffers).
 501  */
 502 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv)
 503 {
 504         int ring;
 505
 506         if (!priv->port_up)
 507                 return;
 508
 509         for (ring = 0; ring < priv->rx_ring_num; ring++) {
 510                 if (mlx4_en_is_ring_empty(priv->rx_ring[ring]))
 511                         napi_reschedule(&priv->rx_cq[ring]->napi);
 512         }
 513 }
 514
 515 /* When the rx ring is running in page-per-packet mode, a released frame can go
 516  * directly into a small cache, to avoid unmapping or touching the page
 517  * allocator. In bpf prog performance scenarios, buffers are either forwarded
 518  * or dropped, never converted to skbs, so every page can come directly from
 519  * this cache when it is sized to be a multiple of the napi budget.
 520  */
 521 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring,
 522                         struct mlx4_en_rx_alloc *frame)
 523 {
 524         struct mlx4_en_page_cache *cache = &ring->page_cache;
 525
 526         if (cache->index >= MLX4_EN_CACHE_SIZE)
 527                 return false;
 528
 529         cache->buf[cache->index++] = *frame;
 530         return true;
 531 }
 532
 533 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
 534                              struct mlx4_en_rx_ring **pring,
 535                              u32 size, u16 stride)
 536 {
 537         struct mlx4_en_dev *mdev = priv->mdev;
 538         struct mlx4_en_rx_ring *ring = *pring;
 539         struct bpf_prog *old_prog;
 540
 541         old_prog = rcu_dereference_protected(
 542                                         ring->xdp_prog,
 543                                         lockdep_is_held(&mdev->state_lock));
 544         if (old_prog)
 545                 bpf_prog_put(old_prog);
 546         mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE);
 547         vfree(ring->rx_info);
 548         ring->rx_info = NULL;
 549         kfree(ring);
 550         *pring = NULL;
 551 }
 552
 553 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
 554                                 struct mlx4_en_rx_ring *ring)
 555 {
 556         int i;
 557
 558         for (i = 0; i < ring->page_cache.index; i++) {
 559                 struct mlx4_en_rx_alloc *frame = &ring->page_cache.buf[i];
 560
 561                 dma_unmap_page(priv->ddev, frame->dma, frame->page_size,
 562                                priv->frag_info[0].dma_dir);
 563                 put_page(frame->page);
 564         }
 565         ring->page_cache.index = 0;
 566         mlx4_en_free_rx_buf(priv, ring);
 567         if (ring->stride <= TXBB_SIZE)
 568                 ring->buf -= TXBB_SIZE;
 569         mlx4_en_destroy_allocator(priv, ring);
 570 }
 571
 572
 573 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
 574                                     struct mlx4_en_rx_desc *rx_desc,
 575                                     struct mlx4_en_rx_alloc *frags,
 576                                     struct sk_buff *skb,
 577                                     int length)
 578 {
 579         struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags;
 580         struct mlx4_en_frag_info *frag_info;
 581         int nr;
 582         dma_addr_t dma;
 583
 584         /* Collect used fragments while replacing them in the HW descriptors */
 585         for (nr = 0; nr < priv->num_frags; nr++) {
 586                 frag_info = &priv->frag_info[nr];
 587                 if (length <= frag_info->frag_prefix_size)
 588                         break;
 589                 if (unlikely(!frags[nr].page))
 590                         goto fail;
 591
 592                 dma = be64_to_cpu(rx_desc->data[nr].addr);
 593                 dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size,
 594                                         DMA_FROM_DEVICE);
 595
 596                 /* Save page reference in skb */
 597                 __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page);
 598                 skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size);
 599                 skb_frags_rx[nr].page_offset = frags[nr].page_offset;
 600                 skb->truesize += frag_info->frag_stride;
 601                 frags[nr].page = NULL;
 602         }
 603         /* Adjust size of last fragment to match actual length */
 604         if (nr > 0)
 605                 skb_frag_size_set(&skb_frags_rx[nr - 1],
 606                         length - priv->frag_info[nr - 1].frag_prefix_size);
 607         return nr;
 608
 609 fail:
 610         while (nr > 0) {
 611                 nr--;
 612                 __skb_frag_unref(&skb_frags_rx[nr]);
 613         }
 614         return 0;
 615 }
 616
 617
 618 static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
 619                                       struct mlx4_en_rx_desc *rx_desc,
 620                                       struct mlx4_en_rx_alloc *frags,
 621                                       unsigned int length)
 622 {
 623         struct sk_buff *skb;
 624         void *va;
 625         int used_frags;
 626         dma_addr_t dma;
 627
 628         skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN);
 629         if (unlikely(!skb)) {
 630                 en_dbg(RX_ERR, priv, "Failed allocating skb\n");
 631                 return NULL;
 632         }
 633         skb_reserve(skb, NET_IP_ALIGN);
 634         skb->len = length;
 635
 636         /* Get pointer to first fragment so we could copy the headers into the
 637          * (linear part of the) skb */
 638         va = page_address(frags[0].page) + frags[0].page_offset;
 639
 640         if (length <= SMALL_PACKET_SIZE) {
 641                 /* We are copying all relevant data to the skb - temporarily
 642                  * sync buffers for the copy */
 643                 dma = be64_to_cpu(rx_desc->data[0].addr);
 644                 dma_sync_single_for_cpu(priv->ddev, dma, length,
 645                                         DMA_FROM_DEVICE);
 646                 skb_copy_to_linear_data(skb, va, length);
 647                 skb->tail += length;
 648         } else {
 649                 unsigned int pull_len;
 650
 651                 /* Move relevant fragments to skb */
 652                 used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags,
 653                                                         skb, length);
 654                 if (unlikely(!used_frags)) {
 655                         kfree_skb(skb);
 656                         return NULL;
 657                 }
 658                 skb_shinfo(skb)->nr_frags = used_frags;
 659
 660                 pull_len = eth_get_headlen(va, SMALL_PACKET_SIZE);
 661                 /* Copy headers into the skb linear buffer */
 662                 memcpy(skb->data, va, pull_len);
 663                 skb->tail += pull_len;
 664
 665                 /* Skip headers in first fragment */
 666                 skb_shinfo(skb)->frags[0].page_offset += pull_len;
 667
 668                 /* Adjust size of first fragment */
 669                 skb_frag_size_sub(&skb_shinfo(skb)->frags[0], pull_len);
 670                 skb->data_len = length - pull_len;
 671         }
 672         return skb;
 673 }
 674
 675 static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb)
 676 {
 677         int i;
 678         int offset = ETH_HLEN;
 679
 680         for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) {
 681                 if (*(skb->data + offset) != (unsigned char) (i & 0xff))
 682                         goto out_loopback;
 683         }
 684         /* Loopback found */
 685         priv->loopback_ok = 1;
 686
 687 out_loopback:
 688         dev_kfree_skb_any(skb);
 689 }
 690
 691 static bool mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv,
 692                                       struct mlx4_en_rx_ring *ring)
 693 {
 694         u32 missing = ring->actual_size - (ring->prod - ring->cons);
 695
 696         /* Try to batch allocations, but not too much. */
 697         if (missing < 8)
 698                 return false;
 699         do {
 700                 if (mlx4_en_prepare_rx_desc(priv, ring,
 701                                             ring->prod & ring->size_mask,
 702                                             GFP_ATOMIC | __GFP_COLD))
 703                         break;
 704                 ring->prod++;
 705         } while (--missing);
 706
 707         return true;
 708 }
 709
 710 /* When hardware doesn't strip the vlan, we need to calculate the checksum
 711  * over it and add it to the hardware's checksum calculation
 712  */
 713 static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum,
 714                                          struct vlan_hdr *vlanh)
 715 {
 716         return csum_add(hw_checksum, *(__wsum *)vlanh);
 717 }
 718
 719 /* Although the stack expects checksum which doesn't include the pseudo
 720  * header, the HW adds it. To address that, we are subtracting the pseudo
 721  * header checksum from the checksum value provided by the HW.
 722  */
 723 static void get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb,
 724                                 struct iphdr *iph)
 725 {
 726         __u16 length_for_csum = 0;
 727         __wsum csum_pseudo_header = 0;
 728
 729         length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2));
 730         csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr,
 731                                                 length_for_csum, iph->protocol, 0);
 732         skb->csum = csum_sub(hw_checksum, csum_pseudo_header);
 733 }
 734
 735 #if IS_ENABLED(CONFIG_IPV6)
 736 /* In IPv6 packets, besides subtracting the pseudo header checksum,
 737  * we also compute/add the IP header checksum which
 738  * is not added by the HW.
 739  */
 740 static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb,
 741                                struct ipv6hdr *ipv6h)
 742 {
 743         __wsum csum_pseudo_hdr = 0;
 744
 745         if (unlikely(ipv6h->nexthdr == IPPROTO_FRAGMENT ||
 746                      ipv6h->nexthdr == IPPROTO_HOPOPTS))
 747                 return -1;
 748         hw_checksum = csum_add(hw_checksum, (__force __wsum)htons(ipv6h->nexthdr));
 749
 750         csum_pseudo_hdr = csum_partial(&ipv6h->saddr,
 751                                        sizeof(ipv6h->saddr) + sizeof(ipv6h->daddr), 0);
 752         csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ipv6h->payload_len);
 753         csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ntohs(ipv6h->nexthdr));
 754
 755         skb->csum = csum_sub(hw_checksum, csum_pseudo_hdr);
 756         skb->csum = csum_add(skb->csum, csum_partial(ipv6h, sizeof(struct ipv6hdr), 0));
 757         return 0;
 758 }
 759 #endif
 760 static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va,
 761                       netdev_features_t dev_features)
 762 {
 763         __wsum hw_checksum = 0;
 764
 765         void *hdr = (u8 *)va + sizeof(struct ethhdr);
 766
 767         hw_checksum = csum_unfold((__force __sum16)cqe->checksum);
 768
 769         if (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK) &&
 770             !(dev_features & NETIF_F_HW_VLAN_CTAG_RX)) {
 771                 hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr);
 772                 hdr += sizeof(struct vlan_hdr);
 773         }
 774
 775         if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4))
 776                 get_fixed_ipv4_csum(hw_checksum, skb, hdr);
 777 #if IS_ENABLED(CONFIG_IPV6)
 778         else if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6))
 779                 if (unlikely(get_fixed_ipv6_csum(hw_checksum, skb, hdr)))
 780                         return -1;
 781 #endif
 782         return 0;
 783 }
 784
 785 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
 786 {
 787         struct mlx4_en_priv *priv = netdev_priv(dev);
 788         struct mlx4_en_dev *mdev = priv->mdev;
 789         struct mlx4_cqe *cqe;
 790         struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring];
 791         struct mlx4_en_rx_alloc *frags;
 792         struct mlx4_en_rx_desc *rx_desc;
 793         struct bpf_prog *xdp_prog;
 794         int doorbell_pending;
 795         struct sk_buff *skb;
 796         int index;
 797         int nr;
 798         unsigned int length;
 799         int polled = 0;
 800         int ip_summed;
 801         int factor = priv->cqe_factor;
 802         u64 timestamp;
 803         bool l2_tunnel;
 804
 805         if (unlikely(!priv->port_up))
 806                 return 0;
 807
 808         if (unlikely(budget <= 0))
 809                 return polled;
 810
 811         /* Protect accesses to: ring->xdp_prog, priv->mac_hash list */
 812         rcu_read_lock();
 813         xdp_prog = rcu_dereference(ring->xdp_prog);
 814         doorbell_pending = 0;
 815
 816         /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
 817          * descriptor offset can be deduced from the CQE index instead of
 818          * reading 'cqe->index' */
 819         index = cq->mcq.cons_index & ring->size_mask;
 820         cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
 821
 822         /* Process all completed CQEs */
 823         while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
 824                     cq->mcq.cons_index & cq->size)) {
 825
 826                 frags = ring->rx_info + (index << priv->log_rx_info);
 827                 rx_desc = ring->buf + (index << ring->log_stride);
 828
 829                 /*
 830                  * make sure we read the CQE after we read the ownership bit
 831                  */
 832                 dma_rmb();
 833
 834                 /* Drop packet on bad receive or bad checksum */
 835                 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
 836                                                 MLX4_CQE_OPCODE_ERROR)) {
 837                         en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n",
 838                                ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome,
 839                                ((struct mlx4_err_cqe *)cqe)->syndrome);
 840                         goto next;
 841                 }
 842                 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
 843                         en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
 844                         goto next;
 845                 }
 846
 847                 /* Check if we need to drop the packet if SRIOV is not enabled
 848                  * and not performing the selftest or flb disabled
 849                  */
 850                 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) {
 851                         struct ethhdr *ethh;
 852                         dma_addr_t dma;
 853                         /* Get pointer to first fragment since we haven't
 854                          * skb yet and cast it to ethhdr struct
 855                          */
 856                         dma = be64_to_cpu(rx_desc->data[0].addr);
 857                         dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh),
 858                                                 DMA_FROM_DEVICE);
 859                         ethh = (struct ethhdr *)(page_address(frags[0].page) +
 860                                                  frags[0].page_offset);
 861
 862                         if (is_multicast_ether_addr(ethh->h_dest)) {
 863                                 struct mlx4_mac_entry *entry;
 864                                 struct hlist_head *bucket;
 865                                 unsigned int mac_hash;
 866
 867                                 /* Drop the packet, since HW loopback-ed it */
 868                                 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX];
 869                                 bucket = &priv->mac_hash[mac_hash];
 870                                 hlist_for_each_entry_rcu(entry, bucket, hlist) {
 871                                         if (ether_addr_equal_64bits(entry->mac,
 872                                                                     ethh->h_source))
 873                                                 goto next;
 874                                 }
 875                         }
 876                 }
 877
 878                 /*
 879                  * Packet is OK - process it.
 880                  */
 881                 length = be32_to_cpu(cqe->byte_cnt);
 882                 length -= ring->fcs_del;
 883                 l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) &&
 884                         (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL));
 885
 886                 /* A bpf program gets first chance to drop the packet. It may
 887                  * read bytes but not past the end of the frag.
 888                  */
 889                 if (xdp_prog) {
 890                         struct xdp_buff xdp;
 891                         dma_addr_t dma;
 892                         u32 act;
 893
 894                         dma = be64_to_cpu(rx_desc->data[0].addr);
 895                         dma_sync_single_for_cpu(priv->ddev, dma,
 896                                                 priv->frag_info[0].frag_size,
 897                                                 DMA_FROM_DEVICE);
 898
 899                         xdp.data = page_address(frags[0].page) +
 900                                                         frags[0].page_offset;
 901                         xdp.data_end = xdp.data + length;
 902
 903                         act = bpf_prog_run_xdp(xdp_prog, &xdp);
 904                         switch (act) {
 905                         case XDP_PASS:
 906                                 break;
 907                         case XDP_TX:
 908                                 if (likely(!mlx4_en_xmit_frame(ring, frags, dev,
 909                                                         length, cq->ring,
 910                                                         &doorbell_pending)))
 911                                         goto consumed;
 912                                 goto xdp_drop_no_cnt; /* Drop on xmit failure */
 913                         default:
 914                                 bpf_warn_invalid_xdp_action(act);
 915                         case XDP_ABORTED:
 916                         case XDP_DROP:
 917                                 ring->xdp_drop++;
 918 xdp_drop_no_cnt:
 919                                 if (likely(mlx4_en_rx_recycle(ring, frags)))
 920                                         goto consumed;
 921                                 goto next;
 922                         }
 923                 }
 924
 925                 ring->bytes += length;
 926                 ring->packets++;
 927
 928                 if (likely(dev->features & NETIF_F_RXCSUM)) {
 929                         if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP |
 930                                                       MLX4_CQE_STATUS_UDP)) {
 931                                 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
 932                                     cqe->checksum == cpu_to_be16(0xffff)) {
 933                                         ip_summed = CHECKSUM_UNNECESSARY;
 934                                         ring->csum_ok++;
 935                                 } else {
 936                                         ip_summed = CHECKSUM_NONE;
 937                                         ring->csum_none++;
 938                                 }
 939                         } else {
 940                                 if (priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP &&
 941                                     (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
 942                                                                MLX4_CQE_STATUS_IPV6))) {
 943                                         ip_summed = CHECKSUM_COMPLETE;
 944                                         ring->csum_complete++;
 945                                 } else {
 946                                         ip_summed = CHECKSUM_NONE;
 947                                         ring->csum_none++;
 948                                 }
 949                         }
 950                 } else {
 951                         ip_summed = CHECKSUM_NONE;
 952                         ring->csum_none++;
 953                 }
 954
 955                 /* This packet is eligible for GRO if it is:
 956                  * - DIX Ethernet (type interpretation)
 957                  * - TCP/IP (v4)
 958                  * - without IP options
 959                  * - not an IP fragment
 960                  */
 961                 if (dev->features & NETIF_F_GRO) {
 962                         struct sk_buff *gro_skb = napi_get_frags(&cq->napi);
 963                         if (!gro_skb)
 964                                 goto next;
 965
 966                         nr = mlx4_en_complete_rx_desc(priv,
 967                                 rx_desc, frags, gro_skb,
 968                                 length);
 969                         if (!nr)
 970                                 goto next;
 971
 972                         if (ip_summed == CHECKSUM_COMPLETE) {
 973                                 void *va = skb_frag_address(skb_shinfo(gro_skb)->frags);
 974                                 if (check_csum(cqe, gro_skb, va,
 975                                                dev->features)) {
 976                                         ip_summed = CHECKSUM_NONE;
 977                                         ring->csum_none++;
 978                                         ring->csum_complete--;
 979                                 }
 980                         }
 981
 982                         skb_shinfo(gro_skb)->nr_frags = nr;
 983                         gro_skb->len = length;
 984                         gro_skb->data_len = length;
 985                         gro_skb->ip_summed = ip_summed;
 986
 987                         if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
 988                                 gro_skb->csum_level = 1;
 989
 990                         if ((cqe->vlan_my_qpn &
 991                             cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK)) &&
 992                             (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
 993                                 u16 vid = be16_to_cpu(cqe->sl_vid);
 994
 995                                 __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid);
 996                         } else if ((be32_to_cpu(cqe->vlan_my_qpn) &
 997                                   MLX4_CQE_SVLAN_PRESENT_MASK) &&
 998                                  (dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
 999                                 __vlan_hwaccel_put_tag(gro_skb,
1000                                                        htons(ETH_P_8021AD),
1001                                                        be16_to_cpu(cqe->sl_vid));
1002                         }
1003
1004                         if (dev->features & NETIF_F_RXHASH)
1005                                 skb_set_hash(gro_skb,
1006                                              be32_to_cpu(cqe->immed_rss_invalid),
1007                                              (ip_summed == CHECKSUM_UNNECESSARY) ?
1008                                                 PKT_HASH_TYPE_L4 :
1009                                                 PKT_HASH_TYPE_L3);
1010
1011                         skb_record_rx_queue(gro_skb, cq->ring);
1012
1013                         if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
1014                                 timestamp = mlx4_en_get_cqe_ts(cqe);
1015                                 mlx4_en_fill_hwtstamps(mdev,
1016                                                        skb_hwtstamps(gro_skb),
1017                                                        timestamp);
1018                         }
1019
1020                         napi_gro_frags(&cq->napi);
1021                         goto next;
1022                 }
1023
1024                 /* GRO not possible, complete processing here */
1025                 skb = mlx4_en_rx_skb(priv, rx_desc, frags, length);
1026                 if (unlikely(!skb)) {
1027                         ring->dropped++;
1028                         goto next;
1029                 }
1030
1031                 if (unlikely(priv->validate_loopback)) {
1032                         validate_loopback(priv, skb);
1033                         goto next;
1034                 }
1035
1036                 if (ip_summed == CHECKSUM_COMPLETE) {
1037                         if (check_csum(cqe, skb, skb->data, dev->features)) {
1038                                 ip_summed = CHECKSUM_NONE;
1039                                 ring->csum_complete--;
1040                                 ring->csum_none++;
1041                         }
1042                 }
1043
1044                 skb->ip_summed = ip_summed;
1045                 skb->protocol = eth_type_trans(skb, dev);
1046                 skb_record_rx_queue(skb, cq->ring);
1047
1048                 if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
1049                         skb->csum_level = 1;
1050
1051                 if (dev->features & NETIF_F_RXHASH)
1052                         skb_set_hash(skb,
1053                                      be32_to_cpu(cqe->immed_rss_invalid),
1054                                      (ip_summed == CHECKSUM_UNNECESSARY) ?
1055                                         PKT_HASH_TYPE_L4 :
1056                                         PKT_HASH_TYPE_L3);
1057
1058                 if ((be32_to_cpu(cqe->vlan_my_qpn) &
1059                     MLX4_CQE_CVLAN_PRESENT_MASK) &&
1060                     (dev->features & NETIF_F_HW_VLAN_CTAG_RX))
1061                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid));
1062                 else if ((be32_to_cpu(cqe->vlan_my_qpn) &
1063                           MLX4_CQE_SVLAN_PRESENT_MASK) &&
1064                          (dev->features & NETIF_F_HW_VLAN_STAG_RX))
1065                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD),
1066                                                be16_to_cpu(cqe->sl_vid));
1067
1068                 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
1069                         timestamp = mlx4_en_get_cqe_ts(cqe);
1070                         mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb),
1071                                                timestamp);
1072                 }
1073
1074                 napi_gro_receive(&cq->napi, skb);
1075 next:
1076                 for (nr = 0; nr < priv->num_frags; nr++)
1077                         mlx4_en_free_frag(priv, frags, nr);
1078
1079 consumed:
1080                 ++cq->mcq.cons_index;
1081                 index = (cq->mcq.cons_index) & ring->size_mask;
1082                 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
1083                 if (++polled == budget)
1084                         goto out;
1085         }
1086
1087 out:
1088         rcu_read_unlock();
1089
1090         if (polled) {
1091                 if (doorbell_pending)
1092                         mlx4_en_xmit_doorbell(priv->tx_ring[TX_XDP][cq->ring]);
1093
1094                 mlx4_cq_set_ci(&cq->mcq);
1095                 wmb(); /* ensure HW sees CQ consumer before we post new buffers */
1096                 ring->cons = cq->mcq.cons_index;
1097         }
1098         AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
1099
1100         if (mlx4_en_refill_rx_buffers(priv, ring))
1101                 mlx4_en_update_rx_prod_db(ring);
1102
1103         return polled;
1104 }
1105
1106
1107 void mlx4_en_rx_irq(struct mlx4_cq *mcq)
1108 {
1109         struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
1110         struct mlx4_en_priv *priv = netdev_priv(cq->dev);
1111
1112         if (likely(priv->port_up))
1113                 napi_schedule_irqoff(&cq->napi);
1114         else
1115                 mlx4_en_arm_cq(priv, cq);
1116 }
1117
1118 /* Rx CQ polling - called by NAPI */
1119 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
1120 {
1121         struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
1122         struct net_device *dev = cq->dev;
1123         struct mlx4_en_priv *priv = netdev_priv(dev);
1124         int done;
1125
1126         done = mlx4_en_process_rx_cq(dev, cq, budget);
1127
1128         /* If we used up all the quota - we're probably not done yet... */
1129         if (done == budget) {
1130                 const struct cpumask *aff;
1131                 struct irq_data *idata;
1132                 int cpu_curr;
1133
1134                 INC_PERF_COUNTER(priv->pstats.napi_quota);
1135
1136                 cpu_curr = smp_processor_id();
1137                 idata = irq_desc_get_irq_data(cq->irq_desc);
1138                 aff = irq_data_get_affinity_mask(idata);
1139
1140                 if (likely(cpumask_test_cpu(cpu_curr, aff)))
1141                         return budget;
1142
1143                 /* Current cpu is not according to smp_irq_affinity -
1144                  * probably affinity changed. Need to stop this NAPI
1145                  * poll, and restart it on the right CPU.
1146                  * Try to avoid returning a too small value (like 0),
1147                  * to not fool net_rx_action() and its netdev_budget
1148                  */
1149                 if (done)
1150                         done--;
1151         }
1152         /* Done for now */
1153         if (napi_complete_done(napi, done))
1154                 mlx4_en_arm_cq(priv, cq);
1155         return done;
1156 }
1157
1158 static const int frag_sizes[] = {
1159         FRAG_SZ0,
1160         FRAG_SZ1,
1161         FRAG_SZ2,
1162         FRAG_SZ3
1163 };
1164
1165 void mlx4_en_calc_rx_buf(struct net_device *dev)
1166 {
1167         struct mlx4_en_priv *priv = netdev_priv(dev);
1168         int eff_mtu = MLX4_EN_EFF_MTU(dev->mtu);
1169         int i = 0;
1170
1171         /* bpf requires buffers to be set up as 1 packet per page.
1172          * This only works when num_frags == 1.
1173          */
1174         if (priv->tx_ring_num[TX_XDP]) {
1175                 priv->frag_info[0].order = 0;
1176                 priv->frag_info[0].frag_size = eff_mtu;
1177                 priv->frag_info[0].frag_prefix_size = 0;
1178                 /* This will gain efficient xdp frame recycling at the
1179                  * expense of more costly truesize accounting
1180                  */
1181                 priv->frag_info[0].frag_stride = PAGE_SIZE;
1182                 priv->frag_info[0].dma_dir = PCI_DMA_BIDIRECTIONAL;
1183                 i = 1;
1184         } else {
1185                 int buf_size = 0;
1186
1187                 while (buf_size < eff_mtu) {
1188                         priv->frag_info[i].order = MLX4_EN_ALLOC_PREFER_ORDER;
1189                         priv->frag_info[i].frag_size =
1190                                 (eff_mtu > buf_size + frag_sizes[i]) ?
1191                                         frag_sizes[i] : eff_mtu - buf_size;
1192                         priv->frag_info[i].frag_prefix_size = buf_size;
1193                         priv->frag_info[i].frag_stride =
1194                                 ALIGN(priv->frag_info[i].frag_size,
1195                                       SMP_CACHE_BYTES);
1196                         priv->frag_info[i].dma_dir = PCI_DMA_FROMDEVICE;
1197                         buf_size += priv->frag_info[i].frag_size;
1198                         i++;
1199                 }
1200         }
1201
1202         priv->num_frags = i;
1203         priv->rx_skb_size = eff_mtu;
1204         priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc));
1205
1206         en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n",
1207                eff_mtu, priv->num_frags);
1208         for (i = 0; i < priv->num_frags; i++) {
1209                 en_err(priv,
1210                        "  frag:%d - size:%d prefix:%d stride:%d\n",
1211                        i,
1212                        priv->frag_info[i].frag_size,
1213                        priv->frag_info[i].frag_prefix_size,
1214                        priv->frag_info[i].frag_stride);
1215         }
1216 }
1217
1218 /* RSS related functions */
1219
1220 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
1221                                  struct mlx4_en_rx_ring *ring,
1222                                  enum mlx4_qp_state *state,
1223                                  struct mlx4_qp *qp)
1224 {
1225         struct mlx4_en_dev *mdev = priv->mdev;
1226         struct mlx4_qp_context *context;
1227         int err = 0;
1228
1229         context = kmalloc(sizeof(*context), GFP_KERNEL);
1230         if (!context)
1231                 return -ENOMEM;
1232
1233         err = mlx4_qp_alloc(mdev->dev, qpn, qp, GFP_KERNEL);
1234         if (err) {
1235                 en_err(priv, "Failed to allocate qp #%x\n", qpn);
1236                 goto out;
1237         }
1238         qp->event = mlx4_en_sqp_event;
1239
1240         memset(context, 0, sizeof *context);
1241         mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
1242                                 qpn, ring->cqn, -1, context);
1243         context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
1244
1245         /* Cancel FCS removal if FW allows */
1246         if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {
1247                 context->param3 |= cpu_to_be32(1 << 29);
1248                 if (priv->dev->features & NETIF_F_RXFCS)
1249                         ring->fcs_del = 0;
1250                 else
1251                         ring->fcs_del = ETH_FCS_LEN;
1252         } else
1253                 ring->fcs_del = 0;
1254
1255         err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
1256         if (err) {
1257                 mlx4_qp_remove(mdev->dev, qp);
1258                 mlx4_qp_free(mdev->dev, qp);
1259         }
1260         mlx4_en_update_rx_prod_db(ring);
1261 out:
1262         kfree(context);
1263         return err;
1264 }
1265
1266 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv)
1267 {
1268         int err;
1269         u32 qpn;
1270
1271         err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn,
1272                                     MLX4_RESERVE_A0_QP);
1273         if (err) {
1274                 en_err(priv, "Failed reserving drop qpn\n");
1275                 return err;
1276         }
1277         err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp, GFP_KERNEL);
1278         if (err) {
1279                 en_err(priv, "Failed allocating drop qp\n");
1280                 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1281                 return err;
1282         }
1283
1284         return 0;
1285 }
1286
1287 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv)
1288 {
1289         u32 qpn;
1290
1291         qpn = priv->drop_qp.qpn;
1292         mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp);
1293         mlx4_qp_free(priv->mdev->dev, &priv->drop_qp);
1294         mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1295 }
1296
1297 /* Allocate rx qp's and configure them according to rss map */
1298 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
1299 {
1300         struct mlx4_en_dev *mdev = priv->mdev;
1301         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1302         struct mlx4_qp_context context;
1303         struct mlx4_rss_context *rss_context;
1304         int rss_rings;
1305         void *ptr;
1306         u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |
1307                         MLX4_RSS_TCP_IPV6);
1308         int i, qpn;
1309         int err = 0;
1310         int good_qps = 0;
1311
1312         en_dbg(DRV, priv, "Configuring rss steering\n");
1313         err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
1314                                     priv->rx_ring_num,
1315                                     &rss_map->base_qpn, 0);
1316         if (err) {
1317                 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
1318                 return err;
1319         }
1320
1321         for (i = 0; i < priv->rx_ring_num; i++) {
1322                 qpn = rss_map->base_qpn + i;
1323                 err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i],
1324                                             &rss_map->state[i],
1325                                             &rss_map->qps[i]);
1326                 if (err)
1327                         goto rss_err;
1328
1329                 ++good_qps;
1330         }
1331
1332         /* Configure RSS indirection qp */
1333         err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp, GFP_KERNEL);
1334         if (err) {
1335                 en_err(priv, "Failed to allocate RSS indirection QP\n");
1336                 goto rss_err;
1337         }
1338         rss_map->indir_qp.event = mlx4_en_sqp_event;
1339         mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
1340                                 priv->rx_ring[0]->cqn, -1, &context);
1341
1342         if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num)
1343                 rss_rings = priv->rx_ring_num;
1344         else
1345                 rss_rings = priv->prof->rss_rings;
1346
1347         ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path)
1348                                         + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
1349         rss_context = ptr;
1350         rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 |
1351                                             (rss_map->base_qpn));
1352         rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
1353         if (priv->mdev->profile.udp_rss) {
1354                 rss_mask |=  MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;
1355                 rss_context->base_qpn_udp = rss_context->default_qpn;
1356         }
1357
1358         if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1359                 en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n");
1360                 rss_mask |= MLX4_RSS_BY_INNER_HEADERS;
1361         }
1362
1363         rss_context->flags = rss_mask;
1364         rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1365         if (priv->rss_hash_fn == ETH_RSS_HASH_XOR) {
1366                 rss_context->hash_fn = MLX4_RSS_HASH_XOR;
1367         } else if (priv->rss_hash_fn == ETH_RSS_HASH_TOP) {
1368                 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1369                 memcpy(rss_context->rss_key, priv->rss_key,
1370                        MLX4_EN_RSS_KEY_SIZE);
1371         } else {
1372                 en_err(priv, "Unknown RSS hash function requested\n");
1373                 err = -EINVAL;
1374                 goto indir_err;
1375         }
1376         err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
1377                                &rss_map->indir_qp, &rss_map->indir_state);
1378         if (err)
1379                 goto indir_err;
1380
1381         return 0;
1382
1383 indir_err:
1384         mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1385                        MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1386         mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1387         mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1388 rss_err:
1389         for (i = 0; i < good_qps; i++) {
1390                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1391                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1392                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1393                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1394         }
1395         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1396         return err;
1397 }
1398
1399 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
1400 {
1401         struct mlx4_en_dev *mdev = priv->mdev;
1402         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1403         int i;
1404
1405         mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1406                        MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1407         mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1408         mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1409
1410         for (i = 0; i < priv->rx_ring_num; i++) {
1411                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1412                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1413                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1414                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1415         }
1416         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1417 }