2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <linux/export.h>
38 #include <linux/pci.h>
39 #include <linux/errno.h>
41 #include <linux/mlx4/cmd.h>
42 #include <linux/mlx4/device.h>
43 #include <linux/semaphore.h>
44 #include <rdma/ib_smi.h>
51 #define CMD_POLL_TOKEN 0xffff
52 #define INBOX_MASK 0xffffffffffffff00ULL
54 #define CMD_CHAN_VER 1
55 #define CMD_CHAN_IF_REV 1
58 /* command completed successfully: */
60 /* Internal error (such as a bus error) occurred while processing command: */
61 CMD_STAT_INTERNAL_ERR = 0x01,
62 /* Operation/command not supported or opcode modifier not supported: */
63 CMD_STAT_BAD_OP = 0x02,
64 /* Parameter not supported or parameter out of range: */
65 CMD_STAT_BAD_PARAM = 0x03,
66 /* System not enabled or bad system state: */
67 CMD_STAT_BAD_SYS_STATE = 0x04,
68 /* Attempt to access reserved or unallocaterd resource: */
69 CMD_STAT_BAD_RESOURCE = 0x05,
70 /* Requested resource is currently executing a command, or is otherwise busy: */
71 CMD_STAT_RESOURCE_BUSY = 0x06,
72 /* Required capability exceeds device limits: */
73 CMD_STAT_EXCEED_LIM = 0x08,
74 /* Resource is not in the appropriate state or ownership: */
75 CMD_STAT_BAD_RES_STATE = 0x09,
76 /* Index out of range: */
77 CMD_STAT_BAD_INDEX = 0x0a,
78 /* FW image corrupted: */
79 CMD_STAT_BAD_NVMEM = 0x0b,
80 /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
81 CMD_STAT_ICM_ERROR = 0x0c,
82 /* Attempt to modify a QP/EE which is not in the presumed state: */
83 CMD_STAT_BAD_QP_STATE = 0x10,
84 /* Bad segment parameters (Address/Size): */
85 CMD_STAT_BAD_SEG_PARAM = 0x20,
86 /* Memory Region has Memory Windows bound to: */
87 CMD_STAT_REG_BOUND = 0x21,
88 /* HCA local attached memory not present: */
89 CMD_STAT_LAM_NOT_PRE = 0x22,
90 /* Bad management packet (silently discarded): */
91 CMD_STAT_BAD_PKT = 0x30,
92 /* More outstanding CQEs in CQ than new CQ size: */
93 CMD_STAT_BAD_SIZE = 0x40,
94 /* Multi Function device support required: */
95 CMD_STAT_MULTI_FUNC_REQ = 0x50,
99 HCR_IN_PARAM_OFFSET = 0x00,
100 HCR_IN_MODIFIER_OFFSET = 0x08,
101 HCR_OUT_PARAM_OFFSET = 0x0c,
102 HCR_TOKEN_OFFSET = 0x14,
103 HCR_STATUS_OFFSET = 0x18,
105 HCR_OPMOD_SHIFT = 12,
112 GO_BIT_TIMEOUT_MSECS = 10000
115 enum mlx4_vlan_transition {
116 MLX4_VLAN_TRANSITION_VST_VST = 0,
117 MLX4_VLAN_TRANSITION_VST_VGT = 1,
118 MLX4_VLAN_TRANSITION_VGT_VST = 2,
119 MLX4_VLAN_TRANSITION_VGT_VGT = 3,
123 struct mlx4_cmd_context {
124 struct completion done;
132 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
133 struct mlx4_vhcr_cmd *in_vhcr);
135 static int mlx4_status_to_errno(u8 status)
137 static const int trans_table[] = {
138 [CMD_STAT_INTERNAL_ERR] = -EIO,
139 [CMD_STAT_BAD_OP] = -EPERM,
140 [CMD_STAT_BAD_PARAM] = -EINVAL,
141 [CMD_STAT_BAD_SYS_STATE] = -ENXIO,
142 [CMD_STAT_BAD_RESOURCE] = -EBADF,
143 [CMD_STAT_RESOURCE_BUSY] = -EBUSY,
144 [CMD_STAT_EXCEED_LIM] = -ENOMEM,
145 [CMD_STAT_BAD_RES_STATE] = -EBADF,
146 [CMD_STAT_BAD_INDEX] = -EBADF,
147 [CMD_STAT_BAD_NVMEM] = -EFAULT,
148 [CMD_STAT_ICM_ERROR] = -ENFILE,
149 [CMD_STAT_BAD_QP_STATE] = -EINVAL,
150 [CMD_STAT_BAD_SEG_PARAM] = -EFAULT,
151 [CMD_STAT_REG_BOUND] = -EBUSY,
152 [CMD_STAT_LAM_NOT_PRE] = -EAGAIN,
153 [CMD_STAT_BAD_PKT] = -EINVAL,
154 [CMD_STAT_BAD_SIZE] = -ENOMEM,
155 [CMD_STAT_MULTI_FUNC_REQ] = -EACCES,
158 if (status >= ARRAY_SIZE(trans_table) ||
159 (status != CMD_STAT_OK && trans_table[status] == 0))
162 return trans_table[status];
165 static u8 mlx4_errno_to_status(int errno)
169 return CMD_STAT_BAD_OP;
171 return CMD_STAT_BAD_PARAM;
173 return CMD_STAT_BAD_SYS_STATE;
175 return CMD_STAT_RESOURCE_BUSY;
177 return CMD_STAT_EXCEED_LIM;
179 return CMD_STAT_ICM_ERROR;
181 return CMD_STAT_INTERNAL_ERR;
185 static int comm_pending(struct mlx4_dev *dev)
187 struct mlx4_priv *priv = mlx4_priv(dev);
188 u32 status = readl(&priv->mfunc.comm->slave_read);
190 return (swab32(status) >> 31) != priv->cmd.comm_toggle;
193 static void mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param)
195 struct mlx4_priv *priv = mlx4_priv(dev);
198 priv->cmd.comm_toggle ^= 1;
199 val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31);
200 __raw_writel((__force u32) cpu_to_be32(val),
201 &priv->mfunc.comm->slave_write);
205 static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
206 unsigned long timeout)
208 struct mlx4_priv *priv = mlx4_priv(dev);
211 int ret_from_pending = 0;
213 /* First, verify that the master reports correct status */
214 if (comm_pending(dev)) {
215 mlx4_warn(dev, "Communication channel is not idle - my toggle is %d (cmd:0x%x)\n",
216 priv->cmd.comm_toggle, cmd);
221 down(&priv->cmd.poll_sem);
222 mlx4_comm_cmd_post(dev, cmd, param);
224 end = msecs_to_jiffies(timeout) + jiffies;
225 while (comm_pending(dev) && time_before(jiffies, end))
227 ret_from_pending = comm_pending(dev);
228 if (ret_from_pending) {
229 /* check if the slave is trying to boot in the middle of
230 * FLR process. The only non-zero result in the RESET command
231 * is MLX4_DELAY_RESET_SLAVE*/
232 if ((MLX4_COMM_CMD_RESET == cmd)) {
233 err = MLX4_DELAY_RESET_SLAVE;
235 mlx4_warn(dev, "Communication channel timed out\n");
240 up(&priv->cmd.poll_sem);
244 static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 op,
245 u16 param, unsigned long timeout)
247 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
248 struct mlx4_cmd_context *context;
252 down(&cmd->event_sem);
254 spin_lock(&cmd->context_lock);
255 BUG_ON(cmd->free_head < 0);
256 context = &cmd->context[cmd->free_head];
257 context->token += cmd->token_mask + 1;
258 cmd->free_head = context->next;
259 spin_unlock(&cmd->context_lock);
261 init_completion(&context->done);
263 mlx4_comm_cmd_post(dev, op, param);
265 if (!wait_for_completion_timeout(&context->done,
266 msecs_to_jiffies(timeout))) {
267 mlx4_warn(dev, "communication channel command 0x%x timed out\n",
273 err = context->result;
274 if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) {
275 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
276 op, context->fw_status);
281 /* wait for comm channel ready
282 * this is necessary for prevention the race
283 * when switching between event to polling mode
285 end = msecs_to_jiffies(timeout) + jiffies;
286 while (comm_pending(dev) && time_before(jiffies, end))
289 spin_lock(&cmd->context_lock);
290 context->next = cmd->free_head;
291 cmd->free_head = context - cmd->context;
292 spin_unlock(&cmd->context_lock);
298 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
299 unsigned long timeout)
301 if (mlx4_priv(dev)->cmd.use_events)
302 return mlx4_comm_cmd_wait(dev, cmd, param, timeout);
303 return mlx4_comm_cmd_poll(dev, cmd, param, timeout);
306 static int cmd_pending(struct mlx4_dev *dev)
310 if (pci_channel_offline(dev->pdev))
313 status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
315 return (status & swab32(1 << HCR_GO_BIT)) ||
316 (mlx4_priv(dev)->cmd.toggle ==
317 !!(status & swab32(1 << HCR_T_BIT)));
320 static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
321 u32 in_modifier, u8 op_modifier, u16 op, u16 token,
324 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
325 u32 __iomem *hcr = cmd->hcr;
329 mutex_lock(&cmd->hcr_mutex);
331 if (pci_channel_offline(dev->pdev)) {
333 * Device is going through error recovery
334 * and cannot accept commands.
342 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
344 while (cmd_pending(dev)) {
345 if (pci_channel_offline(dev->pdev)) {
347 * Device is going through error recovery
348 * and cannot accept commands.
354 if (time_after_eq(jiffies, end)) {
355 mlx4_err(dev, "%s:cmd_pending failed\n", __func__);
362 * We use writel (instead of something like memcpy_toio)
363 * because writes of less than 32 bits to the HCR don't work
364 * (and some architectures such as ia64 implement memcpy_toio
365 * in terms of writeb).
367 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), hcr + 0);
368 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), hcr + 1);
369 __raw_writel((__force u32) cpu_to_be32(in_modifier), hcr + 2);
370 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), hcr + 3);
371 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
372 __raw_writel((__force u32) cpu_to_be32(token << 16), hcr + 5);
374 /* __raw_writel may not order writes. */
377 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
378 (cmd->toggle << HCR_T_BIT) |
379 (event ? (1 << HCR_E_BIT) : 0) |
380 (op_modifier << HCR_OPMOD_SHIFT) |
384 * Make sure that our HCR writes don't get mixed in with
385 * writes from another CPU starting a FW command.
389 cmd->toggle = cmd->toggle ^ 1;
394 mutex_unlock(&cmd->hcr_mutex);
398 static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
399 int out_is_imm, u32 in_modifier, u8 op_modifier,
400 u16 op, unsigned long timeout)
402 struct mlx4_priv *priv = mlx4_priv(dev);
403 struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr;
406 mutex_lock(&priv->cmd.slave_cmd_mutex);
408 vhcr->in_param = cpu_to_be64(in_param);
409 vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0;
410 vhcr->in_modifier = cpu_to_be32(in_modifier);
411 vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff));
412 vhcr->token = cpu_to_be16(CMD_POLL_TOKEN);
414 vhcr->flags = !!(priv->cmd.use_events) << 6;
416 if (mlx4_is_master(dev)) {
417 ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr);
422 be64_to_cpu(vhcr->out_param);
424 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
426 vhcr->status = CMD_STAT_BAD_PARAM;
429 ret = mlx4_status_to_errno(vhcr->status);
432 ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0,
433 MLX4_COMM_TIME + timeout);
438 be64_to_cpu(vhcr->out_param);
440 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
442 vhcr->status = CMD_STAT_BAD_PARAM;
445 ret = mlx4_status_to_errno(vhcr->status);
447 mlx4_err(dev, "failed execution of VHCR_POST command opcode 0x%x\n",
451 mutex_unlock(&priv->cmd.slave_cmd_mutex);
455 static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
456 int out_is_imm, u32 in_modifier, u8 op_modifier,
457 u16 op, unsigned long timeout)
459 struct mlx4_priv *priv = mlx4_priv(dev);
460 void __iomem *hcr = priv->cmd.hcr;
465 down(&priv->cmd.poll_sem);
467 if (pci_channel_offline(dev->pdev)) {
469 * Device is going through error recovery
470 * and cannot accept commands.
476 if (out_is_imm && !out_param) {
477 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
483 err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
484 in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
488 end = msecs_to_jiffies(timeout) + jiffies;
489 while (cmd_pending(dev) && time_before(jiffies, end)) {
490 if (pci_channel_offline(dev->pdev)) {
492 * Device is going through error recovery
493 * and cannot accept commands.
502 if (cmd_pending(dev)) {
503 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
511 (u64) be32_to_cpu((__force __be32)
512 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
513 (u64) be32_to_cpu((__force __be32)
514 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
515 stat = be32_to_cpu((__force __be32)
516 __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24;
517 err = mlx4_status_to_errno(stat);
519 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
523 up(&priv->cmd.poll_sem);
527 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
529 struct mlx4_priv *priv = mlx4_priv(dev);
530 struct mlx4_cmd_context *context =
531 &priv->cmd.context[token & priv->cmd.token_mask];
533 /* previously timed out command completing at long last */
534 if (token != context->token)
537 context->fw_status = status;
538 context->result = mlx4_status_to_errno(status);
539 context->out_param = out_param;
541 complete(&context->done);
544 static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
545 int out_is_imm, u32 in_modifier, u8 op_modifier,
546 u16 op, unsigned long timeout)
548 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
549 struct mlx4_cmd_context *context;
552 down(&cmd->event_sem);
554 spin_lock(&cmd->context_lock);
555 BUG_ON(cmd->free_head < 0);
556 context = &cmd->context[cmd->free_head];
557 context->token += cmd->token_mask + 1;
558 cmd->free_head = context->next;
559 spin_unlock(&cmd->context_lock);
561 if (out_is_imm && !out_param) {
562 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
568 init_completion(&context->done);
570 mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
571 in_modifier, op_modifier, op, context->token, 1);
573 if (!wait_for_completion_timeout(&context->done,
574 msecs_to_jiffies(timeout))) {
575 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
581 err = context->result;
583 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
584 op, context->fw_status);
589 *out_param = context->out_param;
592 spin_lock(&cmd->context_lock);
593 context->next = cmd->free_head;
594 cmd->free_head = context - cmd->context;
595 spin_unlock(&cmd->context_lock);
601 int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
602 int out_is_imm, u32 in_modifier, u8 op_modifier,
603 u16 op, unsigned long timeout, int native)
605 if (pci_channel_offline(dev->pdev))
608 if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) {
609 if (mlx4_priv(dev)->cmd.use_events)
610 return mlx4_cmd_wait(dev, in_param, out_param,
611 out_is_imm, in_modifier,
612 op_modifier, op, timeout);
614 return mlx4_cmd_poll(dev, in_param, out_param,
615 out_is_imm, in_modifier,
616 op_modifier, op, timeout);
618 return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm,
619 in_modifier, op_modifier, op, timeout);
621 EXPORT_SYMBOL_GPL(__mlx4_cmd);
624 static int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev)
626 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL,
627 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
630 static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr,
631 int slave, u64 slave_addr,
632 int size, int is_read)
637 if ((slave_addr & 0xfff) | (master_addr & 0xfff) |
638 (slave & ~0x7f) | (size & 0xff)) {
639 mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx master_addr:0x%llx slave_id:%d size:%d\n",
640 slave_addr, master_addr, slave, size);
645 in_param = (u64) slave | slave_addr;
646 out_param = (u64) dev->caps.function | master_addr;
648 in_param = (u64) dev->caps.function | master_addr;
649 out_param = (u64) slave | slave_addr;
652 return mlx4_cmd_imm(dev, in_param, &out_param, size, 0,
654 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
657 static int query_pkey_block(struct mlx4_dev *dev, u8 port, u16 index, u16 *pkey,
658 struct mlx4_cmd_mailbox *inbox,
659 struct mlx4_cmd_mailbox *outbox)
661 struct ib_smp *in_mad = (struct ib_smp *)(inbox->buf);
662 struct ib_smp *out_mad = (struct ib_smp *)(outbox->buf);
669 in_mad->attr_mod = cpu_to_be32(index / 32);
671 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3,
672 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
677 for (i = 0; i < 32; ++i)
678 pkey[i] = be16_to_cpu(((__be16 *) out_mad->data)[i]);
683 static int get_full_pkey_table(struct mlx4_dev *dev, u8 port, u16 *table,
684 struct mlx4_cmd_mailbox *inbox,
685 struct mlx4_cmd_mailbox *outbox)
690 for (i = 0; i < dev->caps.pkey_table_len[port]; i += 32) {
691 err = query_pkey_block(dev, port, i, table + i, inbox, outbox);
698 #define PORT_CAPABILITY_LOCATION_IN_SMP 20
699 #define PORT_STATE_OFFSET 32
701 static enum ib_port_state vf_port_state(struct mlx4_dev *dev, int port, int vf)
703 if (mlx4_get_slave_port_state(dev, vf, port) == SLAVE_PORT_UP)
704 return IB_PORT_ACTIVE;
709 static int mlx4_MAD_IFC_wrapper(struct mlx4_dev *dev, int slave,
710 struct mlx4_vhcr *vhcr,
711 struct mlx4_cmd_mailbox *inbox,
712 struct mlx4_cmd_mailbox *outbox,
713 struct mlx4_cmd_info *cmd)
715 struct ib_smp *smp = inbox->buf;
723 struct mlx4_priv *priv = mlx4_priv(dev);
724 struct ib_smp *outsmp = outbox->buf;
725 __be16 *outtab = (__be16 *)(outsmp->data);
726 __be32 slave_cap_mask;
727 __be64 slave_node_guid;
729 port = vhcr->in_modifier;
731 /* network-view bit is for driver use only, and should not be passed to FW */
732 opcode_modifier = vhcr->op_modifier & ~0x8; /* clear netw view bit */
733 network_view = !!(vhcr->op_modifier & 0x8);
735 if (smp->base_version == 1 &&
736 smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
737 smp->class_version == 1) {
738 /* host view is paravirtualized */
739 if (!network_view && smp->method == IB_MGMT_METHOD_GET) {
740 if (smp->attr_id == IB_SMP_ATTR_PKEY_TABLE) {
741 index = be32_to_cpu(smp->attr_mod);
742 if (port < 1 || port > dev->caps.num_ports)
744 table = kcalloc(dev->caps.pkey_table_len[port], sizeof *table, GFP_KERNEL);
747 /* need to get the full pkey table because the paravirtualized
748 * pkeys may be scattered among several pkey blocks.
750 err = get_full_pkey_table(dev, port, table, inbox, outbox);
752 for (vidx = index * 32; vidx < (index + 1) * 32; ++vidx) {
753 pidx = priv->virt2phys_pkey[slave][port - 1][vidx];
754 outtab[vidx % 32] = cpu_to_be16(table[pidx]);
760 if (smp->attr_id == IB_SMP_ATTR_PORT_INFO) {
761 /*get the slave specific caps:*/
763 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
764 vhcr->in_modifier, opcode_modifier,
765 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
766 /* modify the response for slaves */
767 if (!err && slave != mlx4_master_func_num(dev)) {
768 u8 *state = outsmp->data + PORT_STATE_OFFSET;
770 *state = (*state & 0xf0) | vf_port_state(dev, port, slave);
771 slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
772 memcpy(outsmp->data + PORT_CAPABILITY_LOCATION_IN_SMP, &slave_cap_mask, 4);
776 if (smp->attr_id == IB_SMP_ATTR_GUID_INFO) {
777 /* compute slave's gid block */
778 smp->attr_mod = cpu_to_be32(slave / 8);
780 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
781 vhcr->in_modifier, opcode_modifier,
782 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
784 /* if needed, move slave gid to index 0 */
787 outsmp->data + (slave % 8) * 8, 8);
788 /* delete all other gids */
789 memset(outsmp->data + 8, 0, 56);
793 if (smp->attr_id == IB_SMP_ATTR_NODE_INFO) {
794 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
795 vhcr->in_modifier, opcode_modifier,
796 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
798 slave_node_guid = mlx4_get_slave_node_guid(dev, slave);
799 memcpy(outsmp->data + 12, &slave_node_guid, 8);
806 /* Non-privileged VFs are only allowed "host" view LID-routed 'Get' MADs.
807 * These are the MADs used by ib verbs (such as ib_query_gids).
809 if (slave != mlx4_master_func_num(dev) &&
810 !mlx4_vf_smi_enabled(dev, slave, port)) {
811 if (!(smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
812 smp->method == IB_MGMT_METHOD_GET) || network_view) {
813 mlx4_err(dev, "Unprivileged slave %d is trying to execute a Subnet MGMT MAD, class 0x%x, method 0x%x, view=%s for attr 0x%x. Rejecting\n",
814 slave, smp->method, smp->mgmt_class,
815 network_view ? "Network" : "Host",
816 be16_to_cpu(smp->attr_id));
821 return mlx4_cmd_box(dev, inbox->dma, outbox->dma,
822 vhcr->in_modifier, opcode_modifier,
823 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
826 static int mlx4_CMD_EPERM_wrapper(struct mlx4_dev *dev, int slave,
827 struct mlx4_vhcr *vhcr,
828 struct mlx4_cmd_mailbox *inbox,
829 struct mlx4_cmd_mailbox *outbox,
830 struct mlx4_cmd_info *cmd)
835 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
836 struct mlx4_vhcr *vhcr,
837 struct mlx4_cmd_mailbox *inbox,
838 struct mlx4_cmd_mailbox *outbox,
839 struct mlx4_cmd_info *cmd)
845 in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param;
846 out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param;
847 if (cmd->encode_slave_id) {
848 in_param &= 0xffffffffffffff00ll;
852 err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm,
853 vhcr->in_modifier, vhcr->op_modifier, vhcr->op,
854 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
857 vhcr->out_param = out_param;
862 static struct mlx4_cmd_info cmd_info[] = {
864 .opcode = MLX4_CMD_QUERY_FW,
868 .encode_slave_id = false,
870 .wrapper = mlx4_QUERY_FW_wrapper
873 .opcode = MLX4_CMD_QUERY_HCA,
877 .encode_slave_id = false,
882 .opcode = MLX4_CMD_QUERY_DEV_CAP,
886 .encode_slave_id = false,
888 .wrapper = mlx4_QUERY_DEV_CAP_wrapper
891 .opcode = MLX4_CMD_QUERY_FUNC_CAP,
895 .encode_slave_id = false,
897 .wrapper = mlx4_QUERY_FUNC_CAP_wrapper
900 .opcode = MLX4_CMD_QUERY_ADAPTER,
904 .encode_slave_id = false,
909 .opcode = MLX4_CMD_INIT_PORT,
913 .encode_slave_id = false,
915 .wrapper = mlx4_INIT_PORT_wrapper
918 .opcode = MLX4_CMD_CLOSE_PORT,
922 .encode_slave_id = false,
924 .wrapper = mlx4_CLOSE_PORT_wrapper
927 .opcode = MLX4_CMD_QUERY_PORT,
931 .encode_slave_id = false,
933 .wrapper = mlx4_QUERY_PORT_wrapper
936 .opcode = MLX4_CMD_SET_PORT,
940 .encode_slave_id = false,
942 .wrapper = mlx4_SET_PORT_wrapper
945 .opcode = MLX4_CMD_MAP_EQ,
949 .encode_slave_id = false,
951 .wrapper = mlx4_MAP_EQ_wrapper
954 .opcode = MLX4_CMD_SW2HW_EQ,
958 .encode_slave_id = true,
960 .wrapper = mlx4_SW2HW_EQ_wrapper
963 .opcode = MLX4_CMD_HW_HEALTH_CHECK,
967 .encode_slave_id = false,
972 .opcode = MLX4_CMD_NOP,
976 .encode_slave_id = false,
981 .opcode = MLX4_CMD_CONFIG_DEV,
985 .encode_slave_id = false,
987 .wrapper = mlx4_CMD_EPERM_wrapper
990 .opcode = MLX4_CMD_ALLOC_RES,
994 .encode_slave_id = false,
996 .wrapper = mlx4_ALLOC_RES_wrapper
999 .opcode = MLX4_CMD_FREE_RES,
1001 .has_outbox = false,
1002 .out_is_imm = false,
1003 .encode_slave_id = false,
1005 .wrapper = mlx4_FREE_RES_wrapper
1008 .opcode = MLX4_CMD_SW2HW_MPT,
1010 .has_outbox = false,
1011 .out_is_imm = false,
1012 .encode_slave_id = true,
1014 .wrapper = mlx4_SW2HW_MPT_wrapper
1017 .opcode = MLX4_CMD_QUERY_MPT,
1020 .out_is_imm = false,
1021 .encode_slave_id = false,
1023 .wrapper = mlx4_QUERY_MPT_wrapper
1026 .opcode = MLX4_CMD_HW2SW_MPT,
1028 .has_outbox = false,
1029 .out_is_imm = false,
1030 .encode_slave_id = false,
1032 .wrapper = mlx4_HW2SW_MPT_wrapper
1035 .opcode = MLX4_CMD_READ_MTT,
1038 .out_is_imm = false,
1039 .encode_slave_id = false,
1044 .opcode = MLX4_CMD_WRITE_MTT,
1046 .has_outbox = false,
1047 .out_is_imm = false,
1048 .encode_slave_id = false,
1050 .wrapper = mlx4_WRITE_MTT_wrapper
1053 .opcode = MLX4_CMD_SYNC_TPT,
1055 .has_outbox = false,
1056 .out_is_imm = false,
1057 .encode_slave_id = false,
1062 .opcode = MLX4_CMD_HW2SW_EQ,
1065 .out_is_imm = false,
1066 .encode_slave_id = true,
1068 .wrapper = mlx4_HW2SW_EQ_wrapper
1071 .opcode = MLX4_CMD_QUERY_EQ,
1074 .out_is_imm = false,
1075 .encode_slave_id = true,
1077 .wrapper = mlx4_QUERY_EQ_wrapper
1080 .opcode = MLX4_CMD_SW2HW_CQ,
1082 .has_outbox = false,
1083 .out_is_imm = false,
1084 .encode_slave_id = true,
1086 .wrapper = mlx4_SW2HW_CQ_wrapper
1089 .opcode = MLX4_CMD_HW2SW_CQ,
1091 .has_outbox = false,
1092 .out_is_imm = false,
1093 .encode_slave_id = false,
1095 .wrapper = mlx4_HW2SW_CQ_wrapper
1098 .opcode = MLX4_CMD_QUERY_CQ,
1101 .out_is_imm = false,
1102 .encode_slave_id = false,
1104 .wrapper = mlx4_QUERY_CQ_wrapper
1107 .opcode = MLX4_CMD_MODIFY_CQ,
1109 .has_outbox = false,
1111 .encode_slave_id = false,
1113 .wrapper = mlx4_MODIFY_CQ_wrapper
1116 .opcode = MLX4_CMD_SW2HW_SRQ,
1118 .has_outbox = false,
1119 .out_is_imm = false,
1120 .encode_slave_id = true,
1122 .wrapper = mlx4_SW2HW_SRQ_wrapper
1125 .opcode = MLX4_CMD_HW2SW_SRQ,
1127 .has_outbox = false,
1128 .out_is_imm = false,
1129 .encode_slave_id = false,
1131 .wrapper = mlx4_HW2SW_SRQ_wrapper
1134 .opcode = MLX4_CMD_QUERY_SRQ,
1137 .out_is_imm = false,
1138 .encode_slave_id = false,
1140 .wrapper = mlx4_QUERY_SRQ_wrapper
1143 .opcode = MLX4_CMD_ARM_SRQ,
1145 .has_outbox = false,
1146 .out_is_imm = false,
1147 .encode_slave_id = false,
1149 .wrapper = mlx4_ARM_SRQ_wrapper
1152 .opcode = MLX4_CMD_RST2INIT_QP,
1154 .has_outbox = false,
1155 .out_is_imm = false,
1156 .encode_slave_id = true,
1158 .wrapper = mlx4_RST2INIT_QP_wrapper
1161 .opcode = MLX4_CMD_INIT2INIT_QP,
1163 .has_outbox = false,
1164 .out_is_imm = false,
1165 .encode_slave_id = false,
1167 .wrapper = mlx4_INIT2INIT_QP_wrapper
1170 .opcode = MLX4_CMD_INIT2RTR_QP,
1172 .has_outbox = false,
1173 .out_is_imm = false,
1174 .encode_slave_id = false,
1176 .wrapper = mlx4_INIT2RTR_QP_wrapper
1179 .opcode = MLX4_CMD_RTR2RTS_QP,
1181 .has_outbox = false,
1182 .out_is_imm = false,
1183 .encode_slave_id = false,
1185 .wrapper = mlx4_RTR2RTS_QP_wrapper
1188 .opcode = MLX4_CMD_RTS2RTS_QP,
1190 .has_outbox = false,
1191 .out_is_imm = false,
1192 .encode_slave_id = false,
1194 .wrapper = mlx4_RTS2RTS_QP_wrapper
1197 .opcode = MLX4_CMD_SQERR2RTS_QP,
1199 .has_outbox = false,
1200 .out_is_imm = false,
1201 .encode_slave_id = false,
1203 .wrapper = mlx4_SQERR2RTS_QP_wrapper
1206 .opcode = MLX4_CMD_2ERR_QP,
1208 .has_outbox = false,
1209 .out_is_imm = false,
1210 .encode_slave_id = false,
1212 .wrapper = mlx4_GEN_QP_wrapper
1215 .opcode = MLX4_CMD_RTS2SQD_QP,
1217 .has_outbox = false,
1218 .out_is_imm = false,
1219 .encode_slave_id = false,
1221 .wrapper = mlx4_GEN_QP_wrapper
1224 .opcode = MLX4_CMD_SQD2SQD_QP,
1226 .has_outbox = false,
1227 .out_is_imm = false,
1228 .encode_slave_id = false,
1230 .wrapper = mlx4_SQD2SQD_QP_wrapper
1233 .opcode = MLX4_CMD_SQD2RTS_QP,
1235 .has_outbox = false,
1236 .out_is_imm = false,
1237 .encode_slave_id = false,
1239 .wrapper = mlx4_SQD2RTS_QP_wrapper
1242 .opcode = MLX4_CMD_2RST_QP,
1244 .has_outbox = false,
1245 .out_is_imm = false,
1246 .encode_slave_id = false,
1248 .wrapper = mlx4_2RST_QP_wrapper
1251 .opcode = MLX4_CMD_QUERY_QP,
1254 .out_is_imm = false,
1255 .encode_slave_id = false,
1257 .wrapper = mlx4_GEN_QP_wrapper
1260 .opcode = MLX4_CMD_SUSPEND_QP,
1262 .has_outbox = false,
1263 .out_is_imm = false,
1264 .encode_slave_id = false,
1266 .wrapper = mlx4_GEN_QP_wrapper
1269 .opcode = MLX4_CMD_UNSUSPEND_QP,
1271 .has_outbox = false,
1272 .out_is_imm = false,
1273 .encode_slave_id = false,
1275 .wrapper = mlx4_GEN_QP_wrapper
1278 .opcode = MLX4_CMD_UPDATE_QP,
1280 .has_outbox = false,
1281 .out_is_imm = false,
1282 .encode_slave_id = false,
1284 .wrapper = mlx4_UPDATE_QP_wrapper
1287 .opcode = MLX4_CMD_GET_OP_REQ,
1289 .has_outbox = false,
1290 .out_is_imm = false,
1291 .encode_slave_id = false,
1293 .wrapper = mlx4_CMD_EPERM_wrapper,
1296 .opcode = MLX4_CMD_CONF_SPECIAL_QP,
1298 .has_outbox = false,
1299 .out_is_imm = false,
1300 .encode_slave_id = false,
1301 .verify = NULL, /* XXX verify: only demux can do this */
1305 .opcode = MLX4_CMD_MAD_IFC,
1308 .out_is_imm = false,
1309 .encode_slave_id = false,
1311 .wrapper = mlx4_MAD_IFC_wrapper
1314 .opcode = MLX4_CMD_QUERY_IF_STAT,
1317 .out_is_imm = false,
1318 .encode_slave_id = false,
1320 .wrapper = mlx4_QUERY_IF_STAT_wrapper
1322 /* Native multicast commands are not available for guests */
1324 .opcode = MLX4_CMD_QP_ATTACH,
1326 .has_outbox = false,
1327 .out_is_imm = false,
1328 .encode_slave_id = false,
1330 .wrapper = mlx4_QP_ATTACH_wrapper
1333 .opcode = MLX4_CMD_PROMISC,
1335 .has_outbox = false,
1336 .out_is_imm = false,
1337 .encode_slave_id = false,
1339 .wrapper = mlx4_PROMISC_wrapper
1341 /* Ethernet specific commands */
1343 .opcode = MLX4_CMD_SET_VLAN_FLTR,
1345 .has_outbox = false,
1346 .out_is_imm = false,
1347 .encode_slave_id = false,
1349 .wrapper = mlx4_SET_VLAN_FLTR_wrapper
1352 .opcode = MLX4_CMD_SET_MCAST_FLTR,
1354 .has_outbox = false,
1355 .out_is_imm = false,
1356 .encode_slave_id = false,
1358 .wrapper = mlx4_SET_MCAST_FLTR_wrapper
1361 .opcode = MLX4_CMD_DUMP_ETH_STATS,
1364 .out_is_imm = false,
1365 .encode_slave_id = false,
1367 .wrapper = mlx4_DUMP_ETH_STATS_wrapper
1370 .opcode = MLX4_CMD_INFORM_FLR_DONE,
1372 .has_outbox = false,
1373 .out_is_imm = false,
1374 .encode_slave_id = false,
1378 /* flow steering commands */
1380 .opcode = MLX4_QP_FLOW_STEERING_ATTACH,
1382 .has_outbox = false,
1384 .encode_slave_id = false,
1386 .wrapper = mlx4_QP_FLOW_STEERING_ATTACH_wrapper
1389 .opcode = MLX4_QP_FLOW_STEERING_DETACH,
1391 .has_outbox = false,
1392 .out_is_imm = false,
1393 .encode_slave_id = false,
1395 .wrapper = mlx4_QP_FLOW_STEERING_DETACH_wrapper
1398 .opcode = MLX4_FLOW_STEERING_IB_UC_QP_RANGE,
1400 .has_outbox = false,
1401 .out_is_imm = false,
1402 .encode_slave_id = false,
1404 .wrapper = mlx4_CMD_EPERM_wrapper
1408 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
1409 struct mlx4_vhcr_cmd *in_vhcr)
1411 struct mlx4_priv *priv = mlx4_priv(dev);
1412 struct mlx4_cmd_info *cmd = NULL;
1413 struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr;
1414 struct mlx4_vhcr *vhcr;
1415 struct mlx4_cmd_mailbox *inbox = NULL;
1416 struct mlx4_cmd_mailbox *outbox = NULL;
1423 /* Create sw representation of Virtual HCR */
1424 vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL);
1428 /* DMA in the vHCR */
1430 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1431 priv->mfunc.master.slave_state[slave].vhcr_dma,
1432 ALIGN(sizeof(struct mlx4_vhcr_cmd),
1433 MLX4_ACCESS_MEM_ALIGN), 1);
1435 mlx4_err(dev, "%s: Failed reading vhcr ret: 0x%x\n",
1442 /* Fill SW VHCR fields */
1443 vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param);
1444 vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param);
1445 vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier);
1446 vhcr->token = be16_to_cpu(vhcr_cmd->token);
1447 vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff;
1448 vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12);
1449 vhcr->e_bit = vhcr_cmd->flags & (1 << 6);
1451 /* Lookup command */
1452 for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) {
1453 if (vhcr->op == cmd_info[i].opcode) {
1459 mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n",
1461 vhcr_cmd->status = CMD_STAT_BAD_PARAM;
1466 if (cmd->has_inbox) {
1467 vhcr->in_param &= INBOX_MASK;
1468 inbox = mlx4_alloc_cmd_mailbox(dev);
1469 if (IS_ERR(inbox)) {
1470 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1475 if (mlx4_ACCESS_MEM(dev, inbox->dma, slave,
1477 MLX4_MAILBOX_SIZE, 1)) {
1478 mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n",
1479 __func__, cmd->opcode);
1480 vhcr_cmd->status = CMD_STAT_INTERNAL_ERR;
1485 /* Apply permission and bound checks if applicable */
1486 if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) {
1487 mlx4_warn(dev, "Command:0x%x from slave: %d failed protection checks for resource_id:%d\n",
1488 vhcr->op, slave, vhcr->in_modifier);
1489 vhcr_cmd->status = CMD_STAT_BAD_OP;
1493 /* Allocate outbox */
1494 if (cmd->has_outbox) {
1495 outbox = mlx4_alloc_cmd_mailbox(dev);
1496 if (IS_ERR(outbox)) {
1497 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1503 /* Execute the command! */
1505 err = cmd->wrapper(dev, slave, vhcr, inbox, outbox,
1507 if (cmd->out_is_imm)
1508 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1510 in_param = cmd->has_inbox ? (u64) inbox->dma :
1512 out_param = cmd->has_outbox ? (u64) outbox->dma :
1514 err = __mlx4_cmd(dev, in_param, &out_param,
1515 cmd->out_is_imm, vhcr->in_modifier,
1516 vhcr->op_modifier, vhcr->op,
1517 MLX4_CMD_TIME_CLASS_A,
1520 if (cmd->out_is_imm) {
1521 vhcr->out_param = out_param;
1522 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1527 mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with error:%d, status %d\n",
1528 vhcr->op, slave, vhcr->errno, err);
1529 vhcr_cmd->status = mlx4_errno_to_status(err);
1534 /* Write outbox if command completed successfully */
1535 if (cmd->has_outbox && !vhcr_cmd->status) {
1536 ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave,
1538 MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED);
1540 /* If we failed to write back the outbox after the
1541 *command was successfully executed, we must fail this
1542 * slave, as it is now in undefined state */
1543 mlx4_err(dev, "%s:Failed writing outbox\n", __func__);
1549 /* DMA back vhcr result */
1551 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1552 priv->mfunc.master.slave_state[slave].vhcr_dma,
1553 ALIGN(sizeof(struct mlx4_vhcr),
1554 MLX4_ACCESS_MEM_ALIGN),
1557 mlx4_err(dev, "%s:Failed writing vhcr result\n",
1559 else if (vhcr->e_bit &&
1560 mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe))
1561 mlx4_warn(dev, "Failed to generate command completion eqe for slave %d\n",
1567 mlx4_free_cmd_mailbox(dev, inbox);
1568 mlx4_free_cmd_mailbox(dev, outbox);
1572 static int mlx4_master_immediate_activate_vlan_qos(struct mlx4_priv *priv,
1573 int slave, int port)
1575 struct mlx4_vport_oper_state *vp_oper;
1576 struct mlx4_vport_state *vp_admin;
1577 struct mlx4_vf_immed_vlan_work *work;
1578 struct mlx4_dev *dev = &(priv->dev);
1580 int admin_vlan_ix = NO_INDX;
1582 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1583 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1585 if (vp_oper->state.default_vlan == vp_admin->default_vlan &&
1586 vp_oper->state.default_qos == vp_admin->default_qos &&
1587 vp_oper->state.link_state == vp_admin->link_state)
1590 if (!(priv->mfunc.master.slave_state[slave].active &&
1591 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP)) {
1592 /* even if the UPDATE_QP command isn't supported, we still want
1593 * to set this VF link according to the admin directive
1595 vp_oper->state.link_state = vp_admin->link_state;
1599 mlx4_dbg(dev, "updating immediately admin params slave %d port %d\n",
1601 mlx4_dbg(dev, "vlan %d QoS %d link down %d\n",
1602 vp_admin->default_vlan, vp_admin->default_qos,
1603 vp_admin->link_state);
1605 work = kzalloc(sizeof(*work), GFP_KERNEL);
1609 if (vp_oper->state.default_vlan != vp_admin->default_vlan) {
1610 if (MLX4_VGT != vp_admin->default_vlan) {
1611 err = __mlx4_register_vlan(&priv->dev, port,
1612 vp_admin->default_vlan,
1616 mlx4_warn(&priv->dev,
1617 "No vlan resources slave %d, port %d\n",
1622 admin_vlan_ix = NO_INDX;
1624 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_VLAN;
1625 mlx4_dbg(&priv->dev,
1626 "alloc vlan %d idx %d slave %d port %d\n",
1627 (int)(vp_admin->default_vlan),
1628 admin_vlan_ix, slave, port);
1631 /* save original vlan ix and vlan id */
1632 work->orig_vlan_id = vp_oper->state.default_vlan;
1633 work->orig_vlan_ix = vp_oper->vlan_idx;
1635 /* handle new qos */
1636 if (vp_oper->state.default_qos != vp_admin->default_qos)
1637 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_QOS;
1639 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN)
1640 vp_oper->vlan_idx = admin_vlan_ix;
1642 vp_oper->state.default_vlan = vp_admin->default_vlan;
1643 vp_oper->state.default_qos = vp_admin->default_qos;
1644 vp_oper->state.link_state = vp_admin->link_state;
1646 if (vp_admin->link_state == IFLA_VF_LINK_STATE_DISABLE)
1647 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE;
1649 /* iterate over QPs owned by this slave, using UPDATE_QP */
1651 work->slave = slave;
1652 work->qos = vp_oper->state.default_qos;
1653 work->vlan_id = vp_oper->state.default_vlan;
1654 work->vlan_ix = vp_oper->vlan_idx;
1656 INIT_WORK(&work->work, mlx4_vf_immed_vlan_work_handler);
1657 queue_work(priv->mfunc.master.comm_wq, &work->work);
1663 static int mlx4_master_activate_admin_state(struct mlx4_priv *priv, int slave)
1666 struct mlx4_vport_state *vp_admin;
1667 struct mlx4_vport_oper_state *vp_oper;
1668 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
1670 int min_port = find_first_bit(actv_ports.ports,
1671 priv->dev.caps.num_ports) + 1;
1672 int max_port = min_port - 1 +
1673 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
1675 for (port = min_port; port <= max_port; port++) {
1676 if (!test_bit(port - 1, actv_ports.ports))
1678 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
1679 priv->mfunc.master.vf_admin[slave].enable_smi[port];
1680 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1681 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1682 vp_oper->state = *vp_admin;
1683 if (MLX4_VGT != vp_admin->default_vlan) {
1684 err = __mlx4_register_vlan(&priv->dev, port,
1685 vp_admin->default_vlan, &(vp_oper->vlan_idx));
1687 vp_oper->vlan_idx = NO_INDX;
1688 mlx4_warn(&priv->dev,
1689 "No vlan resorces slave %d, port %d\n",
1693 mlx4_dbg(&priv->dev, "alloc vlan %d idx %d slave %d port %d\n",
1694 (int)(vp_oper->state.default_vlan),
1695 vp_oper->vlan_idx, slave, port);
1697 if (vp_admin->spoofchk) {
1698 vp_oper->mac_idx = __mlx4_register_mac(&priv->dev,
1701 if (0 > vp_oper->mac_idx) {
1702 err = vp_oper->mac_idx;
1703 vp_oper->mac_idx = NO_INDX;
1704 mlx4_warn(&priv->dev,
1705 "No mac resorces slave %d, port %d\n",
1709 mlx4_dbg(&priv->dev, "alloc mac %llx idx %d slave %d port %d\n",
1710 vp_oper->state.mac, vp_oper->mac_idx, slave, port);
1716 static void mlx4_master_deactivate_admin_state(struct mlx4_priv *priv, int slave)
1719 struct mlx4_vport_oper_state *vp_oper;
1720 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
1722 int min_port = find_first_bit(actv_ports.ports,
1723 priv->dev.caps.num_ports) + 1;
1724 int max_port = min_port - 1 +
1725 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
1728 for (port = min_port; port <= max_port; port++) {
1729 if (!test_bit(port - 1, actv_ports.ports))
1731 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
1732 MLX4_VF_SMI_DISABLED;
1733 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1734 if (NO_INDX != vp_oper->vlan_idx) {
1735 __mlx4_unregister_vlan(&priv->dev,
1736 port, vp_oper->state.default_vlan);
1737 vp_oper->vlan_idx = NO_INDX;
1739 if (NO_INDX != vp_oper->mac_idx) {
1740 __mlx4_unregister_mac(&priv->dev, port, vp_oper->state.mac);
1741 vp_oper->mac_idx = NO_INDX;
1747 static void mlx4_master_do_cmd(struct mlx4_dev *dev, int slave, u8 cmd,
1748 u16 param, u8 toggle)
1750 struct mlx4_priv *priv = mlx4_priv(dev);
1751 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
1753 u8 is_going_down = 0;
1755 unsigned long flags;
1757 slave_state[slave].comm_toggle ^= 1;
1758 reply = (u32) slave_state[slave].comm_toggle << 31;
1759 if (toggle != slave_state[slave].comm_toggle) {
1760 mlx4_warn(dev, "Incorrect toggle %d from slave %d. *** MASTER STATE COMPROMISED ***\n",
1764 if (cmd == MLX4_COMM_CMD_RESET) {
1765 mlx4_warn(dev, "Received reset from slave:%d\n", slave);
1766 slave_state[slave].active = false;
1767 slave_state[slave].old_vlan_api = false;
1768 mlx4_master_deactivate_admin_state(priv, slave);
1769 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) {
1770 slave_state[slave].event_eq[i].eqn = -1;
1771 slave_state[slave].event_eq[i].token = 0;
1773 /*check if we are in the middle of FLR process,
1774 if so return "retry" status to the slave*/
1775 if (MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd)
1776 goto inform_slave_state;
1778 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN, slave);
1780 /* write the version in the event field */
1781 reply |= mlx4_comm_get_version();
1785 /*command from slave in the middle of FLR*/
1786 if (cmd != MLX4_COMM_CMD_RESET &&
1787 MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) {
1788 mlx4_warn(dev, "slave:%d is Trying to run cmd(0x%x) in the middle of FLR\n",
1794 case MLX4_COMM_CMD_VHCR0:
1795 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_RESET)
1797 slave_state[slave].vhcr_dma = ((u64) param) << 48;
1798 priv->mfunc.master.slave_state[slave].cookie = 0;
1799 mutex_init(&priv->mfunc.master.gen_eqe_mutex[slave]);
1801 case MLX4_COMM_CMD_VHCR1:
1802 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR0)
1804 slave_state[slave].vhcr_dma |= ((u64) param) << 32;
1806 case MLX4_COMM_CMD_VHCR2:
1807 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR1)
1809 slave_state[slave].vhcr_dma |= ((u64) param) << 16;
1811 case MLX4_COMM_CMD_VHCR_EN:
1812 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR2)
1814 slave_state[slave].vhcr_dma |= param;
1815 if (mlx4_master_activate_admin_state(priv, slave))
1817 slave_state[slave].active = true;
1818 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_INIT, slave);
1820 case MLX4_COMM_CMD_VHCR_POST:
1821 if ((slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_EN) &&
1822 (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_POST))
1825 mutex_lock(&priv->cmd.slave_cmd_mutex);
1826 if (mlx4_master_process_vhcr(dev, slave, NULL)) {
1827 mlx4_err(dev, "Failed processing vhcr for slave:%d, resetting slave\n",
1829 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1832 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1835 mlx4_warn(dev, "Bad comm cmd:%d from slave:%d\n", cmd, slave);
1838 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
1839 if (!slave_state[slave].is_slave_going_down)
1840 slave_state[slave].last_cmd = cmd;
1843 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
1844 if (is_going_down) {
1845 mlx4_warn(dev, "Slave is going down aborting command(%d) executing from slave:%d\n",
1849 __raw_writel((__force u32) cpu_to_be32(reply),
1850 &priv->mfunc.comm[slave].slave_read);
1856 /* cleanup any slave resources */
1857 mlx4_delete_all_resources_for_slave(dev, slave);
1858 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
1859 if (!slave_state[slave].is_slave_going_down)
1860 slave_state[slave].last_cmd = MLX4_COMM_CMD_RESET;
1861 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
1862 /*with slave in the middle of flr, no need to clean resources again.*/
1864 memset(&slave_state[slave].event_eq, 0,
1865 sizeof(struct mlx4_slave_event_eq_info));
1866 __raw_writel((__force u32) cpu_to_be32(reply),
1867 &priv->mfunc.comm[slave].slave_read);
1871 /* master command processing */
1872 void mlx4_master_comm_channel(struct work_struct *work)
1874 struct mlx4_mfunc_master_ctx *master =
1876 struct mlx4_mfunc_master_ctx,
1878 struct mlx4_mfunc *mfunc =
1879 container_of(master, struct mlx4_mfunc, master);
1880 struct mlx4_priv *priv =
1881 container_of(mfunc, struct mlx4_priv, mfunc);
1882 struct mlx4_dev *dev = &priv->dev;
1892 bit_vec = master->comm_arm_bit_vector;
1893 for (i = 0; i < COMM_CHANNEL_BIT_ARRAY_SIZE; i++) {
1894 vec = be32_to_cpu(bit_vec[i]);
1895 for (j = 0; j < 32; j++) {
1896 if (!(vec & (1 << j)))
1899 slave = (i * 32) + j;
1900 comm_cmd = swab32(readl(
1901 &mfunc->comm[slave].slave_write));
1902 slt = swab32(readl(&mfunc->comm[slave].slave_read))
1904 toggle = comm_cmd >> 31;
1905 if (toggle != slt) {
1906 if (master->slave_state[slave].comm_toggle
1908 pr_info("slave %d out of sync. read toggle %d, state toggle %d. Resynching.\n",
1910 master->slave_state[slave].comm_toggle);
1911 master->slave_state[slave].comm_toggle =
1914 mlx4_master_do_cmd(dev, slave,
1915 comm_cmd >> 16 & 0xff,
1916 comm_cmd & 0xffff, toggle);
1922 if (reported && reported != served)
1923 mlx4_warn(dev, "Got command event with bitmask from %d slaves but %d were served\n",
1926 if (mlx4_ARM_COMM_CHANNEL(dev))
1927 mlx4_warn(dev, "Failed to arm comm channel events\n");
1930 static int sync_toggles(struct mlx4_dev *dev)
1932 struct mlx4_priv *priv = mlx4_priv(dev);
1937 wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write)) >> 31;
1938 end = jiffies + msecs_to_jiffies(5000);
1940 while (time_before(jiffies, end)) {
1941 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read)) >> 31;
1942 if (rd_toggle == wr_toggle) {
1943 priv->cmd.comm_toggle = rd_toggle;
1951 * we could reach here if for example the previous VM using this
1952 * function misbehaved and left the channel with unsynced state. We
1953 * should fix this here and give this VM a chance to use a properly
1956 mlx4_warn(dev, "recovering from previously mis-behaved VM\n");
1957 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read);
1958 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write);
1959 priv->cmd.comm_toggle = 0;
1964 int mlx4_multi_func_init(struct mlx4_dev *dev)
1966 struct mlx4_priv *priv = mlx4_priv(dev);
1967 struct mlx4_slave_state *s_state;
1968 int i, j, err, port;
1970 if (mlx4_is_master(dev))
1972 ioremap(pci_resource_start(dev->pdev, priv->fw.comm_bar) +
1973 priv->fw.comm_base, MLX4_COMM_PAGESIZE);
1976 ioremap(pci_resource_start(dev->pdev, 2) +
1977 MLX4_SLAVE_COMM_BASE, MLX4_COMM_PAGESIZE);
1978 if (!priv->mfunc.comm) {
1979 mlx4_err(dev, "Couldn't map communication vector\n");
1983 if (mlx4_is_master(dev)) {
1984 priv->mfunc.master.slave_state =
1985 kzalloc(dev->num_slaves *
1986 sizeof(struct mlx4_slave_state), GFP_KERNEL);
1987 if (!priv->mfunc.master.slave_state)
1990 priv->mfunc.master.vf_admin =
1991 kzalloc(dev->num_slaves *
1992 sizeof(struct mlx4_vf_admin_state), GFP_KERNEL);
1993 if (!priv->mfunc.master.vf_admin)
1994 goto err_comm_admin;
1996 priv->mfunc.master.vf_oper =
1997 kzalloc(dev->num_slaves *
1998 sizeof(struct mlx4_vf_oper_state), GFP_KERNEL);
1999 if (!priv->mfunc.master.vf_oper)
2002 for (i = 0; i < dev->num_slaves; ++i) {
2003 s_state = &priv->mfunc.master.slave_state[i];
2004 s_state->last_cmd = MLX4_COMM_CMD_RESET;
2005 for (j = 0; j < MLX4_EVENT_TYPES_NUM; ++j)
2006 s_state->event_eq[j].eqn = -1;
2007 __raw_writel((__force u32) 0,
2008 &priv->mfunc.comm[i].slave_write);
2009 __raw_writel((__force u32) 0,
2010 &priv->mfunc.comm[i].slave_read);
2012 for (port = 1; port <= MLX4_MAX_PORTS; port++) {
2013 s_state->vlan_filter[port] =
2014 kzalloc(sizeof(struct mlx4_vlan_fltr),
2016 if (!s_state->vlan_filter[port]) {
2018 kfree(s_state->vlan_filter[port]);
2021 INIT_LIST_HEAD(&s_state->mcast_filters[port]);
2022 priv->mfunc.master.vf_admin[i].vport[port].default_vlan = MLX4_VGT;
2023 priv->mfunc.master.vf_oper[i].vport[port].state.default_vlan = MLX4_VGT;
2024 priv->mfunc.master.vf_oper[i].vport[port].vlan_idx = NO_INDX;
2025 priv->mfunc.master.vf_oper[i].vport[port].mac_idx = NO_INDX;
2027 spin_lock_init(&s_state->lock);
2030 memset(&priv->mfunc.master.cmd_eqe, 0, dev->caps.eqe_size);
2031 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD;
2032 INIT_WORK(&priv->mfunc.master.comm_work,
2033 mlx4_master_comm_channel);
2034 INIT_WORK(&priv->mfunc.master.slave_event_work,
2035 mlx4_gen_slave_eqe);
2036 INIT_WORK(&priv->mfunc.master.slave_flr_event_work,
2037 mlx4_master_handle_slave_flr);
2038 spin_lock_init(&priv->mfunc.master.slave_state_lock);
2039 spin_lock_init(&priv->mfunc.master.slave_eq.event_lock);
2040 priv->mfunc.master.comm_wq =
2041 create_singlethread_workqueue("mlx4_comm");
2042 if (!priv->mfunc.master.comm_wq)
2045 if (mlx4_init_resource_tracker(dev))
2048 err = mlx4_ARM_COMM_CHANNEL(dev);
2050 mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
2056 err = sync_toggles(dev);
2058 mlx4_err(dev, "Couldn't sync toggles\n");
2065 mlx4_free_resource_tracker(dev, RES_TR_FREE_ALL);
2067 flush_workqueue(priv->mfunc.master.comm_wq);
2068 destroy_workqueue(priv->mfunc.master.comm_wq);
2071 for (port = 1; port <= MLX4_MAX_PORTS; port++)
2072 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2074 kfree(priv->mfunc.master.vf_oper);
2076 kfree(priv->mfunc.master.vf_admin);
2078 kfree(priv->mfunc.master.slave_state);
2080 iounmap(priv->mfunc.comm);
2082 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
2084 priv->mfunc.vhcr_dma);
2085 priv->mfunc.vhcr = NULL;
2089 int mlx4_cmd_init(struct mlx4_dev *dev)
2091 struct mlx4_priv *priv = mlx4_priv(dev);
2093 mutex_init(&priv->cmd.hcr_mutex);
2094 mutex_init(&priv->cmd.slave_cmd_mutex);
2095 sema_init(&priv->cmd.poll_sem, 1);
2096 priv->cmd.use_events = 0;
2097 priv->cmd.toggle = 1;
2099 priv->cmd.hcr = NULL;
2100 priv->mfunc.vhcr = NULL;
2102 if (!mlx4_is_slave(dev)) {
2103 priv->cmd.hcr = ioremap(pci_resource_start(dev->pdev, 0) +
2104 MLX4_HCR_BASE, MLX4_HCR_SIZE);
2105 if (!priv->cmd.hcr) {
2106 mlx4_err(dev, "Couldn't map command register\n");
2111 if (mlx4_is_mfunc(dev)) {
2112 priv->mfunc.vhcr = dma_alloc_coherent(&(dev->pdev->dev), PAGE_SIZE,
2113 &priv->mfunc.vhcr_dma,
2115 if (!priv->mfunc.vhcr)
2119 priv->cmd.pool = pci_pool_create("mlx4_cmd", dev->pdev,
2121 MLX4_MAILBOX_SIZE, 0);
2122 if (!priv->cmd.pool)
2128 if (mlx4_is_mfunc(dev))
2129 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
2130 priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
2131 priv->mfunc.vhcr = NULL;
2134 if (!mlx4_is_slave(dev))
2135 iounmap(priv->cmd.hcr);
2139 void mlx4_multi_func_cleanup(struct mlx4_dev *dev)
2141 struct mlx4_priv *priv = mlx4_priv(dev);
2144 if (mlx4_is_master(dev)) {
2145 flush_workqueue(priv->mfunc.master.comm_wq);
2146 destroy_workqueue(priv->mfunc.master.comm_wq);
2147 for (i = 0; i < dev->num_slaves; i++) {
2148 for (port = 1; port <= MLX4_MAX_PORTS; port++)
2149 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2151 kfree(priv->mfunc.master.slave_state);
2152 kfree(priv->mfunc.master.vf_admin);
2153 kfree(priv->mfunc.master.vf_oper);
2156 iounmap(priv->mfunc.comm);
2159 void mlx4_cmd_cleanup(struct mlx4_dev *dev)
2161 struct mlx4_priv *priv = mlx4_priv(dev);
2163 pci_pool_destroy(priv->cmd.pool);
2165 if (!mlx4_is_slave(dev))
2166 iounmap(priv->cmd.hcr);
2167 if (mlx4_is_mfunc(dev))
2168 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
2169 priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
2170 priv->mfunc.vhcr = NULL;
2174 * Switch to using events to issue FW commands (can only be called
2175 * after event queue for command events has been initialized).
2177 int mlx4_cmd_use_events(struct mlx4_dev *dev)
2179 struct mlx4_priv *priv = mlx4_priv(dev);
2183 priv->cmd.context = kmalloc(priv->cmd.max_cmds *
2184 sizeof (struct mlx4_cmd_context),
2186 if (!priv->cmd.context)
2189 for (i = 0; i < priv->cmd.max_cmds; ++i) {
2190 priv->cmd.context[i].token = i;
2191 priv->cmd.context[i].next = i + 1;
2194 priv->cmd.context[priv->cmd.max_cmds - 1].next = -1;
2195 priv->cmd.free_head = 0;
2197 sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds);
2198 spin_lock_init(&priv->cmd.context_lock);
2200 for (priv->cmd.token_mask = 1;
2201 priv->cmd.token_mask < priv->cmd.max_cmds;
2202 priv->cmd.token_mask <<= 1)
2204 --priv->cmd.token_mask;
2206 down(&priv->cmd.poll_sem);
2207 priv->cmd.use_events = 1;
2213 * Switch back to polling (used when shutting down the device)
2215 void mlx4_cmd_use_polling(struct mlx4_dev *dev)
2217 struct mlx4_priv *priv = mlx4_priv(dev);
2220 priv->cmd.use_events = 0;
2222 for (i = 0; i < priv->cmd.max_cmds; ++i)
2223 down(&priv->cmd.event_sem);
2225 kfree(priv->cmd.context);
2227 up(&priv->cmd.poll_sem);
2230 struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev)
2232 struct mlx4_cmd_mailbox *mailbox;
2234 mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL);
2236 return ERR_PTR(-ENOMEM);
2238 mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL,
2240 if (!mailbox->buf) {
2242 return ERR_PTR(-ENOMEM);
2245 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
2249 EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox);
2251 void mlx4_free_cmd_mailbox(struct mlx4_dev *dev,
2252 struct mlx4_cmd_mailbox *mailbox)
2257 pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma);
2260 EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox);
2262 u32 mlx4_comm_get_version(void)
2264 return ((u32) CMD_CHAN_IF_REV << 8) | (u32) CMD_CHAN_VER;
2267 static int mlx4_get_slave_indx(struct mlx4_dev *dev, int vf)
2269 if ((vf < 0) || (vf >= dev->num_vfs)) {
2270 mlx4_err(dev, "Bad vf number:%d (number of activated vf: %d)\n", vf, dev->num_vfs);
2277 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave)
2279 if (slave < 1 || slave > dev->num_vfs) {
2281 "Bad slave number:%d (number of activated slaves: %lu)\n",
2282 slave, dev->num_slaves);
2288 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave)
2290 struct mlx4_active_ports actv_ports;
2293 bitmap_zero(actv_ports.ports, MLX4_MAX_PORTS);
2296 bitmap_fill(actv_ports.ports, dev->caps.num_ports);
2300 vf = mlx4_get_vf_indx(dev, slave);
2304 bitmap_set(actv_ports.ports, dev->dev_vfs[vf].min_port - 1,
2305 min((int)dev->dev_vfs[mlx4_get_vf_indx(dev, slave)].n_ports,
2306 dev->caps.num_ports));
2310 EXPORT_SYMBOL_GPL(mlx4_get_active_ports);
2312 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port)
2315 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2316 unsigned m = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
2318 if (port <= 0 || port > m)
2321 n = find_first_bit(actv_ports.ports, dev->caps.num_ports);
2327 EXPORT_SYMBOL_GPL(mlx4_slave_convert_port);
2329 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port)
2331 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2332 if (test_bit(port - 1, actv_ports.ports))
2334 find_first_bit(actv_ports.ports, dev->caps.num_ports);
2338 EXPORT_SYMBOL_GPL(mlx4_phys_to_slave_port);
2340 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
2344 struct mlx4_slaves_pport slaves_pport;
2346 bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2348 if (port <= 0 || port > dev->caps.num_ports)
2349 return slaves_pport;
2351 for (i = 0; i < dev->num_vfs + 1; i++) {
2352 struct mlx4_active_ports actv_ports =
2353 mlx4_get_active_ports(dev, i);
2354 if (test_bit(port - 1, actv_ports.ports))
2355 set_bit(i, slaves_pport.slaves);
2358 return slaves_pport;
2360 EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport);
2362 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
2363 struct mlx4_dev *dev,
2364 const struct mlx4_active_ports *crit_ports)
2367 struct mlx4_slaves_pport slaves_pport;
2369 bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2371 for (i = 0; i < dev->num_vfs + 1; i++) {
2372 struct mlx4_active_ports actv_ports =
2373 mlx4_get_active_ports(dev, i);
2374 if (bitmap_equal(crit_ports->ports, actv_ports.ports,
2375 dev->caps.num_ports))
2376 set_bit(i, slaves_pport.slaves);
2379 return slaves_pport;
2381 EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport_actv);
2383 int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u64 mac)
2385 struct mlx4_priv *priv = mlx4_priv(dev);
2386 struct mlx4_vport_state *s_info;
2389 if (!mlx4_is_master(dev))
2390 return -EPROTONOSUPPORT;
2392 slave = mlx4_get_slave_indx(dev, vf);
2396 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2398 mlx4_info(dev, "default mac on vf %d port %d to %llX will take afect only after vf restart\n",
2399 vf, port, s_info->mac);
2402 EXPORT_SYMBOL_GPL(mlx4_set_vf_mac);
2405 int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos)
2407 struct mlx4_priv *priv = mlx4_priv(dev);
2408 struct mlx4_vport_state *vf_admin;
2411 if ((!mlx4_is_master(dev)) ||
2412 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VLAN_CONTROL))
2413 return -EPROTONOSUPPORT;
2415 if ((vlan > 4095) || (qos > 7))
2418 slave = mlx4_get_slave_indx(dev, vf);
2422 vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
2424 if ((0 == vlan) && (0 == qos))
2425 vf_admin->default_vlan = MLX4_VGT;
2427 vf_admin->default_vlan = vlan;
2428 vf_admin->default_qos = qos;
2430 if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
2432 "updating vf %d port %d config will take effect on next VF restart\n",
2436 EXPORT_SYMBOL_GPL(mlx4_set_vf_vlan);
2438 /* mlx4_get_slave_default_vlan -
2439 * return true if VST ( default vlan)
2440 * if VST, will return vlan & qos (if not NULL)
2442 bool mlx4_get_slave_default_vlan(struct mlx4_dev *dev, int port, int slave,
2445 struct mlx4_vport_oper_state *vp_oper;
2446 struct mlx4_priv *priv;
2448 priv = mlx4_priv(dev);
2449 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
2451 if (MLX4_VGT != vp_oper->state.default_vlan) {
2453 *vlan = vp_oper->state.default_vlan;
2455 *qos = vp_oper->state.default_qos;
2460 EXPORT_SYMBOL_GPL(mlx4_get_slave_default_vlan);
2462 int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting)
2464 struct mlx4_priv *priv = mlx4_priv(dev);
2465 struct mlx4_vport_state *s_info;
2468 if ((!mlx4_is_master(dev)) ||
2469 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FSM))
2470 return -EPROTONOSUPPORT;
2472 slave = mlx4_get_slave_indx(dev, vf);
2476 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2477 s_info->spoofchk = setting;
2481 EXPORT_SYMBOL_GPL(mlx4_set_vf_spoofchk);
2483 int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf)
2485 struct mlx4_priv *priv = mlx4_priv(dev);
2486 struct mlx4_vport_state *s_info;
2489 if (!mlx4_is_master(dev))
2490 return -EPROTONOSUPPORT;
2492 slave = mlx4_get_slave_indx(dev, vf);
2496 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2499 /* need to convert it to a func */
2500 ivf->mac[0] = ((s_info->mac >> (5*8)) & 0xff);
2501 ivf->mac[1] = ((s_info->mac >> (4*8)) & 0xff);
2502 ivf->mac[2] = ((s_info->mac >> (3*8)) & 0xff);
2503 ivf->mac[3] = ((s_info->mac >> (2*8)) & 0xff);
2504 ivf->mac[4] = ((s_info->mac >> (1*8)) & 0xff);
2505 ivf->mac[5] = ((s_info->mac) & 0xff);
2507 ivf->vlan = s_info->default_vlan;
2508 ivf->qos = s_info->default_qos;
2509 ivf->max_tx_rate = s_info->tx_rate;
2510 ivf->min_tx_rate = 0;
2511 ivf->spoofchk = s_info->spoofchk;
2512 ivf->linkstate = s_info->link_state;
2516 EXPORT_SYMBOL_GPL(mlx4_get_vf_config);
2518 int mlx4_set_vf_link_state(struct mlx4_dev *dev, int port, int vf, int link_state)
2520 struct mlx4_priv *priv = mlx4_priv(dev);
2521 struct mlx4_vport_state *s_info;
2525 slave = mlx4_get_slave_indx(dev, vf);
2529 switch (link_state) {
2530 case IFLA_VF_LINK_STATE_AUTO:
2531 /* get current link state */
2532 if (!priv->sense.do_sense_port[port])
2533 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
2535 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
2538 case IFLA_VF_LINK_STATE_ENABLE:
2539 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
2542 case IFLA_VF_LINK_STATE_DISABLE:
2543 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
2547 mlx4_warn(dev, "unknown value for link_state %02x on slave %d port %d\n",
2548 link_state, slave, port);
2551 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2552 s_info->link_state = link_state;
2555 mlx4_gen_port_state_change_eqe(dev, slave, port, link_stat_event);
2557 if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
2559 "updating vf %d port %d no link state HW enforcment\n",
2563 EXPORT_SYMBOL_GPL(mlx4_set_vf_link_state);
2565 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port)
2567 struct mlx4_priv *priv = mlx4_priv(dev);
2569 if (slave < 1 || slave >= dev->num_slaves ||
2570 port < 1 || port > MLX4_MAX_PORTS)
2573 return priv->mfunc.master.vf_oper[slave].smi_enabled[port] ==
2574 MLX4_VF_SMI_ENABLED;
2576 EXPORT_SYMBOL_GPL(mlx4_vf_smi_enabled);
2578 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port)
2580 struct mlx4_priv *priv = mlx4_priv(dev);
2582 if (slave == mlx4_master_func_num(dev))
2585 if (slave < 1 || slave >= dev->num_slaves ||
2586 port < 1 || port > MLX4_MAX_PORTS)
2589 return priv->mfunc.master.vf_admin[slave].enable_smi[port] ==
2590 MLX4_VF_SMI_ENABLED;
2592 EXPORT_SYMBOL_GPL(mlx4_vf_get_enable_smi_admin);
2594 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
2597 struct mlx4_priv *priv = mlx4_priv(dev);
2599 if (slave == mlx4_master_func_num(dev))
2602 if (slave < 1 || slave >= dev->num_slaves ||
2603 port < 1 || port > MLX4_MAX_PORTS ||
2604 enabled < 0 || enabled > 1)
2607 priv->mfunc.master.vf_admin[slave].enable_smi[port] = enabled;
2610 EXPORT_SYMBOL_GPL(mlx4_vf_set_enable_smi_admin);