2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <linux/export.h>
38 #include <linux/pci.h>
39 #include <linux/errno.h>
41 #include <linux/mlx4/cmd.h>
42 #include <linux/mlx4/device.h>
43 #include <linux/semaphore.h>
44 #include <rdma/ib_smi.h>
51 #define CMD_POLL_TOKEN 0xffff
52 #define INBOX_MASK 0xffffffffffffff00ULL
54 #define CMD_CHAN_VER 1
55 #define CMD_CHAN_IF_REV 1
58 /* command completed successfully: */
60 /* Internal error (such as a bus error) occurred while processing command: */
61 CMD_STAT_INTERNAL_ERR = 0x01,
62 /* Operation/command not supported or opcode modifier not supported: */
63 CMD_STAT_BAD_OP = 0x02,
64 /* Parameter not supported or parameter out of range: */
65 CMD_STAT_BAD_PARAM = 0x03,
66 /* System not enabled or bad system state: */
67 CMD_STAT_BAD_SYS_STATE = 0x04,
68 /* Attempt to access reserved or unallocaterd resource: */
69 CMD_STAT_BAD_RESOURCE = 0x05,
70 /* Requested resource is currently executing a command, or is otherwise busy: */
71 CMD_STAT_RESOURCE_BUSY = 0x06,
72 /* Required capability exceeds device limits: */
73 CMD_STAT_EXCEED_LIM = 0x08,
74 /* Resource is not in the appropriate state or ownership: */
75 CMD_STAT_BAD_RES_STATE = 0x09,
76 /* Index out of range: */
77 CMD_STAT_BAD_INDEX = 0x0a,
78 /* FW image corrupted: */
79 CMD_STAT_BAD_NVMEM = 0x0b,
80 /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
81 CMD_STAT_ICM_ERROR = 0x0c,
82 /* Attempt to modify a QP/EE which is not in the presumed state: */
83 CMD_STAT_BAD_QP_STATE = 0x10,
84 /* Bad segment parameters (Address/Size): */
85 CMD_STAT_BAD_SEG_PARAM = 0x20,
86 /* Memory Region has Memory Windows bound to: */
87 CMD_STAT_REG_BOUND = 0x21,
88 /* HCA local attached memory not present: */
89 CMD_STAT_LAM_NOT_PRE = 0x22,
90 /* Bad management packet (silently discarded): */
91 CMD_STAT_BAD_PKT = 0x30,
92 /* More outstanding CQEs in CQ than new CQ size: */
93 CMD_STAT_BAD_SIZE = 0x40,
94 /* Multi Function device support required: */
95 CMD_STAT_MULTI_FUNC_REQ = 0x50,
99 HCR_IN_PARAM_OFFSET = 0x00,
100 HCR_IN_MODIFIER_OFFSET = 0x08,
101 HCR_OUT_PARAM_OFFSET = 0x0c,
102 HCR_TOKEN_OFFSET = 0x14,
103 HCR_STATUS_OFFSET = 0x18,
105 HCR_OPMOD_SHIFT = 12,
112 GO_BIT_TIMEOUT_MSECS = 10000
115 enum mlx4_vlan_transition {
116 MLX4_VLAN_TRANSITION_VST_VST = 0,
117 MLX4_VLAN_TRANSITION_VST_VGT = 1,
118 MLX4_VLAN_TRANSITION_VGT_VST = 2,
119 MLX4_VLAN_TRANSITION_VGT_VGT = 3,
123 struct mlx4_cmd_context {
124 struct completion done;
132 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
133 struct mlx4_vhcr_cmd *in_vhcr);
135 static int mlx4_status_to_errno(u8 status)
137 static const int trans_table[] = {
138 [CMD_STAT_INTERNAL_ERR] = -EIO,
139 [CMD_STAT_BAD_OP] = -EPERM,
140 [CMD_STAT_BAD_PARAM] = -EINVAL,
141 [CMD_STAT_BAD_SYS_STATE] = -ENXIO,
142 [CMD_STAT_BAD_RESOURCE] = -EBADF,
143 [CMD_STAT_RESOURCE_BUSY] = -EBUSY,
144 [CMD_STAT_EXCEED_LIM] = -ENOMEM,
145 [CMD_STAT_BAD_RES_STATE] = -EBADF,
146 [CMD_STAT_BAD_INDEX] = -EBADF,
147 [CMD_STAT_BAD_NVMEM] = -EFAULT,
148 [CMD_STAT_ICM_ERROR] = -ENFILE,
149 [CMD_STAT_BAD_QP_STATE] = -EINVAL,
150 [CMD_STAT_BAD_SEG_PARAM] = -EFAULT,
151 [CMD_STAT_REG_BOUND] = -EBUSY,
152 [CMD_STAT_LAM_NOT_PRE] = -EAGAIN,
153 [CMD_STAT_BAD_PKT] = -EINVAL,
154 [CMD_STAT_BAD_SIZE] = -ENOMEM,
155 [CMD_STAT_MULTI_FUNC_REQ] = -EACCES,
158 if (status >= ARRAY_SIZE(trans_table) ||
159 (status != CMD_STAT_OK && trans_table[status] == 0))
162 return trans_table[status];
165 static u8 mlx4_errno_to_status(int errno)
169 return CMD_STAT_BAD_OP;
171 return CMD_STAT_BAD_PARAM;
173 return CMD_STAT_BAD_SYS_STATE;
175 return CMD_STAT_RESOURCE_BUSY;
177 return CMD_STAT_EXCEED_LIM;
179 return CMD_STAT_ICM_ERROR;
181 return CMD_STAT_INTERNAL_ERR;
185 static int comm_pending(struct mlx4_dev *dev)
187 struct mlx4_priv *priv = mlx4_priv(dev);
188 u32 status = readl(&priv->mfunc.comm->slave_read);
190 return (swab32(status) >> 31) != priv->cmd.comm_toggle;
193 static void mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param)
195 struct mlx4_priv *priv = mlx4_priv(dev);
198 priv->cmd.comm_toggle ^= 1;
199 val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31);
200 __raw_writel((__force u32) cpu_to_be32(val),
201 &priv->mfunc.comm->slave_write);
205 static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
206 unsigned long timeout)
208 struct mlx4_priv *priv = mlx4_priv(dev);
211 int ret_from_pending = 0;
213 /* First, verify that the master reports correct status */
214 if (comm_pending(dev)) {
215 mlx4_warn(dev, "Communication channel is not idle."
216 "my toggle is %d (cmd:0x%x)\n",
217 priv->cmd.comm_toggle, cmd);
222 down(&priv->cmd.poll_sem);
223 mlx4_comm_cmd_post(dev, cmd, param);
225 end = msecs_to_jiffies(timeout) + jiffies;
226 while (comm_pending(dev) && time_before(jiffies, end))
228 ret_from_pending = comm_pending(dev);
229 if (ret_from_pending) {
230 /* check if the slave is trying to boot in the middle of
231 * FLR process. The only non-zero result in the RESET command
232 * is MLX4_DELAY_RESET_SLAVE*/
233 if ((MLX4_COMM_CMD_RESET == cmd)) {
234 err = MLX4_DELAY_RESET_SLAVE;
236 mlx4_warn(dev, "Communication channel timed out\n");
241 up(&priv->cmd.poll_sem);
245 static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 op,
246 u16 param, unsigned long timeout)
248 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
249 struct mlx4_cmd_context *context;
253 down(&cmd->event_sem);
255 spin_lock(&cmd->context_lock);
256 BUG_ON(cmd->free_head < 0);
257 context = &cmd->context[cmd->free_head];
258 context->token += cmd->token_mask + 1;
259 cmd->free_head = context->next;
260 spin_unlock(&cmd->context_lock);
262 init_completion(&context->done);
264 mlx4_comm_cmd_post(dev, op, param);
266 if (!wait_for_completion_timeout(&context->done,
267 msecs_to_jiffies(timeout))) {
268 mlx4_warn(dev, "communication channel command 0x%x timed out\n",
274 err = context->result;
275 if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) {
276 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
277 op, context->fw_status);
282 /* wait for comm channel ready
283 * this is necessary for prevention the race
284 * when switching between event to polling mode
286 end = msecs_to_jiffies(timeout) + jiffies;
287 while (comm_pending(dev) && time_before(jiffies, end))
290 spin_lock(&cmd->context_lock);
291 context->next = cmd->free_head;
292 cmd->free_head = context - cmd->context;
293 spin_unlock(&cmd->context_lock);
299 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
300 unsigned long timeout)
302 if (mlx4_priv(dev)->cmd.use_events)
303 return mlx4_comm_cmd_wait(dev, cmd, param, timeout);
304 return mlx4_comm_cmd_poll(dev, cmd, param, timeout);
307 static int cmd_pending(struct mlx4_dev *dev)
311 if (pci_channel_offline(dev->pdev))
314 status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
316 return (status & swab32(1 << HCR_GO_BIT)) ||
317 (mlx4_priv(dev)->cmd.toggle ==
318 !!(status & swab32(1 << HCR_T_BIT)));
321 static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
322 u32 in_modifier, u8 op_modifier, u16 op, u16 token,
325 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
326 u32 __iomem *hcr = cmd->hcr;
330 mutex_lock(&cmd->hcr_mutex);
332 if (pci_channel_offline(dev->pdev)) {
334 * Device is going through error recovery
335 * and cannot accept commands.
343 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
345 while (cmd_pending(dev)) {
346 if (pci_channel_offline(dev->pdev)) {
348 * Device is going through error recovery
349 * and cannot accept commands.
355 if (time_after_eq(jiffies, end)) {
356 mlx4_err(dev, "%s:cmd_pending failed\n", __func__);
363 * We use writel (instead of something like memcpy_toio)
364 * because writes of less than 32 bits to the HCR don't work
365 * (and some architectures such as ia64 implement memcpy_toio
366 * in terms of writeb).
368 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), hcr + 0);
369 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), hcr + 1);
370 __raw_writel((__force u32) cpu_to_be32(in_modifier), hcr + 2);
371 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), hcr + 3);
372 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
373 __raw_writel((__force u32) cpu_to_be32(token << 16), hcr + 5);
375 /* __raw_writel may not order writes. */
378 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
379 (cmd->toggle << HCR_T_BIT) |
380 (event ? (1 << HCR_E_BIT) : 0) |
381 (op_modifier << HCR_OPMOD_SHIFT) |
385 * Make sure that our HCR writes don't get mixed in with
386 * writes from another CPU starting a FW command.
390 cmd->toggle = cmd->toggle ^ 1;
395 mutex_unlock(&cmd->hcr_mutex);
399 static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
400 int out_is_imm, u32 in_modifier, u8 op_modifier,
401 u16 op, unsigned long timeout)
403 struct mlx4_priv *priv = mlx4_priv(dev);
404 struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr;
407 mutex_lock(&priv->cmd.slave_cmd_mutex);
409 vhcr->in_param = cpu_to_be64(in_param);
410 vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0;
411 vhcr->in_modifier = cpu_to_be32(in_modifier);
412 vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff));
413 vhcr->token = cpu_to_be16(CMD_POLL_TOKEN);
415 vhcr->flags = !!(priv->cmd.use_events) << 6;
417 if (mlx4_is_master(dev)) {
418 ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr);
423 be64_to_cpu(vhcr->out_param);
425 mlx4_err(dev, "response expected while"
426 "output mailbox is NULL for "
427 "command 0x%x\n", op);
428 vhcr->status = CMD_STAT_BAD_PARAM;
431 ret = mlx4_status_to_errno(vhcr->status);
434 ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0,
435 MLX4_COMM_TIME + timeout);
440 be64_to_cpu(vhcr->out_param);
442 mlx4_err(dev, "response expected while"
443 "output mailbox is NULL for "
444 "command 0x%x\n", op);
445 vhcr->status = CMD_STAT_BAD_PARAM;
448 ret = mlx4_status_to_errno(vhcr->status);
450 mlx4_err(dev, "failed execution of VHCR_POST command"
451 "opcode 0x%x\n", op);
454 mutex_unlock(&priv->cmd.slave_cmd_mutex);
458 static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
459 int out_is_imm, u32 in_modifier, u8 op_modifier,
460 u16 op, unsigned long timeout)
462 struct mlx4_priv *priv = mlx4_priv(dev);
463 void __iomem *hcr = priv->cmd.hcr;
468 down(&priv->cmd.poll_sem);
470 if (pci_channel_offline(dev->pdev)) {
472 * Device is going through error recovery
473 * and cannot accept commands.
479 err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
480 in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
484 end = msecs_to_jiffies(timeout) + jiffies;
485 while (cmd_pending(dev) && time_before(jiffies, end)) {
486 if (pci_channel_offline(dev->pdev)) {
488 * Device is going through error recovery
489 * and cannot accept commands.
498 if (cmd_pending(dev)) {
499 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
507 (u64) be32_to_cpu((__force __be32)
508 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
509 (u64) be32_to_cpu((__force __be32)
510 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
511 stat = be32_to_cpu((__force __be32)
512 __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24;
513 err = mlx4_status_to_errno(stat);
515 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
519 up(&priv->cmd.poll_sem);
523 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
525 struct mlx4_priv *priv = mlx4_priv(dev);
526 struct mlx4_cmd_context *context =
527 &priv->cmd.context[token & priv->cmd.token_mask];
529 /* previously timed out command completing at long last */
530 if (token != context->token)
533 context->fw_status = status;
534 context->result = mlx4_status_to_errno(status);
535 context->out_param = out_param;
537 complete(&context->done);
540 static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
541 int out_is_imm, u32 in_modifier, u8 op_modifier,
542 u16 op, unsigned long timeout)
544 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
545 struct mlx4_cmd_context *context;
548 down(&cmd->event_sem);
550 spin_lock(&cmd->context_lock);
551 BUG_ON(cmd->free_head < 0);
552 context = &cmd->context[cmd->free_head];
553 context->token += cmd->token_mask + 1;
554 cmd->free_head = context->next;
555 spin_unlock(&cmd->context_lock);
557 init_completion(&context->done);
559 mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
560 in_modifier, op_modifier, op, context->token, 1);
562 if (!wait_for_completion_timeout(&context->done,
563 msecs_to_jiffies(timeout))) {
564 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
570 err = context->result;
572 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
573 op, context->fw_status);
578 *out_param = context->out_param;
581 spin_lock(&cmd->context_lock);
582 context->next = cmd->free_head;
583 cmd->free_head = context - cmd->context;
584 spin_unlock(&cmd->context_lock);
590 int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
591 int out_is_imm, u32 in_modifier, u8 op_modifier,
592 u16 op, unsigned long timeout, int native)
594 if (pci_channel_offline(dev->pdev))
597 if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) {
598 if (mlx4_priv(dev)->cmd.use_events)
599 return mlx4_cmd_wait(dev, in_param, out_param,
600 out_is_imm, in_modifier,
601 op_modifier, op, timeout);
603 return mlx4_cmd_poll(dev, in_param, out_param,
604 out_is_imm, in_modifier,
605 op_modifier, op, timeout);
607 return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm,
608 in_modifier, op_modifier, op, timeout);
610 EXPORT_SYMBOL_GPL(__mlx4_cmd);
613 static int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev)
615 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL,
616 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
619 static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr,
620 int slave, u64 slave_addr,
621 int size, int is_read)
626 if ((slave_addr & 0xfff) | (master_addr & 0xfff) |
627 (slave & ~0x7f) | (size & 0xff)) {
628 mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx "
629 "master_addr:0x%llx slave_id:%d size:%d\n",
630 slave_addr, master_addr, slave, size);
635 in_param = (u64) slave | slave_addr;
636 out_param = (u64) dev->caps.function | master_addr;
638 in_param = (u64) dev->caps.function | master_addr;
639 out_param = (u64) slave | slave_addr;
642 return mlx4_cmd_imm(dev, in_param, &out_param, size, 0,
644 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
647 static int query_pkey_block(struct mlx4_dev *dev, u8 port, u16 index, u16 *pkey,
648 struct mlx4_cmd_mailbox *inbox,
649 struct mlx4_cmd_mailbox *outbox)
651 struct ib_smp *in_mad = (struct ib_smp *)(inbox->buf);
652 struct ib_smp *out_mad = (struct ib_smp *)(outbox->buf);
659 in_mad->attr_mod = cpu_to_be32(index / 32);
661 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3,
662 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
667 for (i = 0; i < 32; ++i)
668 pkey[i] = be16_to_cpu(((__be16 *) out_mad->data)[i]);
673 static int get_full_pkey_table(struct mlx4_dev *dev, u8 port, u16 *table,
674 struct mlx4_cmd_mailbox *inbox,
675 struct mlx4_cmd_mailbox *outbox)
680 for (i = 0; i < dev->caps.pkey_table_len[port]; i += 32) {
681 err = query_pkey_block(dev, port, i, table + i, inbox, outbox);
688 #define PORT_CAPABILITY_LOCATION_IN_SMP 20
689 #define PORT_STATE_OFFSET 32
691 static enum ib_port_state vf_port_state(struct mlx4_dev *dev, int port, int vf)
693 if (mlx4_get_slave_port_state(dev, vf, port) == SLAVE_PORT_UP)
694 return IB_PORT_ACTIVE;
699 static int mlx4_MAD_IFC_wrapper(struct mlx4_dev *dev, int slave,
700 struct mlx4_vhcr *vhcr,
701 struct mlx4_cmd_mailbox *inbox,
702 struct mlx4_cmd_mailbox *outbox,
703 struct mlx4_cmd_info *cmd)
705 struct ib_smp *smp = inbox->buf;
711 struct mlx4_priv *priv = mlx4_priv(dev);
712 struct ib_smp *outsmp = outbox->buf;
713 __be16 *outtab = (__be16 *)(outsmp->data);
714 __be32 slave_cap_mask;
715 __be64 slave_node_guid;
716 port = vhcr->in_modifier;
718 if (smp->base_version == 1 &&
719 smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
720 smp->class_version == 1) {
721 if (smp->method == IB_MGMT_METHOD_GET) {
722 if (smp->attr_id == IB_SMP_ATTR_PKEY_TABLE) {
723 index = be32_to_cpu(smp->attr_mod);
724 if (port < 1 || port > dev->caps.num_ports)
726 table = kcalloc(dev->caps.pkey_table_len[port], sizeof *table, GFP_KERNEL);
729 /* need to get the full pkey table because the paravirtualized
730 * pkeys may be scattered among several pkey blocks.
732 err = get_full_pkey_table(dev, port, table, inbox, outbox);
734 for (vidx = index * 32; vidx < (index + 1) * 32; ++vidx) {
735 pidx = priv->virt2phys_pkey[slave][port - 1][vidx];
736 outtab[vidx % 32] = cpu_to_be16(table[pidx]);
742 if (smp->attr_id == IB_SMP_ATTR_PORT_INFO) {
743 /*get the slave specific caps:*/
745 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
746 vhcr->in_modifier, vhcr->op_modifier,
747 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
748 /* modify the response for slaves */
749 if (!err && slave != mlx4_master_func_num(dev)) {
750 u8 *state = outsmp->data + PORT_STATE_OFFSET;
752 *state = (*state & 0xf0) | vf_port_state(dev, port, slave);
753 slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
754 memcpy(outsmp->data + PORT_CAPABILITY_LOCATION_IN_SMP, &slave_cap_mask, 4);
758 if (smp->attr_id == IB_SMP_ATTR_GUID_INFO) {
759 /* compute slave's gid block */
760 smp->attr_mod = cpu_to_be32(slave / 8);
762 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
763 vhcr->in_modifier, vhcr->op_modifier,
764 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
766 /* if needed, move slave gid to index 0 */
769 outsmp->data + (slave % 8) * 8, 8);
770 /* delete all other gids */
771 memset(outsmp->data + 8, 0, 56);
775 if (smp->attr_id == IB_SMP_ATTR_NODE_INFO) {
776 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
777 vhcr->in_modifier, vhcr->op_modifier,
778 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
780 slave_node_guid = mlx4_get_slave_node_guid(dev, slave);
781 memcpy(outsmp->data + 12, &slave_node_guid, 8);
787 if (slave != mlx4_master_func_num(dev) &&
788 ((smp->mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) ||
789 (smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
790 smp->method == IB_MGMT_METHOD_SET))) {
791 mlx4_err(dev, "slave %d is trying to execute a Subnet MGMT MAD, "
792 "class 0x%x, method 0x%x for attr 0x%x. Rejecting\n",
793 slave, smp->method, smp->mgmt_class,
794 be16_to_cpu(smp->attr_id));
798 return mlx4_cmd_box(dev, inbox->dma, outbox->dma,
799 vhcr->in_modifier, vhcr->op_modifier,
800 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
803 static int mlx4_CMD_EPERM_wrapper(struct mlx4_dev *dev, int slave,
804 struct mlx4_vhcr *vhcr,
805 struct mlx4_cmd_mailbox *inbox,
806 struct mlx4_cmd_mailbox *outbox,
807 struct mlx4_cmd_info *cmd)
812 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
813 struct mlx4_vhcr *vhcr,
814 struct mlx4_cmd_mailbox *inbox,
815 struct mlx4_cmd_mailbox *outbox,
816 struct mlx4_cmd_info *cmd)
822 in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param;
823 out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param;
824 if (cmd->encode_slave_id) {
825 in_param &= 0xffffffffffffff00ll;
829 err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm,
830 vhcr->in_modifier, vhcr->op_modifier, vhcr->op,
831 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
834 vhcr->out_param = out_param;
839 static struct mlx4_cmd_info cmd_info[] = {
841 .opcode = MLX4_CMD_QUERY_FW,
845 .encode_slave_id = false,
847 .wrapper = mlx4_QUERY_FW_wrapper
850 .opcode = MLX4_CMD_QUERY_HCA,
854 .encode_slave_id = false,
859 .opcode = MLX4_CMD_QUERY_DEV_CAP,
863 .encode_slave_id = false,
865 .wrapper = mlx4_QUERY_DEV_CAP_wrapper
868 .opcode = MLX4_CMD_QUERY_FUNC_CAP,
872 .encode_slave_id = false,
874 .wrapper = mlx4_QUERY_FUNC_CAP_wrapper
877 .opcode = MLX4_CMD_QUERY_ADAPTER,
881 .encode_slave_id = false,
886 .opcode = MLX4_CMD_INIT_PORT,
890 .encode_slave_id = false,
892 .wrapper = mlx4_INIT_PORT_wrapper
895 .opcode = MLX4_CMD_CLOSE_PORT,
899 .encode_slave_id = false,
901 .wrapper = mlx4_CLOSE_PORT_wrapper
904 .opcode = MLX4_CMD_QUERY_PORT,
908 .encode_slave_id = false,
910 .wrapper = mlx4_QUERY_PORT_wrapper
913 .opcode = MLX4_CMD_SET_PORT,
917 .encode_slave_id = false,
919 .wrapper = mlx4_SET_PORT_wrapper
922 .opcode = MLX4_CMD_MAP_EQ,
926 .encode_slave_id = false,
928 .wrapper = mlx4_MAP_EQ_wrapper
931 .opcode = MLX4_CMD_SW2HW_EQ,
935 .encode_slave_id = true,
937 .wrapper = mlx4_SW2HW_EQ_wrapper
940 .opcode = MLX4_CMD_HW_HEALTH_CHECK,
944 .encode_slave_id = false,
949 .opcode = MLX4_CMD_NOP,
953 .encode_slave_id = false,
958 .opcode = MLX4_CMD_CONFIG_DEV,
962 .encode_slave_id = false,
964 .wrapper = mlx4_CMD_EPERM_wrapper
967 .opcode = MLX4_CMD_ALLOC_RES,
971 .encode_slave_id = false,
973 .wrapper = mlx4_ALLOC_RES_wrapper
976 .opcode = MLX4_CMD_FREE_RES,
980 .encode_slave_id = false,
982 .wrapper = mlx4_FREE_RES_wrapper
985 .opcode = MLX4_CMD_SW2HW_MPT,
989 .encode_slave_id = true,
991 .wrapper = mlx4_SW2HW_MPT_wrapper
994 .opcode = MLX4_CMD_QUERY_MPT,
998 .encode_slave_id = false,
1000 .wrapper = mlx4_QUERY_MPT_wrapper
1003 .opcode = MLX4_CMD_HW2SW_MPT,
1005 .has_outbox = false,
1006 .out_is_imm = false,
1007 .encode_slave_id = false,
1009 .wrapper = mlx4_HW2SW_MPT_wrapper
1012 .opcode = MLX4_CMD_READ_MTT,
1015 .out_is_imm = false,
1016 .encode_slave_id = false,
1021 .opcode = MLX4_CMD_WRITE_MTT,
1023 .has_outbox = false,
1024 .out_is_imm = false,
1025 .encode_slave_id = false,
1027 .wrapper = mlx4_WRITE_MTT_wrapper
1030 .opcode = MLX4_CMD_SYNC_TPT,
1032 .has_outbox = false,
1033 .out_is_imm = false,
1034 .encode_slave_id = false,
1039 .opcode = MLX4_CMD_HW2SW_EQ,
1042 .out_is_imm = false,
1043 .encode_slave_id = true,
1045 .wrapper = mlx4_HW2SW_EQ_wrapper
1048 .opcode = MLX4_CMD_QUERY_EQ,
1051 .out_is_imm = false,
1052 .encode_slave_id = true,
1054 .wrapper = mlx4_QUERY_EQ_wrapper
1057 .opcode = MLX4_CMD_SW2HW_CQ,
1059 .has_outbox = false,
1060 .out_is_imm = false,
1061 .encode_slave_id = true,
1063 .wrapper = mlx4_SW2HW_CQ_wrapper
1066 .opcode = MLX4_CMD_HW2SW_CQ,
1068 .has_outbox = false,
1069 .out_is_imm = false,
1070 .encode_slave_id = false,
1072 .wrapper = mlx4_HW2SW_CQ_wrapper
1075 .opcode = MLX4_CMD_QUERY_CQ,
1078 .out_is_imm = false,
1079 .encode_slave_id = false,
1081 .wrapper = mlx4_QUERY_CQ_wrapper
1084 .opcode = MLX4_CMD_MODIFY_CQ,
1086 .has_outbox = false,
1088 .encode_slave_id = false,
1090 .wrapper = mlx4_MODIFY_CQ_wrapper
1093 .opcode = MLX4_CMD_SW2HW_SRQ,
1095 .has_outbox = false,
1096 .out_is_imm = false,
1097 .encode_slave_id = true,
1099 .wrapper = mlx4_SW2HW_SRQ_wrapper
1102 .opcode = MLX4_CMD_HW2SW_SRQ,
1104 .has_outbox = false,
1105 .out_is_imm = false,
1106 .encode_slave_id = false,
1108 .wrapper = mlx4_HW2SW_SRQ_wrapper
1111 .opcode = MLX4_CMD_QUERY_SRQ,
1114 .out_is_imm = false,
1115 .encode_slave_id = false,
1117 .wrapper = mlx4_QUERY_SRQ_wrapper
1120 .opcode = MLX4_CMD_ARM_SRQ,
1122 .has_outbox = false,
1123 .out_is_imm = false,
1124 .encode_slave_id = false,
1126 .wrapper = mlx4_ARM_SRQ_wrapper
1129 .opcode = MLX4_CMD_RST2INIT_QP,
1131 .has_outbox = false,
1132 .out_is_imm = false,
1133 .encode_slave_id = true,
1135 .wrapper = mlx4_RST2INIT_QP_wrapper
1138 .opcode = MLX4_CMD_INIT2INIT_QP,
1140 .has_outbox = false,
1141 .out_is_imm = false,
1142 .encode_slave_id = false,
1144 .wrapper = mlx4_INIT2INIT_QP_wrapper
1147 .opcode = MLX4_CMD_INIT2RTR_QP,
1149 .has_outbox = false,
1150 .out_is_imm = false,
1151 .encode_slave_id = false,
1153 .wrapper = mlx4_INIT2RTR_QP_wrapper
1156 .opcode = MLX4_CMD_RTR2RTS_QP,
1158 .has_outbox = false,
1159 .out_is_imm = false,
1160 .encode_slave_id = false,
1162 .wrapper = mlx4_RTR2RTS_QP_wrapper
1165 .opcode = MLX4_CMD_RTS2RTS_QP,
1167 .has_outbox = false,
1168 .out_is_imm = false,
1169 .encode_slave_id = false,
1171 .wrapper = mlx4_RTS2RTS_QP_wrapper
1174 .opcode = MLX4_CMD_SQERR2RTS_QP,
1176 .has_outbox = false,
1177 .out_is_imm = false,
1178 .encode_slave_id = false,
1180 .wrapper = mlx4_SQERR2RTS_QP_wrapper
1183 .opcode = MLX4_CMD_2ERR_QP,
1185 .has_outbox = false,
1186 .out_is_imm = false,
1187 .encode_slave_id = false,
1189 .wrapper = mlx4_GEN_QP_wrapper
1192 .opcode = MLX4_CMD_RTS2SQD_QP,
1194 .has_outbox = false,
1195 .out_is_imm = false,
1196 .encode_slave_id = false,
1198 .wrapper = mlx4_GEN_QP_wrapper
1201 .opcode = MLX4_CMD_SQD2SQD_QP,
1203 .has_outbox = false,
1204 .out_is_imm = false,
1205 .encode_slave_id = false,
1207 .wrapper = mlx4_SQD2SQD_QP_wrapper
1210 .opcode = MLX4_CMD_SQD2RTS_QP,
1212 .has_outbox = false,
1213 .out_is_imm = false,
1214 .encode_slave_id = false,
1216 .wrapper = mlx4_SQD2RTS_QP_wrapper
1219 .opcode = MLX4_CMD_2RST_QP,
1221 .has_outbox = false,
1222 .out_is_imm = false,
1223 .encode_slave_id = false,
1225 .wrapper = mlx4_2RST_QP_wrapper
1228 .opcode = MLX4_CMD_QUERY_QP,
1231 .out_is_imm = false,
1232 .encode_slave_id = false,
1234 .wrapper = mlx4_GEN_QP_wrapper
1237 .opcode = MLX4_CMD_SUSPEND_QP,
1239 .has_outbox = false,
1240 .out_is_imm = false,
1241 .encode_slave_id = false,
1243 .wrapper = mlx4_GEN_QP_wrapper
1246 .opcode = MLX4_CMD_UNSUSPEND_QP,
1248 .has_outbox = false,
1249 .out_is_imm = false,
1250 .encode_slave_id = false,
1252 .wrapper = mlx4_GEN_QP_wrapper
1255 .opcode = MLX4_CMD_UPDATE_QP,
1257 .has_outbox = false,
1258 .out_is_imm = false,
1259 .encode_slave_id = false,
1261 .wrapper = mlx4_CMD_EPERM_wrapper
1264 .opcode = MLX4_CMD_GET_OP_REQ,
1266 .has_outbox = false,
1267 .out_is_imm = false,
1268 .encode_slave_id = false,
1270 .wrapper = mlx4_CMD_EPERM_wrapper,
1273 .opcode = MLX4_CMD_CONF_SPECIAL_QP,
1275 .has_outbox = false,
1276 .out_is_imm = false,
1277 .encode_slave_id = false,
1278 .verify = NULL, /* XXX verify: only demux can do this */
1282 .opcode = MLX4_CMD_MAD_IFC,
1285 .out_is_imm = false,
1286 .encode_slave_id = false,
1288 .wrapper = mlx4_MAD_IFC_wrapper
1291 .opcode = MLX4_CMD_QUERY_IF_STAT,
1294 .out_is_imm = false,
1295 .encode_slave_id = false,
1297 .wrapper = mlx4_QUERY_IF_STAT_wrapper
1299 /* Native multicast commands are not available for guests */
1301 .opcode = MLX4_CMD_QP_ATTACH,
1303 .has_outbox = false,
1304 .out_is_imm = false,
1305 .encode_slave_id = false,
1307 .wrapper = mlx4_QP_ATTACH_wrapper
1310 .opcode = MLX4_CMD_PROMISC,
1312 .has_outbox = false,
1313 .out_is_imm = false,
1314 .encode_slave_id = false,
1316 .wrapper = mlx4_PROMISC_wrapper
1318 /* Ethernet specific commands */
1320 .opcode = MLX4_CMD_SET_VLAN_FLTR,
1322 .has_outbox = false,
1323 .out_is_imm = false,
1324 .encode_slave_id = false,
1326 .wrapper = mlx4_SET_VLAN_FLTR_wrapper
1329 .opcode = MLX4_CMD_SET_MCAST_FLTR,
1331 .has_outbox = false,
1332 .out_is_imm = false,
1333 .encode_slave_id = false,
1335 .wrapper = mlx4_SET_MCAST_FLTR_wrapper
1338 .opcode = MLX4_CMD_DUMP_ETH_STATS,
1341 .out_is_imm = false,
1342 .encode_slave_id = false,
1344 .wrapper = mlx4_DUMP_ETH_STATS_wrapper
1347 .opcode = MLX4_CMD_INFORM_FLR_DONE,
1349 .has_outbox = false,
1350 .out_is_imm = false,
1351 .encode_slave_id = false,
1355 /* flow steering commands */
1357 .opcode = MLX4_QP_FLOW_STEERING_ATTACH,
1359 .has_outbox = false,
1361 .encode_slave_id = false,
1363 .wrapper = mlx4_QP_FLOW_STEERING_ATTACH_wrapper
1366 .opcode = MLX4_QP_FLOW_STEERING_DETACH,
1368 .has_outbox = false,
1369 .out_is_imm = false,
1370 .encode_slave_id = false,
1372 .wrapper = mlx4_QP_FLOW_STEERING_DETACH_wrapper
1375 .opcode = MLX4_FLOW_STEERING_IB_UC_QP_RANGE,
1377 .has_outbox = false,
1378 .out_is_imm = false,
1379 .encode_slave_id = false,
1381 .wrapper = mlx4_CMD_EPERM_wrapper
1385 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
1386 struct mlx4_vhcr_cmd *in_vhcr)
1388 struct mlx4_priv *priv = mlx4_priv(dev);
1389 struct mlx4_cmd_info *cmd = NULL;
1390 struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr;
1391 struct mlx4_vhcr *vhcr;
1392 struct mlx4_cmd_mailbox *inbox = NULL;
1393 struct mlx4_cmd_mailbox *outbox = NULL;
1400 /* Create sw representation of Virtual HCR */
1401 vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL);
1405 /* DMA in the vHCR */
1407 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1408 priv->mfunc.master.slave_state[slave].vhcr_dma,
1409 ALIGN(sizeof(struct mlx4_vhcr_cmd),
1410 MLX4_ACCESS_MEM_ALIGN), 1);
1412 mlx4_err(dev, "%s:Failed reading vhcr"
1413 "ret: 0x%x\n", __func__, ret);
1419 /* Fill SW VHCR fields */
1420 vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param);
1421 vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param);
1422 vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier);
1423 vhcr->token = be16_to_cpu(vhcr_cmd->token);
1424 vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff;
1425 vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12);
1426 vhcr->e_bit = vhcr_cmd->flags & (1 << 6);
1428 /* Lookup command */
1429 for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) {
1430 if (vhcr->op == cmd_info[i].opcode) {
1436 mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n",
1438 vhcr_cmd->status = CMD_STAT_BAD_PARAM;
1443 if (cmd->has_inbox) {
1444 vhcr->in_param &= INBOX_MASK;
1445 inbox = mlx4_alloc_cmd_mailbox(dev);
1446 if (IS_ERR(inbox)) {
1447 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1452 if (mlx4_ACCESS_MEM(dev, inbox->dma, slave,
1454 MLX4_MAILBOX_SIZE, 1)) {
1455 mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n",
1456 __func__, cmd->opcode);
1457 vhcr_cmd->status = CMD_STAT_INTERNAL_ERR;
1462 /* Apply permission and bound checks if applicable */
1463 if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) {
1464 mlx4_warn(dev, "Command:0x%x from slave: %d failed protection "
1465 "checks for resource_id:%d\n", vhcr->op, slave,
1467 vhcr_cmd->status = CMD_STAT_BAD_OP;
1471 /* Allocate outbox */
1472 if (cmd->has_outbox) {
1473 outbox = mlx4_alloc_cmd_mailbox(dev);
1474 if (IS_ERR(outbox)) {
1475 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1481 /* Execute the command! */
1483 err = cmd->wrapper(dev, slave, vhcr, inbox, outbox,
1485 if (cmd->out_is_imm)
1486 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1488 in_param = cmd->has_inbox ? (u64) inbox->dma :
1490 out_param = cmd->has_outbox ? (u64) outbox->dma :
1492 err = __mlx4_cmd(dev, in_param, &out_param,
1493 cmd->out_is_imm, vhcr->in_modifier,
1494 vhcr->op_modifier, vhcr->op,
1495 MLX4_CMD_TIME_CLASS_A,
1498 if (cmd->out_is_imm) {
1499 vhcr->out_param = out_param;
1500 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1505 mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with"
1506 " error:%d, status %d\n",
1507 vhcr->op, slave, vhcr->errno, err);
1508 vhcr_cmd->status = mlx4_errno_to_status(err);
1513 /* Write outbox if command completed successfully */
1514 if (cmd->has_outbox && !vhcr_cmd->status) {
1515 ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave,
1517 MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED);
1519 /* If we failed to write back the outbox after the
1520 *command was successfully executed, we must fail this
1521 * slave, as it is now in undefined state */
1522 mlx4_err(dev, "%s:Failed writing outbox\n", __func__);
1528 /* DMA back vhcr result */
1530 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1531 priv->mfunc.master.slave_state[slave].vhcr_dma,
1532 ALIGN(sizeof(struct mlx4_vhcr),
1533 MLX4_ACCESS_MEM_ALIGN),
1536 mlx4_err(dev, "%s:Failed writing vhcr result\n",
1538 else if (vhcr->e_bit &&
1539 mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe))
1540 mlx4_warn(dev, "Failed to generate command completion "
1541 "eqe for slave %d\n", slave);
1546 mlx4_free_cmd_mailbox(dev, inbox);
1547 mlx4_free_cmd_mailbox(dev, outbox);
1551 static int mlx4_master_immediate_activate_vlan_qos(struct mlx4_priv *priv,
1552 int slave, int port)
1554 struct mlx4_vport_oper_state *vp_oper;
1555 struct mlx4_vport_state *vp_admin;
1556 struct mlx4_vf_immed_vlan_work *work;
1557 struct mlx4_dev *dev = &(priv->dev);
1559 int admin_vlan_ix = NO_INDX;
1561 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1562 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1564 if (vp_oper->state.default_vlan == vp_admin->default_vlan &&
1565 vp_oper->state.default_qos == vp_admin->default_qos &&
1566 vp_oper->state.link_state == vp_admin->link_state)
1569 if (!(priv->mfunc.master.slave_state[slave].active &&
1570 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP)) {
1571 /* even if the UPDATE_QP command isn't supported, we still want
1572 * to set this VF link according to the admin directive
1574 vp_oper->state.link_state = vp_admin->link_state;
1578 mlx4_dbg(dev, "updating immediately admin params slave %d port %d\n",
1580 mlx4_dbg(dev, "vlan %d QoS %d link down %d\n", vp_admin->default_vlan,
1581 vp_admin->default_qos, vp_admin->link_state);
1583 work = kzalloc(sizeof(*work), GFP_KERNEL);
1587 if (vp_oper->state.default_vlan != vp_admin->default_vlan) {
1588 if (MLX4_VGT != vp_admin->default_vlan) {
1589 err = __mlx4_register_vlan(&priv->dev, port,
1590 vp_admin->default_vlan,
1594 mlx4_warn((&priv->dev),
1595 "No vlan resources slave %d, port %d\n",
1600 admin_vlan_ix = NO_INDX;
1602 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_VLAN;
1603 mlx4_dbg((&(priv->dev)),
1604 "alloc vlan %d idx %d slave %d port %d\n",
1605 (int)(vp_admin->default_vlan),
1606 admin_vlan_ix, slave, port);
1609 /* save original vlan ix and vlan id */
1610 work->orig_vlan_id = vp_oper->state.default_vlan;
1611 work->orig_vlan_ix = vp_oper->vlan_idx;
1613 /* handle new qos */
1614 if (vp_oper->state.default_qos != vp_admin->default_qos)
1615 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_QOS;
1617 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN)
1618 vp_oper->vlan_idx = admin_vlan_ix;
1620 vp_oper->state.default_vlan = vp_admin->default_vlan;
1621 vp_oper->state.default_qos = vp_admin->default_qos;
1622 vp_oper->state.link_state = vp_admin->link_state;
1624 if (vp_admin->link_state == IFLA_VF_LINK_STATE_DISABLE)
1625 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE;
1627 /* iterate over QPs owned by this slave, using UPDATE_QP */
1629 work->slave = slave;
1630 work->qos = vp_oper->state.default_qos;
1631 work->vlan_id = vp_oper->state.default_vlan;
1632 work->vlan_ix = vp_oper->vlan_idx;
1634 INIT_WORK(&work->work, mlx4_vf_immed_vlan_work_handler);
1635 queue_work(priv->mfunc.master.comm_wq, &work->work);
1641 static int mlx4_master_activate_admin_state(struct mlx4_priv *priv, int slave)
1644 struct mlx4_vport_state *vp_admin;
1645 struct mlx4_vport_oper_state *vp_oper;
1646 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
1648 int min_port = find_first_bit(actv_ports.ports,
1649 priv->dev.caps.num_ports) + 1;
1650 int max_port = min_port - 1 +
1651 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
1653 for (port = min_port; port <= max_port; port++) {
1654 if (!test_bit(port - 1, actv_ports.ports))
1656 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1657 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1658 vp_oper->state = *vp_admin;
1659 if (MLX4_VGT != vp_admin->default_vlan) {
1660 err = __mlx4_register_vlan(&priv->dev, port,
1661 vp_admin->default_vlan, &(vp_oper->vlan_idx));
1663 vp_oper->vlan_idx = NO_INDX;
1664 mlx4_warn((&priv->dev),
1665 "No vlan resorces slave %d, port %d\n",
1669 mlx4_dbg((&(priv->dev)), "alloc vlan %d idx %d slave %d port %d\n",
1670 (int)(vp_oper->state.default_vlan),
1671 vp_oper->vlan_idx, slave, port);
1673 if (vp_admin->spoofchk) {
1674 vp_oper->mac_idx = __mlx4_register_mac(&priv->dev,
1677 if (0 > vp_oper->mac_idx) {
1678 err = vp_oper->mac_idx;
1679 vp_oper->mac_idx = NO_INDX;
1680 mlx4_warn((&priv->dev),
1681 "No mac resorces slave %d, port %d\n",
1685 mlx4_dbg((&(priv->dev)), "alloc mac %llx idx %d slave %d port %d\n",
1686 vp_oper->state.mac, vp_oper->mac_idx, slave, port);
1692 static void mlx4_master_deactivate_admin_state(struct mlx4_priv *priv, int slave)
1695 struct mlx4_vport_oper_state *vp_oper;
1696 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
1698 int min_port = find_first_bit(actv_ports.ports,
1699 priv->dev.caps.num_ports) + 1;
1700 int max_port = min_port - 1 +
1701 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
1704 for (port = min_port; port <= max_port; port++) {
1705 if (!test_bit(port - 1, actv_ports.ports))
1707 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1708 if (NO_INDX != vp_oper->vlan_idx) {
1709 __mlx4_unregister_vlan(&priv->dev,
1710 port, vp_oper->state.default_vlan);
1711 vp_oper->vlan_idx = NO_INDX;
1713 if (NO_INDX != vp_oper->mac_idx) {
1714 __mlx4_unregister_mac(&priv->dev, port, vp_oper->state.mac);
1715 vp_oper->mac_idx = NO_INDX;
1721 static void mlx4_master_do_cmd(struct mlx4_dev *dev, int slave, u8 cmd,
1722 u16 param, u8 toggle)
1724 struct mlx4_priv *priv = mlx4_priv(dev);
1725 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
1727 u8 is_going_down = 0;
1729 unsigned long flags;
1731 slave_state[slave].comm_toggle ^= 1;
1732 reply = (u32) slave_state[slave].comm_toggle << 31;
1733 if (toggle != slave_state[slave].comm_toggle) {
1734 mlx4_warn(dev, "Incorrect toggle %d from slave %d. *** MASTER"
1735 "STATE COMPROMISIED ***\n", toggle, slave);
1738 if (cmd == MLX4_COMM_CMD_RESET) {
1739 mlx4_warn(dev, "Received reset from slave:%d\n", slave);
1740 slave_state[slave].active = false;
1741 slave_state[slave].old_vlan_api = false;
1742 mlx4_master_deactivate_admin_state(priv, slave);
1743 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) {
1744 slave_state[slave].event_eq[i].eqn = -1;
1745 slave_state[slave].event_eq[i].token = 0;
1747 /*check if we are in the middle of FLR process,
1748 if so return "retry" status to the slave*/
1749 if (MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd)
1750 goto inform_slave_state;
1752 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN, slave);
1754 /* write the version in the event field */
1755 reply |= mlx4_comm_get_version();
1759 /*command from slave in the middle of FLR*/
1760 if (cmd != MLX4_COMM_CMD_RESET &&
1761 MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) {
1762 mlx4_warn(dev, "slave:%d is Trying to run cmd(0x%x) "
1763 "in the middle of FLR\n", slave, cmd);
1768 case MLX4_COMM_CMD_VHCR0:
1769 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_RESET)
1771 slave_state[slave].vhcr_dma = ((u64) param) << 48;
1772 priv->mfunc.master.slave_state[slave].cookie = 0;
1773 mutex_init(&priv->mfunc.master.gen_eqe_mutex[slave]);
1775 case MLX4_COMM_CMD_VHCR1:
1776 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR0)
1778 slave_state[slave].vhcr_dma |= ((u64) param) << 32;
1780 case MLX4_COMM_CMD_VHCR2:
1781 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR1)
1783 slave_state[slave].vhcr_dma |= ((u64) param) << 16;
1785 case MLX4_COMM_CMD_VHCR_EN:
1786 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR2)
1788 slave_state[slave].vhcr_dma |= param;
1789 if (mlx4_master_activate_admin_state(priv, slave))
1791 slave_state[slave].active = true;
1792 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_INIT, slave);
1794 case MLX4_COMM_CMD_VHCR_POST:
1795 if ((slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_EN) &&
1796 (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_POST))
1799 mutex_lock(&priv->cmd.slave_cmd_mutex);
1800 if (mlx4_master_process_vhcr(dev, slave, NULL)) {
1801 mlx4_err(dev, "Failed processing vhcr for slave:%d,"
1802 " resetting slave.\n", slave);
1803 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1806 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1809 mlx4_warn(dev, "Bad comm cmd:%d from slave:%d\n", cmd, slave);
1812 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
1813 if (!slave_state[slave].is_slave_going_down)
1814 slave_state[slave].last_cmd = cmd;
1817 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
1818 if (is_going_down) {
1819 mlx4_warn(dev, "Slave is going down aborting command(%d)"
1820 " executing from slave:%d\n",
1824 __raw_writel((__force u32) cpu_to_be32(reply),
1825 &priv->mfunc.comm[slave].slave_read);
1831 /* cleanup any slave resources */
1832 mlx4_delete_all_resources_for_slave(dev, slave);
1833 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
1834 if (!slave_state[slave].is_slave_going_down)
1835 slave_state[slave].last_cmd = MLX4_COMM_CMD_RESET;
1836 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
1837 /*with slave in the middle of flr, no need to clean resources again.*/
1839 memset(&slave_state[slave].event_eq, 0,
1840 sizeof(struct mlx4_slave_event_eq_info));
1841 __raw_writel((__force u32) cpu_to_be32(reply),
1842 &priv->mfunc.comm[slave].slave_read);
1846 /* master command processing */
1847 void mlx4_master_comm_channel(struct work_struct *work)
1849 struct mlx4_mfunc_master_ctx *master =
1851 struct mlx4_mfunc_master_ctx,
1853 struct mlx4_mfunc *mfunc =
1854 container_of(master, struct mlx4_mfunc, master);
1855 struct mlx4_priv *priv =
1856 container_of(mfunc, struct mlx4_priv, mfunc);
1857 struct mlx4_dev *dev = &priv->dev;
1867 bit_vec = master->comm_arm_bit_vector;
1868 for (i = 0; i < COMM_CHANNEL_BIT_ARRAY_SIZE; i++) {
1869 vec = be32_to_cpu(bit_vec[i]);
1870 for (j = 0; j < 32; j++) {
1871 if (!(vec & (1 << j)))
1874 slave = (i * 32) + j;
1875 comm_cmd = swab32(readl(
1876 &mfunc->comm[slave].slave_write));
1877 slt = swab32(readl(&mfunc->comm[slave].slave_read))
1879 toggle = comm_cmd >> 31;
1880 if (toggle != slt) {
1881 if (master->slave_state[slave].comm_toggle
1883 printk(KERN_INFO "slave %d out of sync."
1884 " read toggle %d, state toggle %d. "
1885 "Resynching.\n", slave, slt,
1886 master->slave_state[slave].comm_toggle);
1887 master->slave_state[slave].comm_toggle =
1890 mlx4_master_do_cmd(dev, slave,
1891 comm_cmd >> 16 & 0xff,
1892 comm_cmd & 0xffff, toggle);
1898 if (reported && reported != served)
1899 mlx4_warn(dev, "Got command event with bitmask from %d slaves"
1900 " but %d were served\n",
1903 if (mlx4_ARM_COMM_CHANNEL(dev))
1904 mlx4_warn(dev, "Failed to arm comm channel events\n");
1907 static int sync_toggles(struct mlx4_dev *dev)
1909 struct mlx4_priv *priv = mlx4_priv(dev);
1914 wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write)) >> 31;
1915 end = jiffies + msecs_to_jiffies(5000);
1917 while (time_before(jiffies, end)) {
1918 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read)) >> 31;
1919 if (rd_toggle == wr_toggle) {
1920 priv->cmd.comm_toggle = rd_toggle;
1928 * we could reach here if for example the previous VM using this
1929 * function misbehaved and left the channel with unsynced state. We
1930 * should fix this here and give this VM a chance to use a properly
1933 mlx4_warn(dev, "recovering from previously mis-behaved VM\n");
1934 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read);
1935 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write);
1936 priv->cmd.comm_toggle = 0;
1941 int mlx4_multi_func_init(struct mlx4_dev *dev)
1943 struct mlx4_priv *priv = mlx4_priv(dev);
1944 struct mlx4_slave_state *s_state;
1945 int i, j, err, port;
1947 if (mlx4_is_master(dev))
1949 ioremap(pci_resource_start(dev->pdev, priv->fw.comm_bar) +
1950 priv->fw.comm_base, MLX4_COMM_PAGESIZE);
1953 ioremap(pci_resource_start(dev->pdev, 2) +
1954 MLX4_SLAVE_COMM_BASE, MLX4_COMM_PAGESIZE);
1955 if (!priv->mfunc.comm) {
1956 mlx4_err(dev, "Couldn't map communication vector.\n");
1960 if (mlx4_is_master(dev)) {
1961 priv->mfunc.master.slave_state =
1962 kzalloc(dev->num_slaves *
1963 sizeof(struct mlx4_slave_state), GFP_KERNEL);
1964 if (!priv->mfunc.master.slave_state)
1967 priv->mfunc.master.vf_admin =
1968 kzalloc(dev->num_slaves *
1969 sizeof(struct mlx4_vf_admin_state), GFP_KERNEL);
1970 if (!priv->mfunc.master.vf_admin)
1971 goto err_comm_admin;
1973 priv->mfunc.master.vf_oper =
1974 kzalloc(dev->num_slaves *
1975 sizeof(struct mlx4_vf_oper_state), GFP_KERNEL);
1976 if (!priv->mfunc.master.vf_oper)
1979 for (i = 0; i < dev->num_slaves; ++i) {
1980 s_state = &priv->mfunc.master.slave_state[i];
1981 s_state->last_cmd = MLX4_COMM_CMD_RESET;
1982 for (j = 0; j < MLX4_EVENT_TYPES_NUM; ++j)
1983 s_state->event_eq[j].eqn = -1;
1984 __raw_writel((__force u32) 0,
1985 &priv->mfunc.comm[i].slave_write);
1986 __raw_writel((__force u32) 0,
1987 &priv->mfunc.comm[i].slave_read);
1989 for (port = 1; port <= MLX4_MAX_PORTS; port++) {
1990 s_state->vlan_filter[port] =
1991 kzalloc(sizeof(struct mlx4_vlan_fltr),
1993 if (!s_state->vlan_filter[port]) {
1995 kfree(s_state->vlan_filter[port]);
1998 INIT_LIST_HEAD(&s_state->mcast_filters[port]);
1999 priv->mfunc.master.vf_admin[i].vport[port].default_vlan = MLX4_VGT;
2000 priv->mfunc.master.vf_oper[i].vport[port].state.default_vlan = MLX4_VGT;
2001 priv->mfunc.master.vf_oper[i].vport[port].vlan_idx = NO_INDX;
2002 priv->mfunc.master.vf_oper[i].vport[port].mac_idx = NO_INDX;
2004 spin_lock_init(&s_state->lock);
2007 memset(&priv->mfunc.master.cmd_eqe, 0, dev->caps.eqe_size);
2008 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD;
2009 INIT_WORK(&priv->mfunc.master.comm_work,
2010 mlx4_master_comm_channel);
2011 INIT_WORK(&priv->mfunc.master.slave_event_work,
2012 mlx4_gen_slave_eqe);
2013 INIT_WORK(&priv->mfunc.master.slave_flr_event_work,
2014 mlx4_master_handle_slave_flr);
2015 spin_lock_init(&priv->mfunc.master.slave_state_lock);
2016 spin_lock_init(&priv->mfunc.master.slave_eq.event_lock);
2017 priv->mfunc.master.comm_wq =
2018 create_singlethread_workqueue("mlx4_comm");
2019 if (!priv->mfunc.master.comm_wq)
2022 if (mlx4_init_resource_tracker(dev))
2025 err = mlx4_ARM_COMM_CHANNEL(dev);
2027 mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
2033 err = sync_toggles(dev);
2035 mlx4_err(dev, "Couldn't sync toggles\n");
2042 mlx4_free_resource_tracker(dev, RES_TR_FREE_ALL);
2044 flush_workqueue(priv->mfunc.master.comm_wq);
2045 destroy_workqueue(priv->mfunc.master.comm_wq);
2048 for (port = 1; port <= MLX4_MAX_PORTS; port++)
2049 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2051 kfree(priv->mfunc.master.vf_oper);
2053 kfree(priv->mfunc.master.vf_admin);
2055 kfree(priv->mfunc.master.slave_state);
2057 iounmap(priv->mfunc.comm);
2059 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
2061 priv->mfunc.vhcr_dma);
2062 priv->mfunc.vhcr = NULL;
2066 int mlx4_cmd_init(struct mlx4_dev *dev)
2068 struct mlx4_priv *priv = mlx4_priv(dev);
2070 mutex_init(&priv->cmd.hcr_mutex);
2071 mutex_init(&priv->cmd.slave_cmd_mutex);
2072 sema_init(&priv->cmd.poll_sem, 1);
2073 priv->cmd.use_events = 0;
2074 priv->cmd.toggle = 1;
2076 priv->cmd.hcr = NULL;
2077 priv->mfunc.vhcr = NULL;
2079 if (!mlx4_is_slave(dev)) {
2080 priv->cmd.hcr = ioremap(pci_resource_start(dev->pdev, 0) +
2081 MLX4_HCR_BASE, MLX4_HCR_SIZE);
2082 if (!priv->cmd.hcr) {
2083 mlx4_err(dev, "Couldn't map command register.\n");
2088 if (mlx4_is_mfunc(dev)) {
2089 priv->mfunc.vhcr = dma_alloc_coherent(&(dev->pdev->dev), PAGE_SIZE,
2090 &priv->mfunc.vhcr_dma,
2092 if (!priv->mfunc.vhcr)
2096 priv->cmd.pool = pci_pool_create("mlx4_cmd", dev->pdev,
2098 MLX4_MAILBOX_SIZE, 0);
2099 if (!priv->cmd.pool)
2105 if (mlx4_is_mfunc(dev))
2106 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
2107 priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
2108 priv->mfunc.vhcr = NULL;
2111 if (!mlx4_is_slave(dev))
2112 iounmap(priv->cmd.hcr);
2116 void mlx4_multi_func_cleanup(struct mlx4_dev *dev)
2118 struct mlx4_priv *priv = mlx4_priv(dev);
2121 if (mlx4_is_master(dev)) {
2122 flush_workqueue(priv->mfunc.master.comm_wq);
2123 destroy_workqueue(priv->mfunc.master.comm_wq);
2124 for (i = 0; i < dev->num_slaves; i++) {
2125 for (port = 1; port <= MLX4_MAX_PORTS; port++)
2126 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2128 kfree(priv->mfunc.master.slave_state);
2129 kfree(priv->mfunc.master.vf_admin);
2130 kfree(priv->mfunc.master.vf_oper);
2133 iounmap(priv->mfunc.comm);
2136 void mlx4_cmd_cleanup(struct mlx4_dev *dev)
2138 struct mlx4_priv *priv = mlx4_priv(dev);
2140 pci_pool_destroy(priv->cmd.pool);
2142 if (!mlx4_is_slave(dev))
2143 iounmap(priv->cmd.hcr);
2144 if (mlx4_is_mfunc(dev))
2145 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
2146 priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
2147 priv->mfunc.vhcr = NULL;
2151 * Switch to using events to issue FW commands (can only be called
2152 * after event queue for command events has been initialized).
2154 int mlx4_cmd_use_events(struct mlx4_dev *dev)
2156 struct mlx4_priv *priv = mlx4_priv(dev);
2160 priv->cmd.context = kmalloc(priv->cmd.max_cmds *
2161 sizeof (struct mlx4_cmd_context),
2163 if (!priv->cmd.context)
2166 for (i = 0; i < priv->cmd.max_cmds; ++i) {
2167 priv->cmd.context[i].token = i;
2168 priv->cmd.context[i].next = i + 1;
2171 priv->cmd.context[priv->cmd.max_cmds - 1].next = -1;
2172 priv->cmd.free_head = 0;
2174 sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds);
2175 spin_lock_init(&priv->cmd.context_lock);
2177 for (priv->cmd.token_mask = 1;
2178 priv->cmd.token_mask < priv->cmd.max_cmds;
2179 priv->cmd.token_mask <<= 1)
2181 --priv->cmd.token_mask;
2183 down(&priv->cmd.poll_sem);
2184 priv->cmd.use_events = 1;
2190 * Switch back to polling (used when shutting down the device)
2192 void mlx4_cmd_use_polling(struct mlx4_dev *dev)
2194 struct mlx4_priv *priv = mlx4_priv(dev);
2197 priv->cmd.use_events = 0;
2199 for (i = 0; i < priv->cmd.max_cmds; ++i)
2200 down(&priv->cmd.event_sem);
2202 kfree(priv->cmd.context);
2204 up(&priv->cmd.poll_sem);
2207 struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev)
2209 struct mlx4_cmd_mailbox *mailbox;
2211 mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL);
2213 return ERR_PTR(-ENOMEM);
2215 mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL,
2217 if (!mailbox->buf) {
2219 return ERR_PTR(-ENOMEM);
2222 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
2226 EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox);
2228 void mlx4_free_cmd_mailbox(struct mlx4_dev *dev,
2229 struct mlx4_cmd_mailbox *mailbox)
2234 pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma);
2237 EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox);
2239 u32 mlx4_comm_get_version(void)
2241 return ((u32) CMD_CHAN_IF_REV << 8) | (u32) CMD_CHAN_VER;
2244 static int mlx4_get_slave_indx(struct mlx4_dev *dev, int vf)
2246 if ((vf < 0) || (vf >= dev->num_vfs)) {
2247 mlx4_err(dev, "Bad vf number:%d (number of activated vf: %d)\n", vf, dev->num_vfs);
2254 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave)
2256 if (slave < 1 || slave > dev->num_vfs) {
2258 "Bad slave number:%d (number of activated slaves: %lu)\n",
2259 slave, dev->num_slaves);
2265 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave)
2267 struct mlx4_active_ports actv_ports;
2270 bitmap_zero(actv_ports.ports, MLX4_MAX_PORTS);
2273 bitmap_fill(actv_ports.ports, dev->caps.num_ports);
2277 vf = mlx4_get_vf_indx(dev, slave);
2281 bitmap_set(actv_ports.ports, dev->dev_vfs[vf].min_port - 1,
2282 min((int)dev->dev_vfs[mlx4_get_vf_indx(dev, slave)].n_ports,
2283 dev->caps.num_ports));
2287 EXPORT_SYMBOL_GPL(mlx4_get_active_ports);
2289 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port)
2292 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2293 unsigned m = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
2295 if (port <= 0 || port > m)
2298 n = find_first_bit(actv_ports.ports, dev->caps.num_ports);
2304 EXPORT_SYMBOL_GPL(mlx4_slave_convert_port);
2306 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port)
2308 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2309 if (test_bit(port - 1, actv_ports.ports))
2311 find_first_bit(actv_ports.ports, dev->caps.num_ports);
2315 EXPORT_SYMBOL_GPL(mlx4_phys_to_slave_port);
2317 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
2321 struct mlx4_slaves_pport slaves_pport;
2323 bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2325 if (port <= 0 || port > dev->caps.num_ports)
2326 return slaves_pport;
2328 for (i = 0; i < dev->num_vfs + 1; i++) {
2329 struct mlx4_active_ports actv_ports =
2330 mlx4_get_active_ports(dev, i);
2331 if (test_bit(port - 1, actv_ports.ports))
2332 set_bit(i, slaves_pport.slaves);
2335 return slaves_pport;
2337 EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport);
2339 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
2340 struct mlx4_dev *dev,
2341 const struct mlx4_active_ports *crit_ports)
2344 struct mlx4_slaves_pport slaves_pport;
2346 bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2348 for (i = 0; i < dev->num_vfs + 1; i++) {
2349 struct mlx4_active_ports actv_ports =
2350 mlx4_get_active_ports(dev, i);
2351 if (bitmap_equal(crit_ports->ports, actv_ports.ports,
2352 dev->caps.num_ports))
2353 set_bit(i, slaves_pport.slaves);
2356 return slaves_pport;
2358 EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport_actv);
2360 int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u64 mac)
2362 struct mlx4_priv *priv = mlx4_priv(dev);
2363 struct mlx4_vport_state *s_info;
2366 if (!mlx4_is_master(dev))
2367 return -EPROTONOSUPPORT;
2369 slave = mlx4_get_slave_indx(dev, vf);
2373 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2375 mlx4_info(dev, "default mac on vf %d port %d to %llX will take afect only after vf restart\n",
2376 vf, port, s_info->mac);
2379 EXPORT_SYMBOL_GPL(mlx4_set_vf_mac);
2382 int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos)
2384 struct mlx4_priv *priv = mlx4_priv(dev);
2385 struct mlx4_vport_state *vf_admin;
2388 if ((!mlx4_is_master(dev)) ||
2389 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VLAN_CONTROL))
2390 return -EPROTONOSUPPORT;
2392 if ((vlan > 4095) || (qos > 7))
2395 slave = mlx4_get_slave_indx(dev, vf);
2399 vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
2401 if ((0 == vlan) && (0 == qos))
2402 vf_admin->default_vlan = MLX4_VGT;
2404 vf_admin->default_vlan = vlan;
2405 vf_admin->default_qos = qos;
2407 if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
2409 "updating vf %d port %d config will take effect on next VF restart\n",
2413 EXPORT_SYMBOL_GPL(mlx4_set_vf_vlan);
2415 /* mlx4_get_slave_default_vlan -
2416 * return true if VST ( default vlan)
2417 * if VST, will return vlan & qos (if not NULL)
2419 bool mlx4_get_slave_default_vlan(struct mlx4_dev *dev, int port, int slave,
2422 struct mlx4_vport_oper_state *vp_oper;
2423 struct mlx4_priv *priv;
2425 priv = mlx4_priv(dev);
2426 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
2428 if (MLX4_VGT != vp_oper->state.default_vlan) {
2430 *vlan = vp_oper->state.default_vlan;
2432 *qos = vp_oper->state.default_qos;
2437 EXPORT_SYMBOL_GPL(mlx4_get_slave_default_vlan);
2439 int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting)
2441 struct mlx4_priv *priv = mlx4_priv(dev);
2442 struct mlx4_vport_state *s_info;
2445 if ((!mlx4_is_master(dev)) ||
2446 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FSM))
2447 return -EPROTONOSUPPORT;
2449 slave = mlx4_get_slave_indx(dev, vf);
2453 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2454 s_info->spoofchk = setting;
2458 EXPORT_SYMBOL_GPL(mlx4_set_vf_spoofchk);
2460 int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf)
2462 struct mlx4_priv *priv = mlx4_priv(dev);
2463 struct mlx4_vport_state *s_info;
2466 if (!mlx4_is_master(dev))
2467 return -EPROTONOSUPPORT;
2469 slave = mlx4_get_slave_indx(dev, vf);
2473 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2476 /* need to convert it to a func */
2477 ivf->mac[0] = ((s_info->mac >> (5*8)) & 0xff);
2478 ivf->mac[1] = ((s_info->mac >> (4*8)) & 0xff);
2479 ivf->mac[2] = ((s_info->mac >> (3*8)) & 0xff);
2480 ivf->mac[3] = ((s_info->mac >> (2*8)) & 0xff);
2481 ivf->mac[4] = ((s_info->mac >> (1*8)) & 0xff);
2482 ivf->mac[5] = ((s_info->mac) & 0xff);
2484 ivf->vlan = s_info->default_vlan;
2485 ivf->qos = s_info->default_qos;
2486 ivf->tx_rate = s_info->tx_rate;
2487 ivf->spoofchk = s_info->spoofchk;
2488 ivf->linkstate = s_info->link_state;
2492 EXPORT_SYMBOL_GPL(mlx4_get_vf_config);
2494 int mlx4_set_vf_link_state(struct mlx4_dev *dev, int port, int vf, int link_state)
2496 struct mlx4_priv *priv = mlx4_priv(dev);
2497 struct mlx4_vport_state *s_info;
2501 slave = mlx4_get_slave_indx(dev, vf);
2505 switch (link_state) {
2506 case IFLA_VF_LINK_STATE_AUTO:
2507 /* get current link state */
2508 if (!priv->sense.do_sense_port[port])
2509 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
2511 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
2514 case IFLA_VF_LINK_STATE_ENABLE:
2515 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
2518 case IFLA_VF_LINK_STATE_DISABLE:
2519 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
2523 mlx4_warn(dev, "unknown value for link_state %02x on slave %d port %d\n",
2524 link_state, slave, port);
2527 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2528 s_info->link_state = link_state;
2531 mlx4_gen_port_state_change_eqe(dev, slave, port, link_stat_event);
2533 if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
2535 "updating vf %d port %d no link state HW enforcment\n",
2539 EXPORT_SYMBOL_GPL(mlx4_set_vf_link_state);