1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Ethernet driver
4 * Copyright (C) 2020 Marvell.
11 #include <linux/etherdevice.h>
12 #include <linux/iommu.h>
13 #include <linux/if_vlan.h>
16 #define LBK_CHAN_BASE 0x000
17 #define SDP_CHAN_BASE 0x700
18 #define CGX_CHAN_BASE 0x800
20 #define OTX2_DATA_ALIGN(X) ALIGN(X, OTX2_ALIGN)
21 #define OTX2_HEAD_ROOM OTX2_ALIGN
23 #define OTX2_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN)
24 #define OTX2_MIN_MTU 60
26 #define OTX2_PAGE_POOL_SZ 2048
28 #define OTX2_MAX_GSO_SEGS 255
29 #define OTX2_MAX_FRAGS_IN_SQE 9
31 #define MAX_XDP_MTU (1530 - OTX2_ETH_HLEN)
33 /* Rx buffer size should be in multiples of 128bytes */
34 #define RCV_FRAG_LEN1(x) \
35 ((OTX2_HEAD_ROOM + OTX2_DATA_ALIGN(x)) + \
36 OTX2_DATA_ALIGN(sizeof(struct skb_shared_info)))
38 /* Prefer 2048 byte buffers for better last level cache
39 * utilization or data distribution across regions.
41 #define RCV_FRAG_LEN(x) \
42 ((RCV_FRAG_LEN1(x) < 2048) ? 2048 : RCV_FRAG_LEN1(x))
44 #define DMA_BUFFER_LEN(x) ((x) - OTX2_HEAD_ROOM)
46 /* IRQ triggered when NIX_LF_CINTX_CNT[ECOUNT]
47 * is equal to this value.
49 #define CQ_CQE_THRESH_DEFAULT 10
51 /* IRQ triggered when NIX_LF_CINTX_CNT[ECOUNT]
52 * is nonzero and this much time elapses after that.
54 #define CQ_TIMER_THRESH_DEFAULT 1 /* 1 usec */
55 #define CQ_TIMER_THRESH_MAX 25 /* 25 usec */
57 /* Min number of CQs (of the ones mapped to this CINT)
60 #define CQ_QCOUNT_DEFAULT 1
62 #define CQ_OP_STAT_OP_ERR 63
63 #define CQ_OP_STAT_CQ_ERR 46
70 struct otx2_rcv_queue {
71 struct queue_stats stats;
77 u64 size[OTX2_MAX_FRAGS_IN_SQE];
78 u64 dma_addr[OTX2_MAX_FRAGS_IN_SQE];
81 struct otx2_snd_queue {
95 struct qmem *tso_hdrs;
97 struct qmem *timestamps;
98 struct queue_stats stats;
101 } ____cacheline_aligned_in_smp;
108 CQS_PER_CINT = 4, /* RQ + SQ + XDP + QOS_SQ */
111 struct otx2_cq_poll {
113 #define CINT_INVALID_CQ 255
115 u8 cq_ids[CQS_PER_CINT];
117 struct napi_struct napi;
122 struct qmem *fc_addr;
123 struct page_pool *page_pool;
127 struct otx2_cq_queue {
130 u8 cint_idx; /* CQ interrupt id */
131 u8 refill_task_sched;
140 struct otx2_pool *rbpool;
141 struct xdp_rxq_info xdp_rxq;
142 } ____cacheline_aligned_in_smp;
146 u32 sqe_cnt; /* Keep these two at top */
147 #define OTX2_MAX_CQ_CNT 64
150 struct otx2_pool *pool;
151 struct otx2_cq_poll *napi;
152 struct otx2_cq_queue *cq;
153 struct otx2_snd_queue *sq;
154 struct otx2_rcv_queue *rq;
157 /* Translate IOVA to physical address */
158 static inline u64 otx2_iova_to_phys(void *iommu_domain, dma_addr_t dma_addr)
160 /* Translation is installed only when IOMMU is present */
161 if (likely(iommu_domain))
162 return iommu_iova_to_phys(iommu_domain, dma_addr);
166 int otx2_napi_handler(struct napi_struct *napi, int budget);
167 bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *sq,
168 struct sk_buff *skb, u16 qidx);
169 void cn10k_sqe_flush(void *dev, struct otx2_snd_queue *sq,
171 void otx2_sqe_flush(void *dev, struct otx2_snd_queue *sq,
173 int otx2_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq);
174 int cn10k_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq);
175 #endif /* OTX2_TXRX_H */