1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell OcteonTx2 CGX driver
4 * Copyright (C) 2018 Marvell.
8 #include <linux/acpi.h>
9 #include <linux/module.h>
10 #include <linux/interrupt.h>
11 #include <linux/pci.h>
12 #include <linux/netdevice.h>
13 #include <linux/etherdevice.h>
14 #include <linux/ethtool.h>
15 #include <linux/phy.h>
17 #include <linux/of_mdio.h>
18 #include <linux/of_net.h>
22 #include "lmac_common.h"
24 #define DRV_NAME "Marvell-CGX/RPM"
25 #define DRV_STRING "Marvell CGX/RPM Driver"
27 static LIST_HEAD(cgx_list);
29 /* Convert firmware speed encoding to user format(Mbps) */
30 static const u32 cgx_speed_mbps[CGX_LINK_SPEED_MAX] = {
33 [CGX_LINK_100M] = 100,
35 [CGX_LINK_2HG] = 2500,
37 [CGX_LINK_10G] = 10000,
38 [CGX_LINK_20G] = 20000,
39 [CGX_LINK_25G] = 25000,
40 [CGX_LINK_40G] = 40000,
41 [CGX_LINK_50G] = 50000,
42 [CGX_LINK_80G] = 80000,
43 [CGX_LINK_100G] = 100000,
46 /* Convert firmware lmac type encoding to string */
47 static const char *cgx_lmactype_string[LMAC_MODE_MAX] = {
48 [LMAC_MODE_SGMII] = "SGMII",
49 [LMAC_MODE_XAUI] = "XAUI",
50 [LMAC_MODE_RXAUI] = "RXAUI",
51 [LMAC_MODE_10G_R] = "10G_R",
52 [LMAC_MODE_40G_R] = "40G_R",
53 [LMAC_MODE_QSGMII] = "QSGMII",
54 [LMAC_MODE_25G_R] = "25G_R",
55 [LMAC_MODE_50G_R] = "50G_R",
56 [LMAC_MODE_100G_R] = "100G_R",
57 [LMAC_MODE_USXGMII] = "USXGMII",
58 [LMAC_MODE_USGMII] = "USGMII",
61 /* CGX PHY management internal APIs */
62 static int cgx_fwi_link_change(struct cgx *cgx, int lmac_id, bool en);
64 /* Supported devices */
65 static const struct pci_device_id cgx_id_table[] = {
66 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_CGX) },
67 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM) },
68 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10KB_RPM) },
69 { 0, } /* end of table */
72 MODULE_DEVICE_TABLE(pci, cgx_id_table);
74 static bool is_dev_rpm(void *cgxd)
76 struct cgx *cgx = cgxd;
78 return (cgx->pdev->device == PCI_DEVID_CN10K_RPM) ||
79 (cgx->pdev->device == PCI_DEVID_CN10KB_RPM);
82 bool is_lmac_valid(struct cgx *cgx, int lmac_id)
84 if (!cgx || lmac_id < 0 || lmac_id >= cgx->max_lmac_per_mac)
86 return test_bit(lmac_id, &cgx->lmac_bmap);
89 /* Helper function to get sequential index
90 * given the enabled LMAC of a CGX
92 static int get_sequence_id_of_lmac(struct cgx *cgx, int lmac_id)
96 for_each_set_bit(tmp, &cgx->lmac_bmap, cgx->max_lmac_per_mac) {
105 struct mac_ops *get_mac_ops(void *cgxd)
110 return ((struct cgx *)cgxd)->mac_ops;
113 void cgx_write(struct cgx *cgx, u64 lmac, u64 offset, u64 val)
115 writeq(val, cgx->reg_base + (lmac << cgx->mac_ops->lmac_offset) +
119 u64 cgx_read(struct cgx *cgx, u64 lmac, u64 offset)
121 return readq(cgx->reg_base + (lmac << cgx->mac_ops->lmac_offset) +
125 struct lmac *lmac_pdata(u8 lmac_id, struct cgx *cgx)
127 if (!cgx || lmac_id >= cgx->max_lmac_per_mac)
130 return cgx->lmac_idmap[lmac_id];
133 int cgx_get_cgxcnt_max(void)
138 list_for_each_entry(cgx_dev, &cgx_list, cgx_list)
139 if (cgx_dev->cgx_id > idmax)
140 idmax = cgx_dev->cgx_id;
148 int cgx_get_lmac_cnt(void *cgxd)
150 struct cgx *cgx = cgxd;
155 return cgx->lmac_count;
158 void *cgx_get_pdata(int cgx_id)
162 list_for_each_entry(cgx_dev, &cgx_list, cgx_list) {
163 if (cgx_dev->cgx_id == cgx_id)
169 void cgx_lmac_write(int cgx_id, int lmac_id, u64 offset, u64 val)
171 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
173 /* Software must not access disabled LMAC registers */
174 if (!is_lmac_valid(cgx_dev, lmac_id))
176 cgx_write(cgx_dev, lmac_id, offset, val);
179 u64 cgx_lmac_read(int cgx_id, int lmac_id, u64 offset)
181 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
183 /* Software must not access disabled LMAC registers */
184 if (!is_lmac_valid(cgx_dev, lmac_id))
187 return cgx_read(cgx_dev, lmac_id, offset);
190 int cgx_get_cgxid(void *cgxd)
192 struct cgx *cgx = cgxd;
200 u8 cgx_lmac_get_p2x(int cgx_id, int lmac_id)
202 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
205 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_CFG);
207 return (cfg & CMR_P2X_SEL_MASK) >> CMR_P2X_SEL_SHIFT;
210 /* Ensure the required lock for event queue(where asynchronous events are
211 * posted) is acquired before calling this API. Else an asynchronous event(with
212 * latest link status) can reach the destination before this function returns
213 * and could make the link status appear wrong.
215 int cgx_get_link_info(void *cgxd, int lmac_id,
216 struct cgx_link_user_info *linfo)
218 struct lmac *lmac = lmac_pdata(lmac_id, cgxd);
223 *linfo = lmac->link_info;
227 int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr)
229 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
230 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
231 struct mac_ops *mac_ops;
238 /* access mac_ops to know csr_offset */
239 mac_ops = cgx_dev->mac_ops;
241 /* copy 6bytes from macaddr */
242 /* memcpy(&cfg, mac_addr, 6); */
244 cfg = ether_addr_to_u64(mac_addr);
246 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
248 index = id * lmac->mac_to_index_bmap.max;
250 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)),
251 cfg | CGX_DMAC_CAM_ADDR_ENABLE | ((u64)lmac_id << 49));
253 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
254 cfg |= (CGX_DMAC_CTL0_CAM_ENABLE | CGX_DMAC_BCAST_MODE |
255 CGX_DMAC_MCAST_MODE);
256 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
261 u64 cgx_read_dmac_ctrl(void *cgxd, int lmac_id)
263 struct mac_ops *mac_ops;
264 struct cgx *cgx = cgxd;
266 if (!cgxd || !is_lmac_valid(cgxd, lmac_id))
270 /* Get mac_ops to know csr offset */
271 mac_ops = cgx->mac_ops;
273 return cgx_read(cgxd, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
276 u64 cgx_read_dmac_entry(void *cgxd, int index)
278 struct mac_ops *mac_ops;
285 mac_ops = cgx->mac_ops;
286 return cgx_read(cgx, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 8)));
289 int cgx_lmac_addr_add(u8 cgx_id, u8 lmac_id, u8 *mac_addr)
291 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
292 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
293 struct mac_ops *mac_ops;
301 mac_ops = cgx_dev->mac_ops;
302 /* Get available index where entry is to be installed */
303 idx = rvu_alloc_rsrc(&lmac->mac_to_index_bmap);
307 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
309 index = id * lmac->mac_to_index_bmap.max + idx;
311 cfg = ether_addr_to_u64(mac_addr);
312 cfg |= CGX_DMAC_CAM_ADDR_ENABLE;
313 cfg |= ((u64)lmac_id << 49);
314 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), cfg);
316 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
317 cfg |= (CGX_DMAC_BCAST_MODE | CGX_DMAC_CAM_ACCEPT);
319 if (is_multicast_ether_addr(mac_addr)) {
320 cfg &= ~GENMASK_ULL(2, 1);
321 cfg |= CGX_DMAC_MCAST_MODE_CAM;
322 lmac->mcast_filters_count++;
323 } else if (!lmac->mcast_filters_count) {
324 cfg |= CGX_DMAC_MCAST_MODE;
327 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
332 int cgx_lmac_addr_reset(u8 cgx_id, u8 lmac_id)
334 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
335 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
336 struct mac_ops *mac_ops;
343 mac_ops = cgx_dev->mac_ops;
344 /* Restore index 0 to its default init value as done during
347 set_bit(0, lmac->mac_to_index_bmap.bmap);
349 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
351 index = id * lmac->mac_to_index_bmap.max + index;
352 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), 0);
354 /* Reset CGXX_CMRX_RX_DMAC_CTL0 register to default state */
355 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
356 cfg &= ~CGX_DMAC_CAM_ACCEPT;
357 cfg |= (CGX_DMAC_BCAST_MODE | CGX_DMAC_MCAST_MODE);
358 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
363 /* Allows caller to change macaddress associated with index
364 * in dmac filter table including index 0 reserved for
365 * interface mac address
367 int cgx_lmac_addr_update(u8 cgx_id, u8 lmac_id, u8 *mac_addr, u8 index)
369 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
370 struct mac_ops *mac_ops;
375 lmac = lmac_pdata(lmac_id, cgx_dev);
379 mac_ops = cgx_dev->mac_ops;
380 /* Validate the index */
381 if (index >= lmac->mac_to_index_bmap.max)
384 /* ensure index is already set */
385 if (!test_bit(index, lmac->mac_to_index_bmap.bmap))
388 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
390 index = id * lmac->mac_to_index_bmap.max + index;
392 cfg = cgx_read(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)));
393 cfg &= ~CGX_RX_DMAC_ADR_MASK;
394 cfg |= ether_addr_to_u64(mac_addr);
396 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), cfg);
400 int cgx_lmac_addr_del(u8 cgx_id, u8 lmac_id, u8 index)
402 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
403 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
404 struct mac_ops *mac_ops;
412 mac_ops = cgx_dev->mac_ops;
413 /* Validate the index */
414 if (index >= lmac->mac_to_index_bmap.max)
417 /* Skip deletion for reserved index i.e. index 0 */
421 rvu_free_rsrc(&lmac->mac_to_index_bmap, index);
423 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
425 index = id * lmac->mac_to_index_bmap.max + index;
427 /* Read MAC address to check whether it is ucast or mcast */
428 cfg = cgx_read(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)));
430 u64_to_ether_addr(cfg, mac);
431 if (is_multicast_ether_addr(mac))
432 lmac->mcast_filters_count--;
434 if (!lmac->mcast_filters_count) {
435 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
436 cfg &= ~GENMASK_ULL(2, 1);
437 cfg |= CGX_DMAC_MCAST_MODE;
438 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
441 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), 0);
446 int cgx_lmac_addr_max_entries_get(u8 cgx_id, u8 lmac_id)
448 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
449 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
452 return lmac->mac_to_index_bmap.max;
457 u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id)
459 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
460 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
461 struct mac_ops *mac_ops;
466 mac_ops = cgx_dev->mac_ops;
468 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
470 index = id * lmac->mac_to_index_bmap.max;
472 cfg = cgx_read(cgx_dev, 0, CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8);
473 return cfg & CGX_RX_DMAC_ADR_MASK;
476 int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind)
478 struct cgx *cgx = cgxd;
480 if (!is_lmac_valid(cgx, lmac_id))
483 cgx_write(cgx, lmac_id, cgx->mac_ops->rxid_map_offset, (pkind & 0x3F));
487 static u8 cgx_get_lmac_type(void *cgxd, int lmac_id)
489 struct cgx *cgx = cgxd;
492 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG);
493 return (cfg >> CGX_LMAC_TYPE_SHIFT) & CGX_LMAC_TYPE_MASK;
496 static u32 cgx_get_lmac_fifo_len(void *cgxd, int lmac_id)
498 struct cgx *cgx = cgxd;
502 fifo_len = cgx->mac_ops->fifo_len;
503 num_lmacs = cgx->mac_ops->get_nr_lmacs(cgx);
511 /* LMAC0 gets half of the FIFO, reset 1/4th */
522 /* Configure CGX LMAC in internal loopback mode */
523 int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable)
525 struct cgx *cgx = cgxd;
529 if (!is_lmac_valid(cgx, lmac_id))
532 lmac = lmac_pdata(lmac_id, cgx);
533 if (lmac->lmac_type == LMAC_MODE_SGMII ||
534 lmac->lmac_type == LMAC_MODE_QSGMII) {
535 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_PCS_MRX_CTL);
537 cfg |= CGXX_GMP_PCS_MRX_CTL_LBK;
539 cfg &= ~CGXX_GMP_PCS_MRX_CTL_LBK;
540 cgx_write(cgx, lmac_id, CGXX_GMP_PCS_MRX_CTL, cfg);
542 cfg = cgx_read(cgx, lmac_id, CGXX_SPUX_CONTROL1);
544 cfg |= CGXX_SPUX_CONTROL1_LBK;
546 cfg &= ~CGXX_SPUX_CONTROL1_LBK;
547 cgx_write(cgx, lmac_id, CGXX_SPUX_CONTROL1, cfg);
552 void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable)
554 struct cgx *cgx = cgx_get_pdata(cgx_id);
555 struct lmac *lmac = lmac_pdata(lmac_id, cgx);
556 struct mac_ops *mac_ops;
565 max_dmac = lmac->mac_to_index_bmap.max;
566 id = get_sequence_id_of_lmac(cgx, lmac_id);
568 mac_ops = cgx->mac_ops;
570 /* Enable promiscuous mode on LMAC */
571 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
572 cfg &= ~CGX_DMAC_CAM_ACCEPT;
573 cfg |= (CGX_DMAC_BCAST_MODE | CGX_DMAC_MCAST_MODE);
574 cgx_write(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
576 for (i = 0; i < max_dmac; i++) {
577 index = id * max_dmac + i;
578 cfg = cgx_read(cgx, 0,
579 (CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8));
580 cfg &= ~CGX_DMAC_CAM_ADDR_ENABLE;
582 (CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8), cfg);
585 /* Disable promiscuous mode */
586 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
587 cfg |= CGX_DMAC_CAM_ACCEPT | CGX_DMAC_MCAST_MODE;
588 cgx_write(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
589 for (i = 0; i < max_dmac; i++) {
590 index = id * max_dmac + i;
591 cfg = cgx_read(cgx, 0,
592 (CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8));
593 if ((cfg & CGX_RX_DMAC_ADR_MASK) != 0) {
594 cfg |= CGX_DMAC_CAM_ADDR_ENABLE;
596 (CGXX_CMRX_RX_DMAC_CAM0 +
604 static int cgx_lmac_get_pause_frm_status(void *cgxd, int lmac_id,
605 u8 *tx_pause, u8 *rx_pause)
607 struct cgx *cgx = cgxd;
613 if (!is_lmac_valid(cgx, lmac_id))
616 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
617 *rx_pause = !!(cfg & CGX_SMUX_RX_FRM_CTL_CTL_BCK);
619 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL);
620 *tx_pause = !!(cfg & CGX_SMUX_TX_CTL_L2P_BP_CONV);
624 /* Enable or disable forwarding received pause frames to Tx block */
625 void cgx_lmac_enadis_rx_pause_fwding(void *cgxd, int lmac_id, bool enable)
627 struct cgx *cgx = cgxd;
628 u8 rx_pause, tx_pause;
636 lmac = lmac_pdata(lmac_id, cgx);
640 /* Pause frames are not enabled just return */
641 if (!bitmap_weight(lmac->rx_fc_pfvf_bmap.bmap, lmac->rx_fc_pfvf_bmap.max))
644 cgx_lmac_get_pause_frm_status(cgx, lmac_id, &rx_pause, &tx_pause);
645 is_pfc_enabled = rx_pause ? false : true;
648 if (!is_pfc_enabled) {
649 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
650 cfg |= CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK;
651 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
653 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
654 cfg |= CGX_SMUX_RX_FRM_CTL_CTL_BCK;
655 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
657 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL);
658 cfg |= CGXX_SMUX_CBFC_CTL_BCK_EN;
659 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg);
663 if (!is_pfc_enabled) {
664 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
665 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK;
666 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
668 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
669 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK;
670 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
672 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL);
673 cfg &= ~CGXX_SMUX_CBFC_CTL_BCK_EN;
674 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg);
679 int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat)
681 struct cgx *cgx = cgxd;
683 if (!is_lmac_valid(cgx, lmac_id))
685 *rx_stat = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_STAT0 + (idx * 8));
689 int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat)
691 struct cgx *cgx = cgxd;
693 if (!is_lmac_valid(cgx, lmac_id))
695 *tx_stat = cgx_read(cgx, lmac_id, CGXX_CMRX_TX_STAT0 + (idx * 8));
699 u64 cgx_features_get(void *cgxd)
701 return ((struct cgx *)cgxd)->hw_features;
704 static int cgx_set_fec_stats_count(struct cgx_link_user_info *linfo)
709 switch (linfo->lmac_type_id) {
710 case LMAC_MODE_SGMII:
712 case LMAC_MODE_RXAUI:
713 case LMAC_MODE_QSGMII:
715 case LMAC_MODE_10G_R:
716 case LMAC_MODE_25G_R:
717 case LMAC_MODE_100G_R:
718 case LMAC_MODE_USXGMII:
720 case LMAC_MODE_40G_R:
722 case LMAC_MODE_50G_R:
723 if (linfo->fec == OTX2_FEC_BASER)
732 int cgx_get_fec_stats(void *cgxd, int lmac_id, struct cgx_fec_stats_rsp *rsp)
734 int stats, fec_stats_count = 0;
735 int corr_reg, uncorr_reg;
736 struct cgx *cgx = cgxd;
738 if (!is_lmac_valid(cgx, lmac_id))
741 if (cgx->lmac_idmap[lmac_id]->link_info.fec == OTX2_FEC_NONE)
745 cgx_set_fec_stats_count(&cgx->lmac_idmap[lmac_id]->link_info);
746 if (cgx->lmac_idmap[lmac_id]->link_info.fec == OTX2_FEC_BASER) {
747 corr_reg = CGXX_SPUX_LNX_FEC_CORR_BLOCKS;
748 uncorr_reg = CGXX_SPUX_LNX_FEC_UNCORR_BLOCKS;
750 corr_reg = CGXX_SPUX_RSFEC_CORR;
751 uncorr_reg = CGXX_SPUX_RSFEC_UNCORR;
753 for (stats = 0; stats < fec_stats_count; stats++) {
754 rsp->fec_corr_blks +=
755 cgx_read(cgx, lmac_id, corr_reg + (stats * 8));
756 rsp->fec_uncorr_blks +=
757 cgx_read(cgx, lmac_id, uncorr_reg + (stats * 8));
762 int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable)
764 struct cgx *cgx = cgxd;
767 if (!is_lmac_valid(cgx, lmac_id))
770 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG);
772 cfg |= DATA_PKT_RX_EN | DATA_PKT_TX_EN;
774 cfg &= ~(DATA_PKT_RX_EN | DATA_PKT_TX_EN);
775 cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg);
779 int cgx_lmac_tx_enable(void *cgxd, int lmac_id, bool enable)
781 struct cgx *cgx = cgxd;
784 if (!is_lmac_valid(cgx, lmac_id))
787 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG);
790 cfg |= DATA_PKT_TX_EN;
792 cfg &= ~DATA_PKT_TX_EN;
795 cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg);
796 return !!(last & DATA_PKT_TX_EN);
799 static int cgx_lmac_enadis_pause_frm(void *cgxd, int lmac_id,
800 u8 tx_pause, u8 rx_pause)
802 struct cgx *cgx = cgxd;
808 if (!is_lmac_valid(cgx, lmac_id))
811 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
812 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK;
813 cfg |= rx_pause ? CGX_SMUX_RX_FRM_CTL_CTL_BCK : 0x0;
814 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
816 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL);
817 cfg &= ~CGX_SMUX_TX_CTL_L2P_BP_CONV;
818 cfg |= tx_pause ? CGX_SMUX_TX_CTL_L2P_BP_CONV : 0x0;
819 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_CTL, cfg);
821 cfg = cgx_read(cgx, 0, CGXX_CMR_RX_OVR_BP);
823 cfg &= ~CGX_CMR_RX_OVR_BP_EN(lmac_id);
825 cfg |= CGX_CMR_RX_OVR_BP_EN(lmac_id);
826 cfg &= ~CGX_CMR_RX_OVR_BP_BP(lmac_id);
828 cgx_write(cgx, 0, CGXX_CMR_RX_OVR_BP, cfg);
832 static void cgx_lmac_pause_frm_config(void *cgxd, int lmac_id, bool enable)
834 struct cgx *cgx = cgxd;
837 if (!is_lmac_valid(cgx, lmac_id))
841 /* Set pause time and interval */
842 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_TIME,
844 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_INTERVAL);
846 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_INTERVAL,
847 cfg | (DEFAULT_PAUSE_TIME / 2));
849 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_TX_PAUSE_PKT_TIME,
852 cfg = cgx_read(cgx, lmac_id,
853 CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL);
855 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL,
856 cfg | (DEFAULT_PAUSE_TIME / 2));
859 /* ALL pause frames received are completely ignored */
860 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
861 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK;
862 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
864 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
865 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK;
866 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
868 /* Disable pause frames transmission */
869 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL);
870 cfg &= ~CGX_SMUX_TX_CTL_L2P_BP_CONV;
871 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_CTL, cfg);
873 cfg = cgx_read(cgx, 0, CGXX_CMR_RX_OVR_BP);
874 cfg |= CGX_CMR_RX_OVR_BP_EN(lmac_id);
875 cfg &= ~CGX_CMR_RX_OVR_BP_BP(lmac_id);
876 cgx_write(cgx, 0, CGXX_CMR_RX_OVR_BP, cfg);
878 /* Disable all PFC classes by default */
879 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL);
880 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, 0, cfg);
881 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg);
884 int verify_lmac_fc_cfg(void *cgxd, int lmac_id, u8 tx_pause, u8 rx_pause,
887 struct cgx *cgx = cgxd;
890 lmac = lmac_pdata(lmac_id, cgx);
895 clear_bit(pfvf_idx, lmac->rx_fc_pfvf_bmap.bmap);
897 set_bit(pfvf_idx, lmac->rx_fc_pfvf_bmap.bmap);
900 clear_bit(pfvf_idx, lmac->tx_fc_pfvf_bmap.bmap);
902 set_bit(pfvf_idx, lmac->tx_fc_pfvf_bmap.bmap);
904 /* check if other pfvfs are using flow control */
905 if (!rx_pause && bitmap_weight(lmac->rx_fc_pfvf_bmap.bmap, lmac->rx_fc_pfvf_bmap.max)) {
906 dev_warn(&cgx->pdev->dev,
907 "Receive Flow control disable not permitted as its used by other PFVFs\n");
911 if (!tx_pause && bitmap_weight(lmac->tx_fc_pfvf_bmap.bmap, lmac->tx_fc_pfvf_bmap.max)) {
912 dev_warn(&cgx->pdev->dev,
913 "Transmit Flow control disable not permitted as its used by other PFVFs\n");
920 int cgx_lmac_pfc_config(void *cgxd, int lmac_id, u8 tx_pause,
921 u8 rx_pause, u16 pfc_en)
923 struct cgx *cgx = cgxd;
926 if (!is_lmac_valid(cgx, lmac_id))
929 /* Return as no traffic classes are requested */
930 if (tx_pause && !pfc_en)
933 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL);
934 pfc_en |= FIELD_GET(CGX_PFC_CLASS_MASK, cfg);
937 cfg |= (CGXX_SMUX_CBFC_CTL_RX_EN |
938 CGXX_SMUX_CBFC_CTL_BCK_EN |
939 CGXX_SMUX_CBFC_CTL_DRP_EN);
941 cfg &= ~(CGXX_SMUX_CBFC_CTL_RX_EN |
942 CGXX_SMUX_CBFC_CTL_BCK_EN |
943 CGXX_SMUX_CBFC_CTL_DRP_EN);
947 cfg |= CGXX_SMUX_CBFC_CTL_TX_EN;
948 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, pfc_en, cfg);
950 cfg &= ~CGXX_SMUX_CBFC_CTL_TX_EN;
951 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, 0, cfg);
954 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg);
956 /* Write source MAC address which will be filled into PFC packet */
957 cfg = cgx_lmac_addr_get(cgx->cgx_id, lmac_id);
958 cgx_write(cgx, lmac_id, CGXX_SMUX_SMAC, cfg);
963 int cgx_lmac_get_pfc_frm_cfg(void *cgxd, int lmac_id, u8 *tx_pause,
966 struct cgx *cgx = cgxd;
969 if (!is_lmac_valid(cgx, lmac_id))
972 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL);
974 *rx_pause = !!(cfg & CGXX_SMUX_CBFC_CTL_RX_EN);
975 *tx_pause = !!(cfg & CGXX_SMUX_CBFC_CTL_TX_EN);
980 void cgx_lmac_ptp_config(void *cgxd, int lmac_id, bool enable)
982 struct cgx *cgx = cgxd;
989 /* Enable inbound PTP timestamping */
990 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
991 cfg |= CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE;
992 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
994 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
995 cfg |= CGX_SMUX_RX_FRM_CTL_PTP_MODE;
996 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
998 /* Disable inbound PTP stamping */
999 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
1000 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE;
1001 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
1003 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
1004 cfg &= ~CGX_SMUX_RX_FRM_CTL_PTP_MODE;
1005 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
1009 /* CGX Firmware interface low level support */
1010 int cgx_fwi_cmd_send(u64 req, u64 *resp, struct lmac *lmac)
1012 struct cgx *cgx = lmac->cgx;
1017 /* Ensure no other command is in progress */
1018 err = mutex_lock_interruptible(&lmac->cmd_lock);
1022 /* Ensure command register is free */
1023 cmd = cgx_read(cgx, lmac->lmac_id, CGX_COMMAND_REG);
1024 if (FIELD_GET(CMDREG_OWN, cmd) != CGX_CMD_OWN_NS) {
1029 /* Update ownership in command request */
1030 req = FIELD_SET(CMDREG_OWN, CGX_CMD_OWN_FIRMWARE, req);
1032 /* Mark this lmac as pending, before we start */
1033 lmac->cmd_pend = true;
1035 /* Start command in hardware */
1036 cgx_write(cgx, lmac->lmac_id, CGX_COMMAND_REG, req);
1038 /* Ensure command is completed without errors */
1039 if (!wait_event_timeout(lmac->wq_cmd_cmplt, !lmac->cmd_pend,
1040 msecs_to_jiffies(CGX_CMD_TIMEOUT))) {
1041 dev = &cgx->pdev->dev;
1042 dev_err(dev, "cgx port %d:%d cmd %lld timeout\n",
1043 cgx->cgx_id, lmac->lmac_id, FIELD_GET(CMDREG_ID, req));
1044 err = LMAC_AF_ERR_CMD_TIMEOUT;
1048 /* we have a valid command response */
1049 smp_rmb(); /* Ensure the latest updates are visible */
1053 mutex_unlock(&lmac->cmd_lock);
1058 int cgx_fwi_cmd_generic(u64 req, u64 *resp, struct cgx *cgx, int lmac_id)
1063 lmac = lmac_pdata(lmac_id, cgx);
1067 err = cgx_fwi_cmd_send(req, resp, lmac);
1069 /* Check for valid response */
1071 if (FIELD_GET(EVTREG_STAT, *resp) == CGX_STAT_FAIL)
1080 static int cgx_link_usertable_index_map(int speed)
1084 return CGX_LINK_10M;
1086 return CGX_LINK_100M;
1090 return CGX_LINK_2HG;
1094 return CGX_LINK_10G;
1096 return CGX_LINK_20G;
1098 return CGX_LINK_25G;
1100 return CGX_LINK_40G;
1102 return CGX_LINK_50G;
1104 return CGX_LINK_80G;
1106 return CGX_LINK_100G;
1108 return CGX_LINK_NONE;
1110 return CGX_LINK_NONE;
1113 static void set_mod_args(struct cgx_set_link_mode_args *args,
1114 u32 speed, u8 duplex, u8 autoneg, u64 mode)
1116 /* Fill default values incase of user did not pass
1119 if (args->duplex == DUPLEX_UNKNOWN)
1120 args->duplex = duplex;
1121 if (args->speed == SPEED_UNKNOWN)
1122 args->speed = speed;
1123 if (args->an == AUTONEG_UNKNOWN)
1129 static void otx2_map_ethtool_link_modes(u64 bitmask,
1130 struct cgx_set_link_mode_args *args)
1133 case ETHTOOL_LINK_MODE_10baseT_Half_BIT:
1134 set_mod_args(args, 10, 1, 1, BIT_ULL(CGX_MODE_SGMII));
1136 case ETHTOOL_LINK_MODE_10baseT_Full_BIT:
1137 set_mod_args(args, 10, 0, 1, BIT_ULL(CGX_MODE_SGMII));
1139 case ETHTOOL_LINK_MODE_100baseT_Half_BIT:
1140 set_mod_args(args, 100, 1, 1, BIT_ULL(CGX_MODE_SGMII));
1142 case ETHTOOL_LINK_MODE_100baseT_Full_BIT:
1143 set_mod_args(args, 100, 0, 1, BIT_ULL(CGX_MODE_SGMII));
1145 case ETHTOOL_LINK_MODE_1000baseT_Half_BIT:
1146 set_mod_args(args, 1000, 1, 1, BIT_ULL(CGX_MODE_SGMII));
1148 case ETHTOOL_LINK_MODE_1000baseT_Full_BIT:
1149 set_mod_args(args, 1000, 0, 1, BIT_ULL(CGX_MODE_SGMII));
1151 case ETHTOOL_LINK_MODE_1000baseX_Full_BIT:
1152 set_mod_args(args, 1000, 0, 0, BIT_ULL(CGX_MODE_1000_BASEX));
1154 case ETHTOOL_LINK_MODE_10000baseT_Full_BIT:
1155 set_mod_args(args, 1000, 0, 1, BIT_ULL(CGX_MODE_QSGMII));
1157 case ETHTOOL_LINK_MODE_10000baseSR_Full_BIT:
1158 set_mod_args(args, 10000, 0, 0, BIT_ULL(CGX_MODE_10G_C2C));
1160 case ETHTOOL_LINK_MODE_10000baseLR_Full_BIT:
1161 set_mod_args(args, 10000, 0, 0, BIT_ULL(CGX_MODE_10G_C2M));
1163 case ETHTOOL_LINK_MODE_10000baseKR_Full_BIT:
1164 set_mod_args(args, 10000, 0, 1, BIT_ULL(CGX_MODE_10G_KR));
1166 case ETHTOOL_LINK_MODE_25000baseSR_Full_BIT:
1167 set_mod_args(args, 25000, 0, 0, BIT_ULL(CGX_MODE_25G_C2C));
1169 case ETHTOOL_LINK_MODE_25000baseCR_Full_BIT:
1170 set_mod_args(args, 25000, 0, 1, BIT_ULL(CGX_MODE_25G_CR));
1172 case ETHTOOL_LINK_MODE_25000baseKR_Full_BIT:
1173 set_mod_args(args, 25000, 0, 1, BIT_ULL(CGX_MODE_25G_KR));
1175 case ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT:
1176 set_mod_args(args, 40000, 0, 0, BIT_ULL(CGX_MODE_40G_C2C));
1178 case ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT:
1179 set_mod_args(args, 40000, 0, 0, BIT_ULL(CGX_MODE_40G_C2M));
1181 case ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT:
1182 set_mod_args(args, 40000, 0, 1, BIT_ULL(CGX_MODE_40G_CR4));
1184 case ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT:
1185 set_mod_args(args, 40000, 0, 1, BIT_ULL(CGX_MODE_40G_KR4));
1187 case ETHTOOL_LINK_MODE_50000baseSR_Full_BIT:
1188 set_mod_args(args, 50000, 0, 0, BIT_ULL(CGX_MODE_50G_C2C));
1190 case ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT:
1191 set_mod_args(args, 50000, 0, 0, BIT_ULL(CGX_MODE_50G_C2M));
1193 case ETHTOOL_LINK_MODE_50000baseCR_Full_BIT:
1194 set_mod_args(args, 50000, 0, 1, BIT_ULL(CGX_MODE_50G_CR));
1196 case ETHTOOL_LINK_MODE_50000baseKR_Full_BIT:
1197 set_mod_args(args, 50000, 0, 1, BIT_ULL(CGX_MODE_50G_KR));
1199 case ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT:
1200 set_mod_args(args, 100000, 0, 0, BIT_ULL(CGX_MODE_100G_C2C));
1202 case ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT:
1203 set_mod_args(args, 100000, 0, 0, BIT_ULL(CGX_MODE_100G_C2M));
1205 case ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT:
1206 set_mod_args(args, 100000, 0, 1, BIT_ULL(CGX_MODE_100G_CR4));
1208 case ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT:
1209 set_mod_args(args, 100000, 0, 1, BIT_ULL(CGX_MODE_100G_KR4));
1212 set_mod_args(args, 0, 1, 0, BIT_ULL(CGX_MODE_MAX));
1217 static inline void link_status_user_format(u64 lstat,
1218 struct cgx_link_user_info *linfo,
1219 struct cgx *cgx, u8 lmac_id)
1221 linfo->link_up = FIELD_GET(RESP_LINKSTAT_UP, lstat);
1222 linfo->full_duplex = FIELD_GET(RESP_LINKSTAT_FDUPLEX, lstat);
1223 linfo->speed = cgx_speed_mbps[FIELD_GET(RESP_LINKSTAT_SPEED, lstat)];
1224 linfo->an = FIELD_GET(RESP_LINKSTAT_AN, lstat);
1225 linfo->fec = FIELD_GET(RESP_LINKSTAT_FEC, lstat);
1226 linfo->lmac_type_id = FIELD_GET(RESP_LINKSTAT_LMAC_TYPE, lstat);
1228 if (linfo->lmac_type_id >= LMAC_MODE_MAX) {
1229 dev_err(&cgx->pdev->dev, "Unknown lmac_type_id %d reported by firmware on cgx port%d:%d",
1230 linfo->lmac_type_id, cgx->cgx_id, lmac_id);
1231 strscpy(linfo->lmac_type, "Unknown", sizeof(linfo->lmac_type));
1235 strscpy(linfo->lmac_type, cgx_lmactype_string[linfo->lmac_type_id],
1236 sizeof(linfo->lmac_type));
1239 /* Hardware event handlers */
1240 static inline void cgx_link_change_handler(u64 lstat,
1243 struct cgx_link_user_info *linfo;
1244 struct cgx *cgx = lmac->cgx;
1245 struct cgx_link_event event;
1249 dev = &cgx->pdev->dev;
1251 link_status_user_format(lstat, &event.link_uinfo, cgx, lmac->lmac_id);
1252 err_type = FIELD_GET(RESP_LINKSTAT_ERRTYPE, lstat);
1254 event.cgx_id = cgx->cgx_id;
1255 event.lmac_id = lmac->lmac_id;
1257 /* update the local copy of link status */
1258 lmac->link_info = event.link_uinfo;
1259 linfo = &lmac->link_info;
1261 if (err_type == CGX_ERR_SPEED_CHANGE_INVALID)
1264 /* Ensure callback doesn't get unregistered until we finish it */
1265 spin_lock(&lmac->event_cb_lock);
1267 if (!lmac->event_cb.notify_link_chg) {
1268 dev_dbg(dev, "cgx port %d:%d Link change handler null",
1269 cgx->cgx_id, lmac->lmac_id);
1270 if (err_type != CGX_ERR_NONE) {
1271 dev_err(dev, "cgx port %d:%d Link error %d\n",
1272 cgx->cgx_id, lmac->lmac_id, err_type);
1274 dev_info(dev, "cgx port %d:%d Link is %s %d Mbps\n",
1275 cgx->cgx_id, lmac->lmac_id,
1276 linfo->link_up ? "UP" : "DOWN", linfo->speed);
1280 if (lmac->event_cb.notify_link_chg(&event, lmac->event_cb.data))
1281 dev_err(dev, "event notification failure\n");
1283 spin_unlock(&lmac->event_cb_lock);
1286 static inline bool cgx_cmdresp_is_linkevent(u64 event)
1290 id = FIELD_GET(EVTREG_ID, event);
1291 if (id == CGX_CMD_LINK_BRING_UP ||
1292 id == CGX_CMD_LINK_BRING_DOWN ||
1293 id == CGX_CMD_MODE_CHANGE)
1299 static inline bool cgx_event_is_linkevent(u64 event)
1301 if (FIELD_GET(EVTREG_ID, event) == CGX_EVT_LINK_CHANGE)
1307 static irqreturn_t cgx_fwi_event_handler(int irq, void *data)
1309 u64 event, offset, clear_bit;
1310 struct lmac *lmac = data;
1315 /* Clear SW_INT for RPM and CMR_INT for CGX */
1316 offset = cgx->mac_ops->int_register;
1317 clear_bit = cgx->mac_ops->int_ena_bit;
1319 event = cgx_read(cgx, lmac->lmac_id, CGX_EVENT_REG);
1321 if (!FIELD_GET(EVTREG_ACK, event))
1324 switch (FIELD_GET(EVTREG_EVT_TYPE, event)) {
1325 case CGX_EVT_CMD_RESP:
1326 /* Copy the response. Since only one command is active at a
1327 * time, there is no way a response can get overwritten
1330 /* Ensure response is updated before thread context starts */
1333 /* There wont be separate events for link change initiated from
1334 * software; Hence report the command responses as events
1336 if (cgx_cmdresp_is_linkevent(event))
1337 cgx_link_change_handler(event, lmac);
1339 /* Release thread waiting for completion */
1340 lmac->cmd_pend = false;
1341 wake_up(&lmac->wq_cmd_cmplt);
1344 if (cgx_event_is_linkevent(event))
1345 cgx_link_change_handler(event, lmac);
1349 /* Any new event or command response will be posted by firmware
1350 * only after the current status is acked.
1351 * Ack the interrupt register as well.
1353 cgx_write(lmac->cgx, lmac->lmac_id, CGX_EVENT_REG, 0);
1354 cgx_write(lmac->cgx, lmac->lmac_id, offset, clear_bit);
1359 /* APIs for PHY management using CGX firmware interface */
1361 /* callback registration for hardware events like link change */
1362 int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id)
1364 struct cgx *cgx = cgxd;
1367 lmac = lmac_pdata(lmac_id, cgx);
1371 lmac->event_cb = *cb;
1376 int cgx_lmac_evh_unregister(void *cgxd, int lmac_id)
1379 unsigned long flags;
1380 struct cgx *cgx = cgxd;
1382 lmac = lmac_pdata(lmac_id, cgx);
1386 spin_lock_irqsave(&lmac->event_cb_lock, flags);
1387 lmac->event_cb.notify_link_chg = NULL;
1388 lmac->event_cb.data = NULL;
1389 spin_unlock_irqrestore(&lmac->event_cb_lock, flags);
1394 int cgx_get_fwdata_base(u64 *base)
1401 cgx = list_first_entry_or_null(&cgx_list, struct cgx, cgx_list);
1405 first_lmac = find_first_bit(&cgx->lmac_bmap, cgx->max_lmac_per_mac);
1406 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_FWD_BASE, req);
1407 err = cgx_fwi_cmd_generic(req, &resp, cgx, first_lmac);
1409 *base = FIELD_GET(RESP_FWD_BASE, resp);
1414 int cgx_set_link_mode(void *cgxd, struct cgx_set_link_mode_args args,
1415 int cgx_id, int lmac_id)
1417 struct cgx *cgx = cgxd;
1424 otx2_map_ethtool_link_modes(args.mode, &args);
1425 if (!args.speed && args.duplex && !args.an)
1428 req = FIELD_SET(CMDREG_ID, CGX_CMD_MODE_CHANGE, req);
1429 req = FIELD_SET(CMDMODECHANGE_SPEED,
1430 cgx_link_usertable_index_map(args.speed), req);
1431 req = FIELD_SET(CMDMODECHANGE_DUPLEX, args.duplex, req);
1432 req = FIELD_SET(CMDMODECHANGE_AN, args.an, req);
1433 req = FIELD_SET(CMDMODECHANGE_PORT, args.ports, req);
1434 req = FIELD_SET(CMDMODECHANGE_FLAGS, args.mode, req);
1436 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id);
1438 int cgx_set_fec(u64 fec, int cgx_id, int lmac_id)
1444 cgx = cgx_get_pdata(cgx_id);
1448 req = FIELD_SET(CMDREG_ID, CGX_CMD_SET_FEC, req);
1449 req = FIELD_SET(CMDSETFEC, fec, req);
1450 err = cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id);
1454 cgx->lmac_idmap[lmac_id]->link_info.fec =
1455 FIELD_GET(RESP_LINKSTAT_FEC, resp);
1456 return cgx->lmac_idmap[lmac_id]->link_info.fec;
1459 int cgx_get_phy_fec_stats(void *cgxd, int lmac_id)
1461 struct cgx *cgx = cgxd;
1467 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_PHY_FEC_STATS, req);
1468 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id);
1471 static int cgx_fwi_link_change(struct cgx *cgx, int lmac_id, bool enable)
1477 req = FIELD_SET(CMDREG_ID, CGX_CMD_LINK_BRING_UP, req);
1478 /* On CN10K firmware offloads link bring up/down operations to ECP
1479 * On Octeontx2 link operations are handled by firmware itself
1480 * which can cause mbox errors so configure maximum time firmware
1481 * poll for Link as 1000 ms
1483 if (!is_dev_rpm(cgx))
1484 req = FIELD_SET(LINKCFG_TIMEOUT, 1000, req);
1487 req = FIELD_SET(CMDREG_ID, CGX_CMD_LINK_BRING_DOWN, req);
1489 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id);
1492 static inline int cgx_fwi_read_version(u64 *resp, struct cgx *cgx)
1494 int first_lmac = find_first_bit(&cgx->lmac_bmap, cgx->max_lmac_per_mac);
1497 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_FW_VER, req);
1498 return cgx_fwi_cmd_generic(req, resp, cgx, first_lmac);
1501 static int cgx_lmac_verify_fwi_version(struct cgx *cgx)
1503 struct device *dev = &cgx->pdev->dev;
1504 int major_ver, minor_ver;
1508 if (!cgx->lmac_count)
1511 err = cgx_fwi_read_version(&resp, cgx);
1515 major_ver = FIELD_GET(RESP_MAJOR_VER, resp);
1516 minor_ver = FIELD_GET(RESP_MINOR_VER, resp);
1517 dev_dbg(dev, "Firmware command interface version = %d.%d\n",
1518 major_ver, minor_ver);
1519 if (major_ver != CGX_FIRMWARE_MAJOR_VER)
1525 static void cgx_lmac_linkup_work(struct work_struct *work)
1527 struct cgx *cgx = container_of(work, struct cgx, cgx_cmd_work);
1528 struct device *dev = &cgx->pdev->dev;
1531 /* Do Link up for all the enabled lmacs */
1532 for_each_set_bit(i, &cgx->lmac_bmap, cgx->max_lmac_per_mac) {
1533 err = cgx_fwi_link_change(cgx, i, true);
1535 dev_info(dev, "cgx port %d:%d Link up command failed\n",
1540 int cgx_lmac_linkup_start(void *cgxd)
1542 struct cgx *cgx = cgxd;
1547 queue_work(cgx->cgx_cmd_workq, &cgx->cgx_cmd_work);
1552 int cgx_lmac_reset(void *cgxd, int lmac_id, u8 pf_req_flr)
1554 struct cgx *cgx = cgxd;
1557 if (!is_lmac_valid(cgx, lmac_id))
1560 /* Resetting PFC related CSRs */
1562 cgx_write(cgxd, lmac_id, CGXX_CMRX_RX_LOGL_XON, cfg);
1565 cgx_lmac_internal_loopback(cgxd, lmac_id, false);
1569 static int cgx_configure_interrupt(struct cgx *cgx, struct lmac *lmac,
1570 int cnt, bool req_free)
1572 struct mac_ops *mac_ops = cgx->mac_ops;
1573 u64 offset, ena_bit;
1577 irq = pci_irq_vector(cgx->pdev, mac_ops->lmac_fwi +
1578 cnt * mac_ops->irq_offset);
1579 offset = mac_ops->int_set_reg;
1580 ena_bit = mac_ops->int_ena_bit;
1583 free_irq(irq, lmac);
1587 err = request_irq(irq, cgx_fwi_event_handler, 0, lmac->name, lmac);
1591 /* Enable interrupt */
1592 cgx_write(cgx, lmac->lmac_id, offset, ena_bit);
1596 int cgx_get_nr_lmacs(void *cgxd)
1598 struct cgx *cgx = cgxd;
1600 return cgx_read(cgx, 0, CGXX_CMRX_RX_LMACS) & 0x7ULL;
1603 u8 cgx_get_lmacid(void *cgxd, u8 lmac_index)
1605 struct cgx *cgx = cgxd;
1607 return cgx->lmac_idmap[lmac_index]->lmac_id;
1610 unsigned long cgx_get_lmac_bmap(void *cgxd)
1612 struct cgx *cgx = cgxd;
1614 return cgx->lmac_bmap;
1617 static int cgx_lmac_init(struct cgx *cgx)
1623 /* lmac_list specifies which lmacs are enabled
1624 * when bit n is set to 1, LMAC[n] is enabled
1626 if (cgx->mac_ops->non_contiguous_serdes_lane) {
1627 if (is_dev_rpm2(cgx))
1629 cgx_read(cgx, 0, RPM2_CMRX_RX_LMACS) & 0xFFULL;
1632 cgx_read(cgx, 0, CGXX_CMRX_RX_LMACS) & 0xFULL;
1635 if (cgx->lmac_count > cgx->max_lmac_per_mac)
1636 cgx->lmac_count = cgx->max_lmac_per_mac;
1638 for (i = 0; i < cgx->lmac_count; i++) {
1639 lmac = kzalloc(sizeof(struct lmac), GFP_KERNEL);
1642 lmac->name = kcalloc(1, sizeof("cgx_fwi_xxx_yyy"), GFP_KERNEL);
1647 sprintf(lmac->name, "cgx_fwi_%d_%d", cgx->cgx_id, i);
1648 if (cgx->mac_ops->non_contiguous_serdes_lane) {
1649 lmac->lmac_id = __ffs64(lmac_list);
1650 lmac_list &= ~BIT_ULL(lmac->lmac_id);
1656 lmac->mac_to_index_bmap.max =
1657 cgx->mac_ops->dmac_filter_count /
1660 err = rvu_alloc_bitmap(&lmac->mac_to_index_bmap);
1664 /* Reserve first entry for default MAC address */
1665 set_bit(0, lmac->mac_to_index_bmap.bmap);
1667 lmac->rx_fc_pfvf_bmap.max = 128;
1668 err = rvu_alloc_bitmap(&lmac->rx_fc_pfvf_bmap);
1670 goto err_dmac_bmap_free;
1672 lmac->tx_fc_pfvf_bmap.max = 128;
1673 err = rvu_alloc_bitmap(&lmac->tx_fc_pfvf_bmap);
1675 goto err_rx_fc_bmap_free;
1677 init_waitqueue_head(&lmac->wq_cmd_cmplt);
1678 mutex_init(&lmac->cmd_lock);
1679 spin_lock_init(&lmac->event_cb_lock);
1680 err = cgx_configure_interrupt(cgx, lmac, lmac->lmac_id, false);
1682 goto err_bitmap_free;
1685 cgx->lmac_idmap[lmac->lmac_id] = lmac;
1686 set_bit(lmac->lmac_id, &cgx->lmac_bmap);
1687 cgx->mac_ops->mac_pause_frm_config(cgx, lmac->lmac_id, true);
1688 lmac->lmac_type = cgx->mac_ops->get_lmac_type(cgx, lmac->lmac_id);
1691 return cgx_lmac_verify_fwi_version(cgx);
1694 rvu_free_bitmap(&lmac->tx_fc_pfvf_bmap);
1695 err_rx_fc_bmap_free:
1696 rvu_free_bitmap(&lmac->rx_fc_pfvf_bmap);
1698 rvu_free_bitmap(&lmac->mac_to_index_bmap);
1706 static int cgx_lmac_exit(struct cgx *cgx)
1711 if (cgx->cgx_cmd_workq) {
1712 destroy_workqueue(cgx->cgx_cmd_workq);
1713 cgx->cgx_cmd_workq = NULL;
1716 /* Free all lmac related resources */
1717 for_each_set_bit(i, &cgx->lmac_bmap, cgx->max_lmac_per_mac) {
1718 lmac = cgx->lmac_idmap[i];
1721 cgx->mac_ops->mac_pause_frm_config(cgx, lmac->lmac_id, false);
1722 cgx_configure_interrupt(cgx, lmac, lmac->lmac_id, true);
1723 kfree(lmac->mac_to_index_bmap.bmap);
1731 static void cgx_populate_features(struct cgx *cgx)
1735 cfg = cgx_read(cgx, 0, CGX_CONST);
1736 cgx->mac_ops->fifo_len = FIELD_GET(CGX_CONST_RXFIFO_SIZE, cfg);
1737 cgx->max_lmac_per_mac = FIELD_GET(CGX_CONST_MAX_LMACS, cfg);
1739 if (is_dev_rpm(cgx))
1740 cgx->hw_features = (RVU_LMAC_FEAT_DMACF | RVU_MAC_RPM |
1741 RVU_LMAC_FEAT_FC | RVU_LMAC_FEAT_PTP);
1743 cgx->hw_features = (RVU_LMAC_FEAT_FC | RVU_LMAC_FEAT_HIGIG2 |
1744 RVU_LMAC_FEAT_PTP | RVU_LMAC_FEAT_DMACF);
1747 static u8 cgx_get_rxid_mapoffset(struct cgx *cgx)
1749 if (cgx->pdev->subsystem_device == PCI_SUBSYS_DEVID_CNF10KB_RPM ||
1756 static struct mac_ops cgx_mac_ops = {
1760 .int_register = CGXX_CMRX_INT,
1761 .int_set_reg = CGXX_CMRX_INT_ENA_W1S,
1763 .int_ena_bit = FW_CGX_INT,
1764 .lmac_fwi = CGX_LMAC_FWI,
1765 .non_contiguous_serdes_lane = false,
1768 .dmac_filter_count = 32,
1769 .get_nr_lmacs = cgx_get_nr_lmacs,
1770 .get_lmac_type = cgx_get_lmac_type,
1771 .lmac_fifo_len = cgx_get_lmac_fifo_len,
1772 .mac_lmac_intl_lbk = cgx_lmac_internal_loopback,
1773 .mac_get_rx_stats = cgx_get_rx_stats,
1774 .mac_get_tx_stats = cgx_get_tx_stats,
1775 .get_fec_stats = cgx_get_fec_stats,
1776 .mac_enadis_rx_pause_fwding = cgx_lmac_enadis_rx_pause_fwding,
1777 .mac_get_pause_frm_status = cgx_lmac_get_pause_frm_status,
1778 .mac_enadis_pause_frm = cgx_lmac_enadis_pause_frm,
1779 .mac_pause_frm_config = cgx_lmac_pause_frm_config,
1780 .mac_enadis_ptp_config = cgx_lmac_ptp_config,
1781 .mac_rx_tx_enable = cgx_lmac_rx_tx_enable,
1782 .mac_tx_enable = cgx_lmac_tx_enable,
1783 .pfc_config = cgx_lmac_pfc_config,
1784 .mac_get_pfc_frm_cfg = cgx_lmac_get_pfc_frm_cfg,
1785 .mac_reset = cgx_lmac_reset,
1788 static int cgx_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1790 struct device *dev = &pdev->dev;
1794 cgx = devm_kzalloc(dev, sizeof(*cgx), GFP_KERNEL);
1799 pci_set_drvdata(pdev, cgx);
1801 /* Use mac_ops to get MAC specific features */
1802 if (is_dev_rpm(cgx))
1803 cgx->mac_ops = rpm_get_mac_ops(cgx);
1805 cgx->mac_ops = &cgx_mac_ops;
1807 cgx->mac_ops->rxid_map_offset = cgx_get_rxid_mapoffset(cgx);
1809 err = pci_enable_device(pdev);
1811 dev_err(dev, "Failed to enable PCI device\n");
1812 pci_set_drvdata(pdev, NULL);
1816 err = pci_request_regions(pdev, DRV_NAME);
1818 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1819 goto err_disable_device;
1822 /* MAP configuration registers */
1823 cgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1824 if (!cgx->reg_base) {
1825 dev_err(dev, "CGX: Cannot map CSR memory space, aborting\n");
1827 goto err_release_regions;
1830 cgx->lmac_count = cgx->mac_ops->get_nr_lmacs(cgx);
1831 if (!cgx->lmac_count) {
1832 dev_notice(dev, "CGX %d LMAC count is zero, skipping probe\n", cgx->cgx_id);
1834 goto err_release_regions;
1837 nvec = pci_msix_vec_count(cgx->pdev);
1838 err = pci_alloc_irq_vectors(pdev, nvec, nvec, PCI_IRQ_MSIX);
1839 if (err < 0 || err != nvec) {
1840 dev_err(dev, "Request for %d msix vectors failed, err %d\n",
1842 goto err_release_regions;
1845 cgx->cgx_id = (pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM) >> 24)
1848 /* init wq for processing linkup requests */
1849 INIT_WORK(&cgx->cgx_cmd_work, cgx_lmac_linkup_work);
1850 cgx->cgx_cmd_workq = alloc_workqueue("cgx_cmd_workq", 0, 0);
1851 if (!cgx->cgx_cmd_workq) {
1852 dev_err(dev, "alloc workqueue failed for cgx cmd");
1854 goto err_free_irq_vectors;
1857 list_add(&cgx->cgx_list, &cgx_list);
1860 cgx_populate_features(cgx);
1862 mutex_init(&cgx->lock);
1864 err = cgx_lmac_init(cgx);
1866 goto err_release_lmac;
1872 list_del(&cgx->cgx_list);
1873 err_free_irq_vectors:
1874 pci_free_irq_vectors(pdev);
1875 err_release_regions:
1876 pci_release_regions(pdev);
1878 pci_disable_device(pdev);
1879 pci_set_drvdata(pdev, NULL);
1883 static void cgx_remove(struct pci_dev *pdev)
1885 struct cgx *cgx = pci_get_drvdata(pdev);
1889 list_del(&cgx->cgx_list);
1891 pci_free_irq_vectors(pdev);
1892 pci_release_regions(pdev);
1893 pci_disable_device(pdev);
1894 pci_set_drvdata(pdev, NULL);
1897 struct pci_driver cgx_driver = {
1899 .id_table = cgx_id_table,
1901 .remove = cgx_remove,